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| author | Jean-Philippe Brucker <jean-philippe@linaro.org> | 2022-08-22 18:22:24 +0300 |
|---|---|---|
| committer | Rob Herring <robh@kernel.org> | 2022-08-23 18:41:45 +0300 |
| commit | f1bd8b2e89cc755b2d1b07058b8afbae2fa302dd (patch) | |
| tree | 31e7165dd0d1221bd67e8a5ede7da97b87c6bede /Documentation/devicetree/bindings/crypto/intel,keembay-ocs-ecc.yaml | |
| parent | 92572a8ec3d8b4dc186eeefa1c973645c0753ae0 (diff) | |
| download | linux-f1bd8b2e89cc755b2d1b07058b8afbae2fa302dd.tar.xz | |
dt-bindings: interrupt-controller: arm,gic: Support two address and size cells
It should be valid for a GICv2m node, child of a GICv2 node, to use two
cells per reg address and size. The QEMU virt device-tree currently
fails validation because the schema imposes a single address and size
cell. Amend the rule.
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220822152224.507497-4-jean-philippe@linaro.org
Diffstat (limited to 'Documentation/devicetree/bindings/crypto/intel,keembay-ocs-ecc.yaml')
0 files changed, 0 insertions, 0 deletions