diff options
author | Palmer Dabbelt <palmer@rivosinc.com> | 2022-04-01 22:57:42 +0300 |
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committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-04-02 01:09:50 +0300 |
commit | 2524257bce43610f5ec14feccbacf7a103cae94a (patch) | |
tree | ef9eff4b37caa4dcd22c4df37ab43113eacef81a /Documentation/devicetree/bindings/cpu | |
parent | a3dfc532b8731843c12bdc45e804eacc47e51e50 (diff) | |
download | linux-2524257bce43610f5ec14feccbacf7a103cae94a.tar.xz |
dt-bindings: Fix phandle-array issues in the idle-states bindings
As per 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), the
phandle-array bindings have been disambiguated. This fixes the new
RISC-V idle-states bindings to comply with the schema.
Fixes: 1bd524f7e8d8 ("dt-bindings: Add common bindings for ARM and RISC-V idle states")
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/devicetree/bindings/cpu')
-rw-r--r-- | Documentation/devicetree/bindings/cpu/idle-states.yaml | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/Documentation/devicetree/bindings/cpu/idle-states.yaml b/Documentation/devicetree/bindings/cpu/idle-states.yaml index 5daa219ceb7b..fa4d4142ac93 100644 --- a/Documentation/devicetree/bindings/cpu/idle-states.yaml +++ b/Documentation/devicetree/bindings/cpu/idle-states.yaml @@ -719,8 +719,8 @@ examples: reg = <0x0>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv48"; - cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0 - &CLUSTER_RET_0 &CLUSTER_NONRET_0>; + cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>, + <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>; cpu_intc0: interrupt-controller { #interrupt-cells = <1>; @@ -735,8 +735,8 @@ examples: reg = <0x1>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv48"; - cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0 - &CLUSTER_RET_0 &CLUSTER_NONRET_0>; + cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>, + <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>; cpu_intc1: interrupt-controller { #interrupt-cells = <1>; @@ -751,8 +751,8 @@ examples: reg = <0x10>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv48"; - cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0 - &CLUSTER_RET_1 &CLUSTER_NONRET_1>; + cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>, + <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>; cpu_intc10: interrupt-controller { #interrupt-cells = <1>; @@ -767,8 +767,8 @@ examples: reg = <0x11>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv48"; - cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0 - &CLUSTER_RET_1 &CLUSTER_NONRET_1>; + cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>, + <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>; cpu_intc11: interrupt-controller { #interrupt-cells = <1>; |