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authorChen-Yu Tsai <wens@csie.org>2015-01-27 22:54:07 +0300
committerMaxime Ripard <maxime.ripard@free-electrons.com>2015-02-23 11:25:54 +0300
commit71f32f56cb54303a1b6ce6811373f57d87de40d3 (patch)
treea558860eda063760e331be9389c77f34dc7cde94 /Documentation/devicetree/bindings/clock
parent6089ef19c9dadaf0e3378f75eca65af861cd3974 (diff)
downloadlinux-71f32f56cb54303a1b6ce6811373f57d87de40d3.tar.xz
clk: sunxi: Add support for sun9i A80 USB clocks and resets
The USB controller/phy clocks and reset controls are in a separate address block, unlike previous SoCs where they were in the clock controller. Also, access to the address block is controlled by a clock gate to AHB. Add support for resets requiring a clock to be enabled when asserting/deasserting the reset controls, and add the sun9i USB clocks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt2
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 60b44285250d..3f1dcd879af7 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -66,6 +66,8 @@ Required properties:
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
+ "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
+ "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
Required properties for all clocks:
- reg : shall be the control register address for the clock.