Merge tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux

Pull clk framework changes from Mike Turquette:
 "The first half of the clk framework pull request is made up almost
  entirely of new platform/driver support.  There are some conversions
  of existing drivers to the common-clock Device Tree binding, and a few
  non-critical fixes to the framework.

  Due to an entirely unnecessary cyclical dependency with the arm-soc
  tree this pull request is broken into two pieces.  The second piece
  will be sent out after arm-soc sends you the pull request that merged
  in core support for the HiSilicon 3620 platform.  That same pull
  request from arm-soc depends on this pull request to merge in those
  HiSilicon bits without causing build failures"

[ Just did the ARM SoC merges, so getting ready for the second clk tree
  pull request   - Linus ]

* tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits)
  devicetree: bindings: Document qcom,mmcc
  devicetree: bindings: Document qcom,gcc
  clk: qcom: Add support for MSM8660's global clock controller (GCC)
  clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)
  clk: qcom: Add support for MSM8974's global clock controller (GCC)
  clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)
  clk: qcom: Add support for MSM8960's global clock controller (GCC)
  clk: qcom: Add reset controller support
  clk: qcom: Add support for branches/gate clocks
  clk: qcom: Add support for root clock generators (RCGs)
  clk: qcom: Add support for phase locked loops (PLLs)
  clk: qcom: Add a regmap type clock struct
  clk: Add set_rate_and_parent() op
  reset: Silence warning in reset-controller.h
  clk: sirf: re-arch to make the codes support both prima2 and atlas6
  clk: composite: pass mux_hw into determine_rate
  clk: shmobile: Fix MSTP clock array initialization
  clk: shmobile: Fix MSTP clock index
  ARM: dts: Add clock provider specific properties to max77686 node
  clk: max77686: Register OF clock provider
  ...

1 files changed, 98 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/clock/emev2-clock.txt b/Documentation/devicetree/bindings/clock/emev2-clock.txt
new file mode 100644
index 000000000000..60bbb1a8c69a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/emev2-clock.txt
@@ -0,0 +1,98 @@
+Device tree Clock bindings for Renesas EMMA Mobile EV2
+
+This binding uses the common clock binding.
+
+* SMU
+System Management Unit described in user's manual R19UH0037EJ1000_SMU.
+This is not a clock provider, but clocks under SMU depend on it.
+
+Required properties:
+- compatible: Should be "renesas,emev2-smu"
+- reg: Address and Size of SMU registers
+
+* SMU_CLKDIV
+Function block with an input mux and a divider, which corresponds to
+"Serial clock generator" in fig."Clock System Overview" of the manual,
+and "xxx frequency division setting register" (XXXCLKDIV) registers.
+This makes internal (neither input nor output) clock that is provided
+to input of xxxGCLK block.
+
+Required properties:
+- compatible: Should be "renesas,emev2-smu-clkdiv"
+- reg: Byte offset from SMU base and Bit position in the register
+- clocks: Parent clocks. Input clocks as described in clock-bindings.txt
+- #clock-cells: Should be <0>
+
+* SMU_GCLK
+Clock gating node shown as "Clock stop processing block" in the
+fig."Clock System Overview" of the manual.
+Registers are "xxx clock gate control register" (XXXGCLKCTRL).
+
+Required properties:
+- compatible: Should be "renesas,emev2-smu-gclk"
+- reg: Byte offset from SMU base and Bit position in the register
+- clocks: Input clock as described in clock-bindings.txt
+- #clock-cells: Should be <0>
+
+Example of provider:
+
+usia_u0_sclkdiv: usia_u0_sclkdiv {
+	compatible = "renesas,emev2-smu-clkdiv";
+	reg = <0x610 0>;
+	clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>;
+	#clock-cells = <0>;
+};
+
+usia_u0_sclk: usia_u0_sclk {
+	compatible = "renesas,emev2-smu-gclk";
+	reg = <0x4a0 1>;
+	clocks = <&usia_u0_sclkdiv>;
+	#clock-cells = <0>;
+};
+
+Example of consumer:
+
+uart@e1020000 {
+	compatible = "renesas,em-uart";
+	reg = <0xe1020000 0x38>;
+	interrupts = <0 8 0>;
+	clocks = <&usia_u0_sclk>;
+	clock-names = "sclk";
+};
+
+Example of clock-tree description:
+
+ This describes a clock path in the clock tree
+  c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
+
+smu@e0110000 {
+	compatible = "renesas,emev2-smu";
+	reg = <0xe0110000 0x10000>;
+	#address-cells = <2>;
+	#size-cells = <0>;
+
+	c32ki: c32ki {
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+		#clock-cells = <0>;
+	};
+	pll3_fo: pll3_fo {
+		compatible = "fixed-factor-clock";
+		clocks = <&c32ki>;
+		clock-div = <1>;
+		clock-mult = <7000>;
+		#clock-cells = <0>;
+	};
+	usia_u0_sclkdiv: usia_u0_sclkdiv {
+		compatible = "renesas,emev2-smu-clkdiv";
+		reg = <0x610 0>;
+		clocks = <&pll3_fo>;
+		#clock-cells = <0>;
+	};
+	usia_u0_sclk: usia_u0_sclk {
+		compatible = "renesas,emev2-smu-gclk";
+		reg = <0x4a0 1>;
+		clocks = <&usia_u0_sclkdiv>;
+		#clock-cells = <0>;
+	};
+};