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| author | Jiri Kosina <jkosina@suse.cz> | 2014-06-04 15:09:01 +0400 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2014-06-04 15:09:01 +0400 |
| commit | af5666e0f76023d9c296016024297903a4c83108 (patch) | |
| tree | 9397e7a41dd3eb0c0e14a6407a8e8f12abed4fc5 /Documentation/devicetree/bindings/clock/altr_socfpga.txt | |
| parent | 1b15d2e5b8077670b1e6a33250a0d9577efff4a5 (diff) | |
| parent | 368c96640d10a145da5f258f2d2833668d4f3629 (diff) | |
| download | linux-af5666e0f76023d9c296016024297903a4c83108.tar.xz | |
Merge branches 'for-3.15/upstream-fixes' and 'for-3.16/upstream' into for-linus
Conflicts:
drivers/hid/hid-sensor-hub.c
Diffstat (limited to 'Documentation/devicetree/bindings/clock/altr_socfpga.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/altr_socfpga.txt | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt index 0045433eae1f..5dfd145d3ccf 100644 --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt @@ -23,3 +23,8 @@ Optional properties: and the bit index. - div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift, and width. +- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls + the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second + value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct + hold/delay times that is needed for the SD/MMC CIU clock. The values of both + can be 0-315 degrees, in 45 degree increments. |