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| author | Daniel Palmer <daniel@0x0f.com> | 2020-07-28 13:03:14 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2020-07-28 14:15:47 +0300 |
| commit | 9e30b098f25f525af048e685ccb79fc958cfd200 (patch) | |
| tree | bd184745e5260b5db19a20936fd39114635cb510 /Documentation/devicetree/bindings/arm | |
| parent | 33cabc0bc679022160c48f96e2d358e666710f58 (diff) | |
| download | linux-9e30b098f25f525af048e685ccb79fc958cfd200.tar.xz | |
dt-bindings: arm: mstar: Move existing MStar binding descriptions
Now there is an mstar directory move the existing MStar specific
descriptions into that directory.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'Documentation/devicetree/bindings/arm')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml | 44 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/arm/mstar/mstar.yaml (renamed from Documentation/devicetree/bindings/arm/mstar.yaml) | 2 |
2 files changed, 45 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml new file mode 100644 index 000000000000..6816bd68f9cf --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 thingy.jp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MStar/SigmaStar Armv7 SoC l3bridge + +maintainers: + - Daniel Palmer <daniel@thingy.jp> + +description: | + MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface + between the CPU and memory. This means that before DMA capable + devices are allowed to run the pipeline must be flushed to ensure + everything is in memory. + + The l3bridge region contains registers that allow such a flush + to be triggered. + + This node is used by the platform code to find where the registers + are and install a barrier that triggers the required pipeline flush. + +properties: + compatible: + items: + - const: mstar,l3bridge + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + l3bridge: l3bridge@1f204400 { + compatible = "mstar,l3bridge"; + reg = <0x1f204400 0x200>; + }; diff --git a/Documentation/devicetree/bindings/arm/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml index bdce34b3336e..c2f980b00b06 100644 --- a/Documentation/devicetree/bindings/arm/mstar.yaml +++ b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/mstar.yaml# +$id: http://devicetree.org/schemas/arm/mstar/mstar.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: MStar platforms device tree bindings |