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| author | Haifeng Yan <yanhaifeng@gmail.com> | 2014-04-11 07:54:11 +0400 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2014-07-31 09:32:20 +0400 |
| commit | 06cc5c1d4d7313bc864e9aac1d1cbd63d8b9ca4c (patch) | |
| tree | b96d6476612d08b377597329043f82fb5e15c1fa /Documentation/devicetree/bindings/arm | |
| parent | 7685b125ca84a2da9c7a43578c3081cd209c2ac3 (diff) | |
| download | linux-06cc5c1d4d7313bc864e9aac1d1cbd63d8b9ca4c.tar.xz | |
ARM: hisi: enable hix5hd2 SoC
Enable support for the Hisilicon HiX5HD2 SoC. This HiX5HD2 SoC series
support both single and dual Cortex-A9 cores.
Add ARCH_HIX5HD2 to distinguish HiX5HD2 from Hi3xxx.
They are different in implementation such as SMP, IPs integarted and
earlycon configure.
Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com>
Signed-off-by: Jiancheng Xue <jchxue@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'Documentation/devicetree/bindings/arm')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index df0a452b8526..934f00025cc4 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -31,6 +31,17 @@ Example: reboot-offset = <0x4>; }; +----------------------------------------------------------------------- +Hisilicon CPU controller + +Required properties: +- compatible : "hisilicon,cpuctrl" +- reg : Register address and size + +The clock registers and power registers of secondary cores are defined +in CPU controller, especially in HIX5HD2 SoC. + +----------------------------------------------------------------------- PCTRL: Peripheral misc control register Required Properties: |