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| author | Andre Przywara <andre.przywara@arm.com> | 2020-05-01 00:10:51 +0300 |
|---|---|---|
| committer | Rob Herring <robh@kernel.org> | 2020-05-03 19:10:41 +0300 |
| commit | 04cbb87795f2c5ea35e2474039ca2b62d907b230 (patch) | |
| tree | 750ae24258121a4b7ac40e44fb13bb9f0820833b /Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt | |
| parent | 16be1e40259dfe2cb06257c8ad7c80e768b9ddc4 (diff) | |
| download | linux-04cbb87795f2c5ea35e2474039ca2b62d907b230.tar.xz | |
dt-bindings: arm: Convert Calxeda L2 cache controller to json-schema
Convert the L2-ECC controller binding to DT schema format using
json-schema.
This is indented to be just used for error reporting.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt deleted file mode 100644 index 94e642a33db0..000000000000 --- a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt +++ /dev/null @@ -1,15 +0,0 @@ -Calxeda Highbank L2 cache ECC - -Properties: -- compatible : Should be "calxeda,hb-sregs-l2-ecc" -- reg : Address and size for ECC error interrupt clear registers. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. - -Example: - - sregs@fff3c200 { - compatible = "calxeda,hb-sregs-l2-ecc"; - reg = <0xfff3c200 0x100>; - interrupts = <0 71 4 0 72 4>; - }; |