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| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2021-04-15 13:50:02 +0300 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@microchip.com> | 2021-07-19 16:27:14 +0300 |
| commit | b6862714078c5259ba5eb4785c8575d876bc7bf5 (patch) | |
| tree | a9df3b0c2da1ddfed20cc387c37a9e1562cbe585 /Documentation/devicetree/bindings/arm/atmel-sysregs.txt | |
| parent | 7540629e2fc70dd55dc92f971ff47903d8edb82b (diff) | |
| download | linux-b6862714078c5259ba5eb4785c8575d876bc7bf5.tar.xz | |
dt-bindings: atmel-sysreg: add bindings for sama7g5
Add RAM controller and RAM PHY controller DT bindings.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20210415105010.569620-17-claudiu.beznea@microchip.com
Diffstat (limited to 'Documentation/devicetree/bindings/arm/atmel-sysregs.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 807264a78edc..16eef600d599 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -45,7 +45,8 @@ RAMC SDRAM/DDR Controller required properties: "atmel,at91sam9260-sdramc", "atmel,at91sam9g45-ddramc", "atmel,sama5d3-ddramc", - "microchip,sam9x60-ddramc" + "microchip,sam9x60-ddramc", + "microchip,sama7g5-uddrc" - reg: Should contain registers location and length Examples: @@ -55,6 +56,17 @@ Examples: reg = <0xffffe800 0x200>; }; +RAMC PHY Controller required properties: +- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon" +- reg: Should contain registers location and length + +Example: + + ddr3phy: ddr3phy@e3804000 { + compatible = "microchip,sama7g5-ddr3phy", "syscon"; + reg = <0xe3804000 0x1000>; +}; + SHDWC Shutdown Controller required properties: |