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authorShreyas B. Prabhu <shreyas@linux.vnet.ibm.com>2016-07-08 09:20:52 +0300
committerMichael Ellerman <mpe@ellerman.id.au>2016-07-15 13:18:42 +0300
commit3005c597ba46480b42e1fea3512c408f1830b816 (patch)
tree296bc85154cee248c06f73aaa00ffcc5dba8251a /Documentation/device-mapper
parent957efcedeef4b02f2f7e5776d64448e5c40462b4 (diff)
downloadlinux-3005c597ba46480b42e1fea3512c408f1830b816.tar.xz
cpuidle/powernv: Add support for POWER ISA v3 idle states
POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. b) new per thread SPR named PSSCR is added which controls the behavior of stop instruction. Supported idle states and value to be written to PSSCR register to enter any idle state is exposed via ibm,cpu-idle-state-names and ibm,cpu-idle-state-psscr respectively. To enter an idle state, platform provided power_stop() needs to be invoked with the appropriate PSSCR value. This patch adds support for this new mechanism in cpuidle powernv driver. Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com> Cc: linux-pm@vger.kernel.org Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Paul Mackerras <paulus@ozlabs.org> Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com> Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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