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| author | zhengyan <zhengyan@asrmicro.com> | 2023-05-22 14:06:43 +0300 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2023-05-29 23:19:34 +0300 |
| commit | b4d81fab1ed0b302c71a869e5b93d81dfbfd3175 (patch) | |
| tree | ba32aa1829c189b46f64a9a112eeede8e47202aa /Documentation/arm64 | |
| parent | 3c65cbb7c5ebb4247968936899580c7f508ed223 (diff) | |
| download | linux-b4d81fab1ed0b302c71a869e5b93d81dfbfd3175.tar.xz | |
irqchip/gic-v3: Work around affinity issues on ASR8601
The ASR8601 SoC combines ARMv8.2 CPUs from ARM with a GIC-500,
also from ARM. However, the two are incompatible as the former
expose an affinity in the form of (cluster, core, thread),
while the latter can only deal with (cluster, core). If nothing
is done, the GIC simply cannot route interrupts to the CPUs.
Implement a workaround that shifts the affinity down by a level,
ensuring the delivery of interrupts despite the implementation
mismatch.
Signed-off-by: zhengyan <zhengyan@asrmicro.com>
[maz: rewrote commit message, reimplemented the workaround
in a manageable way]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'Documentation/arm64')
| -rw-r--r-- | Documentation/arm64/silicon-errata.rst | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index 9e311bc43e05..d6430ade349d 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -214,3 +214,7 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 | +----------------+-----------------+-----------------+-----------------------------+ + ++----------------+-----------------+-----------------+-----------------------------+ +| ASR | ASR8601 | #8601001 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ |