diff options
| author | Peter Collingbourne <pcc@google.com> | 2022-04-22 23:29:12 +0300 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2022-04-25 19:15:04 +0300 |
| commit | b6ba1a89f73f11000f6b3062c4dc2503531bd3d2 (patch) | |
| tree | cd68047a2718ead92c03474437bcaa8809b0eeed /Documentation/arm64 | |
| parent | 2a2848e7c2fde1c26ff46998ac10f7bf9ca2de04 (diff) | |
| download | linux-b6ba1a89f73f11000f6b3062c4dc2503531bd3d2.tar.xz | |
arm64: document the boot requirements for MTE
When booting the kernel we access system registers such as GCR_EL1
if MTE is supported. These accesses are defined to trap to EL3 if
SCR_EL3.ATA is disabled. Furthermore, tag accesses will not behave
as expected if SCR_EL3.ATA is not set, or if HCR_EL2.ATA is not set
and we were booted at EL1. Therefore, require that these bits are
enabled when appropriate.
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Link: https://linux-review.googlesource.com/id/Iadcfd4dcd9ba3279b2813970b44d7485b0116709
Link: https://lore.kernel.org/r/20220422202912.292039-1-pcc@google.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'Documentation/arm64')
| -rw-r--r-- | Documentation/arm64/booting.rst | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index 29884b261aa9..8aefa1001ae5 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -350,6 +350,16 @@ Before jumping into the kernel, the following conditions must be met: - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1. + For CPUs with the Memory Tagging Extension feature (FEAT_MTE2): + + - If EL3 is present: + + - SCR_EL3.ATA (bit 26) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - HCR_EL2.ATA (bit 56) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented |