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| author | Fenghua Yu <fenghua.yu@intel.com> | 2017-12-21 01:57:23 +0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-01-18 11:33:31 +0300 |
| commit | 99adde9b370de8e07ef76630c6f60dbf586cdf0e (patch) | |
| tree | 0ad73484ae0f8b38425bcf213338d2214f762daf /Documentation/admin-guide | |
| parent | def10853930a82456ab862a3a8292a3a16c386e7 (diff) | |
| download | linux-99adde9b370de8e07ef76630c6f60dbf586cdf0e.tar.xz | |
x86/intel_rdt: Enable L2 CDP in MSR IA32_L2_QOS_CFG
Bit 0 in MSR IA32_L2_QOS_CFG (0xc82) is L2 CDP enable bit. By default,
the bit is zero, i.e. L2 CAT is enabled, and L2 CDP is disabled. When
the resctrl mount parameter "cdpl2" is given, the bit is set to 1 and L2
CDP is enabled.
In L2 CDP mode, the L2 CAT mask MSRs are re-mapped into interleaved pairs
of mask MSRs for code (referenced by an odd CLOSID) and data (referenced by
an even CLOSID).
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: "Ravi V Shankar" <ravi.v.shankar@intel.com>
Cc: "Tony Luck" <tony.luck@intel.com>
Cc: Vikas" <vikas.shivappa@intel.com>
Cc: Sai Praneeth" <sai.praneeth.prakhya@intel.com>
Cc: Reinette" <reinette.chatre@intel.com>
Link: https://lkml.kernel.org/r/1513810644-78015-6-git-send-email-fenghua.yu@intel.com
Diffstat (limited to 'Documentation/admin-guide')
0 files changed, 0 insertions, 0 deletions