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| author | Eric Auger <eric.auger@redhat.com> | 2020-01-24 17:25:32 +0300 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2020-01-28 15:50:32 +0300 |
| commit | 3837407c1aa1101ed5e214c7d6041e7a23335c6e (patch) | |
| tree | 1a7addbb3015674bffbde53ec6c64cf25396cd69 /Documentation/IRQ-domain.txt | |
| parent | 21aecdbd7f3ab02c9b82597dc733ee759fb8b274 (diff) | |
| download | linux-3837407c1aa1101ed5e214c7d6041e7a23335c6e.tar.xz | |
KVM: arm64: pmu: Don't increment SW_INCR if PMCR.E is unset
The specification says PMSWINC increments PMEVCNTR<n>_EL1 by 1
if PMEVCNTR<n>_EL0 is enabled and configured to count SW_INCR.
For PMEVCNTR<n>_EL0 to be enabled, we need both PMCNTENSET to
be set for the corresponding event counter but we also need
the PMCR.E bit to be set.
Fixes: 7a0adc7064b8 ("arm64: KVM: Add access handler for PMSWINC register")
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200124142535.29386-2-eric.auger@redhat.com
Diffstat (limited to 'Documentation/IRQ-domain.txt')
0 files changed, 0 insertions, 0 deletions