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| author | Mathieu Poirier <mathieu.poirier@linaro.org> | 2014-11-11 00:06:42 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-11-27 06:27:28 +0300 |
| commit | 7a25ec8e481e9c14de13dcacca0d8ee33bfe5f3c (patch) | |
| tree | cbdea440c742f76a33ee04408cd64110b76ab79d /Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10 | |
| parent | 4b7e4f8289c1ca60accb6c1baf31984f69bc2771 (diff) | |
| download | linux-7a25ec8e481e9c14de13dcacca0d8ee33bfe5f3c.tar.xz | |
coresight: Adding ABI documentation
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10')
| -rw-r--r-- | Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10 | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10 b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10 new file mode 100644 index 000000000000..4b8d6ec92e2b --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10 @@ -0,0 +1,24 @@ +What: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink +Date: November 2014 +KernelVersion: 3.19 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Add/remove a sink from a trace path. There can be multiple + source for a single sink. + ex: echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink + +What: /sys/bus/coresight/devices/<memory_map>.etb/status +Date: November 2014 +KernelVersion: 3.19 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (R) List various control and status registers. The specific + layout and content is driver specific. + +What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr +Date: November 2014 +KernelVersion: 3.19 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Disables write access to the Trace RAM by stopping the + formatter after a defined number of words have been stored + following the trigger event. The number of 32-bit words written + into the Trace RAM following the trigger event is equal to the + value stored in this register+1 (from ARM ETB-TRM). |