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| author | Stefano Radaelli <stefano.r@variscite.com> | 2026-03-19 21:40:31 +0300 |
|---|---|---|
| committer | Frank Li <Frank.Li@nxp.com> | 2026-03-27 16:52:39 +0300 |
| commit | b06c76fcd88c4c3f7ec2dc88c368d1fd2770ad91 (patch) | |
| tree | 5f3144b17869c000f3c2c6eb95a6a2c618ead26e | |
| parent | 47fc77cb042d48712d9dee6068066abff4d3e737 (diff) | |
| download | linux-b06c76fcd88c4c3f7ec2dc88c368d1fd2770ad91.tar.xz | |
arm64: dts: imx8mm-var-som-symphony: Enable PCIe
Enable PCIe support on the VAR-SOM Symphony carrier board by adding the
external reference clock, configuring the PHY and providing the required
clock and reset properties.
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index fbad5d2d4a97..857325ef4461 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> #include "imx8mm-var-som.dtsi" #include "imx8mm-var-som-wifi-bt-iw61x.dtsi" @@ -17,6 +18,12 @@ stdout-path = &uart4; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -198,6 +205,29 @@ status = "okay"; }; +&pcie_phy { + clocks = <&pcie0_refclk>; + clock-names = "ref"; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + fsl,clkreq-unsupported; + status = "okay"; +}; + +&pcie0 { + reset-gpio = <&pca6408 1 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + /* Header */ &uart1 { pinctrl-names = "default"; |