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authorTony Lindgren <tony@atomide.com>2019-12-10 19:10:10 +0300
committerTony Lindgren <tony@atomide.com>2019-12-17 19:17:48 +0300
commit6974285ed52a9d28cdad4538ccbc7731c2e71738 (patch)
tree7f66877542701fe3250817d011c5e30b64776aa7
parenta0fc37ff28c00aaea2909e90c785dc5e2fa23dbb (diff)
downloadlinux-6974285ed52a9d28cdad4538ccbc7731c2e71738.tar.xz
ARM: OMAP2+: Drop legacy platform data for omap4 mcpdm
We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. As we're just dropping data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Cc: Keerthy <j-keerthy@ti.com> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Tested-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/boot/dts/omap4-l4-abe.dtsi1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c57
2 files changed, 0 insertions, 58 deletions
diff --git a/arch/arm/boot/dts/omap4-l4-abe.dtsi b/arch/arm/boot/dts/omap4-l4-abe.dtsi
index 80660871c795..6f609447aa8e 100644
--- a/arch/arm/boot/dts/omap4-l4-abe.dtsi
+++ b/arch/arm/boot/dts/omap4-l4-abe.dtsi
@@ -278,7 +278,6 @@
mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mcpdm";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 3cb74c72f972..92f89e6aa15a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1185,54 +1185,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
/*
- * 'mcpdm' class
- * multi channel pdm controller (proprietary interface with phoenix power
- * ic)
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
- .name = "mcpdm",
- .sysc = &omap44xx_mcpdm_sysc,
-};
-
-/* mcpdm */
-static struct omap_hwmod omap44xx_mcpdm_hwmod = {
- .name = "mcpdm",
- .class = &omap44xx_mcpdm_hwmod_class,
- .clkdm_name = "abe_clkdm",
- /*
- * It's suspected that the McPDM requires an off-chip main
- * functional clock, controlled via I2C. This IP block is
- * currently reset very early during boot, before I2C is
- * available, so it doesn't seem that we have any choice in
- * the kernel other than to avoid resetting it.
- *
- * Also, McPDM needs to be configured to NO_IDLE mode when it
- * is in used otherwise vital clocks will be gated which
- * results 'slow motion' audio playback.
- */
- .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
- .main_clk = "pad_clks_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
* 'mmu' class
* The memory management unit performs virtual to physical address translation
* for its requestors.
@@ -2582,14 +2534,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_abe -> mcpdm */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcpdm_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_2 -> ocmc_ram */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
.master = &omap44xx_l3_main_2_hwmod,
@@ -2904,7 +2848,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
/* &omap44xx_iva__sl2if, */
&omap44xx_l3_main_2__iva,
&omap44xx_l4_wkup__kbd,
- &omap44xx_l4_abe__mcpdm,
&omap44xx_l3_main_2__mmu_ipu,
&omap44xx_l4_cfg__mmu_dsp,
&omap44xx_l3_main_2__ocmc_ram,