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author | Stephen Boyd <sboyd@kernel.org> | 2023-08-31 00:37:45 +0300 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2023-08-31 00:37:45 +0300 |
commit | d10ebc7c646a46ba7de68470a0ae385a7eb7b7e3 (patch) | |
tree | 612fad74c67a22d2031f7252b51a08692c3711ea | |
parent | 03d4a1004053ad78f5928f3e869c2df29d25f541 (diff) | |
parent | 0e2b2a76278153d1ac312b0691cb65dabb9aef3e (diff) | |
parent | 096110aa23b9262a87bd8cf71ee4f04895825d00 (diff) | |
parent | 772b455987caacb6f68f8f8e7efe40fd4d5ed789 (diff) | |
parent | 0a26c3f8e0d201279ab27fabb61b9280c068be41 (diff) | |
download | linux-d10ebc7c646a46ba7de68470a0ae385a7eb7b7e3.tar.xz |
Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'clk-cleanup' into clk-next
- Remove OXNAS clk driver
* clk-bindings:
dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml
dt-bindings: clock: xlnx,versal-clk: drop select:false
dt-bindings: clock: versal: Add versal-net compatible string
dt-bindings: clock: ast2600: Add I3C and MAC reset definitions
dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into parent binding
* clk-starfive:
reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support
clk: starfive: Simplify .determine_rate()
clk: starfive: Add StarFive JH7110 Video-Output clock driver
clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver
clk: starfive: Add StarFive JH7110 System-Top-Group clock driver
clk: starfive: jh7110-sys: Add PLL clocks source from DTS
clk: starfive: Add StarFive JH7110 PLL clock driver
dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
dt-bindings: soc: starfive: Add StarFive syscon module
dt-bindings: clock: Add StarFive JH7110 PLL clock generator
* clk-rm:
dt-bindings: clk: oxnas: remove obsolete bindings
clk: oxnas: remove obsolete clock driver
* clk-renesas:
clk: renesas: rcar-gen3: Add ADG clocks
clk: renesas: r8a77965: Add 3DGE and ZG support
clk: renesas: r8a7796: Add 3DGE and ZG support
clk: renesas: r8a7795: Add 3DGE and ZG support
clk: renesas: emev2: Remove obsolete clkdev registration
clk: renesas: r9a07g043: Add MTU3a clock and reset entry
clk: renesas: rzg2l: Simplify .determine_rate()
clk: renesas: r9a09g011: Add CSI related clocks
clk: renesas: r8a774b1: Add 3DGE and ZG support
clk: renesas: r8a774e1: Add 3DGE and ZG support
clk: renesas: r8a774a1: Add 3DGE and ZG support
clk: renesas: rcar-gen3: Add support for ZG clock
* clk-cleanup:
clk: mvebu: Convert to devm_platform_ioremap_resource()
clk: nuvoton: Convert to devm_platform_ioremap_resource()
clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()
clk: ti: Use devm_platform_get_and_ioremap_resource()
clk: mediatek: Convert to devm_platform_ioremap_resource()
clk: hsdk-pll: Convert to devm_platform_ioremap_resource()
clk: gemini: Convert to devm_platform_ioremap_resource()
clk: fsl-sai: Convert to devm_platform_ioremap_resource()
clk: bm1880: Convert to devm_platform_ioremap_resource()
clk: axm5516: Convert to devm_platform_ioremap_resource()
clk: actions: Convert to devm_platform_ioremap_resource()
clk: cdce925: Remove redundant of_match_ptr()
drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init()
clk: Explicitly include correct DT includes