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| author | Martin K. Petersen <martin.petersen@oracle.com> | 2023-02-09 02:06:39 +0300 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2023-02-09 02:06:39 +0300 |
| commit | 67e6216d9c57bb5d404a0930e7863bf9fa3f164e (patch) | |
| tree | c68efc226f91c7e333e6cc613d1c97cd2905e00f | |
| parent | 49f262bc3c7ab90bdb3491a659b28c0b397d52e8 (diff) | |
| parent | b8c203891121bec7d0f4d544377bceb015a3efa5 (diff) | |
| download | linux-67e6216d9c57bb5d404a0930e7863bf9fa3f164e.tar.xz | |
Merge patch series "ufs: host: ufs-qcom: Add support for SM8550"
Abel Vesa <abel.vesa@linaro.org> says:
This patchset adds UFS HC support for the new Qualcomm SM8550 SoC.
Link: https://lore.kernel.org/r/20230119151406.4168685-1-abel.vesa@linaro.org
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
| -rw-r--r-- | Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 | ||||
| -rw-r--r-- | drivers/ufs/host/ufs-qcom.c | 8 | ||||
| -rw-r--r-- | drivers/ufs/host/ufs-qcom.h | 6 |
3 files changed, 13 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index 1f1d286749c0..6bc4c0b59d92 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -33,6 +33,7 @@ properties: - qcom,sm8250-ufshc - qcom,sm8350-ufshc - qcom,sm8450-ufshc + - qcom,sm8550-ufshc - const: qcom,ufshc - const: jedec,ufs-2.0 @@ -105,6 +106,7 @@ allOf: - qcom,sm8250-ufshc - qcom,sm8350-ufshc - qcom,sm8450-ufshc + - qcom,sm8550-ufshc then: properties: clocks: diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index eb66b5f6cf19..2ad03021c92f 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -224,6 +224,10 @@ static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) ufshcd_rmwl(host->hba, QUNIPRO_SEL, ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0, REG_UFS_CFG1); + + if (host->hw_ver.major == 0x05) + ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); + /* make sure above configuration is applied before we return */ mb(); } @@ -513,9 +517,9 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, mb(); } - if (update_link_startup_timer) { + if (update_link_startup_timer && host->hw_ver.major != 0x5) { ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100), - REG_UFS_PA_LINK_STARTUP_TIMER); + REG_UFS_CFG0); /* * make sure that this configuration is applied before * we return diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 8a503aa4f7ab..39e774254fb2 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -36,7 +36,8 @@ enum { REG_UFS_PA_ERR_CODE = 0xCC, /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */ REG_UFS_PARAM0 = 0xD0, - REG_UFS_PA_LINK_STARTUP_TIMER = 0xD8, + /* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */ + REG_UFS_CFG0 = 0xD8, REG_UFS_CFG1 = 0xDC, REG_UFS_CFG2 = 0xE0, REG_UFS_HW_VERSION = 0xE4, @@ -80,6 +81,9 @@ enum { #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x) #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) +/* bit definitions for REG_UFS_CFG0 register */ +#define QUNIPRO_G4_SEL BIT(5) + /* bit definitions for REG_UFS_CFG1 register */ #define QUNIPRO_SEL BIT(0) #define UFS_PHY_SOFT_RESET BIT(1) |