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| author | Dan Williams <dan.j.williams@intel.com> | 2021-09-04 05:21:06 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2021-09-07 21:39:02 +0300 |
| commit | 2b922a9d064f8e86b53b04f5819917b7a04142ed (patch) | |
| tree | da17ae8d4a1bbd57635cfe8f5060bc64fbcb50f1 | |
| parent | a01da6ca7d0ad66b6fa2dc4af0fc97ca8ba28b45 (diff) | |
| download | linux-2b922a9d064f8e86b53b04f5819917b7a04142ed.tar.xz | |
cxl/registers: Fix Documentation warning
Commit 0f06157e0135 ("cxl/core: Move register mapping infrastructure")
neglected to add a DOC header for the new drivers/core/regs.c file.
Reported-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/163072206675.2250120.3527179192933919995.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| -rw-r--r-- | Documentation/driver-api/cxl/memory-devices.rst | 2 | ||||
| -rw-r--r-- | drivers/cxl/core/regs.c | 15 |
2 files changed, 15 insertions, 2 deletions
diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst index df799cdf1c3f..50ebcda17ad0 100644 --- a/Documentation/driver-api/cxl/memory-devices.rst +++ b/Documentation/driver-api/cxl/memory-devices.rst @@ -43,7 +43,7 @@ CXL Core :doc: cxl pmem .. kernel-doc:: drivers/cxl/core/regs.c - :internal: + :doc: cxl registers External Interfaces =================== diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 8535a7b94f28..41de4a136ecd 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright(c) 2020 Intel Corporation. */ - #include <linux/io-64-nonatomic-lo-hi.h> #include <linux/device.h> #include <linux/slab.h> @@ -8,6 +7,20 @@ #include <cxlmem.h> /** + * DOC: cxl registers + * + * CXL device capabilities are enumerated by PCI DVSEC (Designated + * Vendor-specific) and / or descriptors provided by platform firmware. + * They can be defined as a set like the device and component registers + * mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and + * Extended Capabilities, or they can be individual capabilities + * appended to bridged and endpoint devices. + * + * Provide common infrastructure for enumerating and mapping these + * discrete capabilities. + */ + +/** * cxl_probe_component_regs() - Detect CXL Component register blocks * @dev: Host device of the @base mapping * @base: Mapping containing the HDM Decoder Capability Header |