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authorRichard Zhu <hongxing.zhu@nxp.com>2022-08-30 10:46:01 +0300
committerPhilipp Zabel <p.zabel@pengutronix.de>2022-08-30 17:28:48 +0300
commit051d9eb403887bb11852b7a4f744728a6a4b1b58 (patch)
treeb6ef19db506721a16ec0a6b4f3d50d096762444d
parent568035b01cfb107af8d2e4bd2fb9aea22cf5b868 (diff)
downloadlinux-051d9eb403887bb11852b7a4f744728a6a4b1b58.tar.xz
reset: imx7: Fix the iMX8MP PCIe PHY PERST support
On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1. But i.MX8MP has one inversed default value 1b'0 of PERST bit. And the PERST bit should be kept 1b'1 after power and clocks are stable. So fix the i.MX8MP PCIe PHY PERST support here. Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC") Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Marek Vasut <marex@denx.de> Tested-by: Richard Leitner <richard.leitner@skidata.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/1661845564-11373-5-git-send-email-hongxing.zhu@nxp.com
-rw-r--r--drivers/reset/reset-imx7.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 185a333df66c..d2408725eb2c 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -329,6 +329,7 @@ static int imx8mp_reset_set(struct reset_controller_dev *rcdev,
break;
case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
+ case IMX8MP_RESET_PCIEPHY_PERST:
value = assert ? 0 : bit;
break;
}