diff options
| author | Giuseppe CAVALLARO <peppe.cavallaro@st.com> | 2012-06-04 09:51:18 +0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2012-06-04 20:02:40 +0400 |
| commit | 9ec0db71af04f4560e27a3c2f5a0411ba3155198 (patch) | |
| tree | 9361a0d038f515409a1ac105f518967600652cbd | |
| parent | 3ab2cdd02850d53d32369e51c0ae2dbcf8a66e55 (diff) | |
| download | linux-9ec0db71af04f4560e27a3c2f5a0411ba3155198.tar.xz | |
net: icplus: fix interrupt mask
This patch fixes the interrupt mask for IC101 A/G devices
and now enables the link/speed/duplex interrupts.
This is done by setting the "INTR pin used" bit and cleaning
all the other bits in the Register 17.
Reported-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/phy/icplus.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c index 5ac46f5226f3..47f8e8939266 100644 --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c @@ -41,6 +41,8 @@ MODULE_LICENSE("GPL"); #define IP1001_APS_ON 11 /* IP1001 APS Mode bit */ #define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */ #define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */ +#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */ +#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED static int ip175c_config_init(struct phy_device *phydev) { @@ -136,6 +138,11 @@ static int ip1001_config_init(struct phy_device *phydev) if (c < 0) return c; + /* INTR pin used: speed/link/duplex will cause an interrupt */ + c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT); + if (c < 0) + return c; + if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { /* Additional delay (2ns) used to adjust RX clock phase * at RGMII interface */ |