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authorAdam Ford <aford173@gmail.com>2018-06-08 14:29:26 +0300
committerTony Lindgren <tony@atomide.com>2018-07-03 10:19:57 +0300
commit6bf5e3410f190374371d89a5816d1a4aaae66776 (patch)
tree9b797f7496c061482eeb5f5b7321df47ee3ae073
parent5e2e1c4fb3a6b98bd23ea5e0d5cd61714997a0c9 (diff)
downloadlinux-6bf5e3410f190374371d89a5816d1a4aaae66776.tar.xz
ARM: dts: am3517-som: Add WL127x Wifi
Certain models of the AM3517 SOM from Logic PD come with an integrated WL1271 WiFi. This patch enables the WiFi. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/boot/dts/am3517-evm.dts4
-rw-r--r--arch/arm/boot/dts/am3517-som.dtsi80
2 files changed, 80 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index 98aadb0f81c5..d7eb6ad76c29 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -220,10 +220,6 @@
cd-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio_127 */
};
-&mmc2 {
- status = "disabled";
-};
-
&mmc3 {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/am3517-som.dtsi b/arch/arm/boot/dts/am3517-som.dtsi
index 7ff7cd135dca..a2914067d613 100644
--- a/arch/arm/boot/dts/am3517-som.dtsi
+++ b/arch/arm/boot/dts/am3517-som.dtsi
@@ -14,6 +14,32 @@
cpu0-supply = <&vdd_core_reg>;
};
};
+
+ wl12xx_buffer: wl12xx_buf {
+ compatible = "regulator-fixed";
+ regulator-name = "wl1271_buf";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_buffer_pins>;
+ gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */
+ regulator-always-on;
+ vin-supply = <&vdd_1v8_reg>;
+ };
+
+ wl12xx_vmmc2: wl12xx_vmmc2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1271";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_wkup_pins>;
+ gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ regulator-always-on;
+ vin-supply = <&wl12xx_buffer>;
+ };
};
&gpmc {
@@ -121,8 +147,53 @@
};
};
+&mmc2 {
+ interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>;
+
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&wl12xx_vmmc2>;
+ non-removable;
+ bus-width = <4>;
+ cap-power-off-card;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1271";
+ reg = <2>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; /* gpio_170 */
+ ref-clock-frequency = <26000000>;
+ tcxo-clock-frequency = <26000000>;
+ };
+};
+
+
&omap3_pmx_core {
+ wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */
+ >;
+ };
+
+ mmc2_pins: pinmux_mmc2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */
+ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */
+ OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat0.mmc2_dat0 */
+ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat1.mmc2_dat1 */
+ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat2.mmc2_dat2 */
+ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat3.mmc2_dat3 */
+ OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */
+ OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */
+ OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */
+ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */
+ OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */
+ >;
+ };
+
rtc_pins: pinmux_rtc_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */
@@ -135,3 +206,12 @@
>;
};
};
+
+&omap3_pmx_wkup {
+
+ wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins {
+ pinctrl-single,pins = <
+ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
+ >;
+ };
+};