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| author | Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> | 2019-02-01 10:32:27 +0300 |
|---|---|---|
| committer | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2019-02-05 21:28:55 +0300 |
| commit | d6827015e671cd17871c9b7a0fabe06c044f7470 (patch) | |
| tree | 22d3f09e57b7067ce49ce02dee9e3c4b08e95a38 | |
| parent | 0e68eeea9894feeba2edf7ec63e4551b87f39621 (diff) | |
| download | linux-d6827015e671cd17871c9b7a0fabe06c044f7470.tar.xz | |
platform/x86: intel_pmc_core: Fix PCH IP name
For Cannonlake and Icelake, the IP name for Res_6 should be SPF i.e.
South Port F. No functional change is intended other than just renaming
the IP appropriately.
Cc: "David E. Box" <david.e.box@intel.com>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Fixes: 291101f6a735 ("platform/x86: intel_pmc_core: Add CannonLake PCH support")
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| -rw-r--r-- | drivers/platform/x86/intel_pmc_core.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 9f143cdbea05..80936e6bdc61 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -203,7 +203,7 @@ static const struct pmc_bit_map cnp_pfear_map[] = { {"CNVI", BIT(3)}, {"UFS0", BIT(4)}, {"EMMC", BIT(5)}, - {"Res_6", BIT(6)}, + {"SPF", BIT(6)}, {"SBR6", BIT(7)}, {"SBR7", BIT(0)}, |