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| author | Changbin Du <changbin.du@intel.com> | 2017-08-15 08:20:51 +0300 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2017-09-08 09:21:13 +0300 |
| commit | 5d5fe176155e6cfa4a53accb90e4010baa5266d0 (patch) | |
| tree | 87f8eeccc8b7a1ce37cbbd51a10b9690d2c77319 | |
| parent | bb9d2d050503c69695557b8b741276686ca2a396 (diff) | |
| download | linux-5d5fe176155e6cfa4a53accb90e4010baa5266d0.tar.xz | |
drm/i915/kvmgt: Sanitize PCI bar emulation
For PCI, 64bit bar consumes two BAR registers, but this doesn't mean
both of two BAR are valid. Actually the second BAR is regarded as
reserved in this case. So we shouldn't emulate the second BAR.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/kvmgt.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c index 83e88c70272a..9201db0892f1 100644 --- a/drivers/gpu/drm/i915/gvt/kvmgt.c +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c @@ -661,7 +661,6 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf, buf, count); break; case VFIO_PCI_BAR0_REGION_INDEX: - case VFIO_PCI_BAR1_REGION_INDEX: if (is_write) { uint64_t bar0_start = intel_vgpu_get_bar0_addr(vgpu); @@ -674,6 +673,7 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf, bar0_start + pos, buf, count); } break; + case VFIO_PCI_BAR1_REGION_INDEX: case VFIO_PCI_BAR2_REGION_INDEX: case VFIO_PCI_BAR3_REGION_INDEX: case VFIO_PCI_BAR4_REGION_INDEX: |