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| author | Aapo Vienamo <avienamo@nvidia.com> | 2018-08-10 21:13:58 +0300 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2018-10-08 12:40:43 +0300 |
| commit | 3ecea59d27f87b0fe9ab09b0ce8262f5355ec243 (patch) | |
| tree | 22f7ec40b4f69c6711ee5da1c792f115694717b0 | |
| parent | 2ad50051575c6556822c69a9053142462f2e8375 (diff) | |
| download | linux-3ecea59d27f87b0fe9ab09b0ce8262f5355ec243.tar.xz | |
dt-bindings: mmc: Add DQS trim value to Tegra SDHCI
Document HS400 DQS trim value device tree property.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index edecf97231b9..32b4b4e41923 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -71,6 +71,7 @@ Optional properties for Tegra210 and Tegra186: trimmer value for non-tunable modes. - nvidia,default-trim : Specify the default outbound clock trimmer value. +- nvidia,dqs-trim : Specify DQS trim value for HS400 timing Notes on the pad calibration pull up and pulldown offset values: - The property values are drive codes which are programmed into the @@ -87,6 +88,9 @@ Optional properties for Tegra210 and Tegra186: - The values are programmed to the Vendor Clock Control Register. Please refer to the reference manual of the SoC for correct values. + - The DQS trim values are only used on controllers which support + HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports + HS400. Example: sdhci@700b0000 { |