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| author | Mark Brown <broonie@kernel.org> | 2022-07-19 20:43:27 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-07-19 20:43:27 +0300 |
| commit | 09f852894553ac72e25a6b6012a1f5ff34be5be5 (patch) | |
| tree | 4de9fa51e64bc9c8a7118aa53271cfd3cc9ce222 | |
| parent | 2d86cef353b8f3d20b16f8c5615742fd6938c801 (diff) | |
| parent | 99bad468846f7a255dcfc95454401c83ae02e89b (diff) | |
| download | linux-09f852894553ac72e25a6b6012a1f5ff34be5be5.tar.xz | |
ASoC: SOF: mediatek: fix boot sequences
Merge series from Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>:
Changes to DSP_RESET_SW need extra care.
| -rw-r--r-- | sound/soc/sof/mediatek/mt8195/mt8195-loader.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/sound/soc/sof/mediatek/mt8195/mt8195-loader.c b/sound/soc/sof/mediatek/mt8195/mt8195-loader.c index ed18d6379e92..4be99ff4ebd3 100644 --- a/sound/soc/sof/mediatek/mt8195/mt8195-loader.c +++ b/sound/soc/sof/mediatek/mt8195/mt8195-loader.c @@ -21,7 +21,7 @@ void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr) /* pull high StatVectorSel to use AltResetVec (set bit4 to 1) */ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW, - DSP_RESET_SW, DSP_RESET_SW); + STATVECTOR_SEL, STATVECTOR_SEL); /* toggle DReset & BReset */ /* pull high DReset & BReset */ @@ -29,6 +29,9 @@ void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr) ADSP_BRESET_SW | ADSP_DRESET_SW, ADSP_BRESET_SW | ADSP_DRESET_SW); + /* delay 10 DSP cycles at 26M about 1us by IP vendor's suggestion */ + udelay(1); + /* pull low DReset & BReset */ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW, ADSP_BRESET_SW | ADSP_DRESET_SW, @@ -46,11 +49,13 @@ void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr) void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev) { - /* Clear to 0 firstly */ - snd_sof_dsp_write(sdev, DSP_REG_BAR, DSP_RESET_SW, 0x0); - /* RUN_STALL pull high again to reset */ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW, ADSP_RUNSTALL, ADSP_RUNSTALL); + + /* pull high DReset & BReset */ + snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW, + ADSP_BRESET_SW | ADSP_DRESET_SW, + ADSP_BRESET_SW | ADSP_DRESET_SW); } |