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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2013-06-18 20:20:32 +0400 |
|---|---|---|
| committer | Wim Van Sebroeck <wim@iguana.be> | 2013-07-12 00:18:30 +0400 |
| commit | 6910ceb5cababfefffc4ddc58a085a71c0ab9f22 (patch) | |
| tree | e80d0356a22f65ff39be283561d5e3ae8e073803 | |
| parent | fa142ff5b3f67fab01f3d02a501b041b4266afdd (diff) | |
| download | linux-6910ceb5cababfefffc4ddc58a085a71c0ab9f22.tar.xz | |
Watchdog: fix clearing of the watchdog interrupt
The bits in BRIDGE_CAUSE are documented as RW0C - read, write 0 to
clear. If we read the register, mask off the watchdog bit, and
write it back, we're actually clearing every interrupt which wasn't
pending at the time we read the register - and that is racy.
Fix this to only write ~WATCHDOG_BIT to the register, which means
we write as zero only the watchdog bit.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| -rw-r--r-- | drivers/watchdog/orion_wdt.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c index 4074244c7183..4ea5fcccac02 100644 --- a/drivers/watchdog/orion_wdt.c +++ b/drivers/watchdog/orion_wdt.c @@ -70,9 +70,7 @@ static int orion_wdt_start(struct watchdog_device *wdt_dev) writel(wdt_tclk * wdt_dev->timeout, wdt_reg + WDT_VAL); /* Clear watchdog timer interrupt */ - reg = readl(BRIDGE_CAUSE); - reg &= ~WDT_INT_REQ; - writel(reg, BRIDGE_CAUSE); + writel(~WDT_INT_REQ, BRIDGE_CAUSE); /* Enable watchdog timer */ reg = readl(wdt_reg + TIMER_CTRL); |