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| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2018-11-04 13:49:52 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-11-11 22:36:16 +0300 |
| commit | 301c15be69afa98b188545d83422245c01f69743 (patch) | |
| tree | c283d7c78208504e0c6355e435bfa8b6e3c442db | |
| parent | a4b2eb912bb13c3c55d2389ee7e954468d0df052 (diff) | |
| download | linux-301c15be69afa98b188545d83422245c01f69743.tar.xz | |
staging: mt7621-pci: rewrite hardcoded code for enabling ports
There are some hardcoded values in the process for enabling and
disabling some stuff inside 'mt7621_pcie_enable_ports' function.
Create some preprocessor definitions to make code more readable.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 604b2871a336..0e898a4b7b63 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -80,6 +80,13 @@ #define RALINK_PCI_STATUS 0x0050 /* Some definition values */ +#define PCIE_REVISION_ID BIT(0) +#define PCIE_CLASS_CODE (0x60400 << 8) +#define PCIE_BAR_MAP_MAX GENMASK(30, 16) +#define PCIE_BAR_ENABLE BIT(0) +#define PCIE_PORT_INT_EN(x) BIT(20 + (x)) +#define PCIE_PORT_CLK_EN(x) BIT(24 + (x)) + #define RALINK_PCI_IO_MAP_BASE 0x1e160000 #define MEMORY_BASE 0x0 @@ -584,13 +591,13 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port) if ((pcie_port_read(port, RALINK_PCI_STATUS) & 0x1) == 0) { dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot); reset_control_assert(port->pcie_rst); - rt_sysc_m32(BIT(24 + slot), 0, RALINK_CLKCFG1); + rt_sysc_m32(PCIE_PORT_CLK_EN(slot), 0, RALINK_CLKCFG1); port->enabled = false; } else { port->enabled = true; - val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR); /* enable pcie interrupt */ - val |= BIT(20 + slot); + val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR); + val |= PCIE_PORT_INT_EN(slot); pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR); } @@ -633,12 +640,14 @@ static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie) offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT); if (port->enabled) { - /* open 7FFF:2G; ENABLE */ - pcie_write(pcie, 0x7FFF0001, + /* map 2G DDR region */ + pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, offset + RALINK_PCI_BAR0SETUP_ADDR); pcie_write(pcie, MEMORY_BASE, offset + RALINK_PCI_IMBASEBAR0_ADDR); - pcie_write(pcie, 0x06040001, offset + RALINK_PCI_CLASS); + /* configure class code and revision ID */ + pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID, + offset + RALINK_PCI_CLASS); dev_info(dev, "PCIE%d enabled\n", slot); num_slots_enabled++; } |