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authorGeert Uytterhoeven <geert+renesas@glider.be>2018-05-07 16:24:48 +0300
committerSimon Horman <horms+renesas@verge.net.au>2018-05-14 17:40:40 +0300
commitc02cc235a215e9c518f98da25753b9e02bb7144f (patch)
tree145a77ff41d8f2ead558aa30623aaa66cf0611fe
parent7207b94754b6f503b278b5b200faaf662ffa1da8 (diff)
downloadlinux-c02cc235a215e9c518f98da25753b9e02bb7144f.tar.xz
ARM: dts: r7s72100: Correct watchdog timer interrupt type
According to table 7.3 ("List of Interrupt IDs") in the RZ/A1H Hardware User's Manual rev. 3.00, the watchdog timer interrupt is a level interrupt. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm/boot/dts/r7s72100.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 4a1aade0e751..c7b3dca6d81c 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -387,7 +387,7 @@
wdt: watchdog@fcfe0000 {
compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
reg = <0xfcfe0000 0x6>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&p0_clk>;
};