diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2020-02-26 19:30:54 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2020-02-27 22:14:33 +0300 |
| commit | 041be4811f981dca9db1bcd5ac89d0243ef134f9 (patch) | |
| tree | f6109ea6f7625fd9894e43aae1ae24549d97c3dc | |
| parent | 945fa3bc9dfd0f09fa8cf13602b231ae0a898fff (diff) | |
| download | linux-041be4811f981dca9db1bcd5ac89d0243ef134f9.tar.xz | |
drm/i915: Set up PIPE_MISC truncate bit on tgl+
Looks like the pipe rounding mode bit has moved from PIPE_CHICKEN to
PIPE_MISC on tgl. Frob the new location.
Bspec does still document the old bits as well, so I left the code
for them as is until we get clarification from the hw folks on
whether the old bits still do something useful.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200226163054.9509-1-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ae14b68a9e78..ab2e2454f038 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10138,6 +10138,9 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) BIT(PLANE_CURSOR))) == 0) val |= PIPEMISC_HDR_MODE_PRECISION; + if (INTEL_GEN(dev_priv) >= 12) + val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; + intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b2738145db65..72de9591f77f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5879,6 +5879,7 @@ enum { #define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */ #define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */ #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11) +#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ #define PIPEMISC_DITHER_BPC_MASK (7 << 5) #define PIPEMISC_DITHER_8_BPC (0 << 5) #define PIPEMISC_DITHER_10_BPC (1 << 5) |