diff options
| author | Alan Cox <alan@linux.intel.com> | 2012-04-25 17:38:47 +0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2012-04-27 12:24:36 +0400 |
| commit | 398b4706896ee8d8e72f215a089b58637add5c92 (patch) | |
| tree | c934cc84af9652727a16771ad4cea078d901c0be | |
| parent | ae0a246aef0d185db2947912fe9cf7dae1d91b7a (diff) | |
| download | linux-398b4706896ee8d8e72f215a089b58637add5c92.tar.xz | |
gma500: Set the mapping mask
Some boards such as the Intel D2700MUD allow you to have over 4GB of RAM.
The GTT on the PVR based devices is 32bit however. Hugh Dickins points out
that we should therefore be setting the mapping gfp mask.
This is not the whole fix for the problem. Some further shmem patches will
be needed to deal with the corner cases.
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
| -rw-r--r-- | drivers/gpu/drm/gma500/gem.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/gma500/gtt.c | 4 |
2 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/gma500/gem.c b/drivers/gpu/drm/gma500/gem.c index 9fbb86868e2e..fc7d144bc2d3 100644 --- a/drivers/gpu/drm/gma500/gem.c +++ b/drivers/gpu/drm/gma500/gem.c @@ -124,6 +124,8 @@ static int psb_gem_create(struct drm_file *file, dev_err(dev->dev, "GEM init failed for %lld\n", size); return -ENOMEM; } + /* Limit the object to 32bit mappings */ + mapping_set_gfp_mask(r->gem.filp->f_mapping, GFP_KERNEL | __GFP_DMA32); /* Give the object a handle so we can carry it more easily */ ret = drm_gem_handle_create(file, &r->gem, &handle); if (ret) { diff --git a/drivers/gpu/drm/gma500/gtt.c b/drivers/gpu/drm/gma500/gtt.c index db2e823e8951..54e5c9e1e6fa 100644 --- a/drivers/gpu/drm/gma500/gtt.c +++ b/drivers/gpu/drm/gma500/gtt.c @@ -39,6 +39,10 @@ static inline uint32_t psb_gtt_mask_pte(uint32_t pfn, int type) { uint32_t mask = PSB_PTE_VALID; + /* Ensure we explode rather than put an invalid low mapping of + a high mapping page into the gtt */ + BUG_ON(pfn & ~(0xFFFFFFFF >> PAGE_SHIFT)); + if (type & PSB_MMU_CACHED_MEMORY) mask |= PSB_PTE_CACHED; if (type & PSB_MMU_RO_MEMORY) |