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| author | Chen-Yu Tsai <wens@csie.org> | 2015-10-14 19:32:21 +0300 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2015-10-16 09:44:04 +0300 |
| commit | 6c067963f6e128bdca1e4db947f1a0e8ad2bd846 (patch) | |
| tree | 397e860902672899a5b6bd1f860d4cca83109aee | |
| parent | d92ff4228c57cf781170562fda431163e9f72760 (diff) | |
| download | linux-6c067963f6e128bdca1e4db947f1a0e8ad2bd846.tar.xz | |
ARM: dts: sun8i: Add NMI interrupt controller node
The NMI interrupt controller is in charge of the NMI pin exposed by
the SoC to the PMIC. The PMIC signals interrupts through this.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| -rw-r--r-- | arch/arm/boot/dts/sun8i-a23-a33.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 828aaf52c342..a1e3acd325f4 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -579,6 +579,14 @@ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; + nmi_intc: interrupt-controller@01f00c0c { + compatible = "allwinner,sun6i-a31-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01f00c0c 0x38>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + }; + prcm@01f01400 { compatible = "allwinner,sun8i-a23-prcm"; reg = <0x01f01400 0x200>; |