diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2017-05-22 09:25:47 +0300 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-06-07 16:32:16 +0300 |
| commit | faea8b0e33c2e6a276d34a755258bb2176553616 (patch) | |
| tree | 80a71a679631aca7ecc30b114da601f46ef9fbbf | |
| parent | 05359be1176bd097af9e7e833ff0317c55c5a86c (diff) | |
| download | linux-faea8b0e33c2e6a276d34a755258bb2176553616.tar.xz | |
clk: sunxi-ng: a83t: Fix PLL lock status register offset
The offset for the PLL lock status register was incorrectly set to
0x208, which actually points to an unused register. The correct
register offset is 0x20c.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c index 4a201a7e03b8..a9c5cc87d9d0 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c @@ -28,7 +28,7 @@ #include "ccu-sun8i-a83t.h" -#define CCU_SUN8I_A83T_LOCK_REG 0x208 +#define CCU_SUN8I_A83T_LOCK_REG 0x20c /* * The CPU PLLs are actually NP clocks, with P being /1 or /4. However |