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authorAnson Huang <Anson.Huang@nxp.com>2018-09-14 05:59:21 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2020-01-12 14:17:24 +0300
commit40b049d085f3869bb2f4dfda2ce922a9e14f7cdc (patch)
tree12558eb298c3d503e278a78c01ed07c811cf6f9c
parent4ef576e99d29a6c58a3cc9016f052629f040f111 (diff)
downloadlinux-40b049d085f3869bb2f4dfda2ce922a9e14f7cdc.tar.xz
ARM: dts: imx6ul: use nvmem-cells for cpu speed grading
commit 92f0eb08c66a73594cf200e65689e767f7f0da5e upstream. On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock needs to be enabled first, so use the nvmem-cells binding instead. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Cc: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Cc: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--arch/arm/boot/dts/imx6ul.dtsi6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 50834a43e5fb..adecd6e08468 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -87,6 +87,8 @@
"pll1_sys";
arm-supply = <&reg_arm>;
soc-supply = <&reg_soc>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
};
@@ -930,6 +932,10 @@
tempmon_temp_grade: temp-grade@20 {
reg = <0x20 4>;
};
+
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
};
lcdif: lcdif@21c8000 {