diff options
| author | Gabor Juhos <juhosg@openwrt.org> | 2013-02-15 17:38:19 +0400 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2013-02-19 12:36:26 +0400 |
| commit | f818ca3e6894d4a630a1ecc673c91df8fb6f6898 (patch) | |
| tree | 94cc0d1fcc616ab57f94fd281fde617a79f98cf9 | |
| parent | 53330332f176eaa9567481c69bbad8b2176b4eb5 (diff) | |
| download | linux-f818ca3e6894d4a630a1ecc673c91df8fb6f6898.tar.xz | |
MIPS: ath79: add GPIO setup code for the QCA955X SoCs
The existing code can handle the GPIO controller of
the QCA955x SoCs. Add a minimal glue code to make it
working.
Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4947/
Signed-off-by: John Crispin <blogic@openwrt.org>
| -rw-r--r-- | arch/mips/ath79/gpio.c | 4 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 |
2 files changed, 4 insertions, 1 deletions
diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c index b7ed207e94a1..8d025b028bb1 100644 --- a/arch/mips/ath79/gpio.c +++ b/arch/mips/ath79/gpio.c @@ -194,12 +194,14 @@ void __init ath79_gpio_init(void) ath79_gpio_count = AR933X_GPIO_COUNT; else if (soc_is_ar934x()) ath79_gpio_count = AR934X_GPIO_COUNT; + else if (soc_is_qca955x()) + ath79_gpio_count = QCA955X_GPIO_COUNT; else BUG(); ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); ath79_gpio_chip.ngpio = ath79_gpio_count; - if (soc_is_ar934x()) { + if (soc_is_ar934x() || soc_is_qca955x()) { ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; } diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 8782d8b097a3..4868ed5c149b 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -510,6 +510,7 @@ #define AR913X_GPIO_COUNT 22 #define AR933X_GPIO_COUNT 30 #define AR934X_GPIO_COUNT 23 +#define QCA955X_GPIO_COUNT 24 /* * SRIF block |