diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-10-09 11:08:04 +0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-10-09 11:08:04 +0400 |
| commit | de390bba797aa9a554bc1769b6a8771605854d79 (patch) | |
| tree | ce95610d4a70ec0a7307a30cfd1a66fdf0c901ab | |
| parent | 50e0d10232db05c6776afcf6098459bff47e8b15 (diff) | |
| parent | 382fc33b4a04e2dde89b4c69a6880e0c7d9761e2 (diff) | |
| download | linux-de390bba797aa9a554bc1769b6a8771605854d79.tar.xz | |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS update from Ralf Baechle:
"This is the MIPS update for 3.7.
A fair chunk of them are platform updates to the Cavium Octeon SOC
(which involves machine generated header files of considerable size),
Atheros ATH79xx, RMI aka Netlogic aka Broadcom XLP, Broadcom BCM63xx
platforms.
Support for the commercial MIPS simulator MIPSsim has been removed as
MIPS Technologies is shifting away from this product and Qemu is
offering various more powerful platforms. The generic MIPS code can
now also probe for no-execute / write-only TLB features implemented
without the full SmartMIPS extension as permitted by the latest MIPS
processor architecture. Lots of small changes to generic code."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (78 commits)
MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs
MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x
MIPS: BCM63XX: Properly handle mac address octet overflow
MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user.
MIPS: Replace `-' in defconfig filename wth `_' for consistency.
MIPS: Wire kcmp syscall.
MIPS: MIPSsim: Remove the MIPSsim platform.
MIPS: NOTIFY_RESUME is not needed in TIF masks
MIPS: Merge the identical "return from syscall" per-ABI code
MIPS: Unobfuscate _TIF..._MASK
MIPS: Prevent hitting do_notify_resume() with !user_mode(regs).
MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.
MIPS: Add base architecture support for RI and XI.
MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.
MIPS: uasm: Add INS and EXT instructions.
MIPS: Avoid pipeline stalls on some MIPS32R2 cores.
MIPS: Make VPE count to be one-based.
MIPS: Add new end of interrupt functionality for GIC.
MIPS: Add EIC support for GIC.
MIPS: Code clean-ups for the GIC.
...
175 files changed, 50942 insertions, 3012 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt new file mode 100644 index 000000000000..daa768956069 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt @@ -0,0 +1,83 @@ +Lantiq FALCON pinmux controller + +Required properties: +- compatible: "lantiq,pinctrl-falcon" +- reg: Should contain the physical address and length of the gpio/pinmux + register range + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Lantiq's pin configuration nodes act as a container for an abitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those group(s), and two pin configuration parameters: +pull-up and open-drain + +The name of each subnode is not important as long as it is unique; all subnodes +should be enumerated and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +We support 2 types of nodes. + +Definition of mux function groups: + +Required subnode-properties: +- lantiq,groups : An array of strings. Each string contains the name of a group. + Valid values for these names are listed below. +- lantiq,function: A string containing the name of the function to mux to the + group. Valid values for function names are listed below. + +Valid values for group and function names: + + mux groups: + por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c, + jtag, slic, pcm, asc1 + + functions: + rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm + + +Definition of pin configurations: + +Required subnode-properties: +- lantiq,pins : An array of strings. Each string contains the name of a pin. + Valid values for these names are listed below. + +Optional subnode-properties: +- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. + 0: none, 1: down +- lantiq,drive-current: Boolean, enables drive-current +- lantiq,slew-rate: Boolean, enables slew-rate + +Example: + pinmux0 { + compatible = "lantiq,pinctrl-falcon"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + asc0 { + lantiq,groups = "asc0"; + lantiq,function = "asc"; + }; + ntr { + lantiq,groups = "ntr8k"; + lantiq,function = "ntr"; + }; + i2c { + lantiq,groups = "i2c"; + lantiq,function = "i2c"; + }; + hrst { + lantiq,groups = "hrst"; + lantiq,function = "rst"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt new file mode 100644 index 000000000000..b5469db1d7ad --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt @@ -0,0 +1,97 @@ +Lantiq XWAY pinmux controller + +Required properties: +- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9" +- reg: Should contain the physical address and length of the gpio/pinmux + register range + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Lantiq's pin configuration nodes act as a container for an abitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those group(s), and two pin configuration parameters: +pull-up and open-drain + +The name of each subnode is not important as long as it is unique; all subnodes +should be enumerated and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +We support 2 types of nodes. + +Definition of mux function groups: + +Required subnode-properties: +- lantiq,groups : An array of strings. Each string contains the name of a group. + Valid values for these names are listed below. +- lantiq,function: A string containing the name of the function to mux to the + group. Valid values for function names are listed below. + +Valid values for group and function names: + + mux groups: + exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1, + ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3, + spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2, + gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2, + req3 + + additional mux groups (XR9 only): + mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4 + + functions: + spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio + + + +Definition of pin configurations: + +Required subnode-properties: +- lantiq,pins : An array of strings. Each string contains the name of a pin. + Valid values for these names are listed below. + +Optional subnode-properties: +- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. + 0: none, 1: down, 2: up. +- lantiq,open-drain: Boolean, enables open-drain on the defined pin. + +Valid values for XWAY pin names: + Pinconf pins can be referenced via the names io0-io31. + +Valid values for XR9 pin names: + Pinconf pins can be referenced via the names io0-io55. + +Example: + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xway"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + + state_default: pinmux { + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + }; + pci { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + }; + conf_out { + lantiq,pins = "io4", "io5", "io6"; /* stp */ + lantiq,open-drain; + lantiq,pull = <0>; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/spi/spi-octeon.txt b/Documentation/devicetree/bindings/spi/spi-octeon.txt new file mode 100644 index 000000000000..431add192342 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-octeon.txt @@ -0,0 +1,33 @@ +Cavium, Inc. OCTEON SOC SPI master controller. + +Required properties: +- compatible : "cavium,octeon-3010-spi" +- reg : The register base for the controller. +- interrupts : One interrupt, used by the controller. +- #address-cells : <1>, as required by generic SPI binding. +- #size-cells : <0>, also as required by generic SPI binding. + +Child nodes as per the generic SPI binding. + +Example: + + spi@1070000001000 { + compatible = "cavium,octeon-3010-spi"; + reg = <0x10700 0x00001000 0x0 0x100>; + interrupts = <0 58>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "st,m95256", "atmel,at25"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpha; + spi-cpol; + + pagesize = <64>; + size = <32768>; + address-width = <16>; + }; + }; + diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index d64786d5e2f3..91b9d69f465c 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -15,8 +15,8 @@ platforms += lantiq platforms += lasat platforms += loongson platforms += loongson1 -platforms += mipssim platforms += mti-malta +platforms += mti-sead3 platforms += netlogic platforms += pmc-sierra platforms += pnx833x diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index faf65286574e..4cd538b42a3f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -242,6 +242,8 @@ config LANTIQ select HAVE_MACH_CLKDEV select CLKDEV_LOOKUP select USE_OF + select PINCTRL + select PINCTRL_LANTIQ config LASAT bool "LASAT Networks platforms" @@ -320,24 +322,35 @@ config MIPS_MALTA This enables support for the MIPS Technologies Malta evaluation board. -config MIPS_SIM - bool 'MIPS simulator (MIPSsim)' +config MIPS_SEAD3 + bool "MIPS SEAD3 board" + select BOOT_ELF32 + select BOOT_RAW select CEVT_R4K select CSRC_R4K + select CPU_MIPSR2_IRQ_VI + select CPU_MIPSR2_IRQ_EI select DMA_NONCOHERENT - select SYS_HAS_EARLY_PRINTK select IRQ_CPU - select BOOT_RAW + select IRQ_GIC + select MIPS_BOARDS_GEN + select MIPS_CPU_SCACHE + select MIPS_MSC select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_CPU_MIPS64_R1 select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_MULTITHREADING select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_SMARTMIPS + select USB_ARCH_HAS_EHCI + select USB_EHCI_BIG_ENDIAN_DESC + select USB_EHCI_BIG_ENDIAN_MMIO help - This option enables support for MIPS Technologies MIPSsim software - emulator. + This enables support for the MIPS Technologies SEAD3 evaluation + board. config NEC_MARKEINS bool "NEC EMMA2RH Mark-eins board" @@ -831,6 +844,7 @@ config NLM_XLP_BOARD select ZONE_DMA if 64BIT select SYNC_R4K select SYS_HAS_EARLY_PRINTK + select USE_OF help This board is based on Netlogic XLP Processor. Say Y here if you have a XLP based board. @@ -1749,7 +1763,6 @@ config HARDWARE_WATCHPOINTS menu "Kernel type" choice - prompt "Kernel code model" help You should only select this option if you have a workload that @@ -1880,6 +1893,18 @@ config SIBYTE_DMA_PAGEOPS config CPU_HAS_PREFETCH bool +config CPU_GENERIC_DUMP_TLB + bool + default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX) + +config CPU_R4K_FPU + bool + default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON) + +config CPU_R4K_CACHE_TLB + bool + default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON) + choice prompt "MIPS MT options" @@ -1955,7 +1980,6 @@ config SCHED_SMT config SYS_SUPPORTS_SCHED_SMT bool - config SYS_SUPPORTS_MULTITHREADING bool @@ -2360,12 +2384,10 @@ config SECCOMP If unsure, say Y. Only embedded should say N here. config USE_OF - bool "Flattened Device Tree support" + bool select OF select OF_EARLY_FLATTREE select IRQ_DOMAIN - help - Include support for flattened device tree machine descriptions. endmenu diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c index b91ad3efe29e..579f452c0b45 100644 --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c @@ -17,6 +17,8 @@ #include <linux/err.h> #include <linux/clk.h> +#include <asm/div64.h> + #include <asm/mach-ath79/ath79.h> #include <asm/mach-ath79/ar71xx_regs.h> #include "common.h" @@ -166,11 +168,34 @@ static void __init ar933x_clocks_init(void) ath79_uart_clk.rate = ath79_ref_clk.rate; } +static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, + u32 frac, u32 out_div) +{ + u64 t; + u32 ret; + + t = ath79_ref_clk.rate; + t *= nint; + do_div(t, ref_div); + ret = t; + + t = ath79_ref_clk.rate; + t *= nfrac; + do_div(t, ref_div * frac); + ret += t; + + ret /= (1 << out_div); + return ret; +} + static void __init ar934x_clocks_init(void) { - u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; + u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; u32 cpu_pll, ddr_pll; u32 bootstrap; + void __iomem *dpll_base; + + dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE); bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) @@ -178,33 +203,59 @@ static void __init ar934x_clocks_init(void) else ath79_ref_clk.rate = 25 * 1000 * 1000; - pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); - out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; - ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & - AR934X_PLL_CPU_CONFIG_REFDIV_MASK; - nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & - AR934X_PLL_CPU_CONFIG_NINT_MASK; - frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & - AR934X_PLL_CPU_CONFIG_NFRAC_MASK; - - cpu_pll = nint * ath79_ref_clk.rate / ref_div; - cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); - cpu_pll /= (1 << out_div); - - pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); - out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & - AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; - ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & - AR934X_PLL_DDR_CONFIG_REFDIV_MASK; - nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & - AR934X_PLL_DDR_CONFIG_NINT_MASK; - frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & - AR934X_PLL_DDR_CONFIG_NFRAC_MASK; - - ddr_pll = nint * ath79_ref_clk.rate / ref_div; - ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); - ddr_pll /= (1 << out_div); + pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); + if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { + out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & + AR934X_SRIF_DPLL2_OUTDIV_MASK; + pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); + nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & + AR934X_SRIF_DPLL1_NINT_MASK; + nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; + ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & + AR934X_SRIF_DPLL1_REFDIV_MASK; + frac = 1 << 18; + } else { + pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); + out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & + AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; + ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & + AR934X_PLL_CPU_CONFIG_REFDIV_MASK; + nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & + AR934X_PLL_CPU_CONFIG_NINT_MASK; + nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & + AR934X_PLL_CPU_CONFIG_NFRAC_MASK; + frac = 1 << 6; + } + + cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, + nfrac, frac, out_div); + + pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); + if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { + out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & + AR934X_SRIF_DPLL2_OUTDIV_MASK; + pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); + nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & + AR934X_SRIF_DPLL1_NINT_MASK; + nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; + ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & + AR934X_SRIF_DPLL1_REFDIV_MASK; + frac = 1 << 18; + } else { + pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); + out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & + AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; + ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & + AR934X_PLL_DDR_CONFIG_REFDIV_MASK; + nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & + AR934X_PLL_DDR_CONFIG_NINT_MASK; + nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & + AR934X_PLL_DDR_CONFIG_NFRAC_MASK; + frac = 1 << 10; + } + + ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, + nfrac, frac, out_div); clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); @@ -240,6 +291,8 @@ static void __init ar934x_clocks_init(void) ath79_wdt_clk.rate = ath79_ref_clk.rate; ath79_uart_clk.rate = ath79_ref_clk.rate; + + iounmap(dpll_base); } void __init ath79_clocks_init(void) diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c index b2a2311ec85b..072bb9be2304 100644 --- a/arch/mips/ath79/dev-usb.c +++ b/arch/mips/ath79/dev-usb.c @@ -25,17 +25,7 @@ #include "common.h" #include "dev-usb.h" -static struct resource ath79_ohci_resources[] = { - [0] = { - /* .start and .end fields are filled dynamically */ - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = ATH79_MISC_IRQ_OHCI, - .end = ATH79_MISC_IRQ_OHCI, - .flags = IORESOURCE_IRQ, - }, -}; +static struct resource ath79_ohci_resources[2]; static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32); @@ -54,17 +44,7 @@ static struct platform_device ath79_ohci_device = { }, }; -static struct resource ath79_ehci_resources[] = { - [0] = { - /* .start and .end fields are filled dynamically */ - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = ATH79_CPU_IRQ_USB, - .end = ATH79_CPU_IRQ_USB, - .flags = IORESOURCE_IRQ, - }, -}; +static struct resource ath79_ehci_resources[2]; static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32); @@ -90,6 +70,20 @@ static struct platform_device ath79_ehci_device = { }, }; +static void __init ath79_usb_init_resource(struct resource res[2], + unsigned long base, + unsigned long size, + int irq) +{ + res[0].flags = IORESOURCE_MEM; + res[0].start = base; + res[0].end = base + size - 1; + + res[1].flags = IORESOURCE_IRQ; + res[1].start = irq; + res[1].end = irq; +} + #define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \ AR71XX_RESET_USB_PHY | \ AR71XX_RESET_USB_OHCI_DLL) @@ -114,12 +108,12 @@ static void __init ath79_usb_setup(void) mdelay(900); - ath79_ohci_resources[0].start = AR71XX_OHCI_BASE; - ath79_ohci_resources[0].end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1; + ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE, + AR71XX_OHCI_SIZE, ATH79_MISC_IRQ_OHCI); platform_device_register(&ath79_ohci_device); - ath79_ehci_resources[0].start = AR71XX_EHCI_BASE; - ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1; + ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE, + AR71XX_EHCI_SIZE, ATH79_CPU_IRQ_USB); ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1; platform_device_register(&ath79_ehci_device); } @@ -143,10 +137,8 @@ static void __init ar7240_usb_setup(void) iounmap(usb_ctrl_base); - ath79_ohci_resources[0].start = AR7240_OHCI_BASE; - ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1; - ath79_ohci_resources[1].start = ATH79_CPU_IRQ_USB; - ath79_ohci_resources[1].end = ATH79_CPU_IRQ_USB; + ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE, + AR7240_OHCI_SIZE, ATH79_CPU_IRQ_USB); platform_device_register(&ath79_ohci_device); } @@ -161,8 +153,8 @@ static void __init ar724x_usb_setup(void) ath79_device_reset_clear(AR724X_RESET_USB_PHY); mdelay(10); - ath79_ehci_resources[0].start = AR724X_EHCI_BASE; - ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1; + ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE, + AR724X_EHCI_SIZE, ATH79_CPU_IRQ_USB); ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } @@ -178,8 +170,8 @@ static void __init ar913x_usb_setup(void) ath79_device_reset_clear(AR913X_RESET_USB_PHY); mdelay(10); - ath79_ehci_resources[0].start = AR913X_EHCI_BASE; - ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1; + ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE, + AR913X_EHCI_SIZE, ATH79_CPU_IRQ_USB); ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } @@ -195,8 +187,34 @@ static void __init ar933x_usb_setup(void) ath79_device_reset_clear(AR933X_RESET_USB_PHY); mdelay(10); - ath79_ehci_resources[0].start = AR933X_EHCI_BASE; - ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1; + ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE, + AR933X_EHCI_SIZE, ATH79_CPU_IRQ_USB); + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); +} + +static void __init ar934x_usb_setup(void) +{ + u32 bootstrap; + + bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); + if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) + return; + + ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE); + udelay(1000); + + ath79_device_reset_clear(AR934X_RESET_USB_PHY); + udelay(1000); + + ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG); + udelay(1000); + + ath79_device_reset_clear(AR934X_RESET_USB_HOST); + udelay(1000); + + ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE, + AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB); ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } @@ -213,6 +231,8 @@ void __init ath79_register_usb(void) ar913x_usb_setup(); else if (soc_is_ar933x()) ar933x_usb_setup(); + else if (soc_is_ar934x()) + ar934x_usb_setup(); else BUG(); } diff --git a/arch/mips/ath79/mach-db120.c b/arch/mips/ath79/mach-db120.c index 1983e4d2af4b..42f540a724f4 100644 --- a/arch/mips/ath79/mach-db120.c +++ b/arch/mips/ath79/mach-db120.c @@ -25,6 +25,7 @@ #include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" #include "dev-spi.h" +#include "dev-usb.h" #include "dev-wmac.h" #include "pci.h" @@ -126,6 +127,7 @@ static void __init db120_setup(void) db120_gpio_keys); ath79_register_spi(&db120_spi_data, db120_spi_info, ARRAY_SIZE(db120_spi_info)); + ath79_register_usb(); ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); } diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile index 833af72c852a..9bbb30a9dc20 100644 --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -1,6 +1,6 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \ - dev-spi.o dev-uart.o dev-wdt.o + dev-spi.o dev-uart.o dev-wdt.o dev-usb-usbd.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += boards/ diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index dd18e4b761a8..1cd4d73f23c7 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -24,6 +24,7 @@ #include <bcm63xx_dev_flash.h> #include <bcm63xx_dev_pcmcia.h> #include <bcm63xx_dev_spi.h> +#include <bcm63xx_dev_usb_usbd.h> #include <board_bcm963xx.h> #define PFX "board_bcm963xx: " @@ -42,6 +43,12 @@ static struct board_info __initdata board_96328avng = { .has_uart0 = 1, .has_pci = 1, + .has_usbd = 0, + + .usbd = { + .use_fullspeed = 0, + .port_no = 0, + }, .leds = { { @@ -713,7 +720,7 @@ const char *board_get_name(void) */ static int board_get_mac_address(u8 *mac) { - u8 *p; + u8 *oui; int count; if (mac_addr_used >= nvram.mac_addr_count) { @@ -722,21 +729,23 @@ static int board_get_mac_address(u8 *mac) } memcpy(mac, nvram.mac_addr_base, ETH_ALEN); - p = mac + ETH_ALEN - 1; + oui = mac + ETH_ALEN/2 - 1; count = mac_addr_used; while (count--) { + u8 *p = mac + ETH_ALEN - 1; + do { (*p)++; if (*p != 0) break; p--; - } while (p != mac); - } + } while (p != oui); - if (p == mac) { - printk(KERN_ERR PFX "unable to fetch mac address\n"); - return -ENODEV; + if (p == oui) { + printk(KERN_ERR PFX "unable to fetch mac address\n"); + return -ENODEV; + } } mac_addr_used++; @@ -888,6 +897,9 @@ int __init board_register_devices(void) !board_get_mac_address(board.enet1.mac_addr)) bcm63xx_enet_register(1, &board.enet1); + if (board.has_usbd) + bcm63xx_usbd_register(&board.usbd); + if (board.has_dsp) bcm63xx_dsp_register(&board.dsp); diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c index 1db48adb543a..dff79ab6005e 100644 --- a/arch/mips/bcm63xx/clk.c +++ b/arch/mips/bcm63xx/clk.c @@ -160,7 +160,9 @@ static struct clk clk_pcm = { */ static void usbh_set(struct clk *clk, int enable) { - if (BCMCPU_IS_6348()) + if (BCMCPU_IS_6328()) + bcm_hwclock_set(CKCTL_6328_USBH_EN, enable); + else if (BCMCPU_IS_6348()) bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); else if (BCMCPU_IS_6368()) bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); @@ -171,6 +173,21 @@ static struct clk clk_usbh = { }; /* + * USB device clock + */ +static void usbd_set(struct clk *clk, int enable) +{ + if (BCMCPU_IS_6328()) + bcm_hwclock_set(CKCTL_6328_USBD_EN, enable); + else if (BCMCPU_IS_6368()) + bcm_hwclock_set(CKCTL_6368_USBD_EN, enable); +} + +static struct clk clk_usbd = { + .set = usbd_set, +}; + +/* * SPI clock */ static void spi_set(struct clk *clk, int enable) @@ -284,6 +301,8 @@ struct clk *clk_get(struct device *dev, const char *id) return &clk_ephy; if (!strcmp(id, "usbh")) return &clk_usbh; + if (!strcmp(id, "usbd")) + return &clk_usbd; if (!strcmp(id, "spi")) return &clk_spi; if (!strcmp(id, "xtm")) diff --git a/arch/mips/bcm63xx/dev-usb-usbd.c b/arch/mips/bcm63xx/dev-usb-usbd.c new file mode 100644 index 000000000000..508bd9d8df27 --- /dev/null +++ b/arch/mips/bcm63xx/dev-usb-usbd.c @@ -0,0 +1,65 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> + * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com> + * Copyright (C) 2012 Broadcom Corporation + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <bcm63xx_cpu.h> +#include <bcm63xx_dev_usb_usbd.h> + +#define NUM_MMIO 2 +#define NUM_IRQ 7 + +static struct resource usbd_resources[NUM_MMIO + NUM_IRQ]; + +static u64 usbd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device bcm63xx_usbd_device = { + .name = "bcm63xx_udc", + .id = -1, + .num_resources = ARRAY_SIZE(usbd_resources), + .resource = usbd_resources, + .dev = { + .dma_mask = &usbd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +int __init bcm63xx_usbd_register(const struct bcm63xx_usbd_platform_data *pd) +{ + const int irq_list[NUM_IRQ] = { IRQ_USBD, + IRQ_USBD_RXDMA0, IRQ_USBD_TXDMA0, + IRQ_USBD_RXDMA1, IRQ_USBD_TXDMA1, + IRQ_USBD_RXDMA2, IRQ_USBD_TXDMA2 }; + int i; + + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368()) + return 0; + + usbd_resources[0].start = bcm63xx_regset_address(RSET_USBD); + usbd_resources[0].end = usbd_resources[0].start + RSET_USBD_SIZE - 1; + usbd_resources[0].flags = IORESOURCE_MEM; + + usbd_resources[1].start = bcm63xx_regset_address(RSET_USBDMA); + usbd_resources[1].end = usbd_resources[1].start + RSET_USBDMA_SIZE - 1; + usbd_resources[1].flags = IORESOURCE_MEM; + + for (i = 0; i < NUM_IRQ; i++) { + struct resource *r = &usbd_resources[NUM_MMIO + i]; + + r->start = r->end = bcm63xx_get_irq_number(irq_list[i]); + r->flags = IORESOURCE_IRQ; + } + + platform_device_add_data(&bcm63xx_usbd_device, pd, sizeof(*pd)); + + return platform_device_register(&bcm63xx_usbd_device); +} diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 18e051ad18a5..da24c2bd9b7c 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -56,8 +56,8 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; #define is_ext_irq_cascaded 0 #define ext_irq_start 0 #define ext_irq_end 0 -#define ext_irq_count 0 -#define ext_irq_cfg_reg1 0 +#define ext_irq_count 4 +#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6345 #define ext_irq_cfg_reg2 0 #endif #ifdef CONFIG_BCM63XX_CPU_6348 @@ -143,11 +143,15 @@ static void bcm63xx_init_irq(void) irq_stat_addr += PERF_IRQSTAT_6338_REG; irq_mask_addr += PERF_IRQMASK_6338_REG; irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; break; case BCM6345_CPU_ID: irq_stat_addr += PERF_IRQSTAT_6345_REG; irq_mask_addr += PERF_IRQMASK_6345_REG; irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; break; case BCM6348_CPU_ID: irq_stat_addr += PERF_IRQSTAT_6348_REG; @@ -434,7 +438,8 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, reg = bcm_perf_readl(regaddr); irq %= 4; - if (BCMCPU_IS_6348()) { + switch (bcm63xx_get_cpu_id()) { + case BCM6348_CPU_ID: if (levelsense) reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq); else @@ -447,9 +452,13 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq); else reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); - } + break; - if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) { + case BCM6328_CPU_ID: + case BCM6338_CPU_ID: + case BCM6345_CPU_ID: + case BCM6358_CPU_ID: + case BCM6368_CPU_ID: if (levelsense) reg |= EXTIRQ_CFG_LEVELSENSE(irq); else @@ -462,6 +471,9 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, reg |= EXTIRQ_CFG_BOTHEDGE(irq); else reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); + break; + default: + BUG(); } bcm_perf_writel(reg, regaddr); diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c index 0e74a13639cd..314231be788c 100644 --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -74,6 +74,9 @@ void bcm63xx_machine_reboot(void) case BCM6338_CPU_ID: perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338; break; + case BCM6345_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6345; + break; case BCM6348_CPU_ID: perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348; break; @@ -83,6 +86,9 @@ void bcm63xx_machine_reboot(void) } for (i = 0; i < 2; i++) { + if (!perf_regs[i]) + break; + reg = bcm_perf_readl(perf_regs[i]); if (BCMCPU_IS_6348()) { reg &= ~EXTIRQ_CFG_MASK_ALL_6348; diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c index ce6483a9302a..02193953eb9e 100644 --- a/arch/mips/cavium-octeon/csrc-octeon.c +++ b/arch/mips/cavium-octeon/csrc-octeon.c @@ -4,7 +4,7 @@ * for more details. * * Copyright (C) 2007 by Ralf Baechle - * Copyright (C) 2009, 2010 Cavium Networks, Inc. + * Copyright (C) 2009, 2012 Cavium, Inc. */ #include <linux/clocksource.h> #include <linux/export.h> @@ -18,6 +18,33 @@ #include <asm/octeon/cvmx-ipd-defs.h> #include <asm/octeon/cvmx-mio-defs.h> + +static u64 f; +static u64 rdiv; +static u64 sdiv; +static u64 octeon_udelay_factor; +static u64 octeon_ndelay_factor; + +void __init octeon_setup_delays(void) +{ + octeon_udelay_factor = octeon_get_clock_rate() / 1000000; + /* + * For __ndelay we divide by 2^16, so the factor is multiplied + * by the same amount. + */ + octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull; + + preset_lpj = octeon_get_clock_rate() / HZ; + + if (current_cpu_type() == CPU_CAVIUM_OCTEON2) { + union cvmx_mio_rst_boot rst_boot; + rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); + rdiv = rst_boot.s.c_mul; /* CPU clock */ + sdiv = rst_boot.s.pnr_mul; /* I/O clock */ + f = (0x8000000000000000ull / sdiv) * 2; + } +} + /* * Set the current core's cvmcount counter to the value of the * IPD_CLK_COUNT. We do this on all cores as they are brought @@ -30,17 +57,6 @@ void octeon_init_cvmcount(void) { unsigned long flags; unsigned loops = 2; - u64 f = 0; - u64 rdiv = 0; - u64 sdiv = 0; - if (current_cpu_type() == CPU_CAVIUM_OCTEON2) { - union cvmx_mio_rst_boot rst_boot; - rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); - rdiv = rst_boot.s.c_mul; /* CPU clock */ - sdiv = rst_boot.s.pnr_mul; /* I/O clock */ - f = (0x8000000000000000ull / sdiv) * 2; - } - /* Clobber loops so GCC will not unroll the following while loop. */ asm("" : "+r" (loops)); @@ -57,9 +73,9 @@ void octeon_init_cvmcount(void) if (f != 0) { asm("dmultu\t%[cnt],%[f]\n\t" "mfhi\t%[cnt]" - : [cnt] "+r" (ipd_clk_count), - [f] "=r" (f) - : : "hi", "lo"); + : [cnt] "+r" (ipd_clk_count) + : [f] "r" (f) + : "hi", "lo"); } } write_c0_cvmcount(ipd_clk_count); @@ -109,21 +125,6 @@ void __init plat_time_init(void) clocksource_register_hz(&clocksource_mips, octeon_get_clock_rate()); } -static u64 octeon_udelay_factor; -static u64 octeon_ndelay_factor; - -void __init octeon_setup_delays(void) -{ - octeon_udelay_factor = octeon_get_clock_rate() / 1000000; - /* - * For __ndelay we divide by 2^16, so the factor is multiplied - * by the same amount. - */ - octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull; - - preset_lpj = octeon_get_clock_rate() / HZ; -} - void __udelay(unsigned long us) { u64 cur, end, inc; @@ -163,3 +164,35 @@ void __delay(unsigned long loops) cur = read_c0_cvmcount(); } EXPORT_SYMBOL(__delay); + + +/** + * octeon_io_clk_delay - wait for a given number of io clock cycles to pass. + * + * We scale the wait by the clock ratio, and then wait for the + * corresponding number of core clocks. + * + * @count: The number of clocks to wait. + */ +void octeon_io_clk_delay(unsigned long count) +{ + u64 cur, end; + + cur = read_c0_cvmcount(); + if (rdiv != 0) { + end = count * rdiv; + if (f != 0) { + asm("dmultu\t%[cnt],%[f]\n\t" + "mfhi\t%[cnt]" + : [cnt] "+r" (end) + : [f] "r" (f) + : "hi", "lo"); + } + end = cur + end; + } else { + end = cur + count; + } + while (end > cur) + cur = read_c0_cvmcount(); +} +EXPORT_SYMBOL(octeon_io_clk_delay); diff --git a/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c index bea7538ea4e9..560e034aa024 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c +++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c @@ -130,7 +130,7 @@ void __cvmx_interrupt_gmxx_enable(int interface) if (num_ports) { if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) - gmx_tx_int_en.s.ncb_nxa = 1; + gmx_tx_int_en.cn38xx.ncb_nxa = 1; gmx_tx_int_en.s.pko_nxa = 1; } gmx_tx_int_en.s.undflw = (1 << num_ports) - 1; diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 274cd4fad30c..02b15eed4bcd 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -16,12 +16,11 @@ #include <linux/of.h> #include <asm/octeon/octeon.h> - -static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock); -static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock); +#include <asm/octeon/cvmx-ciu2-defs.h> static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror); static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror); +static DEFINE_PER_CPU(raw_spinlock_t, octeon_irq_ciu_spinlock); static __read_mostly u8 octeon_irq_ciu_to_irq[8][64]; @@ -29,8 +28,9 @@ union octeon_ciu_chip_data { void *p; unsigned long l; struct { - unsigned int line:6; - unsigned int bit:6; + unsigned long line:6; + unsigned long bit:6; + unsigned long gpio_line:6; } s; }; @@ -45,7 +45,7 @@ struct octeon_core_chip_data { static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES]; -static void octeon_irq_set_ciu_mapping(int irq, int line, int bit, +static void octeon_irq_set_ciu_mapping(int irq, int line, int bit, int gpio_line, struct irq_chip *chip, irq_flow_handler_t handler) { @@ -56,6 +56,7 @@ static void octeon_irq_set_ciu_mapping(int irq, int line, int bit, cd.l = 0; cd.s.line = line; cd.s.bit = bit; + cd.s.gpio_line = gpio_line; irq_set_chip_data(irq, cd.p); octeon_irq_ciu_to_irq[line][bit] = irq; @@ -231,22 +232,31 @@ static void octeon_irq_ciu_enable(struct irq_data *data) unsigned long *pen; unsigned long flags; union octeon_ciu_chip_data cd; + raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); cd.p = irq_data_get_irq_chip_data(data); + raw_spin_lock_irqsave(lock, flags); if (cd.s.line == 0) { - raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); - set_bit(cd.s.bit, pen); + __set_bit(cd.s.bit, pen); + /* + * Must be visible to octeon_irq_ip{2,3}_ciu() before + * enabling the irq. + */ + wmb(); cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); - raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); } else { - raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); - set_bit(cd.s.bit, pen); + __set_bit(cd.s.bit, pen); + /* + * Must be visible to octeon_irq_ip{2,3}_ciu() before + * enabling the irq. + */ + wmb(); cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); - raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } + raw_spin_unlock_irqrestore(lock, flags); } static void octeon_irq_ciu_enable_local(struct irq_data *data) @@ -254,22 +264,31 @@ static void octeon_irq_ciu_enable_local(struct irq_data *data) unsigned long *pen; unsigned long flags; union octeon_ciu_chip_data cd; + raw_spinlock_t *lock = &__get_cpu_var(octeon_irq_ciu_spinlock); cd.p = irq_data_get_irq_chip_data(data); + raw_spin_lock_irqsave(lock, flags); if (cd.s.line == 0) { - raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror); - set_bit(cd.s.bit, pen); + __set_bit(cd.s.bit, pen); + /* + * Must be visible to octeon_irq_ip{2,3}_ciu() before + * enabling the irq. + */ + wmb(); cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); - raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); } else { - raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror); - set_bit(cd.s.bit, pen); + __set_bit(cd.s.bit, pen); + /* + * Must be visible to octeon_irq_ip{2,3}_ciu() before + * enabling the irq. + */ + wmb(); cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); - raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } + raw_spin_unlock_irqrestore(lock, flags); } static void octeon_irq_ciu_disable_local(struct irq_data *data) @@ -277,22 +296,31 @@ static void octeon_irq_ciu_disable_local(struct irq_data *data) unsigned long *pen; unsigned long flags; union octeon_ciu_chip_data cd; + raw_spinlock_t *lock = &__get_cpu_var(octeon_irq_ciu_spinlock); cd.p = irq_data_get_irq_chip_data(data); + raw_spin_lock_irqsave(lock, flags); if (cd.s.line == 0) { - raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror); - clear_bit(cd.s.bit, pen); + __clear_bit(cd.s.bit, pen); + /* + * Must be visible to octeon_irq_ip{2,3}_ciu() before + * enabling the irq. + */ + wmb(); cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); - raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); } else { - raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror); - clear_bit(cd.s.bit, pen); + __clear_bit(cd.s.bit, pen); + /* + * Must be visible to octeon_irq_ip{2,3}_ciu() before + * enabling the irq. + */ + wmb(); cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); - raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } + raw_spin_unlock_irqrestore(lock, flags); } static void octeon_irq_ciu_disable_all(struct irq_data *data) @@ -301,29 +329,30 @@ static void octeon_irq_ciu_disable_all(struct irq_data *data) unsigned long *pen; int cpu; union octeon_ciu_chip_data cd; - - wmb(); /* Make sure flag changes arrive before register updates. */ + raw_spinlock_t *lock; cd.p = irq_data_get_irq_chip_data(data); - if (cd.s.line == 0) { - raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); + if (cd.s.line == 0) pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); - clear_bit(cd.s.bit, pen); - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); - } - raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); - } else { - raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); + else pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); - clear_bit(cd.s.bit, pen); + + raw_spin_lock_irqsave(lock, flags); + __clear_bit(cd.s.bit, pen); + /* + * Must be visible to octeon_irq_ip{2,3}_ciu() before + * enabling the irq. + */ + wmb(); + if (cd.s.line == 0) + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); + else cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); - } - raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + raw_spin_unlock_irqrestore(lock, flags); } } @@ -333,27 +362,30 @@ static void octeon_irq_ciu_enable_all(struct irq_data *data) unsigned long *pen; int cpu; union octeon_ciu_chip_data cd; + raw_spinlock_t *lock; cd.p = irq_data_get_irq_chip_data(data); - if (cd.s.line == 0) { - raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); + if (cd.s.line == 0) pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); - set_bit(cd.s.bit, pen); - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); - } - raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); - } else { - raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); + else pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); - set_bit(cd.s.bit, pen); + + raw_spin_lock_irqsave(lock, flags); + __set_bit(cd.s.bit, pen); + /* + * Must be visible to octeon_irq_ip{2,3}_ciu() before + * enabling the irq. + */ + wmb(); + if (cd.s.line == 0) + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); + else cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); - } - raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + raw_spin_unlock_irqrestore(lock, flags); } } @@ -435,7 +467,7 @@ static void octeon_irq_ciu_ack(struct irq_data *data) u64 mask; union octeon_ciu_chip_data cd; - cd.p = data->chip_data; + cd.p = irq_data_get_irq_chip_data(data); mask = 1ull << (cd.s.bit); if (cd.s.line == 0) { @@ -456,9 +488,7 @@ static void octeon_irq_ciu_disable_all_v2(struct irq_data *data) u64 mask; union octeon_ciu_chip_data cd; - wmb(); /* Make sure flag changes arrive before register updates. */ - - cd.p = data->chip_data; + cd.p = irq_data_get_irq_chip_data(data); mask = 1ull << (cd.s.bit); if (cd.s.line == 0) { @@ -486,7 +516,7 @@ static void octeon_irq_ciu_enable_all_v2(struct irq_data *data) u64 mask; union octeon_ciu_chip_data cd; - cd.p = data->chip_data; + cd.p = irq_data_get_irq_chip_data(data); mask = 1ull << (cd.s.bit); if (cd.s.line == 0) { @@ -521,7 +551,7 @@ static void octeon_irq_gpio_setup(struct irq_data *data) cfg.s.fil_cnt = 7; cfg.s.fil_sel = 3; - cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), cfg.u64); + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), cfg.u64); } static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data) @@ -549,7 +579,7 @@ static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data) union octeon_ciu_chip_data cd; cd.p = irq_data_get_irq_chip_data(data); - cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0); + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), 0); octeon_irq_ciu_disable_all_v2(data); } @@ -559,7 +589,7 @@ static void octeon_irq_ciu_disable_gpio(struct irq_data *data) union octeon_ciu_chip_data cd; cd.p = irq_data_get_irq_chip_data(data); - cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0); + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), 0); octeon_irq_ciu_disable_all(data); } @@ -570,7 +600,7 @@ static void octeon_irq_ciu_gpio_ack(struct irq_data *data) u64 mask; cd.p = irq_data_get_irq_chip_data(data); - mask = 1ull << (cd.s.bit - 16); + mask = 1ull << (cd.s.gpio_line); cvmx_write_csr(CVMX_GPIO_INT_CLR, mask); } @@ -615,8 +645,10 @@ static int octeon_irq_ciu_set_affinity(struct irq_data *data, bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data); unsigned long flags; union octeon_ciu_chip_data cd; + unsigned long *pen; + raw_spinlock_t *lock; - cd.p = data->chip_data; + cd.p = irq_data_get_irq_chip_data(data); /* * For non-v2 CIU, we will allow only single CPU affinity. @@ -629,36 +661,36 @@ static int octeon_irq_ciu_set_affinity(struct irq_data *data, if (!enable_one) return 0; - if (cd.s.line == 0) { - raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); - unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); - if (cpumask_test_cpu(cpu, dest) && enable_one) { - enable_one = false; - set_bit(cd.s.bit, pen); - } else { - clear_bit(cd.s.bit, pen); - } - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + + lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); + raw_spin_lock_irqsave(lock, flags); + + if (cd.s.line == 0) + pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); + else + pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + + if (cpumask_test_cpu(cpu, dest) && enable_one) { + enable_one = 0; + __set_bit(cd.s.bit, pen); + } else { + __clear_bit(cd.s.bit, pen); } - raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); - } else { - raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); - unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + /* + * Must be visible to octeon_irq_ip{2,3}_ciu() before + * enabling the irq. + */ + wmb(); - if (cpumask_test_cpu(cpu, dest) && enable_one) { - enable_one = false; - set_bit(cd.s.bit, pen); - } else { - clear_bit(cd.s.bit, pen); - } + if (cd.s.line == 0) + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); + else cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); - } - raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + + raw_spin_unlock_irqrestore(lock, flags); } return 0; } @@ -679,7 +711,7 @@ static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data, if (!enable_one) return 0; - cd.p = data->chip_data; + cd.p = irq_data_get_irq_chip_data(data); mask = 1ull << cd.s.bit; if (cd.s.line == 0) { @@ -714,14 +746,6 @@ static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data, #endif /* - * The v1 CIU code already masks things, so supply a dummy version to - * the core chip code. - */ -static void octeon_irq_dummy_mask(struct irq_data *data) -{ -} - -/* * Newer octeon chips have support for lockless CIU operation. */ static struct irq_chip octeon_irq_chip_ciu_v2 = { @@ -742,7 +766,8 @@ static struct irq_chip octeon_irq_chip_ciu = { .irq_enable = octeon_irq_ciu_enable, .irq_disable = octeon_irq_ciu_disable_all, .irq_ack = octeon_irq_ciu_ack, - .irq_mask = octeon_irq_dummy_mask, + .irq_mask = octeon_irq_ciu_disable_local, + .irq_unmask = octeon_irq_ciu_enable, #ifdef CONFIG_SMP .irq_set_affinity = octeon_irq_ciu_set_affinity, .irq_cpu_offline = octeon_irq_cpu_offline_ciu, @@ -766,6 +791,8 @@ static struct irq_chip octeon_irq_chip_ciu_mbox = { .name = "CIU-M", .irq_enable = octeon_irq_ciu_enable_all, .irq_disable = octeon_irq_ciu_disable_all, + .irq_ack = octeon_irq_ciu_disable_local, + .irq_eoi = octeon_irq_ciu_enable_local, .irq_cpu_online = octeon_irq_ciu_enable_local, .irq_cpu_offline = octeon_irq_ciu_disable_local, @@ -790,7 +817,8 @@ static struct irq_chip octeon_irq_chip_ciu_gpio = { .name = "CIU-GPIO", .irq_enable = octeon_irq_ciu_enable_gpio, .irq_disable = octeon_irq_ciu_disable_gpio, - .irq_mask = octeon_irq_dummy_mask, + .irq_mask = octeon_irq_ciu_disable_local, + .irq_unmask = octeon_irq_ciu_enable, .irq_ack = octeon_irq_ciu_gpio_ack, .irq_set_type = octeon_irq_ciu_gpio_set_type, #ifdef CONFIG_SMP @@ -809,12 +837,18 @@ static void octeon_irq_ciu_wd_enable(struct irq_data *data) unsigned long *pen; int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ int cpu = octeon_cpu_for_coreid(coreid); + raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); - raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + raw_spin_lock_irqsave(lock, flags); pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); - set_bit(coreid, pen); + __set_bit(coreid, pen); + /* + * Must be visible to octeon_irq_ip{2,3}_ciu() before enabling + * the irq. + */ + wmb(); cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); - raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + raw_spin_unlock_irqrestore(lock, flags); } /* @@ -843,7 +877,8 @@ static struct irq_chip octeon_irq_chip_ciu_wd = { .name = "CIU-W", .irq_enable = octeon_irq_ciu_wd_enable, .irq_disable = octeon_irq_ciu_disable_all, - .irq_mask = octeon_irq_dummy_mask, + .irq_mask = octeon_irq_ciu_disable_local, + .irq_unmask = octeon_irq_ciu_enable_local, }; static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit) @@ -976,19 +1011,20 @@ static int octeon_irq_ciu_map(struct irq_domain *d, return -EINVAL; if (octeon_irq_ciu_is_edge(line, bit)) - octeon_irq_set_ciu_mapping(virq, line, bit, + octeon_irq_set_ciu_mapping(virq, line, bit, 0, octeon_irq_ciu_chip, handle_edge_irq); else - octeon_irq_set_ciu_mapping(virq, line, bit, + octeon_irq_set_ciu_mapping(virq, line, bit, 0, octeon_irq_ciu_chip, handle_level_irq); return 0; } -static int octeon_irq_gpio_map(struct irq_domain *d, - unsigned int virq, irq_hw_number_t hw) +static int octeon_irq_gpio_map_common(struct irq_domain *d, + unsigned int virq, irq_hw_number_t hw, + int line_limit, struct irq_chip *chip) { struct octeon_irq_gpio_domain_data *gpiod = d->host_data; unsigned int line, bit; @@ -999,15 +1035,20 @@ static int octeon_irq_gpio_map(struct irq_domain *d, hw += gpiod->base_hwirq; line = hw >> 6; bit = hw & 63; - if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0) + if (line > line_limit || octeon_irq_ciu_to_irq[line][bit] != 0) return -EINVAL; - octeon_irq_set_ciu_mapping(virq, line, bit, - octeon_irq_gpio_chip, - octeon_irq_handle_gpio); + octeon_irq_set_ciu_mapping(virq, line, bit, hw, + chip, octeon_irq_handle_gpio); return 0; } +static int octeon_irq_gpio_map(struct irq_domain *d, + unsigned int virq, irq_hw_number_t hw) +{ + return octeon_irq_gpio_map_common(d, virq, hw, 1, octeon_irq_gpio_chip); +} + static struct irq_domain_ops octeon_irq_domain_ciu_ops = { .map = octeon_irq_ciu_map, .xlate = octeon_irq_ciu_xlat, @@ -1018,13 +1059,12 @@ static struct irq_domain_ops octeon_irq_domain_gpio_ops = { .xlate = octeon_irq_gpio_xlat, }; -static void octeon_irq_ip2_v1(void) +static void octeon_irq_ip2_ciu(void) { const unsigned long core_id = cvmx_get_core_num(); u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2)); ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror); - clear_c0_status(STATUSF_IP2); if (likely(ciu_sum)) { int bit = fls64(ciu_sum) - 1; int irq = octeon_irq_ciu_to_irq[0][bit]; @@ -1035,32 +1075,13 @@ static void octeon_irq_ip2_v1(void) } else { spurious_interrupt(); } - set_c0_status(STATUSF_IP2); } -static void octeon_irq_ip2_v2(void) -{ - const unsigned long core_id = cvmx_get_core_num(); - u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2)); - - ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror); - if (likely(ciu_sum)) { - int bit = fls64(ciu_sum) - 1; - int irq = octeon_irq_ciu_to_irq[0][bit]; - if (likely(irq)) - do_IRQ(irq); - else - spurious_interrupt(); - } else { - spurious_interrupt(); - } -} -static void octeon_irq_ip3_v1(void) +static void octeon_irq_ip3_ciu(void) { u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1); ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror); - clear_c0_status(STATUSF_IP3); if (likely(ciu_sum)) { int bit = fls64(ciu_sum) - 1; int irq = octeon_irq_ciu_to_irq[1][bit]; @@ -1071,24 +1092,13 @@ static void octeon_irq_ip3_v1(void) } else { spurious_interrupt(); } - set_c0_status(STATUSF_IP3); } -static void octeon_irq_ip3_v2(void) -{ - u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1); +static bool octeon_irq_use_ip4; - ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror); - if (likely(ciu_sum)) { - int bit = fls64(ciu_sum) - 1; - int irq = octeon_irq_ciu_to_irq[1][bit]; - if (likely(irq)) - do_IRQ(irq); - else - spurious_interrupt(); - } else { - spurious_interrupt(); - } +static void __cpuinit octeon_irq_local_enable_ip4(void *arg) +{ + set_c0_status(STATUSF_IP4); } static void octeon_irq_ip4_mask(void) @@ -1103,6 +1113,13 @@ static void (*octeon_irq_ip4)(void); void __cpuinitdata (*octeon_irq_setup_secondary)(void); +void __cpuinit octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t h) +{ + octeon_irq_ip4 = h; + octeon_irq_use_ip4 = true; + on_each_cpu(octeon_irq_local_enable_ip4, NULL, 1); +} + static void __cpuinit octeon_irq_percpu_enable(void) { irq_cpu_online(); @@ -1111,6 +1128,12 @@ static void __cpuinit octeon_irq_percpu_enable(void) static void __cpuinit octeon_irq_init_ciu_percpu(void) { int coreid = cvmx_get_core_num(); + + + __get_cpu_var(octeon_irq_ciu0_en_mirror) = 0; + __get_cpu_var(octeon_irq_ciu1_en_mirror) = 0; + wmb(); + raw_spin_lock_init(&__get_cpu_var(octeon_irq_ciu_spinlock)); /* * Disable All CIU Interrupts. The ones we need will be * enabled later. Read the SUM register so we know the write @@ -1123,12 +1146,30 @@ static void __cpuinit octeon_irq_init_ciu_percpu(void) cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); } -static void __cpuinit octeon_irq_setup_secondary_ciu(void) +static void octeon_irq_init_ciu2_percpu(void) { + u64 regx, ipx; + int coreid = cvmx_get_core_num(); + u64 base = CVMX_CIU2_EN_PPX_IP2_WRKQ(coreid); - __get_cpu_var(octeon_irq_ciu0_en_mirror) = 0; - __get_cpu_var(octeon_irq_ciu1_en_mirror) = 0; + /* + * Disable All CIU2 Interrupts. The ones we need will be + * enabled later. Read the SUM register so we know the write + * completed. + * + * There are 9 registers and 3 IPX levels with strides 0x1000 + * and 0x200 respectivly. Use loops to clear them. + */ + for (regx = 0; regx <= 0x8000; regx += 0x1000) { + for (ipx = 0; ipx <= 0x400; ipx += 0x200) + cvmx_write_csr(base + regx + ipx, 0); + } + cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)); +} + +static void __cpuinit octeon_irq_setup_secondary_ciu(void) +{ octeon_irq_init_ciu_percpu(); octeon_irq_percpu_enable(); @@ -1137,6 +1178,19 @@ static void __cpuinit octeon_irq_setup_secondary_ciu(void) clear_c0_status(STATUSF_IP4); } +static void octeon_irq_setup_secondary_ciu2(void) +{ + octeon_irq_init_ciu2_percpu(); + octeon_irq_percpu_enable(); + + /* Enable the CIU lines */ + set_c0_status(STATUSF_IP3 | STATUSF_IP2); + if (octeon_irq_use_ip4) + set_c0_status(STATUSF_IP4); + else + clear_c0_status(STATUSF_IP4); +} + static void __init octeon_irq_init_ciu(void) { unsigned int i; @@ -1150,19 +1204,17 @@ static void __init octeon_irq_init_ciu(void) octeon_irq_init_ciu_percpu(); octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; + octeon_irq_ip2 = octeon_irq_ip2_ciu; + octeon_irq_ip3 = octeon_irq_ip3_ciu; if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) || OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) || OCTEON_IS_MODEL(OCTEON_CN6XXX)) { - octeon_irq_ip2 = octeon_irq_ip2_v2; - octeon_irq_ip3 = octeon_irq_ip3_v2; chip = &octeon_irq_chip_ciu_v2; chip_mbox = &octeon_irq_chip_ciu_mbox_v2; chip_wd = &octeon_irq_chip_ciu_wd_v2; octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2; } else { - octeon_irq_ip2 = octeon_irq_ip2_v1; - octeon_irq_ip3 = octeon_irq_ip3_v1; chip = &octeon_irq_chip_ciu; chip_mbox = &octeon_irq_chip_ciu_mbox; chip_wd = &octeon_irq_chip_ciu_wd; @@ -1192,6 +1244,7 @@ static void __init octeon_irq_init_ciu(void) ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu"); if (ciu_node) { ciu_domain = irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL); + irq_set_default_host(ciu_domain); of_node_put(ciu_node); } else panic("Cannot find device node for cavium,octeon-3860-ciu."); @@ -1200,8 +1253,8 @@ static void __init octeon_irq_init_ciu(void) for (i = 0; i < 16; i++) octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i + 0); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, 0, chip_mbox, handle_percpu_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, 0, chip_mbox, handle_percpu_irq); for (i = 0; i < 4; i++) octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_INT0, 0, i + 36); @@ -1217,7 +1270,7 @@ static void __init octeon_irq_init_ciu(void) /* CIU_1 */ for (i = 0; i < 16; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, 0, chip_wd, handle_level_irq); octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB1, 1, 17); @@ -1226,6 +1279,466 @@ static void __init octeon_irq_init_ciu(void) clear_c0_status(STATUSF_IP4); } +/* + * Watchdog interrupts are special. They are associated with a single + * core, so we hardwire the affinity to that core. + */ +static void octeon_irq_ciu2_wd_enable(struct irq_data *data) +{ + u64 mask; + u64 en_addr; + int coreid = data->irq - OCTEON_IRQ_WDOG0; + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); + mask = 1ull << (cd.s.bit); + + en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) + (0x1000ull * cd.s.line); + cvmx_write_csr(en_addr, mask); + +} + +static void octeon_irq_ciu2_enable(struct irq_data *data) +{ + u64 mask; + u64 en_addr; + int cpu = next_cpu_for_irq(data); + int coreid = octeon_coreid_for_cpu(cpu); + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); + mask = 1ull << (cd.s.bit); + + en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) + (0x1000ull * cd.s.line); + cvmx_write_csr(en_addr, mask); +} + +static void octeon_irq_ciu2_enable_local(struct irq_data *data) +{ + u64 mask; + u64 en_addr; + int coreid = cvmx_get_core_num(); + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); + mask = 1ull << (cd.s.bit); + + en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) + (0x1000ull * cd.s.line); + cvmx_write_csr(en_addr, mask); + +} + +static void octeon_irq_ciu2_disable_local(struct irq_data *data) +{ + u64 mask; + u64 en_addr; + int coreid = cvmx_get_core_num(); + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); + mask = 1ull << (cd.s.bit); + + en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(coreid) + (0x1000ull * cd.s.line); + cvmx_write_csr(en_addr, mask); + +} + +static void octeon_irq_ciu2_ack(struct irq_data *data) +{ + u64 mask; + u64 en_addr; + int coreid = cvmx_get_core_num(); + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); + mask = 1ull << (cd.s.bit); + + en_addr = CVMX_CIU2_RAW_PPX_IP2_WRKQ(coreid) + (0x1000ull * cd.s.line); + cvmx_write_csr(en_addr, mask); + +} + +static void octeon_irq_ciu2_disable_all(struct irq_data *data) +{ + int cpu; + u64 mask; + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); + mask = 1ull << (cd.s.bit); + + for_each_online_cpu(cpu) { + u64 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd.s.line); + cvmx_write_csr(en_addr, mask); + } +} + +static void octeon_irq_ciu2_mbox_enable_all(struct irq_data *data) +{ + int cpu; + u64 mask; + + mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); + + for_each_online_cpu(cpu) { + u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(octeon_coreid_for_cpu(cpu)); + cvmx_write_csr(en_addr, mask); + } +} + +static void octeon_irq_ciu2_mbox_disable_all(struct irq_data *data) +{ + int cpu; + u64 mask; + + mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); + + for_each_online_cpu(cpu) { + u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(octeon_coreid_for_cpu(cpu)); + cvmx_write_csr(en_addr, mask); + } +} + +static void octeon_irq_ciu2_mbox_enable_local(struct irq_data *data) +{ + u64 mask; + u64 en_addr; + int coreid = cvmx_get_core_num(); + + mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); + en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(coreid); + cvmx_write_csr(en_addr, mask); +} + +static void octeon_irq_ciu2_mbox_disable_local(struct irq_data *data) +{ + u64 mask; + u64 en_addr; + int coreid = cvmx_get_core_num(); + + mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); + en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(coreid); + cvmx_write_csr(en_addr, mask); +} + +#ifdef CONFIG_SMP +static int octeon_irq_ciu2_set_affinity(struct irq_data *data, + const struct cpumask *dest, bool force) +{ + int cpu; + bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data); + u64 mask; + union octeon_ciu_chip_data cd; + + if (!enable_one) + return 0; + + cd.p = irq_data_get_irq_chip_data(data); + mask = 1ull << cd.s.bit; + + for_each_online_cpu(cpu) { + u64 en_addr; + if (cpumask_test_cpu(cpu, dest) && enable_one) { + enable_one = false; + en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd.s.line); + } else { + en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd.s.line); + } + cvmx_write_csr(en_addr, mask); + } + + return 0; +} +#endif + +static void octeon_irq_ciu2_enable_gpio(struct irq_data *data) +{ + octeon_irq_gpio_setup(data); + octeon_irq_ciu2_enable(data); +} + +static void octeon_irq_ciu2_disable_gpio(struct irq_data *data) +{ + union octeon_ciu_chip_data cd; + cd.p = irq_data_get_irq_chip_data(data); + + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), 0); + + octeon_irq_ciu2_disable_all(data); +} + +static struct irq_chip octeon_irq_chip_ciu2 = { + .name = "CIU2-E", + .irq_enable = octeon_irq_ciu2_enable, + .irq_disable = octeon_irq_ciu2_disable_all, + .irq_ack = octeon_irq_ciu2_ack, + .irq_mask = octeon_irq_ciu2_disable_local, + .irq_unmask = octeon_irq_ciu2_enable, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu2_set_affinity, + .irq_cpu_offline = octeon_irq_cpu_offline_ciu, +#endif +}; + +static struct irq_chip octeon_irq_chip_ciu2_mbox = { + .name = "CIU2-M", + .irq_enable = octeon_irq_ciu2_mbox_enable_all, + .irq_disable = octeon_irq_ciu2_mbox_disable_all, + .irq_ack = octeon_irq_ciu2_mbox_disable_local, + .irq_eoi = octeon_irq_ciu2_mbox_enable_local, + + .irq_cpu_online = octeon_irq_ciu2_mbox_enable_local, + .irq_cpu_offline = octeon_irq_ciu2_mbox_disable_local, + .flags = IRQCHIP_ONOFFLINE_ENABLED, +}; + +static struct irq_chip octeon_irq_chip_ciu2_wd = { + .name = "CIU2-W", + .irq_enable = octeon_irq_ciu2_wd_enable, + .irq_disable = octeon_irq_ciu2_disable_all, + .irq_mask = octeon_irq_ciu2_disable_local, + .irq_unmask = octeon_irq_ciu2_enable_local, +}; + +static struct irq_chip octeon_irq_chip_ciu2_gpio = { + .name = "CIU-GPIO", + .irq_enable = octeon_irq_ciu2_enable_gpio, + .irq_disable = octeon_irq_ciu2_disable_gpio, + .irq_ack = octeon_irq_ciu_gpio_ack, + .irq_mask = octeon_irq_ciu2_disable_local, + .irq_unmask = octeon_irq_ciu2_enable, + .irq_set_type = octeon_irq_ciu_gpio_set_type, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu2_set_affinity, + .irq_cpu_offline = octeon_irq_cpu_offline_ciu, +#endif + .flags = IRQCHIP_SET_TYPE_MASKED, +}; + +static int octeon_irq_ciu2_xlat(struct irq_domain *d, + struct device_node *node, + const u32 *intspec, + unsigned int intsize, + unsigned long *out_hwirq, + unsigned int *out_type) +{ + unsigned int ciu, bit; + + ciu = intspec[0]; + bit = intspec[1]; + + /* Line 7 are the GPIO lines */ + if (ciu > 6 || bit > 63) + return -EINVAL; + + *out_hwirq = (ciu << 6) | bit; + *out_type = 0; + + return 0; +} + +static bool octeon_irq_ciu2_is_edge(unsigned int line, unsigned int bit) +{ + bool edge = false; + + if (line == 3) /* MIO */ + switch (bit) { + case 2: /* IPD_DRP */ + case 8 ... 11: /* Timers */ + case 48: /* PTP */ + edge = true; + break; + default: + break; + } + else if (line == 6) /* PKT */ + switch (bit) { + case 52 ... 53: /* ILK_DRP */ + case 8 ... 12: /* GMX_DRP */ + edge = true; + break; + default: + break; + } + return edge; +} + +static int octeon_irq_ciu2_map(struct irq_domain *d, + unsigned int virq, irq_hw_number_t hw) +{ + unsigned int line = hw >> 6; + unsigned int bit = hw & 63; + + if (!octeon_irq_virq_in_range(virq)) + return -EINVAL; + + /* Line 7 are the GPIO lines */ + if (line > 6 || octeon_irq_ciu_to_irq[line][bit] != 0) + return -EINVAL; + + if (octeon_irq_ciu2_is_edge(line, bit)) + octeon_irq_set_ciu_mapping(virq, line, bit, 0, + &octeon_irq_chip_ciu2, + handle_edge_irq); + else + octeon_irq_set_ciu_mapping(virq, line, bit, 0, + &octeon_irq_chip_ciu2, + handle_level_irq); + + return 0; +} +static int octeon_irq_ciu2_gpio_map(struct irq_domain *d, + unsigned int virq, irq_hw_number_t hw) +{ + return octeon_irq_gpio_map_common(d, virq, hw, 7, &octeon_irq_chip_ciu2_gpio); +} + +static struct irq_domain_ops octeon_irq_domain_ciu2_ops = { + .map = octeon_irq_ciu2_map, + .xlate = octeon_irq_ciu2_xlat, +}; + +static struct irq_domain_ops octeon_irq_domain_ciu2_gpio_ops = { + .map = octeon_irq_ciu2_gpio_map, + .xlate = octeon_irq_gpio_xlat, +}; + +static void octeon_irq_ciu2(void) +{ + int line; + int bit; + int irq; + u64 src_reg, src, sum; + const unsigned long core_id = cvmx_get_core_num(); + + sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(core_id)) & 0xfful; + + if (unlikely(!sum)) + goto spurious; + + line = fls64(sum) - 1; + src_reg = CVMX_CIU2_SRC_PPX_IP2_WRKQ(core_id) + (0x1000 * line); + src = cvmx_read_csr(src_reg); + + if (unlikely(!src)) + goto spurious; + + bit = fls64(src) - 1; + irq = octeon_irq_ciu_to_irq[line][bit]; + if (unlikely(!irq)) + goto spurious; + + do_IRQ(irq); + goto out; + +spurious: + spurious_interrupt(); +out: + /* CN68XX pass 1.x has an errata that accessing the ACK registers + can stop interrupts from propagating */ + if (OCTEON_IS_MODEL(OCTEON_CN68XX)) + cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY); + else + cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP2(core_id)); + return; +} + +static void octeon_irq_ciu2_mbox(void) +{ + int line; + + const unsigned long core_id = cvmx_get_core_num(); + u64 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP3(core_id)) >> 60; + + if (unlikely(!sum)) + goto spurious; + + line = fls64(sum) - 1; + + do_IRQ(OCTEON_IRQ_MBOX0 + line); + goto out; + +spurious: + spurious_interrupt(); +out: + /* CN68XX pass 1.x has an errata that accessing the ACK registers + can stop interrupts from propagating */ + if (OCTEON_IS_MODEL(OCTEON_CN68XX)) + cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY); + else + cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP3(core_id)); + return; +} + +static void __init octeon_irq_init_ciu2(void) +{ + unsigned int i; + struct device_node *gpio_node; + struct device_node *ciu_node; + struct irq_domain *ciu_domain = NULL; + + octeon_irq_init_ciu2_percpu(); + octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu2; + + octeon_irq_ip2 = octeon_irq_ciu2; + octeon_irq_ip3 = octeon_irq_ciu2_mbox; + octeon_irq_ip4 = octeon_irq_ip4_mask; + + /* Mips internal */ + octeon_irq_init_core(); + + gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio"); + if (gpio_node) { + struct octeon_irq_gpio_domain_data *gpiod; + + gpiod = kzalloc(sizeof(*gpiod), GFP_KERNEL); + if (gpiod) { + /* gpio domain host_data is the base hwirq number. */ + gpiod->base_hwirq = 7 << 6; + irq_domain_add_linear(gpio_node, 16, &octeon_irq_domain_ciu2_gpio_ops, gpiod); + of_node_put(gpio_node); + } else + pr_warn("Cannot allocate memory for GPIO irq_domain.\n"); + } else + pr_warn("Cannot find device node for cavium,octeon-3860-gpio.\n"); + + ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-6880-ciu2"); + if (ciu_node) { + ciu_domain = irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu2_ops, NULL); + irq_set_default_host(ciu_domain); + of_node_put(ciu_node); + } else + panic("Cannot find device node for cavium,octeon-6880-ciu2."); + + /* CUI2 */ + for (i = 0; i < 64; i++) + octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i); + + for (i = 0; i < 32; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i, 0, + &octeon_irq_chip_ciu2_wd, handle_level_irq); + + for (i = 0; i < 4; i++) + octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 3, i + 8); + + octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 3, 44); + + for (i = 0; i < 4; i++) + octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_INT0, 4, i); + + for (i = 0; i < 4; i++) + octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 4, i + 8); + + irq_set_chip_and_handler(OCTEON_IRQ_MBOX0, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq); + irq_set_chip_and_handler(OCTEON_IRQ_MBOX1, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq); + irq_set_chip_and_handler(OCTEON_IRQ_MBOX2, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq); + irq_set_chip_and_handler(OCTEON_IRQ_MBOX3, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq); + + /* Enable the CIU lines */ + set_c0_status(STATUSF_IP3 | STATUSF_IP2); + clear_c0_status(STATUSF_IP4); +} + void __init arch_init_irq(void) { #ifdef CONFIG_SMP @@ -1233,7 +1746,10 @@ void __init arch_init_irq(void) cpumask_clear(irq_default_affinity); cpumask_set_cpu(smp_processor_id(), irq_default_affinity); #endif - octeon_irq_init_ciu(); + if (OCTEON_IS_MODEL(OCTEON_CN68XX)) + octeon_irq_init_ciu2(); + else + octeon_irq_init_ciu(); } asmlinkage void plat_irq_dispatch(void) diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 919b0fb7bb1a..04dd8ff0e0d8 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -548,6 +548,8 @@ void __init prom_init(void) } #endif + octeon_setup_delays(); + /* * BIST should always be enabled when doing a soft reset. L2 * Cache locking for instance is not cleared unless BIST is @@ -611,7 +613,6 @@ void __init prom_init(void) mips_hpt_frequency = octeon_get_clock_rate(); octeon_init_cvmcount(); - octeon_setup_delays(); _machine_restart = octeon_restart; _machine_halt = octeon_halt; diff --git a/arch/mips/configs/cavium-octeon_defconfig b/arch/mips/configs/cavium_octeon_defconfig index 75165dfa60c1..75165dfa60c1 100644 --- a/arch/mips/configs/cavium-octeon_defconfig +++ b/arch/mips/configs/cavium_octeon_defconfig diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig deleted file mode 100644 index b5ad7387bbb0..000000000000 --- a/arch/mips/configs/mipssim_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_MIPS_SIM=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set -CONFIG_EXPERIMENTAL=y -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_STANDALONE is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -# CONFIG_FW_LOADER is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=y -# CONFIG_MISC_DEVICES is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_MIPS_SIM_NET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -CONFIG_ROMFS_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_DEBUG_INFO=y -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp" -# CONFIG_CRC32 is not set diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig index 84624b17b769..5468b1c7b2a5 100644 --- a/arch/mips/configs/nlm_xlp_defconfig +++ b/arch/mips/configs/nlm_xlp_defconfig @@ -1,14 +1,12 @@ CONFIG_NLM_XLP_BOARD=y CONFIG_64BIT=y +CONFIG_PAGE_SIZE_16KB=y +# CONFIG_HW_PERF_EVENTS is not set CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 CONFIG_SMP=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y # CONFIG_SECCOMP is not set -CONFIG_USE_OF=y CONFIG_EXPERIMENTAL=y -CONFIG_CROSS_COMPILE="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -19,13 +17,13 @@ CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_CGROUPS=y CONFIG_NAMESPACES=y CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y -CONFIG_INITRAMFS_COMPRESSION_LZMA=y CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y # CONFIG_COMPAT_BRK is not set @@ -35,6 +33,29 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ACORN_PARTITION=y +CONFIG_ACORN_PARTITION_ICS=y +CONFIG_ACORN_PARTITION_RISCIX=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_SYSV68_PARTITION=y +CONFIG_PCI=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=y CONFIG_MIPS32_COMPAT=y @@ -169,7 +190,6 @@ CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m @@ -185,7 +205,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -196,7 +215,6 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m @@ -247,9 +265,6 @@ CONFIG_IPDDP_ENCAP=y CONFIG_IPDDP_DECAP=y CONFIG_X25=m CONFIG_LAPB=m -CONFIG_ECONET=m -CONFIG_ECONET_AUNUDP=y -CONFIG_ECONET_NATIVE=y CONFIG_WAN_ROUTER=m CONFIG_PHONET=m CONFIG_IEEE802154=m @@ -296,11 +311,21 @@ CONFIG_NET_ACT_SIMP=m CONFIG_NET_ACT_SKBEDIT=m CONFIG_DCB=y CONFIG_NET_PKTGEN=m -# CONFIG_WIRELESS is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_NBD=m @@ -309,7 +334,6 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=65536 CONFIG_CDROM_PKTCDVD=y CONFIG_RAID_ATTRS=m -CONFIG_SCSI=y CONFIG_SCSI_TGT=m CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=m @@ -336,6 +360,48 @@ CONFIG_SCSI_DH_EMC=m CONFIG_SCSI_DH_ALUA=m CONFIG_SCSI_OSD_INITIATOR=m CONFIG_SCSI_OSD_ULD=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_SIL24=y +# CONFIG_ATA_SFF is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HP is not set +CONFIG_E1000E=y +# CONFIG_NET_VENDOR_I825XX is not set +CONFIG_SKY2=y +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_TOSHIBA is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=m @@ -359,16 +425,23 @@ CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_OF_PLATFORM=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_TIMERIOMEM=m CONFIG_RAW_DRIVER=m -# CONFIG_HWMON is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_OCORES=y +CONFIG_SENSORS_LM90=y +CONFIG_THERMAL=y # CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1374=y CONFIG_UIO=y CONFIG_UIO_PDRV=m CONFIG_UIO_PDRV_GENIRQ=m +# CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y @@ -380,15 +453,10 @@ CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y CONFIG_GFS2_FS=m -CONFIG_GFS2_FS_LOCKING_DLM=y -CONFIG_OCFS2_FS=m CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y CONFIG_NILFS2_FS=m CONFIG_QUOTA_NETLINK_INTERFACE=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_QFMT_V1=m -CONFIG_QFMT_V2=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=y CONFIG_CUSE=m @@ -414,6 +482,7 @@ CONFIG_HFSPLUS_FS=m CONFIG_BEFS_FS=m CONFIG_BFS_FS=m CONFIG_EFS_FS=m +CONFIG_JFFS2_FS=y CONFIG_CRAMFS=m CONFIG_SQUASHFS=m CONFIG_VXFS_FS=m @@ -426,7 +495,6 @@ CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_EXOFS_FS=m CONFIG_NFS_FS=m -CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_NFS_FSCACHE=y @@ -449,25 +517,6 @@ CONFIG_NCPFS_NLS=y CONFIG_NCPFS_EXTRAS=y CONFIG_CODA_FS=m CONFIG_AFS_FS=m -CONFIG_PARTITION_ADVANCED=y -CONFIG_ACORN_PARTITION=y -CONFIG_ACORN_PARTITION_ICS=y -CONFIG_ACORN_PARTITION_RISCIX=y -CONFIG_OSF_PARTITION=y -CONFIG_AMIGA_PARTITION=y -CONFIG_ATARI_PARTITION=y -CONFIG_MAC_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -CONFIG_LDM_PARTITION=y -CONFIG_SGI_PARTITION=y -CONFIG_ULTRIX_PARTITION=y -CONFIG_SUN_PARTITION=y -CONFIG_KARMA_PARTITION=y -CONFIG_EFI_PARTITION=y -CONFIG_SYSV68_PARTITION=y CONFIG_NLS=y CONFIG_NLS_DEFAULT="cp437" CONFIG_NLS_CODEPAGE_437=m @@ -517,12 +566,10 @@ CONFIG_SCHEDSTATS=y CONFIG_TIMER_STATS=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_SCHED_TRACER=y CONFIG_BLK_DEV_IO_TRACE=y CONFIG_KGDB=y CONFIG_SECURITY=y -CONFIG_SECURITY_NETWORK=y CONFIG_LSM_MMAP_MIN_ADDR=0 CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SELINUX_BOOTPARAM=y diff --git a/arch/mips/configs/pnx8335-stb225_defconfig b/arch/mips/configs/pnx8335_stb225_defconfig index f2925769dfa3..f2925769dfa3 100644 --- a/arch/mips/configs/pnx8335-stb225_defconfig +++ b/arch/mips/configs/pnx8335_stb225_defconfig diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550_jbs_defconfig index 1d1f2067f3e6..1d1f2067f3e6 100644 --- a/arch/mips/configs/pnx8550-jbs_defconfig +++ b/arch/mips/configs/pnx8550_jbs_defconfig diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550_stb810_defconfig index 15c66a571f99..15c66a571f99 100644 --- a/arch/mips/configs/pnx8550-stb810_defconfig +++ b/arch/mips/configs/pnx8550_stb810_defconfig diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250_swarm_defconfig index 5b0463ef9389..5b0463ef9389 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250_swarm_defconfig diff --git a/arch/mips/configs/sead3_defconfig b/arch/mips/configs/sead3_defconfig new file mode 100644 index 000000000000..e3eec68d9132 --- /dev/null +++ b/arch/mips/configs/sead3_defconfig @@ -0,0 +1,124 @@ +CONFIG_MIPS_SEAD3=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_HZ_100=y +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_MODULES=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_GLUEBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_BROADCOM_PHY=y +CONFIG_ICPLUS_PHY=y +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_CONSOLE_TRANSLATIONS is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_LEGACY_PTY_COUNT=32 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_SPI=y +CONFIG_SENSORS_ADT7475=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_STORAGE=y +CONFIG_MMC=y +CONFIG_MMC_DEBUG=y +CONFIG_MMC_SPI=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_M41T80=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_QUOTA=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +# CONFIG_FTRACE is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index ca400f7c3f59..63002a240c73 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -95,8 +95,8 @@ #ifndef cpu_has_smartmips #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) #endif -#ifndef kernel_uses_smartmips_rixi -#define kernel_uses_smartmips_rixi 0 +#ifndef cpu_has_rixi +#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) #endif #ifndef cpu_has_vtag_icache #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index f21b7c04e95a..554e2d29965d 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -94,6 +94,7 @@ #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 #define PRID_IMP_1004K 0x9900 +#define PRID_IMP_1074K 0x9a00 #define PRID_IMP_M14KC 0x9c00 /* @@ -319,6 +320,7 @@ enum cpu_type_enum { #define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ +#define MIPS_CPU_RIXI 0x00400000 /* CPU has TLB Read/eXec Inhibit */ /* * CPU ASE encodings diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 991b659e2548..37620db588be 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h @@ -33,13 +33,13 @@ REG32(_gic_base + segment##_##SECTION_OFS + offset) #define GIC_ABS_REG(segment, offset) \ - (_gic_base + segment##_##SECTION_OFS + offset##_##OFS) + (_gic_base + segment##_##SECTION_OFS + offset##_##OFS) #define GIC_REG_ABS_ADDR(segment, offset) \ - (_gic_base + segment##_##SECTION_OFS + offset) + (_gic_base + segment##_##SECTION_OFS + offset) #ifdef GICISBYTELITTLEENDIAN -#define GICREAD(reg, data) (data) = (reg), (data) = le32_to_cpu(data) -#define GICWRITE(reg, data) (reg) = cpu_to_le32(data) +#define GICREAD(reg, data) ((data) = (reg), (data) = le32_to_cpu(data)) +#define GICWRITE(reg, data) ((reg) = cpu_to_le32(data)) #define GICBIS(reg, bits) \ ({unsigned int data; \ GICREAD(reg, data); \ @@ -48,9 +48,9 @@ }) #else -#define GICREAD(reg, data) (data) = (reg) -#define GICWRITE(reg, data) (reg) = (data) -#define GICBIS(reg, bits) (reg) |= (bits) +#define GICREAD(reg, data) ((data) = (reg)) +#define GICWRITE(reg, data) ((reg) = (data)) +#define GICBIS(reg, bits) ((reg) |= (bits)) #endif @@ -304,15 +304,15 @@ GIC_SH_MAP_TO_VPE_REG_BIT(vpe)) struct gic_pcpu_mask { - DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS); + DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS); }; struct gic_pending_regs { - DECLARE_BITMAP(pending, GIC_NUM_INTRS); + DECLARE_BITMAP(pending, GIC_NUM_INTRS); }; struct gic_intrmask_regs { - DECLARE_BITMAP(intrmask, GIC_NUM_INTRS); + DECLARE_BITMAP(intrmask, GIC_NUM_INTRS); }; /* @@ -341,15 +341,44 @@ struct gic_shared_intr_map { unsigned int local_intr_mask; }; +/* GIC nomenclature for Core Interrupt Pins. */ +#define GIC_CPU_INT0 0 /* Core Interrupt 2 */ +#define GIC_CPU_INT1 1 /* . */ +#define GIC_CPU_INT2 2 /* . */ +#define GIC_CPU_INT3 3 /* . */ +#define GIC_CPU_INT4 4 /* . */ +#define GIC_CPU_INT5 5 /* Core Interrupt 5 */ + +/* Local GIC interrupts. */ +#define GIC_INT_TMR (GIC_CPU_INT5) +#define GIC_INT_PERFCTR (GIC_CPU_INT5) + +/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */ +#define GIC_CPU_TO_VEC_OFFSET (2) + +/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ +#define GIC_PIN_TO_VEC_OFFSET (1) + +extern unsigned long _gic_base; +extern unsigned int gic_irq_base; +extern unsigned int gic_irq_flags[]; +extern struct gic_shared_intr_map gic_shared_intr_map[]; + extern void gic_init(unsigned long gic_base_addr, unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, unsigned int intrmap_size, unsigned int irqbase); +extern void gic_clocksource_init(unsigned int); extern unsigned int gic_get_int(void); extern void gic_send_ipi(unsigned int intr); extern unsigned int plat_ipi_call_int_xlate(unsigned int); extern unsigned int plat_ipi_resched_int_xlate(unsigned int); extern void gic_bind_eic_interrupt(int irq, int set); extern unsigned int gic_get_timer_pending(void); +extern void gic_enable_interrupt(int irq_vec); +extern void gic_disable_interrupt(int irq_vec); +extern void gic_irq_ack(struct irq_data *d); +extern void gic_finish_irq(struct irq_data *d); +extern void gic_platform_init(int irqs, struct irq_chip *irq_controller); #endif /* _ASM_GICREGS_H */ diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index dde504477fac..a5e0f17ea77c 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -63,6 +63,10 @@ #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) #define AR934X_WMAC_SIZE 0x20000 +#define AR934X_EHCI_BASE 0x1b000000 +#define AR934X_EHCI_SIZE 0x200 +#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define AR934X_SRIF_SIZE 0x1000 /* * DDR_CTRL block @@ -288,6 +292,11 @@ #define AR933X_RESET_USB_PHY BIT(4) #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) +#define AR934X_RESET_USB_PHY_ANALOG BIT(11) +#define AR934X_RESET_USB_HOST BIT(5) +#define AR934X_RESET_USB_PHY BIT(4) +#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) + #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) @@ -399,4 +408,25 @@ #define AR933X_GPIO_COUNT 30 #define AR934X_GPIO_COUNT 23 +/* + * SRIF block + */ +#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 +#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 +#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 + +#define AR934X_SRIF_DDR_DPLL1_REG 0x240 +#define AR934X_SRIF_DDR_DPLL2_REG 0x244 +#define AR934X_SRIF_DDR_DPLL3_REG 0x248 + +#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 +#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff +#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff + +#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 + #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index e104ddb694a8..dbd5b5ad07a5 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -120,6 +120,8 @@ enum bcm63xx_regs_set { RSET_OHCI0, RSET_OHCI_PRIV, RSET_USBH_PRIV, + RSET_USBD, + RSET_USBDMA, RSET_MPI, RSET_PCMCIA, RSET_PCIE, @@ -162,6 +164,8 @@ enum bcm63xx_regs_set { #define RSET_UDC_SIZE 256 #define RSET_OHCI_SIZE 256 #define RSET_EHCI_SIZE 256 +#define RSET_USBD_SIZE 256 +#define RSET_USBDMA_SIZE 1280 #define RSET_PCMCIA_SIZE 12 #define RSET_M2M_SIZE 256 #define RSET_ATM_SIZE 4096 @@ -183,10 +187,11 @@ enum bcm63xx_regs_set { #define BCM_6328_GPIO_BASE (0xb0000080) #define BCM_6328_SPI_BASE (0xdeadbeef) #define BCM_6328_UDC0_BASE (0xdeadbeef) -#define BCM_6328_USBDMA_BASE (0xdeadbeef) -#define BCM_6328_OHCI0_BASE (0xdeadbeef) +#define BCM_6328_USBDMA_BASE (0xb000c000) +#define BCM_6328_OHCI0_BASE (0xb0002600) #define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef) -#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef) +#define BCM_6328_USBH_PRIV_BASE (0xb0002700) +#define BCM_6328_USBD_BASE (0xb0002400) #define BCM_6328_MPI_BASE (0xdeadbeef) #define BCM_6328_PCMCIA_BASE (0xdeadbeef) #define BCM_6328_PCIE_BASE (0xb0e40000) @@ -199,7 +204,7 @@ enum bcm63xx_regs_set { #define BCM_6328_ENETDMAC_BASE (0xb000da00) #define BCM_6328_ENETDMAS_BASE (0xb000dc00) #define BCM_6328_ENETSW_BASE (0xb0e00000) -#define BCM_6328_EHCI0_BASE (0x10002500) +#define BCM_6328_EHCI0_BASE (0xb0002500) #define BCM_6328_SDRAM_BASE (0xdeadbeef) #define BCM_6328_MEMC_BASE (0xdeadbeef) #define BCM_6328_DDR_BASE (0xb0003000) @@ -232,6 +237,7 @@ enum bcm63xx_regs_set { #define BCM_6338_OHCI0_BASE (0xdeadbeef) #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) +#define BCM_6338_USBD_BASE (0xdeadbeef) #define BCM_6338_MPI_BASE (0xfffe3160) #define BCM_6338_PCMCIA_BASE (0xdeadbeef) #define BCM_6338_PCIE_BASE (0xdeadbeef) @@ -286,6 +292,7 @@ enum bcm63xx_regs_set { #define BCM_6345_OHCI0_BASE (0xfffe2100) #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) +#define BCM_6345_USBD_BASE (0xdeadbeef) #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) #define BCM_6345_DSL_BASE (0xdeadbeef) #define BCM_6345_UBUS_BASE (0xdeadbeef) @@ -319,9 +326,11 @@ enum bcm63xx_regs_set { #define BCM_6348_GPIO_BASE (0xfffe0400) #define BCM_6348_SPI_BASE (0xfffe0c00) #define BCM_6348_UDC0_BASE (0xfffe1000) +#define BCM_6348_USBDMA_BASE (0xdeadbeef) #define BCM_6348_OHCI0_BASE (0xfffe1b00) #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) +#define BCM_6348_USBD_BASE (0xdeadbeef) #define BCM_6348_MPI_BASE (0xfffe2000) #define BCM_6348_PCMCIA_BASE (0xfffe2054) #define BCM_6348_PCIE_BASE (0xdeadbeef) @@ -362,9 +371,11 @@ enum bcm63xx_regs_set { #define BCM_6358_GPIO_BASE (0xfffe0080) #define BCM_6358_SPI_BASE (0xfffe0800) #define BCM_6358_UDC0_BASE (0xfffe0800) +#define BCM_6358_USBDMA_BASE (0xdeadbeef) #define BCM_6358_OHCI0_BASE (0xfffe1400) #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) #define BCM_6358_USBH_PRIV_BASE (0xfffe1500) +#define BCM_6358_USBD_BASE (0xdeadbeef) #define BCM_6358_MPI_BASE (0xfffe1000) #define BCM_6358_PCMCIA_BASE (0xfffe1054) #define BCM_6358_PCIE_BASE (0xdeadbeef) @@ -406,9 +417,11 @@ enum bcm63xx_regs_set { #define BCM_6368_GPIO_BASE (0xb0000080) #define BCM_6368_SPI_BASE (0xb0000800) #define BCM_6368_UDC0_BASE (0xdeadbeef) +#define BCM_6368_USBDMA_BASE (0xb0004800) #define BCM_6368_OHCI0_BASE (0xb0001600) #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) #define BCM_6368_USBH_PRIV_BASE (0xb0001700) +#define BCM_6368_USBD_BASE (0xb0001400) #define BCM_6368_MPI_BASE (0xb0001000) #define BCM_6368_PCMCIA_BASE (0xb0001054) #define BCM_6368_PCIE_BASE (0xdeadbeef) @@ -458,6 +471,8 @@ extern const unsigned long *bcm63xx_regs_base; __GEN_RSET_BASE(__cpu, OHCI0) \ __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ __GEN_RSET_BASE(__cpu, USBH_PRIV) \ + __GEN_RSET_BASE(__cpu, USBD) \ + __GEN_RSET_BASE(__cpu, USBDMA) \ __GEN_RSET_BASE(__cpu, MPI) \ __GEN_RSET_BASE(__cpu, PCMCIA) \ __GEN_RSET_BASE(__cpu, PCIE) \ @@ -499,6 +514,8 @@ extern const unsigned long *bcm63xx_regs_base; [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ + [RSET_USBD] = BCM_## __cpu ##_USBD_BASE, \ + [RSET_USBDMA] = BCM_## __cpu ##_USBDMA_BASE, \ [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \ @@ -569,6 +586,13 @@ enum bcm63xx_irq { IRQ_ENET_PHY, IRQ_OHCI0, IRQ_EHCI0, + IRQ_USBD, + IRQ_USBD_RXDMA0, + IRQ_USBD_TXDMA0, + IRQ_USBD_RXDMA1, + IRQ_USBD_TXDMA1, + IRQ_USBD_RXDMA2, + IRQ_USBD_TXDMA2, IRQ_ENET0_RXDMA, IRQ_ENET0_TXDMA, IRQ_ENET1_RXDMA, @@ -602,8 +626,15 @@ enum bcm63xx_irq { #define BCM_6328_ENET0_IRQ 0 #define BCM_6328_ENET1_IRQ 0 #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) -#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) -#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) +#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) +#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) +#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4) +#define BCM_6328_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5) +#define BCM_6328_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6) +#define BCM_6328_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7) +#define BCM_6328_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_6328_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9) +#define BCM_6328_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10) #define BCM_6328_PCMCIA_IRQ 0 #define BCM_6328_ENET0_RXDMA_IRQ 0 #define BCM_6328_ENET0_TXDMA_IRQ 0 @@ -615,10 +646,10 @@ enum bcm63xx_irq { #define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1) #define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2) #define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3) -#define BCM_6328_ENETSW_TXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 4) -#define BCM_6328_ENETSW_TXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 5) -#define BCM_6328_ENETSW_TXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 6) -#define BCM_6328_ENETSW_TXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 7) +#define BCM_6328_ENETSW_TXDMA0_IRQ 0 +#define BCM_6328_ENETSW_TXDMA1_IRQ 0 +#define BCM_6328_ENETSW_TXDMA2_IRQ 0 +#define BCM_6328_ENETSW_TXDMA3_IRQ 0 #define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31) #define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11) @@ -642,6 +673,13 @@ enum bcm63xx_irq { #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) #define BCM_6338_OHCI0_IRQ 0 #define BCM_6338_EHCI0_IRQ 0 +#define BCM_6338_USBD_IRQ 0 +#define BCM_6338_USBD_RXDMA0_IRQ 0 +#define BCM_6338_USBD_TXDMA0_IRQ 0 +#define BCM_6338_USBD_RXDMA1_IRQ 0 +#define BCM_6338_USBD_TXDMA1_IRQ 0 +#define BCM_6338_USBD_RXDMA2_IRQ 0 +#define BCM_6338_USBD_TXDMA2_IRQ 0 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) #define BCM_6338_ENET1_RXDMA_IRQ 0 @@ -673,6 +711,13 @@ enum bcm63xx_irq { #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) #define BCM_6345_OHCI0_IRQ 0 #define BCM_6345_EHCI0_IRQ 0 +#define BCM_6345_USBD_IRQ 0 +#define BCM_6345_USBD_RXDMA0_IRQ 0 +#define BCM_6345_USBD_TXDMA0_IRQ 0 +#define BCM_6345_USBD_RXDMA1_IRQ 0 +#define BCM_6345_USBD_TXDMA1_IRQ 0 +#define BCM_6345_USBD_RXDMA2_IRQ 0 +#define BCM_6345_USBD_TXDMA2_IRQ 0 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) #define BCM_6345_ENET1_RXDMA_IRQ 0 @@ -704,6 +749,13 @@ enum bcm63xx_irq { #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) #define BCM_6348_EHCI0_IRQ 0 +#define BCM_6348_USBD_IRQ 0 +#define BCM_6348_USBD_RXDMA0_IRQ 0 +#define BCM_6348_USBD_TXDMA0_IRQ 0 +#define BCM_6348_USBD_RXDMA1_IRQ 0 +#define BCM_6348_USBD_TXDMA1_IRQ 0 +#define BCM_6348_USBD_RXDMA2_IRQ 0 +#define BCM_6348_USBD_TXDMA2_IRQ 0 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) @@ -735,6 +787,13 @@ enum bcm63xx_irq { #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) +#define BCM_6358_USBD_IRQ 0 +#define BCM_6358_USBD_RXDMA0_IRQ 0 +#define BCM_6358_USBD_TXDMA0_IRQ 0 +#define BCM_6358_USBD_RXDMA1_IRQ 0 +#define BCM_6358_USBD_TXDMA1_IRQ 0 +#define BCM_6358_USBD_RXDMA2_IRQ 0 +#define BCM_6358_USBD_TXDMA2_IRQ 0 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) @@ -775,6 +834,13 @@ enum bcm63xx_irq { #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) +#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_6368_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 26) +#define BCM_6368_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 27) +#define BCM_6368_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 28) +#define BCM_6368_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 29) +#define BCM_6368_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 30) +#define BCM_6368_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 31) #define BCM_6368_PCMCIA_IRQ 0 #define BCM_6368_ENET0_RXDMA_IRQ 0 #define BCM_6368_ENET0_TXDMA_IRQ 0 @@ -815,6 +881,13 @@ extern const int *bcm63xx_irqs; [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ + [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \ + [IRQ_USBD_RXDMA0] = BCM_## __cpu ##_USBD_RXDMA0_IRQ, \ + [IRQ_USBD_TXDMA0] = BCM_## __cpu ##_USBD_TXDMA0_IRQ, \ + [IRQ_USBD_RXDMA1] = BCM_## __cpu ##_USBD_RXDMA1_IRQ, \ + [IRQ_USBD_TXDMA1] = BCM_## __cpu ##_USBD_TXDMA1_IRQ, \ + [IRQ_USBD_RXDMA2] = BCM_## __cpu ##_USBD_RXDMA2_IRQ, \ + [IRQ_USBD_TXDMA2] = BCM_## __cpu ##_USBD_TXDMA2_IRQ, \ [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \ [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \ [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h new file mode 100644 index 000000000000..5d6d6986f40b --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h @@ -0,0 +1,17 @@ +#ifndef BCM63XX_DEV_USB_USBD_H_ +#define BCM63XX_DEV_USB_USBD_H_ + +/* + * usb device platform data + */ +struct bcm63xx_usbd_platform_data { + /* board can only support full speed (USB 1.1) */ + int use_fullspeed; + + /* 0-based port index, for chips with >1 USB PHY */ + int port_no; +}; + +int bcm63xx_usbd_register(const struct bcm63xx_usbd_platform_data *pd); + +#endif /* BCM63XX_DEV_USB_USBD_H_ */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h new file mode 100644 index 000000000000..a5bbff31c898 --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h @@ -0,0 +1,38 @@ +#ifndef BCM63XX_IUDMA_H_ +#define BCM63XX_IUDMA_H_ + +#include <linux/types.h> + +/* + * rx/tx dma descriptor + */ +struct bcm_enet_desc { + u32 len_stat; + u32 address; +}; + +/* control */ +#define DMADESC_LENGTH_SHIFT 16 +#define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT) +#define DMADESC_OWNER_MASK (1 << 15) +#define DMADESC_EOP_MASK (1 << 14) +#define DMADESC_SOP_MASK (1 << 13) +#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK) +#define DMADESC_WRAP_MASK (1 << 12) +#define DMADESC_USB_NOZERO_MASK (1 << 1) +#define DMADESC_USB_ZERO_MASK (1 << 0) + +/* status */ +#define DMADESC_UNDER_MASK (1 << 9) +#define DMADESC_APPEND_CRC (1 << 8) +#define DMADESC_OVSIZE_MASK (1 << 4) +#define DMADESC_RXER_MASK (1 << 2) +#define DMADESC_CRC_MASK (1 << 1) +#define DMADESC_OV_MASK (1 << 0) +#define DMADESC_ERR_MASK (DMADESC_UNDER_MASK | \ + DMADESC_OVSIZE_MASK | \ + DMADESC_RXER_MASK | \ + DMADESC_CRC_MASK | \ + DMADESC_OV_MASK) + +#endif /* ! BCM63XX_IUDMA_H_ */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 61f2a2a5099d..12963d05da86 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -161,6 +161,7 @@ /* External Interrupt Configuration register */ #define PERF_EXTIRQ_CFG_REG_6328 0x18 #define PERF_EXTIRQ_CFG_REG_6338 0x14 +#define PERF_EXTIRQ_CFG_REG_6345 0x14 #define PERF_EXTIRQ_CFG_REG_6348 0x14 #define PERF_EXTIRQ_CFG_REG_6358 0x14 #define PERF_EXTIRQ_CFG_REG_6368 0x18 @@ -543,6 +544,12 @@ #define GPIO_MODE_6368_SPI_SSN5 (1 << 31) +#define GPIO_PINMUX_OTHR_REG 0x24 +#define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12 +#define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) +#define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) +#define GPIO_PINMUX_OTHR_6328_USB_DEV (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) + #define GPIO_BASEMODE_6368_REG 0x38 #define GPIO_BASEMODE_6368_UART2 0x1 #define GPIO_BASEMODE_6368_GPIO 0x0 @@ -670,6 +677,12 @@ #define ENETDMA_BUFALLOC_FORCE_SHIFT 31 #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) +/* Global interrupt status */ +#define ENETDMA_GLB_IRQSTAT_REG (0x40) + +/* Global interrupt mask */ +#define ENETDMA_GLB_IRQMASK_REG (0x44) + /* Channel Configuration register */ #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) #define ENETDMA_CHANCFG_EN_SHIFT 0 @@ -709,9 +722,11 @@ /* Channel Configuration register */ #define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10) #define ENETDMAC_CHANCFG_EN_SHIFT 0 -#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) +#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT) #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1 -#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) +#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT) +#define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2 +#define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT) /* Interrupt Control/Status register */ #define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10) @@ -770,6 +785,8 @@ #define USBH_PRIV_SWAP_6358_REG 0x0 #define USBH_PRIV_SWAP_6368_REG 0x1c +#define USBH_PRIV_SWAP_USBD_SHIFT 6 +#define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT) #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 @@ -779,6 +796,12 @@ #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) +#define USBH_PRIV_UTMI_CTL_6368_REG 0x10 +#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12 +#define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT) +#define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0 +#define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT) + #define USBH_PRIV_TEST_6358_REG 0x24 #define USBH_PRIV_TEST_6368_REG 0x14 @@ -787,6 +810,147 @@ #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) +/************************************************************************* + * _REG relative to RSET_USBD + *************************************************************************/ + +/* General control */ +#define USBD_CONTROL_REG 0x00 +#define USBD_CONTROL_TXZLENINS_SHIFT 14 +#define USBD_CONTROL_TXZLENINS_MASK (1 << USBD_CONTROL_TXZLENINS_SHIFT) +#define USBD_CONTROL_AUTO_CSRS_SHIFT 13 +#define USBD_CONTROL_AUTO_CSRS_MASK (1 << USBD_CONTROL_AUTO_CSRS_SHIFT) +#define USBD_CONTROL_RXZSCFG_SHIFT 12 +#define USBD_CONTROL_RXZSCFG_MASK (1 << USBD_CONTROL_RXZSCFG_SHIFT) +#define USBD_CONTROL_INIT_SEL_SHIFT 8 +#define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT) +#define USBD_CONTROL_FIFO_RESET_SHIFT 6 +#define USBD_CONTROL_FIFO_RESET_MASK (3 << USBD_CONTROL_FIFO_RESET_SHIFT) +#define USBD_CONTROL_SETUPERRLOCK_SHIFT 5 +#define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT) +#define USBD_CONTROL_DONE_CSRS_SHIFT 0 +#define USBD_CONTROL_DONE_CSRS_MASK (1 << USBD_CONTROL_DONE_CSRS_SHIFT) + +/* Strap options */ +#define USBD_STRAPS_REG 0x04 +#define USBD_STRAPS_APP_SELF_PWR_SHIFT 10 +#define USBD_STRAPS_APP_SELF_PWR_MASK (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT) +#define USBD_STRAPS_APP_DISCON_SHIFT 9 +#define USBD_STRAPS_APP_DISCON_MASK (1 << USBD_STRAPS_APP_DISCON_SHIFT) +#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8 +#define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT) +#define USBD_STRAPS_APP_RMTWKUP_SHIFT 6 +#define USBD_STRAPS_APP_RMTWKUP_MASK (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT) +#define USBD_STRAPS_APP_RAM_IF_SHIFT 7 +#define USBD_STRAPS_APP_RAM_IF_MASK (1 << USBD_STRAPS_APP_RAM_IF_SHIFT) +#define USBD_STRAPS_APP_8BITPHY_SHIFT 2 +#define USBD_STRAPS_APP_8BITPHY_MASK (1 << USBD_STRAPS_APP_8BITPHY_SHIFT) +#define USBD_STRAPS_SPEED_SHIFT 0 +#define USBD_STRAPS_SPEED_MASK (3 << USBD_STRAPS_SPEED_SHIFT) + +/* Stall control */ +#define USBD_STALL_REG 0x08 +#define USBD_STALL_UPDATE_SHIFT 7 +#define USBD_STALL_UPDATE_MASK (1 << USBD_STALL_UPDATE_SHIFT) +#define USBD_STALL_ENABLE_SHIFT 6 +#define USBD_STALL_ENABLE_MASK (1 << USBD_STALL_ENABLE_SHIFT) +#define USBD_STALL_EPNUM_SHIFT 0 +#define USBD_STALL_EPNUM_MASK (0xf << USBD_STALL_EPNUM_SHIFT) + +/* General status */ +#define USBD_STATUS_REG 0x0c +#define USBD_STATUS_SOF_SHIFT 16 +#define USBD_STATUS_SOF_MASK (0x7ff << USBD_STATUS_SOF_SHIFT) +#define USBD_STATUS_SPD_SHIFT 12 +#define USBD_STATUS_SPD_MASK (3 << USBD_STATUS_SPD_SHIFT) +#define USBD_STATUS_ALTINTF_SHIFT 8 +#define USBD_STATUS_ALTINTF_MASK (0xf << USBD_STATUS_ALTINTF_SHIFT) +#define USBD_STATUS_INTF_SHIFT 4 +#define USBD_STATUS_INTF_MASK (0xf << USBD_STATUS_INTF_SHIFT) +#define USBD_STATUS_CFG_SHIFT 0 +#define USBD_STATUS_CFG_MASK (0xf << USBD_STATUS_CFG_SHIFT) + +/* Other events */ +#define USBD_EVENTS_REG 0x10 +#define USBD_EVENTS_USB_LINK_SHIFT 10 +#define USBD_EVENTS_USB_LINK_MASK (1 << USBD_EVENTS_USB_LINK_SHIFT) + +/* IRQ status */ +#define USBD_EVENT_IRQ_STATUS_REG 0x14 + +/* IRQ level (2 bits per IRQ event) */ +#define USBD_EVENT_IRQ_CFG_HI_REG 0x18 + +#define USBD_EVENT_IRQ_CFG_LO_REG 0x1c + +#define USBD_EVENT_IRQ_CFG_SHIFT(x) ((x & 0xf) << 1) +#define USBD_EVENT_IRQ_CFG_MASK(x) (3 << USBD_EVENT_IRQ_CFG_SHIFT(x)) +#define USBD_EVENT_IRQ_CFG_RISING(x) (0 << USBD_EVENT_IRQ_CFG_SHIFT(x)) +#define USBD_EVENT_IRQ_CFG_FALLING(x) (1 << USBD_EVENT_IRQ_CFG_SHIFT(x)) + +/* IRQ mask (1=unmasked) */ +#define USBD_EVENT_IRQ_MASK_REG 0x20 + +/* IRQ bits */ +#define USBD_EVENT_IRQ_USB_LINK 10 +#define USBD_EVENT_IRQ_SETCFG 9 +#define USBD_EVENT_IRQ_SETINTF 8 +#define USBD_EVENT_IRQ_ERRATIC_ERR 7 +#define USBD_EVENT_IRQ_SET_CSRS 6 +#define USBD_EVENT_IRQ_SUSPEND 5 +#define USBD_EVENT_IRQ_EARLY_SUSPEND 4 +#define USBD_EVENT_IRQ_SOF 3 +#define USBD_EVENT_IRQ_ENUM_ON 2 +#define USBD_EVENT_IRQ_SETUP 1 +#define USBD_EVENT_IRQ_USB_RESET 0 + +/* TX FIFO partitioning */ +#define USBD_TXFIFO_CONFIG_REG 0x40 +#define USBD_TXFIFO_CONFIG_END_SHIFT 16 +#define USBD_TXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) +#define USBD_TXFIFO_CONFIG_START_SHIFT 0 +#define USBD_TXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) + +/* RX FIFO partitioning */ +#define USBD_RXFIFO_CONFIG_REG 0x44 +#define USBD_RXFIFO_CONFIG_END_SHIFT 16 +#define USBD_RXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) +#define USBD_RXFIFO_CONFIG_START_SHIFT 0 +#define USBD_RXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) + +/* TX FIFO/endpoint configuration */ +#define USBD_TXFIFO_EPSIZE_REG 0x48 + +/* RX FIFO/endpoint configuration */ +#define USBD_RXFIFO_EPSIZE_REG 0x4c + +/* Endpoint<->DMA mappings */ +#define USBD_EPNUM_TYPEMAP_REG 0x50 +#define USBD_EPNUM_TYPEMAP_TYPE_SHIFT 8 +#define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT) +#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0 +#define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT) + +/* Misc per-endpoint settings */ +#define USBD_CSR_SETUPADDR_REG 0x80 +#define USBD_CSR_SETUPADDR_DEF 0xb550 + +#define USBD_CSR_EP_REG(x) (0x84 + (x) * 4) +#define USBD_CSR_EP_MAXPKT_SHIFT 19 +#define USBD_CSR_EP_MAXPKT_MASK (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT) +#define USBD_CSR_EP_ALTIFACE_SHIFT 15 +#define USBD_CSR_EP_ALTIFACE_MASK (0xf << USBD_CSR_EP_ALTIFACE_SHIFT) +#define USBD_CSR_EP_IFACE_SHIFT 11 +#define USBD_CSR_EP_IFACE_MASK (0xf << USBD_CSR_EP_IFACE_SHIFT) +#define USBD_CSR_EP_CFG_SHIFT 7 +#define USBD_CSR_EP_CFG_MASK (0xf << USBD_CSR_EP_CFG_SHIFT) +#define USBD_CSR_EP_TYPE_SHIFT 5 +#define USBD_CSR_EP_TYPE_MASK (3 << USBD_CSR_EP_TYPE_SHIFT) +#define USBD_CSR_EP_DIR_SHIFT 4 +#define USBD_CSR_EP_DIR_MASK (1 << USBD_CSR_EP_DIR_SHIFT) +#define USBD_CSR_EP_LOG_SHIFT 0 +#define USBD_CSR_EP_LOG_MASK (0xf << USBD_CSR_EP_LOG_SHIFT) + /************************************************************************* * _REG relative to RSET_MPI diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h index 474daaa53497..b0dd4bb53f7e 100644 --- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h @@ -5,6 +5,7 @@ #include <linux/gpio.h> #include <linux/leds.h> #include <bcm63xx_dev_enet.h> +#include <bcm63xx_dev_usb_usbd.h> #include <bcm63xx_dev_dsp.h> /* @@ -44,6 +45,7 @@ struct board_info { unsigned int has_pccard:1; unsigned int has_ohci0:1; unsigned int has_ehci0:1; + unsigned int has_usbd:1; unsigned int has_dsp:1; unsigned int has_uart0:1; unsigned int has_uart1:1; @@ -52,6 +54,9 @@ struct board_info { struct bcm63xx_enet_platform_data enet0; struct bcm63xx_enet_platform_data enet1; + /* USB config */ + struct bcm63xx_usbd_platform_data usbd; + /* DSP config */ struct bcm63xx_dsp_platform_data dsp; diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h index a58addb98cfd..375ad0c815fe 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h @@ -58,7 +58,7 @@ #define cpu_has_veic 0 #define cpu_hwrena_impl_bits 0xc0000000 -#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON) +#define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON) #define ARCH_HAS_IRQ_PER_CPU 1 #define ARCH_HAS_SPINLOCK_PREFETCH 1 diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h index c22a3078bf11..ff0d4909d848 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/irq.h +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h @@ -21,10 +21,11 @@ enum octeon_irq { OCTEON_IRQ_TIMER, /* sources in CIU_INTX_EN0 */ OCTEON_IRQ_WORKQ0, - OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 16, - OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15, - OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16, + OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 64, + OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 32, OCTEON_IRQ_MBOX1, + OCTEON_IRQ_MBOX2, + OCTEON_IRQ_MBOX3, OCTEON_IRQ_PCI_INT0, OCTEON_IRQ_PCI_INT1, OCTEON_IRQ_PCI_INT2, diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h index 318f982f04ff..c6b63a409641 100644 --- a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h +++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h @@ -20,4 +20,6 @@ #define MIPS_CPU_TIMER_IRQ 7 +#define MAX_IM 5 + #endif /* _FALCON_IRQ__ */ diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h index b385252584ee..fccac3592651 100644 --- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h @@ -57,6 +57,10 @@ extern __iomem void *ltq_sys1_membase; #define ltq_sys1_w32_mask(clear, set, reg) \ ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg) +/* allow the gpio and pinctrl drivers to talk to eachother */ +extern int pinctrl_falcon_get_range_size(int id); +extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range); + /* * to keep the irq code generic we need to define this to 0 as falcon * has no EIU/EBU diff --git a/arch/mips/include/asm/mach-lantiq/gpio.h b/arch/mips/include/asm/mach-lantiq/gpio.h index f79505b43609..9ba1caebca5f 100644 --- a/arch/mips/include/asm/mach-lantiq/gpio.h +++ b/arch/mips/include/asm/mach-lantiq/gpio.h @@ -1,10 +1,7 @@ #ifndef __ASM_MIPS_MACH_LANTIQ_GPIO_H #define __ASM_MIPS_MACH_LANTIQ_GPIO_H -static inline int gpio_to_irq(unsigned int gpio) -{ - return -1; -} +#define gpio_to_irq __gpio_to_irq #define gpio_get_value __gpio_get_value #define gpio_set_value __gpio_set_value diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h index aa0b3b866f84..5eadfe582529 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h @@ -21,4 +21,6 @@ #define MIPS_CPU_TIMER_IRQ 7 +#define MAX_IM 5 + #endif diff --git a/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h index 27aaaa5d925e..7f3e3f9bd23a 100644 --- a/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h @@ -4,9 +4,10 @@ * for more details. * * Copyright (C) 2003, 2004 Chris Dearman + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) */ -#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H +#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H /* @@ -16,7 +17,7 @@ #define cpu_has_tlb 1 #define cpu_has_4kex 1 #define cpu_has_4k_cache 1 -#define cpu_has_fpu 0 +/* #define cpu_has_fpu ? */ /* #define cpu_has_32fpr ? */ #define cpu_has_counter 1 /* #define cpu_has_watch ? */ @@ -27,15 +28,19 @@ /* #define cpu_has_prefetch ? */ #define cpu_has_mcheck 1 /* #define cpu_has_ejtag ? */ +#ifdef CONFIG_CPU_HAS_LLSC #define cpu_has_llsc 1 +#else +#define cpu_has_llsc 0 +#endif /* #define cpu_has_vtag_icache ? */ /* #define cpu_has_dc_aliases ? */ /* #define cpu_has_ic_fills_f_dc ? */ -#define cpu_has_clo_clz 1 #define cpu_has_nofpuex 0 /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ /* #define cpu_has_inclusive_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 #endif #ifdef CONFIG_CPU_MIPS64 @@ -57,11 +62,11 @@ /* #define cpu_has_vtag_icache ? */ /* #define cpu_has_dc_aliases ? */ /* #define cpu_has_ic_fills_f_dc ? */ -#define cpu_has_clo_clz 1 #define cpu_has_nofpuex 0 /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ /* #define cpu_has_inclusive_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 #endif #endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h new file mode 100644 index 000000000000..652ea4c38cda --- /dev/null +++ b/arch/mips/include/asm/mach-sead3/irq.h @@ -0,0 +1,9 @@ +#ifndef __ASM_MACH_MIPS_IRQ_H +#define __ASM_MACH_MIPS_IRQ_H + +#define NR_IRQS 256 + + +#include_next <irq.h> + +#endif /* __ASM_MACH_MIPS_IRQ_H */ diff --git a/arch/mips/include/asm/mach-sead3/kernel-entry-init.h b/arch/mips/include/asm/mach-sead3/kernel-entry-init.h new file mode 100644 index 000000000000..3dfbd8e7947f --- /dev/null +++ b/arch/mips/include/asm/mach-sead3/kernel-entry-init.h @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Chris Dearman (chris@mips.com) + * Copyright (C) 2007 Mips Technologies, Inc. + */ +#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H +#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H + + .macro kernel_entry_setup +#ifdef CONFIG_MIPS_MT_SMTC + mfc0 t0, CP0_CONFIG + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 1 + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 2 + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 3 + and t0, 1<<2 + bnez t0, 0f +9 : + /* Assume we came from YAMON... */ + PTR_LA v0, 0x9fc00534 /* YAMON print */ + lw v0, (v0) + move a0, zero + PTR_LA a1, nonmt_processor + jal v0 + + PTR_LA v0, 0x9fc00520 /* YAMON exit */ + lw v0, (v0) + li a0, 1 + jal v0 + +1 : b 1b + + __INITDATA +nonmt_processor : + .asciz "SMTC kernel requires the MT ASE to run\n" + __FINIT +0 : +#endif + .endm + +/* + * Do SMP slave processor setup necessary before we can safely execute C code. + */ + .macro smp_slave_setup + .endm + +#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */ diff --git a/arch/mips/include/asm/mach-mipssim/war.h b/arch/mips/include/asm/mach-sead3/war.h index c8a74a3515e0..7c6931d5f45f 100644 --- a/arch/mips/include/asm/mach-mipssim/war.h +++ b/arch/mips/include/asm/mach-sead3/war.h @@ -5,8 +5,8 @@ * * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> */ -#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H -#define __ASM_MIPS_MACH_MIPSSIM_WAR_H +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H +#define __ASM_MIPS_MACH_MIPS_WAR_H #define R4600_V1_INDEX_ICACHEOP_WAR 0 #define R4600_V1_HIT_CACHEOP_WAR 0 @@ -14,12 +14,12 @@ #define R5432_CP0_INTERRUPT_WAR 0 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 1 +#define MIPS_CACHE_SYNC_WAR 1 #define TX49XX_ICACHE_INDEX_INV_WAR 0 #define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 #define R10000_LLSC_WAR 0 #define MIPS34K_MISSED_ITLB_WAR 0 -#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */ +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h index 5447d9fc4219..669244815753 100644 --- a/arch/mips/include/asm/mips-boards/maltaint.h +++ b/arch/mips/include/asm/mips-boards/maltaint.h @@ -1,31 +1,16 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Defines for the Malta interrupt controller. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * + * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved. + * Carsten Langgaard <carstenl@mips.com> + * Steven J. Hill <sjhill@mips.com> */ #ifndef _MIPS_MALTAINT_H #define _MIPS_MALTAINT_H -#include <irq.h> +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) /* * Interrupts 0..15 are used for Malta ISA compatible interrupts @@ -78,26 +63,6 @@ #define MSC01E_INT_PERFCTR 10 #define MSC01E_INT_CPUCTR 11 -/* GIC's Nomenclature for Core Interrupt Pins on the Malta */ -#define GIC_CPU_INT0 0 /* Core Interrupt 2 */ -#define GIC_CPU_INT1 1 /* . */ -#define GIC_CPU_INT2 2 /* . */ -#define GIC_CPU_INT3 3 /* . */ -#define GIC_CPU_INT4 4 /* . */ -#define GIC_CPU_INT5 5 /* Core Interrupt 5 */ - -/* MALTA GIC local interrupts */ -#define GIC_INT_TMR (GIC_CPU_INT5) -#define GIC_INT_PERFCTR (GIC_CPU_INT5) - -/* GIC constants */ -/* Add 2 to convert non-eic hw int # to eic vector # */ -#define GIC_CPU_TO_VEC_OFFSET (2) -/* If we map an intr to pin X, GIC will actually generate vector X+1 */ -#define GIC_PIN_TO_VEC_OFFSET (1) - -#define GIC_EXT_INTR(x) x - /* External Interrupts used for IPI */ #define GIC_IPI_EXT_INTR_RESCHED_VPE0 16 #define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17 @@ -108,10 +73,4 @@ #define GIC_IPI_EXT_INTR_RESCHED_VPE3 22 #define GIC_IPI_EXT_INTR_CALLFNC_VPE3 23 -#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) - -#ifndef __ASSEMBLY__ -extern void maltaint_init(void); -#endif - #endif /* !(_MIPS_MALTAINT_H) */ diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h new file mode 100644 index 000000000000..d634d9a807f6 --- /dev/null +++ b/arch/mips/include/asm/mips-boards/sead3int.h @@ -0,0 +1,19 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved. + * Douglas Leung <douglas@mips.com> + * Steven J. Hill <sjhill@mips.com> + */ +#ifndef _MIPS_SEAD3INT_H +#define _MIPS_SEAD3INT_H + +/* SEAD-3 GIC address space definitions. */ +#define GIC_BASE_ADDR 0x1b1c0000 +#define GIC_ADDRSPACE_SZ (128 * 1024) + +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0) + +#endif /* !(_MIPS_SEAD3INT_H) */ diff --git a/arch/mips/include/asm/mips-boards/simint.h b/arch/mips/include/asm/mips-boards/simint.h deleted file mode 100644 index 8ef6db76d5c1..000000000000 --- a/arch/mips/include/asm/mips-boards/simint.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#ifndef _MIPS_SIMINT_H -#define _MIPS_SIMINT_H - -#include <irq.h> - -#define SIM_INT_BASE 0 -#define MIPSCPU_INT_MB0 2 -#define MIPS_CPU_TIMER_IRQ 7 - - -#define MSC01E_INT_BASE 64 - -#define MSC01E_INT_CPUCTR 11 - -#endif diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 7f87d824eeb0..528fda1e957c 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -590,12 +590,15 @@ #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) +#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) +#define MIPS_CONF6_SYND (_ULCAST_(1) << 13) + #define MIPS_CONF7_WII (_ULCAST_(1) << 31) #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h index 30d68f2365e0..542ee09510b3 100644 --- a/arch/mips/include/asm/octeon/cvmx-agl-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -106,6 +106,7 @@ union cvmx_agl_gmx_bad_reg { uint64_t u64; struct cvmx_agl_gmx_bad_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t txpsh1:1; uint64_t txpop1:1; @@ -120,8 +121,25 @@ union cvmx_agl_gmx_bad_reg { uint64_t reserved_4_21:18; uint64_t out_ovr:2; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t out_ovr:2; + uint64_t reserved_4_21:18; + uint64_t loststat:2; + uint64_t reserved_24_25:2; + uint64_t statovr:1; + uint64_t reserved_27_31:5; + uint64_t ovrflw:1; + uint64_t txpop:1; + uint64_t txpsh:1; + uint64_t ovrflw1:1; + uint64_t txpop1:1; + uint64_t txpsh1:1; + uint64_t reserved_38_63:26; +#endif } s; struct cvmx_agl_gmx_bad_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t txpsh1:1; uint64_t txpop1:1; @@ -136,9 +154,26 @@ union cvmx_agl_gmx_bad_reg { uint64_t reserved_4_21:18; uint64_t out_ovr:2; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t out_ovr:2; + uint64_t reserved_4_21:18; + uint64_t loststat:1; + uint64_t reserved_23_25:3; + uint64_t statovr:1; + uint64_t reserved_27_31:5; + uint64_t ovrflw:1; + uint64_t txpop:1; + uint64_t txpsh:1; + uint64_t ovrflw1:1; + uint64_t txpop1:1; + uint64_t txpsh1:1; + uint64_t reserved_38_63:26; +#endif } cn52xx; struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1; struct cvmx_agl_gmx_bad_reg_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t txpsh:1; uint64_t txpop:1; @@ -150,32 +185,64 @@ union cvmx_agl_gmx_bad_reg { uint64_t reserved_3_21:19; uint64_t out_ovr:1; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t out_ovr:1; + uint64_t reserved_3_21:19; + uint64_t loststat:1; + uint64_t reserved_23_25:3; + uint64_t statovr:1; + uint64_t reserved_27_31:5; + uint64_t ovrflw:1; + uint64_t txpop:1; + uint64_t txpsh:1; + uint64_t reserved_35_63:29; +#endif } cn56xx; struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1; + struct cvmx_agl_gmx_bad_reg_s cn61xx; struct cvmx_agl_gmx_bad_reg_s cn63xx; struct cvmx_agl_gmx_bad_reg_s cn63xxp1; + struct cvmx_agl_gmx_bad_reg_s cn66xx; + struct cvmx_agl_gmx_bad_reg_s cn68xx; + struct cvmx_agl_gmx_bad_reg_s cn68xxp1; }; union cvmx_agl_gmx_bist { uint64_t u64; struct cvmx_agl_gmx_bist_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t status:25; +#else + uint64_t status:25; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_agl_gmx_bist_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t status:10; +#else + uint64_t status:10; + uint64_t reserved_10_63:54; +#endif } cn52xx; struct cvmx_agl_gmx_bist_cn52xx cn52xxp1; struct cvmx_agl_gmx_bist_cn52xx cn56xx; struct cvmx_agl_gmx_bist_cn52xx cn56xxp1; + struct cvmx_agl_gmx_bist_s cn61xx; struct cvmx_agl_gmx_bist_s cn63xx; struct cvmx_agl_gmx_bist_s cn63xxp1; + struct cvmx_agl_gmx_bist_s cn66xx; + struct cvmx_agl_gmx_bist_s cn68xx; + struct cvmx_agl_gmx_bist_s cn68xxp1; }; union cvmx_agl_gmx_drv_ctl { uint64_t u64; struct cvmx_agl_gmx_drv_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t byp_en1:1; uint64_t reserved_45_47:3; @@ -188,16 +255,39 @@ union cvmx_agl_gmx_drv_ctl { uint64_t pctl:5; uint64_t reserved_5_7:3; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t reserved_5_7:3; + uint64_t pctl:5; + uint64_t reserved_13_15:3; + uint64_t byp_en:1; + uint64_t reserved_17_31:15; + uint64_t nctl1:5; + uint64_t reserved_37_39:3; + uint64_t pctl1:5; + uint64_t reserved_45_47:3; + uint64_t byp_en1:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_agl_gmx_drv_ctl_s cn52xx; struct cvmx_agl_gmx_drv_ctl_s cn52xxp1; struct cvmx_agl_gmx_drv_ctl_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t byp_en:1; uint64_t reserved_13_15:3; uint64_t pctl:5; uint64_t reserved_5_7:3; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t reserved_5_7:3; + uint64_t pctl:5; + uint64_t reserved_13_15:3; + uint64_t byp_en:1; + uint64_t reserved_17_63:47; +#endif } cn56xx; struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1; }; @@ -205,9 +295,15 @@ union cvmx_agl_gmx_drv_ctl { union cvmx_agl_gmx_inf_mode { uint64_t u64; struct cvmx_agl_gmx_inf_mode_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t en:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t en:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_agl_gmx_inf_mode_s cn52xx; struct cvmx_agl_gmx_inf_mode_s cn52xxp1; @@ -218,6 +314,7 @@ union cvmx_agl_gmx_inf_mode { union cvmx_agl_gmx_prtx_cfg { uint64_t u64; struct cvmx_agl_gmx_prtx_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t tx_idle:1; uint64_t rx_idle:1; @@ -231,8 +328,24 @@ union cvmx_agl_gmx_prtx_cfg { uint64_t duplex:1; uint64_t speed:1; uint64_t en:1; +#else + uint64_t en:1; + uint64_t speed:1; + uint64_t duplex:1; + uint64_t slottime:1; + uint64_t rx_en:1; + uint64_t tx_en:1; + uint64_t burst:1; + uint64_t reserved_7_7:1; + uint64_t speed_msb:1; + uint64_t reserved_9_11:3; + uint64_t rx_idle:1; + uint64_t tx_idle:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_agl_gmx_prtx_cfg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t tx_en:1; uint64_t rx_en:1; @@ -240,139 +353,230 @@ union cvmx_agl_gmx_prtx_cfg { uint64_t duplex:1; uint64_t speed:1; uint64_t en:1; +#else + uint64_t en:1; + uint64_t speed:1; + uint64_t duplex:1; + uint64_t slottime:1; + uint64_t rx_en:1; + uint64_t tx_en:1; + uint64_t reserved_6_63:58; +#endif } cn52xx; struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1; struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx; struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1; + struct cvmx_agl_gmx_prtx_cfg_s cn61xx; struct cvmx_agl_gmx_prtx_cfg_s cn63xx; struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1; + struct cvmx_agl_gmx_prtx_cfg_s cn66xx; + struct cvmx_agl_gmx_prtx_cfg_s cn68xx; + struct cvmx_agl_gmx_prtx_cfg_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam0 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; +#else + uint64_t adr:64; +#endif } s; struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_cam0_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_cam0_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam1 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; +#else + uint64_t adr:64; +#endif } s; struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_cam1_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_cam1_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam2 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; +#else + uint64_t adr:64; +#endif } s; struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_cam2_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_cam2_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam3 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; +#else + uint64_t adr:64; +#endif } s; struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_cam3_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_cam3_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam4 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam4_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; +#else + uint64_t adr:64; +#endif } s; struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_cam4_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_cam4_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam5 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam5_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t adr:64; +#else uint64_t adr:64; +#endif } s; struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_cam5_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_cam5_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam_en { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t en:8; +#else + uint64_t en:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_cam_en_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_cam_en_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_ctl { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t cam_mode:1; uint64_t mcst:2; uint64_t bcst:1; +#else + uint64_t bcst:1; + uint64_t mcst:2; + uint64_t cam_mode:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx; struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx; struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_ctl_s cn61xx; struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx; struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_ctl_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xxp1; }; union cvmx_agl_gmx_rxx_decision { uint64_t u64; struct cvmx_agl_gmx_rxx_decision_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t cnt:5; +#else + uint64_t cnt:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_agl_gmx_rxx_decision_s cn52xx; struct cvmx_agl_gmx_rxx_decision_s cn52xxp1; struct cvmx_agl_gmx_rxx_decision_s cn56xx; struct cvmx_agl_gmx_rxx_decision_s cn56xxp1; + struct cvmx_agl_gmx_rxx_decision_s cn61xx; struct cvmx_agl_gmx_rxx_decision_s cn63xx; struct cvmx_agl_gmx_rxx_decision_s cn63xxp1; + struct cvmx_agl_gmx_rxx_decision_s cn66xx; + struct cvmx_agl_gmx_rxx_decision_s cn68xx; + struct cvmx_agl_gmx_rxx_decision_s cn68xxp1; }; union cvmx_agl_gmx_rxx_frm_chk { uint64_t u64; struct cvmx_agl_gmx_rxx_frm_chk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t niberr:1; uint64_t skperr:1; @@ -384,8 +588,22 @@ union cvmx_agl_gmx_rxx_frm_chk { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_agl_gmx_rxx_frm_chk_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t skperr:1; uint64_t rcverr:1; @@ -396,17 +614,34 @@ union cvmx_agl_gmx_rxx_frm_chk { uint64_t maxerr:1; uint64_t reserved_1_1:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t reserved_1_1:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_63:55; +#endif } cn52xx; struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1; struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx; struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1; + struct cvmx_agl_gmx_rxx_frm_chk_s cn61xx; struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx; struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1; + struct cvmx_agl_gmx_rxx_frm_chk_s cn66xx; + struct cvmx_agl_gmx_rxx_frm_chk_s cn68xx; + struct cvmx_agl_gmx_rxx_frm_chk_s cn68xxp1; }; union cvmx_agl_gmx_rxx_frm_ctl { uint64_t u64; struct cvmx_agl_gmx_rxx_frm_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t ptp_mode:1; uint64_t reserved_11_11:1; @@ -421,8 +656,25 @@ union cvmx_agl_gmx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t pre_align:1; + uint64_t null_dis:1; + uint64_t reserved_11_11:1; + uint64_t ptp_mode:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pre_align:1; uint64_t pad_len:1; @@ -434,59 +686,104 @@ union cvmx_agl_gmx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t pre_align:1; + uint64_t reserved_10_63:54; +#endif } cn52xx; struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1; struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx; struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1; + struct cvmx_agl_gmx_rxx_frm_ctl_s cn61xx; struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx; struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1; + struct cvmx_agl_gmx_rxx_frm_ctl_s cn66xx; + struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xx; + struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xxp1; }; union cvmx_agl_gmx_rxx_frm_max { uint64_t u64; struct cvmx_agl_gmx_rxx_frm_max_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t len:16; +#else + uint64_t len:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_rxx_frm_max_s cn52xx; struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1; struct cvmx_agl_gmx_rxx_frm_max_s cn56xx; struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1; + struct cvmx_agl_gmx_rxx_frm_max_s cn61xx; struct cvmx_agl_gmx_rxx_frm_max_s cn63xx; struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1; + struct cvmx_agl_gmx_rxx_frm_max_s cn66xx; + struct cvmx_agl_gmx_rxx_frm_max_s cn68xx; + struct cvmx_agl_gmx_rxx_frm_max_s cn68xxp1; }; union cvmx_agl_gmx_rxx_frm_min { uint64_t u64; struct cvmx_agl_gmx_rxx_frm_min_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t len:16; +#else + uint64_t len:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_rxx_frm_min_s cn52xx; struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1; struct cvmx_agl_gmx_rxx_frm_min_s cn56xx; struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1; + struct cvmx_agl_gmx_rxx_frm_min_s cn61xx; struct cvmx_agl_gmx_rxx_frm_min_s cn63xx; struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1; + struct cvmx_agl_gmx_rxx_frm_min_s cn66xx; + struct cvmx_agl_gmx_rxx_frm_min_s cn68xx; + struct cvmx_agl_gmx_rxx_frm_min_s cn68xxp1; }; union cvmx_agl_gmx_rxx_ifg { uint64_t u64; struct cvmx_agl_gmx_rxx_ifg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t ifg:4; +#else + uint64_t ifg:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_agl_gmx_rxx_ifg_s cn52xx; struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1; struct cvmx_agl_gmx_rxx_ifg_s cn56xx; struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1; + struct cvmx_agl_gmx_rxx_ifg_s cn61xx; struct cvmx_agl_gmx_rxx_ifg_s cn63xx; struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1; + struct cvmx_agl_gmx_rxx_ifg_s cn66xx; + struct cvmx_agl_gmx_rxx_ifg_s cn68xx; + struct cvmx_agl_gmx_rxx_ifg_s cn68xxp1; }; union cvmx_agl_gmx_rxx_int_en { uint64_t u64; struct cvmx_agl_gmx_rxx_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -508,8 +805,32 @@ union cvmx_agl_gmx_rxx_int_en { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_agl_gmx_rxx_int_en_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t reserved_16_18:3; @@ -529,17 +850,43 @@ union cvmx_agl_gmx_rxx_int_en { uint64_t maxerr:1; uint64_t reserved_1_1:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t reserved_1_1:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1; struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx; struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1; + struct cvmx_agl_gmx_rxx_int_en_s cn61xx; struct cvmx_agl_gmx_rxx_int_en_s cn63xx; struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1; + struct cvmx_agl_gmx_rxx_int_en_s cn66xx; + struct cvmx_agl_gmx_rxx_int_en_s cn68xx; + struct cvmx_agl_gmx_rxx_int_en_s cn68xxp1; }; union cvmx_agl_gmx_rxx_int_reg { uint64_t u64; struct cvmx_agl_gmx_rxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -561,8 +908,32 @@ union cvmx_agl_gmx_rxx_int_reg { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_agl_gmx_rxx_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t reserved_16_18:3; @@ -582,666 +953,1130 @@ union cvmx_agl_gmx_rxx_int_reg { uint64_t maxerr:1; uint64_t reserved_1_1:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t reserved_1_1:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1; struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx; struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1; + struct cvmx_agl_gmx_rxx_int_reg_s cn61xx; struct cvmx_agl_gmx_rxx_int_reg_s cn63xx; struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1; + struct cvmx_agl_gmx_rxx_int_reg_s cn66xx; + struct cvmx_agl_gmx_rxx_int_reg_s cn68xx; + struct cvmx_agl_gmx_rxx_int_reg_s cn68xxp1; }; union cvmx_agl_gmx_rxx_jabber { uint64_t u64; struct cvmx_agl_gmx_rxx_jabber_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt:16; +#else + uint64_t cnt:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_rxx_jabber_s cn52xx; struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1; struct cvmx_agl_gmx_rxx_jabber_s cn56xx; struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1; + struct cvmx_agl_gmx_rxx_jabber_s cn61xx; struct cvmx_agl_gmx_rxx_jabber_s cn63xx; struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1; + struct cvmx_agl_gmx_rxx_jabber_s cn66xx; + struct cvmx_agl_gmx_rxx_jabber_s cn68xx; + struct cvmx_agl_gmx_rxx_jabber_s cn68xxp1; }; union cvmx_agl_gmx_rxx_pause_drop_time { uint64_t u64; struct cvmx_agl_gmx_rxx_pause_drop_time_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t status:16; +#else + uint64_t status:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1; + struct cvmx_agl_gmx_rxx_pause_drop_time_s cn61xx; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1; + struct cvmx_agl_gmx_rxx_pause_drop_time_s cn66xx; + struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xx; + struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xxp1; }; union cvmx_agl_gmx_rxx_rx_inbnd { uint64_t u64; struct cvmx_agl_gmx_rxx_rx_inbnd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t duplex:1; uint64_t speed:2; uint64_t status:1; +#else + uint64_t status:1; + uint64_t speed:2; + uint64_t duplex:1; + uint64_t reserved_4_63:60; +#endif } s; + struct cvmx_agl_gmx_rxx_rx_inbnd_s cn61xx; struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx; struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1; + struct cvmx_agl_gmx_rxx_rx_inbnd_s cn66xx; + struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xx; + struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_ctl { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rd_clr:1; +#else + uint64_t rd_clr:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx; struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx; struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_ctl_s cn61xx; struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx; struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_ctl_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_octs { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_octs_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx; struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx; struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_s cn61xx; struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx; struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_octs_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_octs_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_octs_ctl { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn61xx; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_octs_dmac { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn61xx; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_octs_drp { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_octs_drp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn61xx; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_pkts { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_pkts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx; struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx; struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_s cn61xx; struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx; struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_pkts_bad { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn61xx; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_pkts_ctl { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn61xx; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_pkts_dmac { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn61xx; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_pkts_drp { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn61xx; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xxp1; }; union cvmx_agl_gmx_rxx_udd_skp { uint64_t u64; struct cvmx_agl_gmx_rxx_udd_skp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t fcssel:1; uint64_t reserved_7_7:1; uint64_t len:7; +#else + uint64_t len:7; + uint64_t reserved_7_7:1; + uint64_t fcssel:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx; struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1; struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx; struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1; + struct cvmx_agl_gmx_rxx_udd_skp_s cn61xx; struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx; struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1; + struct cvmx_agl_gmx_rxx_udd_skp_s cn66xx; + struct cvmx_agl_gmx_rxx_udd_skp_s cn68xx; + struct cvmx_agl_gmx_rxx_udd_skp_s cn68xxp1; }; union cvmx_agl_gmx_rx_bp_dropx { uint64_t u64; struct cvmx_agl_gmx_rx_bp_dropx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mark:6; +#else + uint64_t mark:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx; struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1; struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx; struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1; + struct cvmx_agl_gmx_rx_bp_dropx_s cn61xx; struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx; struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1; + struct cvmx_agl_gmx_rx_bp_dropx_s cn66xx; + struct cvmx_agl_gmx_rx_bp_dropx_s cn68xx; + struct cvmx_agl_gmx_rx_bp_dropx_s cn68xxp1; }; union cvmx_agl_gmx_rx_bp_offx { uint64_t u64; struct cvmx_agl_gmx_rx_bp_offx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mark:6; +#else + uint64_t mark:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_agl_gmx_rx_bp_offx_s cn52xx; struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1; struct cvmx_agl_gmx_rx_bp_offx_s cn56xx; struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1; + struct cvmx_agl_gmx_rx_bp_offx_s cn61xx; struct cvmx_agl_gmx_rx_bp_offx_s cn63xx; struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1; + struct cvmx_agl_gmx_rx_bp_offx_s cn66xx; + struct cvmx_agl_gmx_rx_bp_offx_s cn68xx; + struct cvmx_agl_gmx_rx_bp_offx_s cn68xxp1; }; union cvmx_agl_gmx_rx_bp_onx { uint64_t u64; struct cvmx_agl_gmx_rx_bp_onx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t mark:9; +#else + uint64_t mark:9; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_agl_gmx_rx_bp_onx_s cn52xx; struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1; struct cvmx_agl_gmx_rx_bp_onx_s cn56xx; struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1; + struct cvmx_agl_gmx_rx_bp_onx_s cn61xx; struct cvmx_agl_gmx_rx_bp_onx_s cn63xx; struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1; + struct cvmx_agl_gmx_rx_bp_onx_s cn66xx; + struct cvmx_agl_gmx_rx_bp_onx_s cn68xx; + struct cvmx_agl_gmx_rx_bp_onx_s cn68xxp1; }; union cvmx_agl_gmx_rx_prt_info { uint64_t u64; struct cvmx_agl_gmx_rx_prt_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t drop:2; uint64_t reserved_2_15:14; uint64_t commit:2; +#else + uint64_t commit:2; + uint64_t reserved_2_15:14; + uint64_t drop:2; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_agl_gmx_rx_prt_info_s cn52xx; struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1; struct cvmx_agl_gmx_rx_prt_info_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t drop:1; uint64_t reserved_1_15:15; uint64_t commit:1; +#else + uint64_t commit:1; + uint64_t reserved_1_15:15; + uint64_t drop:1; + uint64_t reserved_17_63:47; +#endif } cn56xx; struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1; + struct cvmx_agl_gmx_rx_prt_info_s cn61xx; struct cvmx_agl_gmx_rx_prt_info_s cn63xx; struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1; + struct cvmx_agl_gmx_rx_prt_info_s cn66xx; + struct cvmx_agl_gmx_rx_prt_info_s cn68xx; + struct cvmx_agl_gmx_rx_prt_info_s cn68xxp1; }; union cvmx_agl_gmx_rx_tx_status { uint64_t u64; struct cvmx_agl_gmx_rx_tx_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t tx:2; uint64_t reserved_2_3:2; uint64_t rx:2; +#else + uint64_t rx:2; + uint64_t reserved_2_3:2; + uint64_t tx:2; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_agl_gmx_rx_tx_status_s cn52xx; struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1; struct cvmx_agl_gmx_rx_tx_status_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t tx:1; uint64_t reserved_1_3:3; uint64_t rx:1; +#else + uint64_t rx:1; + uint64_t reserved_1_3:3; + uint64_t tx:1; + uint64_t reserved_5_63:59; +#endif } cn56xx; struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1; + struct cvmx_agl_gmx_rx_tx_status_s cn61xx; struct cvmx_agl_gmx_rx_tx_status_s cn63xx; struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1; + struct cvmx_agl_gmx_rx_tx_status_s cn66xx; + struct cvmx_agl_gmx_rx_tx_status_s cn68xx; + struct cvmx_agl_gmx_rx_tx_status_s cn68xxp1; }; union cvmx_agl_gmx_smacx { uint64_t u64; struct cvmx_agl_gmx_smacx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t smac:48; +#else + uint64_t smac:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_agl_gmx_smacx_s cn52xx; struct cvmx_agl_gmx_smacx_s cn52xxp1; struct cvmx_agl_gmx_smacx_s cn56xx; struct cvmx_agl_gmx_smacx_s cn56xxp1; + struct cvmx_agl_gmx_smacx_s cn61xx; struct cvmx_agl_gmx_smacx_s cn63xx; struct cvmx_agl_gmx_smacx_s cn63xxp1; + struct cvmx_agl_gmx_smacx_s cn66xx; + struct cvmx_agl_gmx_smacx_s cn68xx; + struct cvmx_agl_gmx_smacx_s cn68xxp1; }; union cvmx_agl_gmx_stat_bp { uint64_t u64; struct cvmx_agl_gmx_stat_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t bp:1; uint64_t cnt:16; +#else + uint64_t cnt:16; + uint64_t bp:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_agl_gmx_stat_bp_s cn52xx; struct cvmx_agl_gmx_stat_bp_s cn52xxp1; struct cvmx_agl_gmx_stat_bp_s cn56xx; struct cvmx_agl_gmx_stat_bp_s cn56xxp1; + struct cvmx_agl_gmx_stat_bp_s cn61xx; struct cvmx_agl_gmx_stat_bp_s cn63xx; struct cvmx_agl_gmx_stat_bp_s cn63xxp1; + struct cvmx_agl_gmx_stat_bp_s cn66xx; + struct cvmx_agl_gmx_stat_bp_s cn68xx; + struct cvmx_agl_gmx_stat_bp_s cn68xxp1; }; union cvmx_agl_gmx_txx_append { uint64_t u64; struct cvmx_agl_gmx_txx_append_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t force_fcs:1; uint64_t fcs:1; uint64_t pad:1; uint64_t preamble:1; +#else + uint64_t preamble:1; + uint64_t pad:1; + uint64_t fcs:1; + uint64_t force_fcs:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_agl_gmx_txx_append_s cn52xx; struct cvmx_agl_gmx_txx_append_s cn52xxp1; struct cvmx_agl_gmx_txx_append_s cn56xx; struct cvmx_agl_gmx_txx_append_s cn56xxp1; + struct cvmx_agl_gmx_txx_append_s cn61xx; struct cvmx_agl_gmx_txx_append_s cn63xx; struct cvmx_agl_gmx_txx_append_s cn63xxp1; + struct cvmx_agl_gmx_txx_append_s cn66xx; + struct cvmx_agl_gmx_txx_append_s cn68xx; + struct cvmx_agl_gmx_txx_append_s cn68xxp1; }; union cvmx_agl_gmx_txx_clk { uint64_t u64; struct cvmx_agl_gmx_txx_clk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t clk_cnt:6; +#else + uint64_t clk_cnt:6; + uint64_t reserved_6_63:58; +#endif } s; + struct cvmx_agl_gmx_txx_clk_s cn61xx; struct cvmx_agl_gmx_txx_clk_s cn63xx; struct cvmx_agl_gmx_txx_clk_s cn63xxp1; + struct cvmx_agl_gmx_txx_clk_s cn66xx; + struct cvmx_agl_gmx_txx_clk_s cn68xx; + struct cvmx_agl_gmx_txx_clk_s cn68xxp1; }; union cvmx_agl_gmx_txx_ctl { uint64_t u64; struct cvmx_agl_gmx_txx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t xsdef_en:1; uint64_t xscol_en:1; +#else + uint64_t xscol_en:1; + uint64_t xsdef_en:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_agl_gmx_txx_ctl_s cn52xx; struct cvmx_agl_gmx_txx_ctl_s cn52xxp1; struct cvmx_agl_gmx_txx_ctl_s cn56xx; struct cvmx_agl_gmx_txx_ctl_s cn56xxp1; + struct cvmx_agl_gmx_txx_ctl_s cn61xx; struct cvmx_agl_gmx_txx_ctl_s cn63xx; struct cvmx_agl_gmx_txx_ctl_s cn63xxp1; + struct cvmx_agl_gmx_txx_ctl_s cn66xx; + struct cvmx_agl_gmx_txx_ctl_s cn68xx; + struct cvmx_agl_gmx_txx_ctl_s cn68xxp1; }; union cvmx_agl_gmx_txx_min_pkt { uint64_t u64; struct cvmx_agl_gmx_txx_min_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t min_size:8; +#else + uint64_t min_size:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_agl_gmx_txx_min_pkt_s cn52xx; struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1; struct cvmx_agl_gmx_txx_min_pkt_s cn56xx; struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1; + struct cvmx_agl_gmx_txx_min_pkt_s cn61xx; struct cvmx_agl_gmx_txx_min_pkt_s cn63xx; struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1; + struct cvmx_agl_gmx_txx_min_pkt_s cn66xx; + struct cvmx_agl_gmx_txx_min_pkt_s cn68xx; + struct cvmx_agl_gmx_txx_min_pkt_s cn68xxp1; }; union cvmx_agl_gmx_txx_pause_pkt_interval { uint64_t u64; struct cvmx_agl_gmx_txx_pause_pkt_interval_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t interval:16; +#else + uint64_t interval:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1; + struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn61xx; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1; + struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn66xx; + struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xx; + struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xxp1; }; union cvmx_agl_gmx_txx_pause_pkt_time { uint64_t u64; struct cvmx_agl_gmx_txx_pause_pkt_time_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; +#else + uint64_t time:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1; + struct cvmx_agl_gmx_txx_pause_pkt_time_s cn61xx; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1; + struct cvmx_agl_gmx_txx_pause_pkt_time_s cn66xx; + struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xx; + struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xxp1; }; union cvmx_agl_gmx_txx_pause_togo { uint64_t u64; struct cvmx_agl_gmx_txx_pause_togo_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; +#else + uint64_t time:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_txx_pause_togo_s cn52xx; struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1; struct cvmx_agl_gmx_txx_pause_togo_s cn56xx; struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1; + struct cvmx_agl_gmx_txx_pause_togo_s cn61xx; struct cvmx_agl_gmx_txx_pause_togo_s cn63xx; struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1; + struct cvmx_agl_gmx_txx_pause_togo_s cn66xx; + struct cvmx_agl_gmx_txx_pause_togo_s cn68xx; + struct cvmx_agl_gmx_txx_pause_togo_s cn68xxp1; }; union cvmx_agl_gmx_txx_pause_zero { uint64_t u64; struct cvmx_agl_gmx_txx_pause_zero_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t send:1; +#else + uint64_t send:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_agl_gmx_txx_pause_zero_s cn52xx; struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1; struct cvmx_agl_gmx_txx_pause_zero_s cn56xx; struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1; + struct cvmx_agl_gmx_txx_pause_zero_s cn61xx; struct cvmx_agl_gmx_txx_pause_zero_s cn63xx; struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1; + struct cvmx_agl_gmx_txx_pause_zero_s cn66xx; + struct cvmx_agl_gmx_txx_pause_zero_s cn68xx; + struct cvmx_agl_gmx_txx_pause_zero_s cn68xxp1; }; union cvmx_agl_gmx_txx_soft_pause { uint64_t u64; struct cvmx_agl_gmx_txx_soft_pause_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; +#else + uint64_t time:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_txx_soft_pause_s cn52xx; struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1; struct cvmx_agl_gmx_txx_soft_pause_s cn56xx; struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1; + struct cvmx_agl_gmx_txx_soft_pause_s cn61xx; struct cvmx_agl_gmx_txx_soft_pause_s cn63xx; struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1; + struct cvmx_agl_gmx_txx_soft_pause_s cn66xx; + struct cvmx_agl_gmx_txx_soft_pause_s cn68xx; + struct cvmx_agl_gmx_txx_soft_pause_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat0 { uint64_t u64; struct cvmx_agl_gmx_txx_stat0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t xsdef:32; uint64_t xscol:32; +#else + uint64_t xscol:32; + uint64_t xsdef:32; +#endif } s; struct cvmx_agl_gmx_txx_stat0_s cn52xx; struct cvmx_agl_gmx_txx_stat0_s cn52xxp1; struct cvmx_agl_gmx_txx_stat0_s cn56xx; struct cvmx_agl_gmx_txx_stat0_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat0_s cn61xx; struct cvmx_agl_gmx_txx_stat0_s cn63xx; struct cvmx_agl_gmx_txx_stat0_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat0_s cn66xx; + struct cvmx_agl_gmx_txx_stat0_s cn68xx; + struct cvmx_agl_gmx_txx_stat0_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat1 { uint64_t u64; struct cvmx_agl_gmx_txx_stat1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t scol:32; uint64_t mcol:32; +#else + uint64_t mcol:32; + uint64_t scol:32; +#endif } s; struct cvmx_agl_gmx_txx_stat1_s cn52xx; struct cvmx_agl_gmx_txx_stat1_s cn52xxp1; struct cvmx_agl_gmx_txx_stat1_s cn56xx; struct cvmx_agl_gmx_txx_stat1_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat1_s cn61xx; struct cvmx_agl_gmx_txx_stat1_s cn63xx; struct cvmx_agl_gmx_txx_stat1_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat1_s cn66xx; + struct cvmx_agl_gmx_txx_stat1_s cn68xx; + struct cvmx_agl_gmx_txx_stat1_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat2 { uint64_t u64; struct cvmx_agl_gmx_txx_stat2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t octs:48; +#else + uint64_t octs:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_agl_gmx_txx_stat2_s cn52xx; struct cvmx_agl_gmx_txx_stat2_s cn52xxp1; struct cvmx_agl_gmx_txx_stat2_s cn56xx; struct cvmx_agl_gmx_txx_stat2_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat2_s cn61xx; struct cvmx_agl_gmx_txx_stat2_s cn63xx; struct cvmx_agl_gmx_txx_stat2_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat2_s cn66xx; + struct cvmx_agl_gmx_txx_stat2_s cn68xx; + struct cvmx_agl_gmx_txx_stat2_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat3 { uint64_t u64; struct cvmx_agl_gmx_txx_stat3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pkts:32; +#else + uint64_t pkts:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_agl_gmx_txx_stat3_s cn52xx; struct cvmx_agl_gmx_txx_stat3_s cn52xxp1; struct cvmx_agl_gmx_txx_stat3_s cn56xx; struct cvmx_agl_gmx_txx_stat3_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat3_s cn61xx; struct cvmx_agl_gmx_txx_stat3_s cn63xx; struct cvmx_agl_gmx_txx_stat3_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat3_s cn66xx; + struct cvmx_agl_gmx_txx_stat3_s cn68xx; + struct cvmx_agl_gmx_txx_stat3_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat4 { uint64_t u64; struct cvmx_agl_gmx_txx_stat4_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist1:32; uint64_t hist0:32; +#else + uint64_t hist0:32; + uint64_t hist1:32; +#endif } s; struct cvmx_agl_gmx_txx_stat4_s cn52xx; struct cvmx_agl_gmx_txx_stat4_s cn52xxp1; struct cvmx_agl_gmx_txx_stat4_s cn56xx; struct cvmx_agl_gmx_txx_stat4_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat4_s cn61xx; struct cvmx_agl_gmx_txx_stat4_s cn63xx; struct cvmx_agl_gmx_txx_stat4_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat4_s cn66xx; + struct cvmx_agl_gmx_txx_stat4_s cn68xx; + struct cvmx_agl_gmx_txx_stat4_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat5 { uint64_t u64; struct cvmx_agl_gmx_txx_stat5_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist3:32; uint64_t hist2:32; +#else + uint64_t hist2:32; + uint64_t hist3:32; +#endif } s; struct cvmx_agl_gmx_txx_stat5_s cn52xx; struct cvmx_agl_gmx_txx_stat5_s cn52xxp1; struct cvmx_agl_gmx_txx_stat5_s cn56xx; struct cvmx_agl_gmx_txx_stat5_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat5_s cn61xx; struct cvmx_agl_gmx_txx_stat5_s cn63xx; struct cvmx_agl_gmx_txx_stat5_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat5_s cn66xx; + struct cvmx_agl_gmx_txx_stat5_s cn68xx; + struct cvmx_agl_gmx_txx_stat5_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat6 { uint64_t u64; struct cvmx_agl_gmx_txx_stat6_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist5:32; uint64_t hist4:32; +#else + uint64_t hist4:32; + uint64_t hist5:32; +#endif } s; struct cvmx_agl_gmx_txx_stat6_s cn52xx; struct cvmx_agl_gmx_txx_stat6_s cn52xxp1; struct cvmx_agl_gmx_txx_stat6_s cn56xx; struct cvmx_agl_gmx_txx_stat6_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat6_s cn61xx; struct cvmx_agl_gmx_txx_stat6_s cn63xx; struct cvmx_agl_gmx_txx_stat6_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat6_s cn66xx; + struct cvmx_agl_gmx_txx_stat6_s cn68xx; + struct cvmx_agl_gmx_txx_stat6_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat7 { uint64_t u64; struct cvmx_agl_gmx_txx_stat7_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist7:32; uint64_t hist6:32; +#else + uint64_t hist6:32; + uint64_t hist7:32; +#endif } s; struct cvmx_agl_gmx_txx_stat7_s cn52xx; struct cvmx_agl_gmx_txx_stat7_s cn52xxp1; struct cvmx_agl_gmx_txx_stat7_s cn56xx; struct cvmx_agl_gmx_txx_stat7_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat7_s cn61xx; struct cvmx_agl_gmx_txx_stat7_s cn63xx; struct cvmx_agl_gmx_txx_stat7_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat7_s cn66xx; + struct cvmx_agl_gmx_txx_stat7_s cn68xx; + struct cvmx_agl_gmx_txx_stat7_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat8 { uint64_t u64; struct cvmx_agl_gmx_txx_stat8_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mcst:32; uint64_t bcst:32; +#else + uint64_t bcst:32; + uint64_t mcst:32; +#endif } s; struct cvmx_agl_gmx_txx_stat8_s cn52xx; struct cvmx_agl_gmx_txx_stat8_s cn52xxp1; struct cvmx_agl_gmx_txx_stat8_s cn56xx; struct cvmx_agl_gmx_txx_stat8_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat8_s cn61xx; struct cvmx_agl_gmx_txx_stat8_s cn63xx; struct cvmx_agl_gmx_txx_stat8_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat8_s cn66xx; + struct cvmx_agl_gmx_txx_stat8_s cn68xx; + struct cvmx_agl_gmx_txx_stat8_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat9 { uint64_t u64; struct cvmx_agl_gmx_txx_stat9_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t undflw:32; uint64_t ctl:32; +#else + uint64_t ctl:32; + uint64_t undflw:32; +#endif } s; struct cvmx_agl_gmx_txx_stat9_s cn52xx; struct cvmx_agl_gmx_txx_stat9_s cn52xxp1; struct cvmx_agl_gmx_txx_stat9_s cn56xx; struct cvmx_agl_gmx_txx_stat9_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat9_s cn61xx; struct cvmx_agl_gmx_txx_stat9_s cn63xx; struct cvmx_agl_gmx_txx_stat9_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat9_s cn66xx; + struct cvmx_agl_gmx_txx_stat9_s cn68xx; + struct cvmx_agl_gmx_txx_stat9_s cn68xxp1; }; union cvmx_agl_gmx_txx_stats_ctl { uint64_t u64; struct cvmx_agl_gmx_txx_stats_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rd_clr:1; +#else + uint64_t rd_clr:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx; struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1; struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx; struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1; + struct cvmx_agl_gmx_txx_stats_ctl_s cn61xx; struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx; struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1; + struct cvmx_agl_gmx_txx_stats_ctl_s cn66xx; + struct cvmx_agl_gmx_txx_stats_ctl_s cn68xx; + struct cvmx_agl_gmx_txx_stats_ctl_s cn68xxp1; }; union cvmx_agl_gmx_txx_thresh { uint64_t u64; struct cvmx_agl_gmx_txx_thresh_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t cnt:6; +#else + uint64_t cnt:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_agl_gmx_txx_thresh_s cn52xx; struct cvmx_agl_gmx_txx_thresh_s cn52xxp1; struct cvmx_agl_gmx_txx_thresh_s cn56xx; struct cvmx_agl_gmx_txx_thresh_s cn56xxp1; + struct cvmx_agl_gmx_txx_thresh_s cn61xx; struct cvmx_agl_gmx_txx_thresh_s cn63xx; struct cvmx_agl_gmx_txx_thresh_s cn63xxp1; + struct cvmx_agl_gmx_txx_thresh_s cn66xx; + struct cvmx_agl_gmx_txx_thresh_s cn68xx; + struct cvmx_agl_gmx_txx_thresh_s cn68xxp1; }; union cvmx_agl_gmx_tx_bp { uint64_t u64; struct cvmx_agl_gmx_tx_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t bp:2; +#else + uint64_t bp:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_agl_gmx_tx_bp_s cn52xx; struct cvmx_agl_gmx_tx_bp_s cn52xxp1; struct cvmx_agl_gmx_tx_bp_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t bp:1; +#else + uint64_t bp:1; + uint64_t reserved_1_63:63; +#endif } cn56xx; struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1; + struct cvmx_agl_gmx_tx_bp_s cn61xx; struct cvmx_agl_gmx_tx_bp_s cn63xx; struct cvmx_agl_gmx_tx_bp_s cn63xxp1; + struct cvmx_agl_gmx_tx_bp_s cn66xx; + struct cvmx_agl_gmx_tx_bp_s cn68xx; + struct cvmx_agl_gmx_tx_bp_s cn68xxp1; }; union cvmx_agl_gmx_tx_col_attempt { uint64_t u64; struct cvmx_agl_gmx_tx_col_attempt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t limit:5; +#else + uint64_t limit:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_agl_gmx_tx_col_attempt_s cn52xx; struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1; struct cvmx_agl_gmx_tx_col_attempt_s cn56xx; struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1; + struct cvmx_agl_gmx_tx_col_attempt_s cn61xx; struct cvmx_agl_gmx_tx_col_attempt_s cn63xx; struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1; + struct cvmx_agl_gmx_tx_col_attempt_s cn66xx; + struct cvmx_agl_gmx_tx_col_attempt_s cn68xx; + struct cvmx_agl_gmx_tx_col_attempt_s cn68xxp1; }; union cvmx_agl_gmx_tx_ifg { uint64_t u64; struct cvmx_agl_gmx_tx_ifg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ifg2:4; uint64_t ifg1:4; +#else + uint64_t ifg1:4; + uint64_t ifg2:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_agl_gmx_tx_ifg_s cn52xx; struct cvmx_agl_gmx_tx_ifg_s cn52xxp1; struct cvmx_agl_gmx_tx_ifg_s cn56xx; struct cvmx_agl_gmx_tx_ifg_s cn56xxp1; + struct cvmx_agl_gmx_tx_ifg_s cn61xx; struct cvmx_agl_gmx_tx_ifg_s cn63xx; struct cvmx_agl_gmx_tx_ifg_s cn63xxp1; + struct cvmx_agl_gmx_tx_ifg_s cn66xx; + struct cvmx_agl_gmx_tx_ifg_s cn68xx; + struct cvmx_agl_gmx_tx_ifg_s cn68xxp1; }; union cvmx_agl_gmx_tx_int_en { uint64_t u64; struct cvmx_agl_gmx_tx_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t ptp_lost:2; uint64_t reserved_18_19:2; @@ -1254,8 +2089,23 @@ union cvmx_agl_gmx_tx_int_en { uint64_t undflw:2; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:2; + uint64_t reserved_4_7:4; + uint64_t xscol:2; + uint64_t reserved_10_11:2; + uint64_t xsdef:2; + uint64_t reserved_14_15:2; + uint64_t late_col:2; + uint64_t reserved_18_19:2; + uint64_t ptp_lost:2; + uint64_t reserved_22_63:42; +#endif } s; struct cvmx_agl_gmx_tx_int_en_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t late_col:2; uint64_t reserved_14_15:2; @@ -1266,9 +2116,22 @@ union cvmx_agl_gmx_tx_int_en { uint64_t undflw:2; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:2; + uint64_t reserved_4_7:4; + uint64_t xscol:2; + uint64_t reserved_10_11:2; + uint64_t xsdef:2; + uint64_t reserved_14_15:2; + uint64_t late_col:2; + uint64_t reserved_18_63:46; +#endif } cn52xx; struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1; struct cvmx_agl_gmx_tx_int_en_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t late_col:1; uint64_t reserved_13_15:3; @@ -1279,15 +2142,32 @@ union cvmx_agl_gmx_tx_int_en { uint64_t undflw:1; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:1; + uint64_t reserved_3_7:5; + uint64_t xscol:1; + uint64_t reserved_9_11:3; + uint64_t xsdef:1; + uint64_t reserved_13_15:3; + uint64_t late_col:1; + uint64_t reserved_17_63:47; +#endif } cn56xx; struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1; + struct cvmx_agl_gmx_tx_int_en_s cn61xx; struct cvmx_agl_gmx_tx_int_en_s cn63xx; struct cvmx_agl_gmx_tx_int_en_s cn63xxp1; + struct cvmx_agl_gmx_tx_int_en_s cn66xx; + struct cvmx_agl_gmx_tx_int_en_s cn68xx; + struct cvmx_agl_gmx_tx_int_en_s cn68xxp1; }; union cvmx_agl_gmx_tx_int_reg { uint64_t u64; struct cvmx_agl_gmx_tx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t ptp_lost:2; uint64_t reserved_18_19:2; @@ -1300,8 +2180,23 @@ union cvmx_agl_gmx_tx_int_reg { uint64_t undflw:2; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:2; + uint64_t reserved_4_7:4; + uint64_t xscol:2; + uint64_t reserved_10_11:2; + uint64_t xsdef:2; + uint64_t reserved_14_15:2; + uint64_t late_col:2; + uint64_t reserved_18_19:2; + uint64_t ptp_lost:2; + uint64_t reserved_22_63:42; +#endif } s; struct cvmx_agl_gmx_tx_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t late_col:2; uint64_t reserved_14_15:2; @@ -1312,9 +2207,22 @@ union cvmx_agl_gmx_tx_int_reg { uint64_t undflw:2; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:2; + uint64_t reserved_4_7:4; + uint64_t xscol:2; + uint64_t reserved_10_11:2; + uint64_t xsdef:2; + uint64_t reserved_14_15:2; + uint64_t late_col:2; + uint64_t reserved_18_63:46; +#endif } cn52xx; struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1; struct cvmx_agl_gmx_tx_int_reg_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t late_col:1; uint64_t reserved_13_15:3; @@ -1325,96 +2233,171 @@ union cvmx_agl_gmx_tx_int_reg { uint64_t undflw:1; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:1; + uint64_t reserved_3_7:5; + uint64_t xscol:1; + uint64_t reserved_9_11:3; + uint64_t xsdef:1; + uint64_t reserved_13_15:3; + uint64_t late_col:1; + uint64_t reserved_17_63:47; +#endif } cn56xx; struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1; + struct cvmx_agl_gmx_tx_int_reg_s cn61xx; struct cvmx_agl_gmx_tx_int_reg_s cn63xx; struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1; + struct cvmx_agl_gmx_tx_int_reg_s cn66xx; + struct cvmx_agl_gmx_tx_int_reg_s cn68xx; + struct cvmx_agl_gmx_tx_int_reg_s cn68xxp1; }; union cvmx_agl_gmx_tx_jam { uint64_t u64; struct cvmx_agl_gmx_tx_jam_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t jam:8; +#else + uint64_t jam:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_agl_gmx_tx_jam_s cn52xx; struct cvmx_agl_gmx_tx_jam_s cn52xxp1; struct cvmx_agl_gmx_tx_jam_s cn56xx; struct cvmx_agl_gmx_tx_jam_s cn56xxp1; + struct cvmx_agl_gmx_tx_jam_s cn61xx; struct cvmx_agl_gmx_tx_jam_s cn63xx; struct cvmx_agl_gmx_tx_jam_s cn63xxp1; + struct cvmx_agl_gmx_tx_jam_s cn66xx; + struct cvmx_agl_gmx_tx_jam_s cn68xx; + struct cvmx_agl_gmx_tx_jam_s cn68xxp1; }; union cvmx_agl_gmx_tx_lfsr { uint64_t u64; struct cvmx_agl_gmx_tx_lfsr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t lfsr:16; +#else + uint64_t lfsr:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_tx_lfsr_s cn52xx; struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1; struct cvmx_agl_gmx_tx_lfsr_s cn56xx; struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1; + struct cvmx_agl_gmx_tx_lfsr_s cn61xx; struct cvmx_agl_gmx_tx_lfsr_s cn63xx; struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1; + struct cvmx_agl_gmx_tx_lfsr_s cn66xx; + struct cvmx_agl_gmx_tx_lfsr_s cn68xx; + struct cvmx_agl_gmx_tx_lfsr_s cn68xxp1; }; union cvmx_agl_gmx_tx_ovr_bp { uint64_t u64; struct cvmx_agl_gmx_tx_ovr_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t en:2; uint64_t reserved_6_7:2; uint64_t bp:2; uint64_t reserved_2_3:2; uint64_t ign_full:2; +#else + uint64_t ign_full:2; + uint64_t reserved_2_3:2; + uint64_t bp:2; + uint64_t reserved_6_7:2; + uint64_t en:2; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx; struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1; struct cvmx_agl_gmx_tx_ovr_bp_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t en:1; uint64_t reserved_5_7:3; uint64_t bp:1; uint64_t reserved_1_3:3; uint64_t ign_full:1; +#else + uint64_t ign_full:1; + uint64_t reserved_1_3:3; + uint64_t bp:1; + uint64_t reserved_5_7:3; + uint64_t en:1; + uint64_t reserved_9_63:55; +#endif } cn56xx; struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1; + struct cvmx_agl_gmx_tx_ovr_bp_s cn61xx; struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx; struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1; + struct cvmx_agl_gmx_tx_ovr_bp_s cn66xx; + struct cvmx_agl_gmx_tx_ovr_bp_s cn68xx; + struct cvmx_agl_gmx_tx_ovr_bp_s cn68xxp1; }; union cvmx_agl_gmx_tx_pause_pkt_dmac { uint64_t u64; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t dmac:48; +#else + uint64_t dmac:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1; + struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn61xx; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1; + struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn66xx; + struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xx; + struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xxp1; }; union cvmx_agl_gmx_tx_pause_pkt_type { uint64_t u64; struct cvmx_agl_gmx_tx_pause_pkt_type_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t type:16; +#else + uint64_t type:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1; + struct cvmx_agl_gmx_tx_pause_pkt_type_s cn61xx; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1; + struct cvmx_agl_gmx_tx_pause_pkt_type_s cn66xx; + struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xx; + struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xxp1; }; union cvmx_agl_prtx_ctl { uint64_t u64; struct cvmx_agl_prtx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t drv_byp:1; uint64_t reserved_62_62:1; uint64_t cmp_pctl:6; @@ -1438,9 +2421,38 @@ union cvmx_agl_prtx_ctl { uint64_t enable:1; uint64_t clkrst:1; uint64_t mode:1; +#else + uint64_t mode:1; + uint64_t clkrst:1; + uint64_t enable:1; + uint64_t comp:1; + uint64_t dllrst:1; + uint64_t reserved_5_7:3; + uint64_t clktx_set:5; + uint64_t reserved_13_14:2; + uint64_t clktx_byp:1; + uint64_t clkrx_set:5; + uint64_t reserved_21_22:2; + uint64_t clkrx_byp:1; + uint64_t clk_set:5; + uint64_t reserved_29_31:3; + uint64_t drv_nctl:6; + uint64_t reserved_38_39:2; + uint64_t drv_pctl:6; + uint64_t reserved_46_47:2; + uint64_t cmp_nctl:6; + uint64_t reserved_54_55:2; + uint64_t cmp_pctl:6; + uint64_t reserved_62_62:1; + uint64_t drv_byp:1; +#endif } s; + struct cvmx_agl_prtx_ctl_s cn61xx; struct cvmx_agl_prtx_ctl_s cn63xx; struct cvmx_agl_prtx_ctl_s cn63xxp1; + struct cvmx_agl_prtx_ctl_s cn66xx; + struct cvmx_agl_prtx_ctl_s cn68xx; + struct cvmx_agl_prtx_ctl_s cn68xxp1; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-asxx-defs.h b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h index 91415a85e8d2..a1e21a3854cf 100644 --- a/arch/mips/include/asm/octeon/cvmx-asxx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,64 +28,43 @@ #ifndef __CVMX_ASXX_DEFS_H__ #define __CVMX_ASXX_DEFS_H__ -#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000180ull + (((block_id) & 0) * 0x8000000ull)) -#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000188ull + (((block_id) & 0) * 0x8000000ull)) -#define CVMX_ASXX_INT_EN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000018ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_INT_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000010ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_MII_RX_DAT_SET(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000190ull + (((block_id) & 0) * 0x8000000ull)) -#define CVMX_ASXX_PRT_LOOP(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000040ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_BYPASS(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000248ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000250ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_COMP(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000220ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_DATA_DRV(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000218ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000210ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000230ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000240ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000228ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000238ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_SETTING(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000258ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000020ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_PRT_EN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000000ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_WOL(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000100ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_WOL_MSK(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000108ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_WOL_POWOK(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000118ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_WOL_SIG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000110ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000048ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_TX_COMP_BYP(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000068ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000080ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_TX_PRT_EN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000008ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull)) +#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull)) +#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull)) +#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull) union cvmx_asxx_gmii_rx_clk_set { uint64_t u64; struct cvmx_asxx_gmii_rx_clk_set_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_gmii_rx_clk_set_s cn30xx; struct cvmx_asxx_gmii_rx_clk_set_s cn31xx; @@ -95,8 +74,13 @@ union cvmx_asxx_gmii_rx_clk_set { union cvmx_asxx_gmii_rx_dat_set { uint64_t u64; struct cvmx_asxx_gmii_rx_dat_set_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_gmii_rx_dat_set_s cn30xx; struct cvmx_asxx_gmii_rx_dat_set_s cn31xx; @@ -106,18 +90,34 @@ union cvmx_asxx_gmii_rx_dat_set { union cvmx_asxx_int_en { uint64_t u64; struct cvmx_asxx_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t txpsh:4; uint64_t txpop:4; uint64_t ovrflw:4; +#else + uint64_t ovrflw:4; + uint64_t txpop:4; + uint64_t txpsh:4; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_asxx_int_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t txpsh:3; uint64_t reserved_7_7:1; uint64_t txpop:3; uint64_t reserved_3_3:1; uint64_t ovrflw:3; +#else + uint64_t ovrflw:3; + uint64_t reserved_3_3:1; + uint64_t txpop:3; + uint64_t reserved_7_7:1; + uint64_t txpsh:3; + uint64_t reserved_11_63:53; +#endif } cn30xx; struct cvmx_asxx_int_en_cn30xx cn31xx; struct cvmx_asxx_int_en_s cn38xx; @@ -130,18 +130,34 @@ union cvmx_asxx_int_en { union cvmx_asxx_int_reg { uint64_t u64; struct cvmx_asxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t txpsh:4; uint64_t txpop:4; uint64_t ovrflw:4; +#else + uint64_t ovrflw:4; + uint64_t txpop:4; + uint64_t txpsh:4; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_asxx_int_reg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t txpsh:3; uint64_t reserved_7_7:1; uint64_t txpop:3; uint64_t reserved_3_3:1; uint64_t ovrflw:3; +#else + uint64_t ovrflw:3; + uint64_t reserved_3_3:1; + uint64_t txpop:3; + uint64_t reserved_7_7:1; + uint64_t txpsh:3; + uint64_t reserved_11_63:53; +#endif } cn30xx; struct cvmx_asxx_int_reg_cn30xx cn31xx; struct cvmx_asxx_int_reg_s cn38xx; @@ -154,8 +170,13 @@ union cvmx_asxx_int_reg { union cvmx_asxx_mii_rx_dat_set { uint64_t u64; struct cvmx_asxx_mii_rx_dat_set_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_mii_rx_dat_set_s cn30xx; struct cvmx_asxx_mii_rx_dat_set_s cn50xx; @@ -164,15 +185,28 @@ union cvmx_asxx_mii_rx_dat_set { union cvmx_asxx_prt_loop { uint64_t u64; struct cvmx_asxx_prt_loop_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ext_loop:4; uint64_t int_loop:4; +#else + uint64_t int_loop:4; + uint64_t ext_loop:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_asxx_prt_loop_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t ext_loop:3; uint64_t reserved_3_3:1; uint64_t int_loop:3; +#else + uint64_t int_loop:3; + uint64_t reserved_3_3:1; + uint64_t ext_loop:3; + uint64_t reserved_7_63:57; +#endif } cn30xx; struct cvmx_asxx_prt_loop_cn30xx cn31xx; struct cvmx_asxx_prt_loop_s cn38xx; @@ -185,8 +219,13 @@ union cvmx_asxx_prt_loop { union cvmx_asxx_rld_bypass { uint64_t u64; struct cvmx_asxx_rld_bypass_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t bypass:1; +#else + uint64_t bypass:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_asxx_rld_bypass_s cn38xx; struct cvmx_asxx_rld_bypass_s cn38xxp2; @@ -197,8 +236,13 @@ union cvmx_asxx_rld_bypass { union cvmx_asxx_rld_bypass_setting { uint64_t u64; struct cvmx_asxx_rld_bypass_setting_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_rld_bypass_setting_s cn38xx; struct cvmx_asxx_rld_bypass_setting_s cn38xxp2; @@ -209,14 +253,26 @@ union cvmx_asxx_rld_bypass_setting { union cvmx_asxx_rld_comp { uint64_t u64; struct cvmx_asxx_rld_comp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t pctl:5; uint64_t nctl:4; +#else + uint64_t nctl:4; + uint64_t pctl:5; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_asxx_rld_comp_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t pctl:4; uint64_t nctl:4; +#else + uint64_t nctl:4; + uint64_t pctl:4; + uint64_t reserved_8_63:56; +#endif } cn38xx; struct cvmx_asxx_rld_comp_cn38xx cn38xxp2; struct cvmx_asxx_rld_comp_s cn58xx; @@ -226,9 +282,15 @@ union cvmx_asxx_rld_comp { union cvmx_asxx_rld_data_drv { uint64_t u64; struct cvmx_asxx_rld_data_drv_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t pctl:4; uint64_t nctl:4; +#else + uint64_t nctl:4; + uint64_t pctl:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_asxx_rld_data_drv_s cn38xx; struct cvmx_asxx_rld_data_drv_s cn38xxp2; @@ -239,8 +301,13 @@ union cvmx_asxx_rld_data_drv { union cvmx_asxx_rld_fcram_mode { uint64_t u64; struct cvmx_asxx_rld_fcram_mode_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t mode:1; +#else + uint64_t mode:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_asxx_rld_fcram_mode_s cn38xx; struct cvmx_asxx_rld_fcram_mode_s cn38xxp2; @@ -249,8 +316,13 @@ union cvmx_asxx_rld_fcram_mode { union cvmx_asxx_rld_nctl_strong { uint64_t u64; struct cvmx_asxx_rld_nctl_strong_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_rld_nctl_strong_s cn38xx; struct cvmx_asxx_rld_nctl_strong_s cn38xxp2; @@ -261,8 +333,13 @@ union cvmx_asxx_rld_nctl_strong { union cvmx_asxx_rld_nctl_weak { uint64_t u64; struct cvmx_asxx_rld_nctl_weak_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_rld_nctl_weak_s cn38xx; struct cvmx_asxx_rld_nctl_weak_s cn38xxp2; @@ -273,8 +350,13 @@ union cvmx_asxx_rld_nctl_weak { union cvmx_asxx_rld_pctl_strong { uint64_t u64; struct cvmx_asxx_rld_pctl_strong_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t pctl:5; +#else + uint64_t pctl:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_rld_pctl_strong_s cn38xx; struct cvmx_asxx_rld_pctl_strong_s cn38xxp2; @@ -285,8 +367,13 @@ union cvmx_asxx_rld_pctl_strong { union cvmx_asxx_rld_pctl_weak { uint64_t u64; struct cvmx_asxx_rld_pctl_weak_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t pctl:5; +#else + uint64_t pctl:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_rld_pctl_weak_s cn38xx; struct cvmx_asxx_rld_pctl_weak_s cn38xxp2; @@ -297,16 +384,30 @@ union cvmx_asxx_rld_pctl_weak { union cvmx_asxx_rld_setting { uint64_t u64; struct cvmx_asxx_rld_setting_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t dfaset:5; uint64_t dfalag:1; uint64_t dfalead:1; uint64_t dfalock:1; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t dfalock:1; + uint64_t dfalead:1; + uint64_t dfalag:1; + uint64_t dfaset:5; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_asxx_rld_setting_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t reserved_5_63:59; +#endif } cn38xx; struct cvmx_asxx_rld_setting_cn38xx cn38xxp2; struct cvmx_asxx_rld_setting_s cn58xx; @@ -316,8 +417,13 @@ union cvmx_asxx_rld_setting { union cvmx_asxx_rx_clk_setx { uint64_t u64; struct cvmx_asxx_rx_clk_setx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_rx_clk_setx_s cn30xx; struct cvmx_asxx_rx_clk_setx_s cn31xx; @@ -331,12 +437,22 @@ union cvmx_asxx_rx_clk_setx { union cvmx_asxx_rx_prt_en { uint64_t u64; struct cvmx_asxx_rx_prt_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t prt_en:4; +#else + uint64_t prt_en:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_asxx_rx_prt_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t prt_en:3; +#else + uint64_t prt_en:3; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_asxx_rx_prt_en_cn30xx cn31xx; struct cvmx_asxx_rx_prt_en_s cn38xx; @@ -349,9 +465,15 @@ union cvmx_asxx_rx_prt_en { union cvmx_asxx_rx_wol { uint64_t u64; struct cvmx_asxx_rx_wol_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t status:1; uint64_t enable:1; +#else + uint64_t enable:1; + uint64_t status:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_asxx_rx_wol_s cn38xx; struct cvmx_asxx_rx_wol_s cn38xxp2; @@ -360,7 +482,11 @@ union cvmx_asxx_rx_wol { union cvmx_asxx_rx_wol_msk { uint64_t u64; struct cvmx_asxx_rx_wol_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t msk:64; +#else uint64_t msk:64; +#endif } s; struct cvmx_asxx_rx_wol_msk_s cn38xx; struct cvmx_asxx_rx_wol_msk_s cn38xxp2; @@ -369,8 +495,13 @@ union cvmx_asxx_rx_wol_msk { union cvmx_asxx_rx_wol_powok { uint64_t u64; struct cvmx_asxx_rx_wol_powok_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t powerok:1; +#else + uint64_t powerok:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_asxx_rx_wol_powok_s cn38xx; struct cvmx_asxx_rx_wol_powok_s cn38xxp2; @@ -379,8 +510,13 @@ union cvmx_asxx_rx_wol_powok { union cvmx_asxx_rx_wol_sig { uint64_t u64; struct cvmx_asxx_rx_wol_sig_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t sig:32; +#else + uint64_t sig:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_asxx_rx_wol_sig_s cn38xx; struct cvmx_asxx_rx_wol_sig_s cn38xxp2; @@ -389,8 +525,13 @@ union cvmx_asxx_rx_wol_sig { union cvmx_asxx_tx_clk_setx { uint64_t u64; struct cvmx_asxx_tx_clk_setx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_tx_clk_setx_s cn30xx; struct cvmx_asxx_tx_clk_setx_s cn31xx; @@ -404,34 +545,67 @@ union cvmx_asxx_tx_clk_setx { union cvmx_asxx_tx_comp_byp { uint64_t u64; struct cvmx_asxx_tx_comp_byp_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else uint64_t reserved_0_63:64; +#endif } s; struct cvmx_asxx_tx_comp_byp_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t bypass:1; uint64_t pctl:4; uint64_t nctl:4; +#else + uint64_t nctl:4; + uint64_t pctl:4; + uint64_t bypass:1; + uint64_t reserved_9_63:55; +#endif } cn30xx; struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx; struct cvmx_asxx_tx_comp_byp_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t pctl:4; uint64_t nctl:4; +#else + uint64_t nctl:4; + uint64_t pctl:4; + uint64_t reserved_8_63:56; +#endif } cn38xx; struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2; struct cvmx_asxx_tx_comp_byp_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t bypass:1; uint64_t reserved_13_15:3; uint64_t pctl:5; uint64_t reserved_5_7:3; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t reserved_5_7:3; + uint64_t pctl:5; + uint64_t reserved_13_15:3; + uint64_t bypass:1; + uint64_t reserved_17_63:47; +#endif } cn50xx; struct cvmx_asxx_tx_comp_byp_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t pctl:5; uint64_t reserved_5_7:3; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t reserved_5_7:3; + uint64_t pctl:5; + uint64_t reserved_13_63:51; +#endif } cn58xx; struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1; }; @@ -439,12 +613,22 @@ union cvmx_asxx_tx_comp_byp { union cvmx_asxx_tx_hi_waterx { uint64_t u64; struct cvmx_asxx_tx_hi_waterx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t mark:4; +#else + uint64_t mark:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_asxx_tx_hi_waterx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t mark:3; +#else + uint64_t mark:3; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx; struct cvmx_asxx_tx_hi_waterx_s cn38xx; @@ -457,12 +641,22 @@ union cvmx_asxx_tx_hi_waterx { union cvmx_asxx_tx_prt_en { uint64_t u64; struct cvmx_asxx_tx_prt_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t prt_en:4; +#else + uint64_t prt_en:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_asxx_tx_prt_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t prt_en:3; +#else + uint64_t prt_en:3; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_asxx_tx_prt_en_cn30xx cn31xx; struct cvmx_asxx_tx_prt_en_s cn38xx; diff --git a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h index 27cead370411..0dd0e40c96d4 100644 --- a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -31,6 +31,18 @@ #define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull)) #define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull)) #define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull)) +#define CVMX_CIU_EN2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8) +#define CVMX_CIU_EN2_IOX_INT_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8) +#define CVMX_CIU_EN2_IOX_INT_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8) +#define CVMX_CIU_EN2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP2_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP2_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP3_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP3_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP4_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP4_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8) #define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull)) #define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull)) #define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull)) @@ -50,59 +62,378 @@ #define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8) #define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull)) #define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull)) -#define CVMX_CIU_MBOX_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8) -#define CVMX_CIU_MBOX_SETX(offset) (CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8) +static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070100100600ull) + (offset) * 8; + } + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; +} + +static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070100100400ull) + (offset) * 8; + } + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; +} + #define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull)) #define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull)) +#define CVMX_CIU_PP_BIST_STAT (CVMX_ADD_IO_SEG(0x00010700000007E0ull)) #define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull)) -#define CVMX_CIU_PP_POKEX(offset) (CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8) +static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070100100200ull) + (offset) * 8; + } + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; +} + #define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull)) #define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull)) #define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull)) #define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull)) +#define CVMX_CIU_QLM3 (CVMX_ADD_IO_SEG(0x0001070000000798ull)) +#define CVMX_CIU_QLM4 (CVMX_ADD_IO_SEG(0x00010700000007A0ull)) #define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull)) #define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull)) #define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull)) #define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull)) #define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull)) #define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull)) +#define CVMX_CIU_SOFT_PRST2 (CVMX_ADD_IO_SEG(0x00010700000007D8ull)) +#define CVMX_CIU_SOFT_PRST3 (CVMX_ADD_IO_SEG(0x00010700000007E0ull)) #define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull)) -#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8) -#define CVMX_CIU_WDOGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8) +#define CVMX_CIU_SUM1_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8) +#define CVMX_CIU_SUM1_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8) +#define CVMX_CIU_SUM1_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8) +#define CVMX_CIU_SUM1_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8) +#define CVMX_CIU_SUM2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8) +#define CVMX_CIU_SUM2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8) +#define CVMX_CIU_SUM2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8) +#define CVMX_CIU_SUM2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8) +#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8) +#define CVMX_CIU_TIM_MULTI_CAST (CVMX_ADD_IO_SEG(0x000107000000C200ull)) +static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070100100000ull) + (offset) * 8; + } + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; +} union cvmx_ciu_bist { uint64_t u64; struct cvmx_ciu_bist_s { - uint64_t reserved_5_63:59; - uint64_t bist:5; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t bist:7; +#else + uint64_t bist:7; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_ciu_bist_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t bist:4; +#else + uint64_t bist:4; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_ciu_bist_cn30xx cn31xx; struct cvmx_ciu_bist_cn30xx cn38xx; struct cvmx_ciu_bist_cn30xx cn38xxp2; struct cvmx_ciu_bist_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t bist:2; +#else + uint64_t bist:2; + uint64_t reserved_2_63:62; +#endif } cn50xx; struct cvmx_ciu_bist_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t bist:3; +#else + uint64_t bist:3; + uint64_t reserved_3_63:61; +#endif } cn52xx; struct cvmx_ciu_bist_cn52xx cn52xxp1; struct cvmx_ciu_bist_cn30xx cn56xx; struct cvmx_ciu_bist_cn30xx cn56xxp1; struct cvmx_ciu_bist_cn30xx cn58xx; struct cvmx_ciu_bist_cn30xx cn58xxp1; - struct cvmx_ciu_bist_s cn63xx; - struct cvmx_ciu_bist_s cn63xxp1; + struct cvmx_ciu_bist_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_63:58; + uint64_t bist:6; +#else + uint64_t bist:6; + uint64_t reserved_6_63:58; +#endif + } cn61xx; + struct cvmx_ciu_bist_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_5_63:59; + uint64_t bist:5; +#else + uint64_t bist:5; + uint64_t reserved_5_63:59; +#endif + } cn63xx; + struct cvmx_ciu_bist_cn63xx cn63xxp1; + struct cvmx_ciu_bist_cn61xx cn66xx; + struct cvmx_ciu_bist_s cn68xx; + struct cvmx_ciu_bist_s cn68xxp1; + struct cvmx_ciu_bist_cn61xx cnf71xx; }; union cvmx_ciu_block_int { uint64_t u64; struct cvmx_ciu_block_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_62_63:2; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_43_59:17; + uint64_t ptp:1; + uint64_t dpi:1; + uint64_t dfm:1; + uint64_t reserved_34_39:6; + uint64_t srio1:1; + uint64_t srio0:1; + uint64_t reserved_31_31:1; + uint64_t iob:1; + uint64_t reserved_29_29:1; + uint64_t agl:1; + uint64_t reserved_27_27:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t reserved_24_24:1; + uint64_t asxpcs1:1; + uint64_t asxpcs0:1; + uint64_t reserved_21_21:1; + uint64_t pip:1; + uint64_t reserved_18_19:2; + uint64_t lmc0:1; + uint64_t l2c:1; + uint64_t reserved_15_15:1; + uint64_t rad:1; + uint64_t usb:1; + uint64_t pow:1; + uint64_t tim:1; + uint64_t pko:1; + uint64_t ipd:1; + uint64_t reserved_8_8:1; + uint64_t zip:1; + uint64_t dfa:1; + uint64_t fpa:1; + uint64_t key:1; + uint64_t sli:1; + uint64_t gmx1:1; + uint64_t gmx0:1; + uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t sli:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t reserved_8_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rad:1; + uint64_t reserved_15_15:1; + uint64_t l2c:1; + uint64_t lmc0:1; + uint64_t reserved_18_19:2; + uint64_t pip:1; + uint64_t reserved_21_21:1; + uint64_t asxpcs0:1; + uint64_t asxpcs1:1; + uint64_t reserved_24_24:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_27_27:1; + uint64_t agl:1; + uint64_t reserved_29_29:1; + uint64_t iob:1; + uint64_t reserved_31_31:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t reserved_34_39:6; + uint64_t dfm:1; + uint64_t dpi:1; + uint64_t ptp:1; + uint64_t reserved_43_59:17; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_63:2; +#endif + } s; + struct cvmx_ciu_block_int_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_43_63:21; + uint64_t ptp:1; + uint64_t dpi:1; + uint64_t reserved_31_40:10; + uint64_t iob:1; + uint64_t reserved_29_29:1; + uint64_t agl:1; + uint64_t reserved_27_27:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t reserved_24_24:1; + uint64_t asxpcs1:1; + uint64_t asxpcs0:1; + uint64_t reserved_21_21:1; + uint64_t pip:1; + uint64_t reserved_18_19:2; + uint64_t lmc0:1; + uint64_t l2c:1; + uint64_t reserved_15_15:1; + uint64_t rad:1; + uint64_t usb:1; + uint64_t pow:1; + uint64_t tim:1; + uint64_t pko:1; + uint64_t ipd:1; + uint64_t reserved_8_8:1; + uint64_t zip:1; + uint64_t dfa:1; + uint64_t fpa:1; + uint64_t key:1; + uint64_t sli:1; + uint64_t gmx1:1; + uint64_t gmx0:1; + uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t sli:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t reserved_8_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rad:1; + uint64_t reserved_15_15:1; + uint64_t l2c:1; + uint64_t lmc0:1; + uint64_t reserved_18_19:2; + uint64_t pip:1; + uint64_t reserved_21_21:1; + uint64_t asxpcs0:1; + uint64_t asxpcs1:1; + uint64_t reserved_24_24:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_27_27:1; + uint64_t agl:1; + uint64_t reserved_29_29:1; + uint64_t iob:1; + uint64_t reserved_31_40:10; + uint64_t dpi:1; + uint64_t ptp:1; + uint64_t reserved_43_63:21; +#endif + } cn61xx; + struct cvmx_ciu_block_int_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_43_63:21; uint64_t ptp:1; uint64_t dpi:1; @@ -140,88 +471,789 @@ union cvmx_ciu_block_int { uint64_t reserved_2_2:1; uint64_t gmx0:1; uint64_t mio:1; - } s; - struct cvmx_ciu_block_int_s cn63xx; - struct cvmx_ciu_block_int_s cn63xxp1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t reserved_2_2:1; + uint64_t sli:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t reserved_8_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rad:1; + uint64_t reserved_15_15:1; + uint64_t l2c:1; + uint64_t lmc0:1; + uint64_t reserved_18_19:2; + uint64_t pip:1; + uint64_t reserved_21_21:1; + uint64_t asxpcs0:1; + uint64_t reserved_23_24:2; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_27_27:1; + uint64_t agl:1; + uint64_t reserved_29_29:1; + uint64_t iob:1; + uint64_t reserved_31_31:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t reserved_34_39:6; + uint64_t dfm:1; + uint64_t dpi:1; + uint64_t ptp:1; + uint64_t reserved_43_63:21; +#endif + } cn63xx; + struct cvmx_ciu_block_int_cn63xx cn63xxp1; + struct cvmx_ciu_block_int_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_62_63:2; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_43_59:17; + uint64_t ptp:1; + uint64_t dpi:1; + uint64_t dfm:1; + uint64_t reserved_33_39:7; + uint64_t srio0:1; + uint64_t reserved_31_31:1; + uint64_t iob:1; + uint64_t reserved_29_29:1; + uint64_t agl:1; + uint64_t reserved_27_27:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t reserved_24_24:1; + uint64_t asxpcs1:1; + uint64_t asxpcs0:1; + uint64_t reserved_21_21:1; + uint64_t pip:1; + uint64_t reserved_18_19:2; + uint64_t lmc0:1; + uint64_t l2c:1; + uint64_t reserved_15_15:1; + uint64_t rad:1; + uint64_t usb:1; + uint64_t pow:1; + uint64_t tim:1; + uint64_t pko:1; + uint64_t ipd:1; + uint64_t reserved_8_8:1; + uint64_t zip:1; + uint64_t dfa:1; + uint64_t fpa:1; + uint64_t key:1; + uint64_t sli:1; + uint64_t gmx1:1; + uint64_t gmx0:1; + uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t sli:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t reserved_8_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rad:1; + uint64_t reserved_15_15:1; + uint64_t l2c:1; + uint64_t lmc0:1; + uint64_t reserved_18_19:2; + uint64_t pip:1; + uint64_t reserved_21_21:1; + uint64_t asxpcs0:1; + uint64_t asxpcs1:1; + uint64_t reserved_24_24:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_27_27:1; + uint64_t agl:1; + uint64_t reserved_29_29:1; + uint64_t iob:1; + uint64_t reserved_31_31:1; + uint64_t srio0:1; + uint64_t reserved_33_39:7; + uint64_t dfm:1; + uint64_t dpi:1; + uint64_t ptp:1; + uint64_t reserved_43_59:17; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_63:2; +#endif + } cn66xx; + struct cvmx_ciu_block_int_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_43_63:21; + uint64_t ptp:1; + uint64_t dpi:1; + uint64_t reserved_31_40:10; + uint64_t iob:1; + uint64_t reserved_27_29:3; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t reserved_23_24:2; + uint64_t asxpcs0:1; + uint64_t reserved_21_21:1; + uint64_t pip:1; + uint64_t reserved_18_19:2; + uint64_t lmc0:1; + uint64_t l2c:1; + uint64_t reserved_15_15:1; + uint64_t rad:1; + uint64_t usb:1; + uint64_t pow:1; + uint64_t tim:1; + uint64_t pko:1; + uint64_t ipd:1; + uint64_t reserved_6_8:3; + uint64_t fpa:1; + uint64_t key:1; + uint64_t sli:1; + uint64_t reserved_2_2:1; + uint64_t gmx0:1; + uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t reserved_2_2:1; + uint64_t sli:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t reserved_6_8:3; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rad:1; + uint64_t reserved_15_15:1; + uint64_t l2c:1; + uint64_t lmc0:1; + uint64_t reserved_18_19:2; + uint64_t pip:1; + uint64_t reserved_21_21:1; + uint64_t asxpcs0:1; + uint64_t reserved_23_24:2; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_27_29:3; + uint64_t iob:1; + uint64_t reserved_31_40:10; + uint64_t dpi:1; + uint64_t ptp:1; + uint64_t reserved_43_63:21; +#endif + } cnf71xx; }; union cvmx_ciu_dint { uint64_t u64; struct cvmx_ciu_dint_s { - uint64_t reserved_16_63:48; - uint64_t dint:16; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t dint:32; +#else + uint64_t dint:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ciu_dint_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t dint:1; +#else + uint64_t dint:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_ciu_dint_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dint:2; +#else + uint64_t dint:2; + uint64_t reserved_2_63:62; +#endif } cn31xx; - struct cvmx_ciu_dint_s cn38xx; - struct cvmx_ciu_dint_s cn38xxp2; + struct cvmx_ciu_dint_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t dint:16; +#else + uint64_t dint:16; + uint64_t reserved_16_63:48; +#endif + } cn38xx; + struct cvmx_ciu_dint_cn38xx cn38xxp2; struct cvmx_ciu_dint_cn31xx cn50xx; struct cvmx_ciu_dint_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t dint:4; +#else + uint64_t dint:4; + uint64_t reserved_4_63:60; +#endif } cn52xx; struct cvmx_ciu_dint_cn52xx cn52xxp1; struct cvmx_ciu_dint_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t dint:12; +#else + uint64_t dint:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_dint_cn56xx cn56xxp1; - struct cvmx_ciu_dint_s cn58xx; - struct cvmx_ciu_dint_s cn58xxp1; + struct cvmx_ciu_dint_cn38xx cn58xx; + struct cvmx_ciu_dint_cn38xx cn58xxp1; + struct cvmx_ciu_dint_cn52xx cn61xx; struct cvmx_ciu_dint_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t dint:6; +#else + uint64_t dint:6; + uint64_t reserved_6_63:58; +#endif } cn63xx; struct cvmx_ciu_dint_cn63xx cn63xxp1; + struct cvmx_ciu_dint_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t dint:10; +#else + uint64_t dint:10; + uint64_t reserved_10_63:54; +#endif + } cn66xx; + struct cvmx_ciu_dint_s cn68xx; + struct cvmx_ciu_dint_s cn68xxp1; + struct cvmx_ciu_dint_cn52xx cnf71xx; +}; + +union cvmx_ciu_en2_iox_int { + uint64_t u64; + struct cvmx_ciu_en2_iox_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_iox_int_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_iox_int_cn61xx cn66xx; + struct cvmx_ciu_en2_iox_int_s cnf71xx; +}; + +union cvmx_ciu_en2_iox_int_w1c { + uint64_t u64; + struct cvmx_ciu_en2_iox_int_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_iox_int_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_iox_int_w1c_cn61xx cn66xx; + struct cvmx_ciu_en2_iox_int_w1c_s cnf71xx; +}; + +union cvmx_ciu_en2_iox_int_w1s { + uint64_t u64; + struct cvmx_ciu_en2_iox_int_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_iox_int_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_iox_int_w1s_cn61xx cn66xx; + struct cvmx_ciu_en2_iox_int_w1s_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip2 { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip2_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip2_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip2_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip2_w1c { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip2_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip2_w1c_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip2_w1s { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip2_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip2_w1s_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip3 { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip3_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip3_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip3_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip3_w1c { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip3_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip3_w1c_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip3_w1s { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip3_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip3_w1s_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip4 { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip4_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip4_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip4_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip4_w1c { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip4_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip4_w1c_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip4_w1s { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip4_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip4_w1s_s cnf71xx; }; union cvmx_ciu_fuse { uint64_t u64; struct cvmx_ciu_fuse_s { - uint64_t reserved_16_63:48; - uint64_t fuse:16; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t fuse:32; +#else + uint64_t fuse:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ciu_fuse_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t fuse:1; +#else + uint64_t fuse:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_ciu_fuse_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t fuse:2; +#else + uint64_t fuse:2; + uint64_t reserved_2_63:62; +#endif } cn31xx; - struct cvmx_ciu_fuse_s cn38xx; - struct cvmx_ciu_fuse_s cn38xxp2; + struct cvmx_ciu_fuse_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t fuse:16; +#else + uint64_t fuse:16; + uint64_t reserved_16_63:48; +#endif + } cn38xx; + struct cvmx_ciu_fuse_cn38xx cn38xxp2; struct cvmx_ciu_fuse_cn31xx cn50xx; struct cvmx_ciu_fuse_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t fuse:4; +#else + uint64_t fuse:4; + uint64_t reserved_4_63:60; +#endif } cn52xx; struct cvmx_ciu_fuse_cn52xx cn52xxp1; struct cvmx_ciu_fuse_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t fuse:12; +#else + uint64_t fuse:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_fuse_cn56xx cn56xxp1; - struct cvmx_ciu_fuse_s cn58xx; - struct cvmx_ciu_fuse_s cn58xxp1; + struct cvmx_ciu_fuse_cn38xx cn58xx; + struct cvmx_ciu_fuse_cn38xx cn58xxp1; + struct cvmx_ciu_fuse_cn52xx cn61xx; struct cvmx_ciu_fuse_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t fuse:6; +#else + uint64_t fuse:6; + uint64_t reserved_6_63:58; +#endif } cn63xx; struct cvmx_ciu_fuse_cn63xx cn63xxp1; + struct cvmx_ciu_fuse_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t fuse:10; +#else + uint64_t fuse:10; + uint64_t reserved_10_63:54; +#endif + } cn66xx; + struct cvmx_ciu_fuse_s cn68xx; + struct cvmx_ciu_fuse_s cn68xxp1; + struct cvmx_ciu_fuse_cn52xx cnf71xx; }; union cvmx_ciu_gstop { uint64_t u64; struct cvmx_ciu_gstop_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t gstop:1; +#else + uint64_t gstop:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_ciu_gstop_s cn30xx; struct cvmx_ciu_gstop_s cn31xx; @@ -234,13 +1266,19 @@ union cvmx_ciu_gstop { struct cvmx_ciu_gstop_s cn56xxp1; struct cvmx_ciu_gstop_s cn58xx; struct cvmx_ciu_gstop_s cn58xxp1; + struct cvmx_ciu_gstop_s cn61xx; struct cvmx_ciu_gstop_s cn63xx; struct cvmx_ciu_gstop_s cn63xxp1; + struct cvmx_ciu_gstop_s cn66xx; + struct cvmx_ciu_gstop_s cn68xx; + struct cvmx_ciu_gstop_s cn68xxp1; + struct cvmx_ciu_gstop_s cnf71xx; }; union cvmx_ciu_intx_en0 { uint64_t u64; struct cvmx_ciu_intx_en0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -263,8 +1301,33 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_en0_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t mpi:1; uint64_t pcm:1; @@ -284,8 +1347,30 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t reserved_47_47:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t reserved_59_63:5; +#endif } cn30xx; struct cvmx_ciu_intx_en0_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t mpi:1; uint64_t pcm:1; @@ -305,8 +1390,30 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t reserved_59_63:5; +#endif } cn31xx; struct cvmx_ciu_intx_en0_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -322,10 +1429,28 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn38xx; struct cvmx_ciu_intx_en0_cn38xx cn38xxp2; struct cvmx_ciu_intx_en0_cn30xx cn50xx; struct cvmx_ciu_intx_en0_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -348,9 +1473,34 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; struct cvmx_ciu_intx_en0_cn52xx cn52xxp1; struct cvmx_ciu_intx_en0_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -372,23 +1522,197 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn56xx; struct cvmx_ciu_intx_en0_cn56xx cn56xxp1; struct cvmx_ciu_intx_en0_cn38xx cn58xx; struct cvmx_ciu_intx_en0_cn38xx cn58xxp1; + struct cvmx_ciu_intx_en0_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en0_cn52xx cn63xx; struct cvmx_ciu_intx_en0_cn52xx cn63xxp1; + struct cvmx_ciu_intx_en0_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en0_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en0_w1c { uint64_t u64; struct cvmx_ciu_intx_en0_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; uint64_t powiq:1; uint64_t twsi2:1; - uint64_t reserved_57_58:2; + uint64_t mpi:1; + uint64_t pcm:1; uint64_t usb:1; uint64_t timer:4; uint64_t key_zero:1; @@ -404,8 +1728,33 @@ union cvmx_ciu_intx_en0_w1c { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_en0_w1c_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -428,9 +1777,80 @@ union cvmx_ciu_intx_en0_w1c { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; - struct cvmx_ciu_intx_en0_w1c_s cn56xx; + struct cvmx_ciu_intx_en0_w1c_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; + uint64_t usb:1; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn56xx; struct cvmx_ciu_intx_en0_w1c_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -446,20 +1866,188 @@ union cvmx_ciu_intx_en0_w1c { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn58xx; + struct cvmx_ciu_intx_en0_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx; struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1; + struct cvmx_ciu_intx_en0_w1c_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en0_w1c_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en0_w1s { uint64_t u64; struct cvmx_ciu_intx_en0_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; uint64_t powiq:1; uint64_t twsi2:1; - uint64_t reserved_57_58:2; + uint64_t mpi:1; + uint64_t pcm:1; uint64_t usb:1; uint64_t timer:4; uint64_t key_zero:1; @@ -475,8 +2063,33 @@ union cvmx_ciu_intx_en0_w1s { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_en0_w1s_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -499,9 +2112,80 @@ union cvmx_ciu_intx_en0_w1s { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; - struct cvmx_ciu_intx_en0_w1s_s cn56xx; + struct cvmx_ciu_intx_en0_w1s_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; + uint64_t usb:1; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn56xx; struct cvmx_ciu_intx_en0_w1s_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -517,16 +2201,186 @@ union cvmx_ciu_intx_en0_w1s { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn58xx; + struct cvmx_ciu_intx_en0_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx; struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1; + struct cvmx_ciu_intx_en0_w1s_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en0_w1s_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en1 { uint64_t u64; struct cvmx_ciu_intx_en1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; - uint64_t reserved_57_62:6; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; @@ -536,7 +2390,10 @@ union cvmx_ciu_intx_en1 { uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_37_45:9; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -559,22 +2416,80 @@ union cvmx_ciu_intx_en1 { uint64_t usb1:1; uint64_t uart2:1; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif } s; struct cvmx_ciu_intx_en1_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t wdog:1; +#else + uint64_t wdog:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_ciu_intx_en1_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t wdog:2; +#else + uint64_t wdog:2; + uint64_t reserved_2_63:62; +#endif } cn31xx; struct cvmx_ciu_intx_en1_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_ciu_intx_en1_cn38xx cn38xxp2; struct cvmx_ciu_intx_en1_cn31xx cn50xx; struct cvmx_ciu_intx_en1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t nand:1; uint64_t mii1:1; @@ -582,23 +2497,118 @@ union cvmx_ciu_intx_en1 { uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_ciu_intx_en1_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t mii1:1; uint64_t usb1:1; uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t reserved_19_63:45; +#endif } cn52xxp1; struct cvmx_ciu_intx_en1_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t wdog:12; +#else + uint64_t wdog:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_intx_en1_cn56xx cn56xxp1; struct cvmx_ciu_intx_en1_cn38xx cn58xx; struct cvmx_ciu_intx_en1_cn38xx cn58xxp1; + struct cvmx_ciu_intx_en1_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en1_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; uint64_t reserved_57_62:6; uint64_t dfm:1; @@ -632,15 +2642,198 @@ union cvmx_ciu_intx_en1 { uint64_t mii1:1; uint64_t reserved_6_17:12; uint64_t wdog:6; +#else + uint64_t wdog:6; + uint64_t reserved_6_17:12; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_45:9; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_62:6; + uint64_t rst:1; +#endif } cn63xx; struct cvmx_ciu_intx_en1_cn63xx cn63xxp1; + struct cvmx_ciu_intx_en1_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en1_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en1_w1c { uint64_t u64; struct cvmx_ciu_intx_en1_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; - uint64_t reserved_57_62:6; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; @@ -650,7 +2843,10 @@ union cvmx_ciu_intx_en1_w1c { uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_37_45:9; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -673,8 +2869,51 @@ union cvmx_ciu_intx_en1_w1c { uint64_t usb1:1; uint64_t uart2:1; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif } s; struct cvmx_ciu_intx_en1_w1c_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t nand:1; uint64_t mii1:1; @@ -682,16 +2921,107 @@ union cvmx_ciu_intx_en1_w1c { uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_ciu_intx_en1_w1c_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t wdog:12; +#else + uint64_t wdog:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_intx_en1_w1c_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t reserved_16_63:48; +#endif } cn58xx; + struct cvmx_ciu_intx_en1_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en1_w1c_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; uint64_t reserved_57_62:6; uint64_t dfm:1; @@ -725,15 +3055,198 @@ union cvmx_ciu_intx_en1_w1c { uint64_t mii1:1; uint64_t reserved_6_17:12; uint64_t wdog:6; +#else + uint64_t wdog:6; + uint64_t reserved_6_17:12; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_45:9; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_62:6; + uint64_t rst:1; +#endif } cn63xx; struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1; + struct cvmx_ciu_intx_en1_w1c_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en1_w1c_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en1_w1s { uint64_t u64; struct cvmx_ciu_intx_en1_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; - uint64_t reserved_57_62:6; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; @@ -743,7 +3256,10 @@ union cvmx_ciu_intx_en1_w1s { uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_37_45:9; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -766,8 +3282,51 @@ union cvmx_ciu_intx_en1_w1s { uint64_t usb1:1; uint64_t uart2:1; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif } s; struct cvmx_ciu_intx_en1_w1s_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t nand:1; uint64_t mii1:1; @@ -775,16 +3334,107 @@ union cvmx_ciu_intx_en1_w1s { uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_ciu_intx_en1_w1s_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t wdog:12; +#else + uint64_t wdog:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_intx_en1_w1s_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t reserved_16_63:48; +#endif } cn58xx; + struct cvmx_ciu_intx_en1_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en1_w1s_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; uint64_t reserved_57_62:6; uint64_t dfm:1; @@ -818,13 +3468,193 @@ union cvmx_ciu_intx_en1_w1s { uint64_t mii1:1; uint64_t reserved_6_17:12; uint64_t wdog:6; +#else + uint64_t wdog:6; + uint64_t reserved_6_17:12; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_45:9; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_62:6; + uint64_t rst:1; +#endif } cn63xx; struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1; + struct cvmx_ciu_intx_en1_w1s_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en1_w1s_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en4_0 { uint64_t u64; struct cvmx_ciu_intx_en4_0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -847,8 +3677,33 @@ union cvmx_ciu_intx_en4_0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_en4_0_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t mpi:1; uint64_t pcm:1; @@ -868,8 +3723,30 @@ union cvmx_ciu_intx_en4_0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t reserved_47_47:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t reserved_59_63:5; +#endif } cn50xx; struct cvmx_ciu_intx_en4_0_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -892,9 +3769,34 @@ union cvmx_ciu_intx_en4_0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1; struct cvmx_ciu_intx_en4_0_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -916,9 +3818,33 @@ union cvmx_ciu_intx_en4_0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn56xx; struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1; struct cvmx_ciu_intx_en4_0_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -934,21 +3860,189 @@ union cvmx_ciu_intx_en4_0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn58xx; struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1; + struct cvmx_ciu_intx_en4_0_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en4_0_cn52xx cn63xx; struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1; + struct cvmx_ciu_intx_en4_0_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en4_0_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en4_0_w1c { uint64_t u64; struct cvmx_ciu_intx_en4_0_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; uint64_t powiq:1; uint64_t twsi2:1; - uint64_t reserved_57_58:2; + uint64_t mpi:1; + uint64_t pcm:1; uint64_t usb:1; uint64_t timer:4; uint64_t key_zero:1; @@ -964,8 +4058,33 @@ union cvmx_ciu_intx_en4_0_w1c { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_en4_0_w1c_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -988,9 +4107,80 @@ union cvmx_ciu_intx_en4_0_w1c { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; - struct cvmx_ciu_intx_en4_0_w1c_s cn56xx; + struct cvmx_ciu_intx_en4_0_w1c_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; + uint64_t usb:1; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn56xx; struct cvmx_ciu_intx_en4_0_w1c_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -1006,20 +4196,188 @@ union cvmx_ciu_intx_en4_0_w1c { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn58xx; + struct cvmx_ciu_intx_en4_0_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx; struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1; + struct cvmx_ciu_intx_en4_0_w1c_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en4_0_w1c_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en4_0_w1s { uint64_t u64; struct cvmx_ciu_intx_en4_0_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; uint64_t powiq:1; uint64_t twsi2:1; - uint64_t reserved_57_58:2; + uint64_t mpi:1; + uint64_t pcm:1; uint64_t usb:1; uint64_t timer:4; uint64_t key_zero:1; @@ -1035,8 +4393,33 @@ union cvmx_ciu_intx_en4_0_w1s { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_en4_0_w1s_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1059,9 +4442,80 @@ union cvmx_ciu_intx_en4_0_w1s { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; - struct cvmx_ciu_intx_en4_0_w1s_s cn56xx; + struct cvmx_ciu_intx_en4_0_w1s_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; + uint64_t usb:1; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn56xx; struct cvmx_ciu_intx_en4_0_w1s_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -1077,16 +4531,186 @@ union cvmx_ciu_intx_en4_0_w1s { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn58xx; + struct cvmx_ciu_intx_en4_0_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx; struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1; + struct cvmx_ciu_intx_en4_0_w1s_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en4_0_w1s_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en4_1 { uint64_t u64; struct cvmx_ciu_intx_en4_1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; - uint64_t reserved_57_62:6; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; @@ -1096,7 +4720,10 @@ union cvmx_ciu_intx_en4_1 { uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_37_45:9; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -1119,12 +4746,60 @@ union cvmx_ciu_intx_en4_1 { uint64_t usb1:1; uint64_t uart2:1; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif } s; struct cvmx_ciu_intx_en4_1_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t wdog:2; +#else + uint64_t wdog:2; + uint64_t reserved_2_63:62; +#endif } cn50xx; struct cvmx_ciu_intx_en4_1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t nand:1; uint64_t mii1:1; @@ -1132,26 +4807,126 @@ union cvmx_ciu_intx_en4_1 { uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_ciu_intx_en4_1_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t mii1:1; uint64_t usb1:1; uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t reserved_19_63:45; +#endif } cn52xxp1; struct cvmx_ciu_intx_en4_1_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t wdog:12; +#else + uint64_t wdog:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1; struct cvmx_ciu_intx_en4_1_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t reserved_16_63:48; +#endif } cn58xx; struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1; + struct cvmx_ciu_intx_en4_1_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en4_1_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; uint64_t reserved_57_62:6; uint64_t dfm:1; @@ -1185,15 +4960,198 @@ union cvmx_ciu_intx_en4_1 { uint64_t mii1:1; uint64_t reserved_6_17:12; uint64_t wdog:6; +#else + uint64_t wdog:6; + uint64_t reserved_6_17:12; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_45:9; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_62:6; + uint64_t rst:1; +#endif } cn63xx; struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1; + struct cvmx_ciu_intx_en4_1_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en4_1_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en4_1_w1c { uint64_t u64; struct cvmx_ciu_intx_en4_1_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; - uint64_t reserved_57_62:6; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; @@ -1203,7 +5161,10 @@ union cvmx_ciu_intx_en4_1_w1c { uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_37_45:9; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -1226,8 +5187,51 @@ union cvmx_ciu_intx_en4_1_w1c { uint64_t usb1:1; uint64_t uart2:1; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif } s; struct cvmx_ciu_intx_en4_1_w1c_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t nand:1; uint64_t mii1:1; @@ -1235,16 +5239,107 @@ union cvmx_ciu_intx_en4_1_w1c { uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_ciu_intx_en4_1_w1c_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t wdog:12; +#else + uint64_t wdog:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_intx_en4_1_w1c_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t reserved_16_63:48; +#endif } cn58xx; + struct cvmx_ciu_intx_en4_1_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en4_1_w1c_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; uint64_t reserved_57_62:6; uint64_t dfm:1; @@ -1278,15 +5373,198 @@ union cvmx_ciu_intx_en4_1_w1c { uint64_t mii1:1; uint64_t reserved_6_17:12; uint64_t wdog:6; +#else + uint64_t wdog:6; + uint64_t reserved_6_17:12; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_45:9; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_62:6; + uint64_t rst:1; +#endif } cn63xx; struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1; + struct cvmx_ciu_intx_en4_1_w1c_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en4_1_w1c_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en4_1_w1s { uint64_t u64; struct cvmx_ciu_intx_en4_1_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; - uint64_t reserved_57_62:6; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; @@ -1296,7 +5574,10 @@ union cvmx_ciu_intx_en4_1_w1s { uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_37_45:9; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -1319,8 +5600,51 @@ union cvmx_ciu_intx_en4_1_w1s { uint64_t usb1:1; uint64_t uart2:1; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif } s; struct cvmx_ciu_intx_en4_1_w1s_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t nand:1; uint64_t mii1:1; @@ -1328,16 +5652,107 @@ union cvmx_ciu_intx_en4_1_w1s { uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_ciu_intx_en4_1_w1s_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t wdog:12; +#else + uint64_t wdog:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_intx_en4_1_w1s_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t reserved_16_63:48; +#endif } cn58xx; + struct cvmx_ciu_intx_en4_1_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en4_1_w1s_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; uint64_t reserved_57_62:6; uint64_t dfm:1; @@ -1371,13 +5786,193 @@ union cvmx_ciu_intx_en4_1_w1s { uint64_t mii1:1; uint64_t reserved_6_17:12; uint64_t wdog:6; +#else + uint64_t wdog:6; + uint64_t reserved_6_17:12; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_45:9; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_62:6; + uint64_t rst:1; +#endif } cn63xx; struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1; + struct cvmx_ciu_intx_en4_1_w1s_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en4_1_w1s_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_sum0 { uint64_t u64; struct cvmx_ciu_intx_sum0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1387,7 +5982,7 @@ union cvmx_ciu_intx_sum0 { uint64_t pcm:1; uint64_t usb:1; uint64_t timer:4; - uint64_t key_zero:1; + uint64_t reserved_51_51:1; uint64_t ipd_drp:1; uint64_t gmx_drp:2; uint64_t trace:1; @@ -1400,8 +5995,33 @@ union cvmx_ciu_intx_sum0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_sum0_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t mpi:1; uint64_t pcm:1; @@ -1421,8 +6041,30 @@ union cvmx_ciu_intx_sum0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t reserved_47_47:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t reserved_59_63:5; +#endif } cn30xx; struct cvmx_ciu_intx_sum0_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t mpi:1; uint64_t pcm:1; @@ -1442,8 +6084,30 @@ union cvmx_ciu_intx_sum0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t reserved_59_63:5; +#endif } cn31xx; struct cvmx_ciu_intx_sum0_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -1459,10 +6123,28 @@ union cvmx_ciu_intx_sum0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn38xx; struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2; struct cvmx_ciu_intx_sum0_cn30xx cn50xx; struct cvmx_ciu_intx_sum0_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1485,9 +6167,34 @@ union cvmx_ciu_intx_sum0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1; struct cvmx_ciu_intx_sum0_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1509,17 +6216,190 @@ union cvmx_ciu_intx_sum0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn56xx; struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1; struct cvmx_ciu_intx_sum0_cn38xx cn58xx; struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1; + struct cvmx_ciu_intx_sum0_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_sum0_cn52xx cn63xx; struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1; + struct cvmx_ciu_intx_sum0_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_sum0_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_sum4 { uint64_t u64; struct cvmx_ciu_intx_sum4_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1529,7 +6409,7 @@ union cvmx_ciu_intx_sum4 { uint64_t pcm:1; uint64_t usb:1; uint64_t timer:4; - uint64_t key_zero:1; + uint64_t reserved_51_51:1; uint64_t ipd_drp:1; uint64_t gmx_drp:2; uint64_t trace:1; @@ -1542,8 +6422,33 @@ union cvmx_ciu_intx_sum4 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_sum4_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t mpi:1; uint64_t pcm:1; @@ -1563,8 +6468,30 @@ union cvmx_ciu_intx_sum4 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t reserved_47_47:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t reserved_59_63:5; +#endif } cn50xx; struct cvmx_ciu_intx_sum4_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1587,9 +6514,34 @@ union cvmx_ciu_intx_sum4 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1; struct cvmx_ciu_intx_sum4_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1611,9 +6563,33 @@ union cvmx_ciu_intx_sum4 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn56xx; struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1; struct cvmx_ciu_intx_sum4_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -1629,15 +6605,232 @@ union cvmx_ciu_intx_sum4 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn58xx; struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1; + struct cvmx_ciu_intx_sum4_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_sum4_cn52xx cn63xx; struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1; + struct cvmx_ciu_intx_sum4_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_sum4_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_int33_sum0 { uint64_t u64; struct cvmx_ciu_int33_sum0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } s; + struct cvmx_ciu_int33_sum0_s cn61xx; + struct cvmx_ciu_int33_sum0_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1660,29 +6853,202 @@ union cvmx_ciu_int33_sum0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; - } s; - struct cvmx_ciu_int33_sum0_s cn63xx; - struct cvmx_ciu_int33_sum0_s cn63xxp1; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn63xx; + struct cvmx_ciu_int33_sum0_cn63xx cn63xxp1; + struct cvmx_ciu_int33_sum0_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_int33_sum0_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_int_dbg_sel { uint64_t u64; struct cvmx_ciu_int_dbg_sel_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_19_63:45; + uint64_t sel:3; + uint64_t reserved_10_15:6; + uint64_t irq:2; + uint64_t reserved_5_7:3; + uint64_t pp:5; +#else + uint64_t pp:5; + uint64_t reserved_5_7:3; + uint64_t irq:2; + uint64_t reserved_10_15:6; + uint64_t sel:3; + uint64_t reserved_19_63:45; +#endif + } s; + struct cvmx_ciu_int_dbg_sel_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_19_63:45; + uint64_t sel:3; + uint64_t reserved_10_15:6; + uint64_t irq:2; + uint64_t reserved_4_7:4; + uint64_t pp:4; +#else + uint64_t pp:4; + uint64_t reserved_4_7:4; + uint64_t irq:2; + uint64_t reserved_10_15:6; + uint64_t sel:3; + uint64_t reserved_19_63:45; +#endif + } cn61xx; + struct cvmx_ciu_int_dbg_sel_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t sel:3; uint64_t reserved_10_15:6; uint64_t irq:2; uint64_t reserved_3_7:5; uint64_t pp:3; - } s; - struct cvmx_ciu_int_dbg_sel_s cn63xx; +#else + uint64_t pp:3; + uint64_t reserved_3_7:5; + uint64_t irq:2; + uint64_t reserved_10_15:6; + uint64_t sel:3; + uint64_t reserved_19_63:45; +#endif + } cn63xx; + struct cvmx_ciu_int_dbg_sel_cn61xx cn66xx; + struct cvmx_ciu_int_dbg_sel_s cn68xx; + struct cvmx_ciu_int_dbg_sel_s cn68xxp1; + struct cvmx_ciu_int_dbg_sel_cn61xx cnf71xx; }; union cvmx_ciu_int_sum1 { uint64_t u64; struct cvmx_ciu_int_sum1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; - uint64_t reserved_57_62:6; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; @@ -1692,7 +7058,8 @@ union cvmx_ciu_int_sum1 { uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_37_45:9; + uint64_t reserved_38_45:8; + uint64_t agx1:1; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -1715,22 +7082,78 @@ union cvmx_ciu_int_sum1 { uint64_t usb1:1; uint64_t uart2:1; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif } s; struct cvmx_ciu_int_sum1_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t wdog:1; +#else + uint64_t wdog:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_ciu_int_sum1_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t wdog:2; +#else + uint64_t wdog:2; + uint64_t reserved_2_63:62; +#endif } cn31xx; struct cvmx_ciu_int_sum1_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_ciu_int_sum1_cn38xx cn38xxp2; struct cvmx_ciu_int_sum1_cn31xx cn50xx; struct cvmx_ciu_int_sum1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t nand:1; uint64_t mii1:1; @@ -1738,23 +7161,114 @@ union cvmx_ciu_int_sum1 { uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_ciu_int_sum1_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t mii1:1; uint64_t usb1:1; uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t reserved_19_63:45; +#endif } cn52xxp1; struct cvmx_ciu_int_sum1_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t wdog:12; +#else + uint64_t wdog:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_int_sum1_cn56xx cn56xxp1; struct cvmx_ciu_int_sum1_cn38xx cn58xx; struct cvmx_ciu_int_sum1_cn38xx cn58xxp1; + struct cvmx_ciu_int_sum1_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; struct cvmx_ciu_int_sum1_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; uint64_t reserved_57_62:6; uint64_t dfm:1; @@ -1788,15 +7302,195 @@ union cvmx_ciu_int_sum1 { uint64_t mii1:1; uint64_t reserved_6_17:12; uint64_t wdog:6; +#else + uint64_t wdog:6; + uint64_t reserved_6_17:12; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_45:9; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_62:6; + uint64_t rst:1; +#endif } cn63xx; struct cvmx_ciu_int_sum1_cn63xx cn63xxp1; + struct cvmx_ciu_int_sum1_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_int_sum1_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_37_46:10; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_46:10; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; }; union cvmx_ciu_mbox_clrx { uint64_t u64; struct cvmx_ciu_mbox_clrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bits:32; +#else + uint64_t bits:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ciu_mbox_clrx_s cn30xx; struct cvmx_ciu_mbox_clrx_s cn31xx; @@ -1809,15 +7503,25 @@ union cvmx_ciu_mbox_clrx { struct cvmx_ciu_mbox_clrx_s cn56xxp1; struct cvmx_ciu_mbox_clrx_s cn58xx; struct cvmx_ciu_mbox_clrx_s cn58xxp1; + struct cvmx_ciu_mbox_clrx_s cn61xx; struct cvmx_ciu_mbox_clrx_s cn63xx; struct cvmx_ciu_mbox_clrx_s cn63xxp1; + struct cvmx_ciu_mbox_clrx_s cn66xx; + struct cvmx_ciu_mbox_clrx_s cn68xx; + struct cvmx_ciu_mbox_clrx_s cn68xxp1; + struct cvmx_ciu_mbox_clrx_s cnf71xx; }; union cvmx_ciu_mbox_setx { uint64_t u64; struct cvmx_ciu_mbox_setx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bits:32; +#else + uint64_t bits:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ciu_mbox_setx_s cn30xx; struct cvmx_ciu_mbox_setx_s cn31xx; @@ -1830,51 +7534,112 @@ union cvmx_ciu_mbox_setx { struct cvmx_ciu_mbox_setx_s cn56xxp1; struct cvmx_ciu_mbox_setx_s cn58xx; struct cvmx_ciu_mbox_setx_s cn58xxp1; + struct cvmx_ciu_mbox_setx_s cn61xx; struct cvmx_ciu_mbox_setx_s cn63xx; struct cvmx_ciu_mbox_setx_s cn63xxp1; + struct cvmx_ciu_mbox_setx_s cn66xx; + struct cvmx_ciu_mbox_setx_s cn68xx; + struct cvmx_ciu_mbox_setx_s cn68xxp1; + struct cvmx_ciu_mbox_setx_s cnf71xx; }; union cvmx_ciu_nmi { uint64_t u64; struct cvmx_ciu_nmi_s { - uint64_t reserved_16_63:48; - uint64_t nmi:16; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t nmi:32; +#else + uint64_t nmi:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ciu_nmi_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t nmi:1; +#else + uint64_t nmi:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_ciu_nmi_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t nmi:2; +#else + uint64_t nmi:2; + uint64_t reserved_2_63:62; +#endif } cn31xx; - struct cvmx_ciu_nmi_s cn38xx; - struct cvmx_ciu_nmi_s cn38xxp2; + struct cvmx_ciu_nmi_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t nmi:16; +#else + uint64_t nmi:16; + uint64_t reserved_16_63:48; +#endif + } cn38xx; + struct cvmx_ciu_nmi_cn38xx cn38xxp2; struct cvmx_ciu_nmi_cn31xx cn50xx; struct cvmx_ciu_nmi_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t nmi:4; +#else + uint64_t nmi:4; + uint64_t reserved_4_63:60; +#endif } cn52xx; struct cvmx_ciu_nmi_cn52xx cn52xxp1; struct cvmx_ciu_nmi_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t nmi:12; +#else + uint64_t nmi:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_nmi_cn56xx cn56xxp1; - struct cvmx_ciu_nmi_s cn58xx; - struct cvmx_ciu_nmi_s cn58xxp1; + struct cvmx_ciu_nmi_cn38xx cn58xx; + struct cvmx_ciu_nmi_cn38xx cn58xxp1; + struct cvmx_ciu_nmi_cn52xx cn61xx; struct cvmx_ciu_nmi_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t nmi:6; +#else + uint64_t nmi:6; + uint64_t reserved_6_63:58; +#endif } cn63xx; struct cvmx_ciu_nmi_cn63xx cn63xxp1; + struct cvmx_ciu_nmi_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t nmi:10; +#else + uint64_t nmi:10; + uint64_t reserved_10_63:54; +#endif + } cn66xx; + struct cvmx_ciu_nmi_s cn68xx; + struct cvmx_ciu_nmi_s cn68xxp1; + struct cvmx_ciu_nmi_cn52xx cnf71xx; }; union cvmx_ciu_pci_inta { uint64_t u64; struct cvmx_ciu_pci_inta_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t intr:2; +#else + uint64_t intr:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_ciu_pci_inta_s cn30xx; struct cvmx_ciu_pci_inta_s cn31xx; @@ -1887,50 +7652,125 @@ union cvmx_ciu_pci_inta { struct cvmx_ciu_pci_inta_s cn56xxp1; struct cvmx_ciu_pci_inta_s cn58xx; struct cvmx_ciu_pci_inta_s cn58xxp1; + struct cvmx_ciu_pci_inta_s cn61xx; struct cvmx_ciu_pci_inta_s cn63xx; struct cvmx_ciu_pci_inta_s cn63xxp1; + struct cvmx_ciu_pci_inta_s cn66xx; + struct cvmx_ciu_pci_inta_s cn68xx; + struct cvmx_ciu_pci_inta_s cn68xxp1; + struct cvmx_ciu_pci_inta_s cnf71xx; +}; + +union cvmx_ciu_pp_bist_stat { + uint64_t u64; + struct cvmx_ciu_pp_bist_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t pp_bist:32; +#else + uint64_t pp_bist:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu_pp_bist_stat_s cn68xx; + struct cvmx_ciu_pp_bist_stat_s cn68xxp1; }; union cvmx_ciu_pp_dbg { uint64_t u64; struct cvmx_ciu_pp_dbg_s { - uint64_t reserved_16_63:48; - uint64_t ppdbg:16; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t ppdbg:32; +#else + uint64_t ppdbg:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ciu_pp_dbg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t ppdbg:1; +#else + uint64_t ppdbg:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_ciu_pp_dbg_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t ppdbg:2; +#else + uint64_t ppdbg:2; + uint64_t reserved_2_63:62; +#endif } cn31xx; - struct cvmx_ciu_pp_dbg_s cn38xx; - struct cvmx_ciu_pp_dbg_s cn38xxp2; + struct cvmx_ciu_pp_dbg_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t ppdbg:16; +#else + uint64_t ppdbg:16; + uint64_t reserved_16_63:48; +#endif + } cn38xx; + struct cvmx_ciu_pp_dbg_cn38xx cn38xxp2; struct cvmx_ciu_pp_dbg_cn31xx cn50xx; struct cvmx_ciu_pp_dbg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t ppdbg:4; +#else + uint64_t ppdbg:4; + uint64_t reserved_4_63:60; +#endif } cn52xx; struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1; struct cvmx_ciu_pp_dbg_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t ppdbg:12; +#else + uint64_t ppdbg:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1; - struct cvmx_ciu_pp_dbg_s cn58xx; - struct cvmx_ciu_pp_dbg_s cn58xxp1; + struct cvmx_ciu_pp_dbg_cn38xx cn58xx; + struct cvmx_ciu_pp_dbg_cn38xx cn58xxp1; + struct cvmx_ciu_pp_dbg_cn52xx cn61xx; struct cvmx_ciu_pp_dbg_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t ppdbg:6; +#else + uint64_t ppdbg:6; + uint64_t reserved_6_63:58; +#endif } cn63xx; struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1; + struct cvmx_ciu_pp_dbg_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t ppdbg:10; +#else + uint64_t ppdbg:10; + uint64_t reserved_10_63:54; +#endif + } cn66xx; + struct cvmx_ciu_pp_dbg_s cn68xx; + struct cvmx_ciu_pp_dbg_s cn68xxp1; + struct cvmx_ciu_pp_dbg_cn52xx cnf71xx; }; union cvmx_ciu_pp_pokex { uint64_t u64; struct cvmx_ciu_pp_pokex_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t poke:64; +#else + uint64_t poke:64; +#endif } s; struct cvmx_ciu_pp_pokex_s cn30xx; struct cvmx_ciu_pp_pokex_s cn31xx; @@ -1943,54 +7783,120 @@ union cvmx_ciu_pp_pokex { struct cvmx_ciu_pp_pokex_s cn56xxp1; struct cvmx_ciu_pp_pokex_s cn58xx; struct cvmx_ciu_pp_pokex_s cn58xxp1; + struct cvmx_ciu_pp_pokex_s cn61xx; struct cvmx_ciu_pp_pokex_s cn63xx; struct cvmx_ciu_pp_pokex_s cn63xxp1; + struct cvmx_ciu_pp_pokex_s cn66xx; + struct cvmx_ciu_pp_pokex_s cn68xx; + struct cvmx_ciu_pp_pokex_s cn68xxp1; + struct cvmx_ciu_pp_pokex_s cnf71xx; }; union cvmx_ciu_pp_rst { uint64_t u64; struct cvmx_ciu_pp_rst_s { - uint64_t reserved_16_63:48; - uint64_t rst:15; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t rst:31; + uint64_t rst0:1; +#else uint64_t rst0:1; + uint64_t rst:31; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ciu_pp_rst_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rst0:1; +#else + uint64_t rst0:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_ciu_pp_rst_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t rst:1; uint64_t rst0:1; +#else + uint64_t rst0:1; + uint64_t rst:1; + uint64_t reserved_2_63:62; +#endif } cn31xx; - struct cvmx_ciu_pp_rst_s cn38xx; - struct cvmx_ciu_pp_rst_s cn38xxp2; + struct cvmx_ciu_pp_rst_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t rst:15; + uint64_t rst0:1; +#else + uint64_t rst0:1; + uint64_t rst:15; + uint64_t reserved_16_63:48; +#endif + } cn38xx; + struct cvmx_ciu_pp_rst_cn38xx cn38xxp2; struct cvmx_ciu_pp_rst_cn31xx cn50xx; struct cvmx_ciu_pp_rst_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t rst:3; uint64_t rst0:1; +#else + uint64_t rst0:1; + uint64_t rst:3; + uint64_t reserved_4_63:60; +#endif } cn52xx; struct cvmx_ciu_pp_rst_cn52xx cn52xxp1; struct cvmx_ciu_pp_rst_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t rst:11; uint64_t rst0:1; +#else + uint64_t rst0:1; + uint64_t rst:11; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_pp_rst_cn56xx cn56xxp1; - struct cvmx_ciu_pp_rst_s cn58xx; - struct cvmx_ciu_pp_rst_s cn58xxp1; + struct cvmx_ciu_pp_rst_cn38xx cn58xx; + struct cvmx_ciu_pp_rst_cn38xx cn58xxp1; + struct cvmx_ciu_pp_rst_cn52xx cn61xx; struct cvmx_ciu_pp_rst_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t rst:5; uint64_t rst0:1; +#else + uint64_t rst0:1; + uint64_t rst:5; + uint64_t reserved_6_63:58; +#endif } cn63xx; struct cvmx_ciu_pp_rst_cn63xx cn63xxp1; + struct cvmx_ciu_pp_rst_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t rst:9; + uint64_t rst0:1; +#else + uint64_t rst0:1; + uint64_t rst:9; + uint64_t reserved_10_63:54; +#endif + } cn66xx; + struct cvmx_ciu_pp_rst_s cn68xx; + struct cvmx_ciu_pp_rst_s cn68xxp1; + struct cvmx_ciu_pp_rst_cn52xx cnf71xx; }; union cvmx_ciu_qlm0 { uint64_t u64; struct cvmx_ciu_qlm0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t g2bypass:1; uint64_t reserved_53_62:10; uint64_t g2deemph:5; @@ -2004,9 +7910,26 @@ union cvmx_ciu_qlm0 { uint64_t txmargin:5; uint64_t reserved_4_7:4; uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:5; + uint64_t reserved_21_30:10; + uint64_t txbypass:1; + uint64_t reserved_32_39:8; + uint64_t g2margin:5; + uint64_t reserved_45_47:3; + uint64_t g2deemph:5; + uint64_t reserved_53_62:10; + uint64_t g2bypass:1; +#endif } s; + struct cvmx_ciu_qlm0_s cn61xx; struct cvmx_ciu_qlm0_s cn63xx; struct cvmx_ciu_qlm0_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t txbypass:1; uint64_t reserved_20_30:11; @@ -2015,12 +7938,47 @@ union cvmx_ciu_qlm0 { uint64_t txmargin:5; uint64_t reserved_4_7:4; uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:4; + uint64_t reserved_20_30:11; + uint64_t txbypass:1; + uint64_t reserved_32_63:32; +#endif } cn63xxp1; + struct cvmx_ciu_qlm0_s cn66xx; + struct cvmx_ciu_qlm0_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t txbypass:1; + uint64_t reserved_21_30:10; + uint64_t txdeemph:5; + uint64_t reserved_13_15:3; + uint64_t txmargin:5; + uint64_t reserved_4_7:4; + uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:5; + uint64_t reserved_21_30:10; + uint64_t txbypass:1; + uint64_t reserved_32_63:32; +#endif + } cn68xx; + struct cvmx_ciu_qlm0_cn68xx cn68xxp1; + struct cvmx_ciu_qlm0_s cnf71xx; }; union cvmx_ciu_qlm1 { uint64_t u64; struct cvmx_ciu_qlm1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t g2bypass:1; uint64_t reserved_53_62:10; uint64_t g2deemph:5; @@ -2034,9 +7992,26 @@ union cvmx_ciu_qlm1 { uint64_t txmargin:5; uint64_t reserved_4_7:4; uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:5; + uint64_t reserved_21_30:10; + uint64_t txbypass:1; + uint64_t reserved_32_39:8; + uint64_t g2margin:5; + uint64_t reserved_45_47:3; + uint64_t g2deemph:5; + uint64_t reserved_53_62:10; + uint64_t g2bypass:1; +#endif } s; + struct cvmx_ciu_qlm1_s cn61xx; struct cvmx_ciu_qlm1_s cn63xx; struct cvmx_ciu_qlm1_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t txbypass:1; uint64_t reserved_20_30:11; @@ -2045,13 +8020,33 @@ union cvmx_ciu_qlm1 { uint64_t txmargin:5; uint64_t reserved_4_7:4; uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:4; + uint64_t reserved_20_30:11; + uint64_t txbypass:1; + uint64_t reserved_32_63:32; +#endif } cn63xxp1; + struct cvmx_ciu_qlm1_s cn66xx; + struct cvmx_ciu_qlm1_s cn68xx; + struct cvmx_ciu_qlm1_s cn68xxp1; + struct cvmx_ciu_qlm1_s cnf71xx; }; union cvmx_ciu_qlm2 { uint64_t u64; struct cvmx_ciu_qlm2_s { - uint64_t reserved_32_63:32; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t g2bypass:1; + uint64_t reserved_53_62:10; + uint64_t g2deemph:5; + uint64_t reserved_45_47:3; + uint64_t g2margin:5; + uint64_t reserved_32_39:8; uint64_t txbypass:1; uint64_t reserved_21_30:10; uint64_t txdeemph:5; @@ -2059,9 +8054,46 @@ union cvmx_ciu_qlm2 { uint64_t txmargin:5; uint64_t reserved_4_7:4; uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:5; + uint64_t reserved_21_30:10; + uint64_t txbypass:1; + uint64_t reserved_32_39:8; + uint64_t g2margin:5; + uint64_t reserved_45_47:3; + uint64_t g2deemph:5; + uint64_t reserved_53_62:10; + uint64_t g2bypass:1; +#endif } s; - struct cvmx_ciu_qlm2_s cn63xx; + struct cvmx_ciu_qlm2_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t txbypass:1; + uint64_t reserved_21_30:10; + uint64_t txdeemph:5; + uint64_t reserved_13_15:3; + uint64_t txmargin:5; + uint64_t reserved_4_7:4; + uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:5; + uint64_t reserved_21_30:10; + uint64_t txbypass:1; + uint64_t reserved_32_63:32; +#endif + } cn61xx; + struct cvmx_ciu_qlm2_cn61xx cn63xx; struct cvmx_ciu_qlm2_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t txbypass:1; uint64_t reserved_20_30:11; @@ -2070,18 +8102,116 @@ union cvmx_ciu_qlm2 { uint64_t txmargin:5; uint64_t reserved_4_7:4; uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:4; + uint64_t reserved_20_30:11; + uint64_t txbypass:1; + uint64_t reserved_32_63:32; +#endif } cn63xxp1; + struct cvmx_ciu_qlm2_cn61xx cn66xx; + struct cvmx_ciu_qlm2_s cn68xx; + struct cvmx_ciu_qlm2_s cn68xxp1; + struct cvmx_ciu_qlm2_cn61xx cnf71xx; +}; + +union cvmx_ciu_qlm3 { + uint64_t u64; + struct cvmx_ciu_qlm3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t g2bypass:1; + uint64_t reserved_53_62:10; + uint64_t g2deemph:5; + uint64_t reserved_45_47:3; + uint64_t g2margin:5; + uint64_t reserved_32_39:8; + uint64_t txbypass:1; + uint64_t reserved_21_30:10; + uint64_t txdeemph:5; + uint64_t reserved_13_15:3; + uint64_t txmargin:5; + uint64_t reserved_4_7:4; + uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:5; + uint64_t reserved_21_30:10; + uint64_t txbypass:1; + uint64_t reserved_32_39:8; + uint64_t g2margin:5; + uint64_t reserved_45_47:3; + uint64_t g2deemph:5; + uint64_t reserved_53_62:10; + uint64_t g2bypass:1; +#endif + } s; + struct cvmx_ciu_qlm3_s cn68xx; + struct cvmx_ciu_qlm3_s cn68xxp1; +}; + +union cvmx_ciu_qlm4 { + uint64_t u64; + struct cvmx_ciu_qlm4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t g2bypass:1; + uint64_t reserved_53_62:10; + uint64_t g2deemph:5; + uint64_t reserved_45_47:3; + uint64_t g2margin:5; + uint64_t reserved_32_39:8; + uint64_t txbypass:1; + uint64_t reserved_21_30:10; + uint64_t txdeemph:5; + uint64_t reserved_13_15:3; + uint64_t txmargin:5; + uint64_t reserved_4_7:4; + uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:5; + uint64_t reserved_21_30:10; + uint64_t txbypass:1; + uint64_t reserved_32_39:8; + uint64_t g2margin:5; + uint64_t reserved_45_47:3; + uint64_t g2deemph:5; + uint64_t reserved_53_62:10; + uint64_t g2bypass:1; +#endif + } s; + struct cvmx_ciu_qlm4_s cn68xx; + struct cvmx_ciu_qlm4_s cn68xxp1; }; union cvmx_ciu_qlm_dcok { uint64_t u64; struct cvmx_ciu_qlm_dcok_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t qlm_dcok:4; +#else + uint64_t qlm_dcok:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_ciu_qlm_dcok_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t qlm_dcok:2; +#else + uint64_t qlm_dcok:2; + uint64_t reserved_2_63:62; +#endif } cn52xx; struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1; struct cvmx_ciu_qlm_dcok_s cn56xx; @@ -2091,47 +8221,108 @@ union cvmx_ciu_qlm_dcok { union cvmx_ciu_qlm_jtgc { uint64_t u64; struct cvmx_ciu_qlm_jtgc_s { - uint64_t reserved_11_63:53; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_17_63:47; + uint64_t bypass_ext:1; + uint64_t reserved_11_15:5; uint64_t clk_div:3; - uint64_t reserved_6_7:2; - uint64_t mux_sel:2; + uint64_t reserved_7_7:1; + uint64_t mux_sel:3; uint64_t bypass:4; +#else + uint64_t bypass:4; + uint64_t mux_sel:3; + uint64_t reserved_7_7:1; + uint64_t clk_div:3; + uint64_t reserved_11_15:5; + uint64_t bypass_ext:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_ciu_qlm_jtgc_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t clk_div:3; uint64_t reserved_5_7:3; uint64_t mux_sel:1; uint64_t reserved_2_3:2; uint64_t bypass:2; +#else + uint64_t bypass:2; + uint64_t reserved_2_3:2; + uint64_t mux_sel:1; + uint64_t reserved_5_7:3; + uint64_t clk_div:3; + uint64_t reserved_11_63:53; +#endif } cn52xx; struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1; - struct cvmx_ciu_qlm_jtgc_s cn56xx; - struct cvmx_ciu_qlm_jtgc_s cn56xxp1; - struct cvmx_ciu_qlm_jtgc_cn63xx { + struct cvmx_ciu_qlm_jtgc_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t clk_div:3; + uint64_t reserved_6_7:2; + uint64_t mux_sel:2; + uint64_t bypass:4; +#else + uint64_t bypass:4; + uint64_t mux_sel:2; + uint64_t reserved_6_7:2; + uint64_t clk_div:3; + uint64_t reserved_11_63:53; +#endif + } cn56xx; + struct cvmx_ciu_qlm_jtgc_cn56xx cn56xxp1; + struct cvmx_ciu_qlm_jtgc_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t clk_div:3; uint64_t reserved_6_7:2; uint64_t mux_sel:2; uint64_t reserved_3_3:1; uint64_t bypass:3; - } cn63xx; - struct cvmx_ciu_qlm_jtgc_cn63xx cn63xxp1; +#else + uint64_t bypass:3; + uint64_t reserved_3_3:1; + uint64_t mux_sel:2; + uint64_t reserved_6_7:2; + uint64_t clk_div:3; + uint64_t reserved_11_63:53; +#endif + } cn61xx; + struct cvmx_ciu_qlm_jtgc_cn61xx cn63xx; + struct cvmx_ciu_qlm_jtgc_cn61xx cn63xxp1; + struct cvmx_ciu_qlm_jtgc_cn61xx cn66xx; + struct cvmx_ciu_qlm_jtgc_s cn68xx; + struct cvmx_ciu_qlm_jtgc_s cn68xxp1; + struct cvmx_ciu_qlm_jtgc_cn61xx cnf71xx; }; union cvmx_ciu_qlm_jtgd { uint64_t u64; struct cvmx_ciu_qlm_jtgd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t capture:1; uint64_t shift:1; uint64_t update:1; - uint64_t reserved_44_60:17; - uint64_t select:4; + uint64_t reserved_45_60:16; + uint64_t select:5; uint64_t reserved_37_39:3; uint64_t shft_cnt:5; uint64_t shft_reg:32; +#else + uint64_t shft_reg:32; + uint64_t shft_cnt:5; + uint64_t reserved_37_39:3; + uint64_t select:5; + uint64_t reserved_45_60:16; + uint64_t update:1; + uint64_t shift:1; + uint64_t capture:1; +#endif } s; struct cvmx_ciu_qlm_jtgd_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t capture:1; uint64_t shift:1; uint64_t update:1; @@ -2140,18 +8331,58 @@ union cvmx_ciu_qlm_jtgd { uint64_t reserved_37_39:3; uint64_t shft_cnt:5; uint64_t shft_reg:32; +#else + uint64_t shft_reg:32; + uint64_t shft_cnt:5; + uint64_t reserved_37_39:3; + uint64_t select:2; + uint64_t reserved_42_60:19; + uint64_t update:1; + uint64_t shift:1; + uint64_t capture:1; +#endif } cn52xx; struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1; - struct cvmx_ciu_qlm_jtgd_s cn56xx; + struct cvmx_ciu_qlm_jtgd_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t capture:1; + uint64_t shift:1; + uint64_t update:1; + uint64_t reserved_44_60:17; + uint64_t select:4; + uint64_t reserved_37_39:3; + uint64_t shft_cnt:5; + uint64_t shft_reg:32; +#else + uint64_t shft_reg:32; + uint64_t shft_cnt:5; + uint64_t reserved_37_39:3; + uint64_t select:4; + uint64_t reserved_44_60:17; + uint64_t update:1; + uint64_t shift:1; + uint64_t capture:1; +#endif + } cn56xx; struct cvmx_ciu_qlm_jtgd_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t capture:1; uint64_t shift:1; uint64_t update:1; uint64_t reserved_37_60:24; uint64_t shft_cnt:5; uint64_t shft_reg:32; +#else + uint64_t shft_reg:32; + uint64_t shft_cnt:5; + uint64_t reserved_37_60:24; + uint64_t update:1; + uint64_t shift:1; + uint64_t capture:1; +#endif } cn56xxp1; - struct cvmx_ciu_qlm_jtgd_cn63xx { + struct cvmx_ciu_qlm_jtgd_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t capture:1; uint64_t shift:1; uint64_t update:1; @@ -2160,15 +8391,35 @@ union cvmx_ciu_qlm_jtgd { uint64_t reserved_37_39:3; uint64_t shft_cnt:5; uint64_t shft_reg:32; - } cn63xx; - struct cvmx_ciu_qlm_jtgd_cn63xx cn63xxp1; +#else + uint64_t shft_reg:32; + uint64_t shft_cnt:5; + uint64_t reserved_37_39:3; + uint64_t select:3; + uint64_t reserved_43_60:18; + uint64_t update:1; + uint64_t shift:1; + uint64_t capture:1; +#endif + } cn61xx; + struct cvmx_ciu_qlm_jtgd_cn61xx cn63xx; + struct cvmx_ciu_qlm_jtgd_cn61xx cn63xxp1; + struct cvmx_ciu_qlm_jtgd_cn61xx cn66xx; + struct cvmx_ciu_qlm_jtgd_s cn68xx; + struct cvmx_ciu_qlm_jtgd_s cn68xxp1; + struct cvmx_ciu_qlm_jtgd_cn61xx cnf71xx; }; union cvmx_ciu_soft_bist { uint64_t u64; struct cvmx_ciu_soft_bist_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t soft_bist:1; +#else + uint64_t soft_bist:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_ciu_soft_bist_s cn30xx; struct cvmx_ciu_soft_bist_s cn31xx; @@ -2181,17 +8432,29 @@ union cvmx_ciu_soft_bist { struct cvmx_ciu_soft_bist_s cn56xxp1; struct cvmx_ciu_soft_bist_s cn58xx; struct cvmx_ciu_soft_bist_s cn58xxp1; + struct cvmx_ciu_soft_bist_s cn61xx; struct cvmx_ciu_soft_bist_s cn63xx; struct cvmx_ciu_soft_bist_s cn63xxp1; + struct cvmx_ciu_soft_bist_s cn66xx; + struct cvmx_ciu_soft_bist_s cn68xx; + struct cvmx_ciu_soft_bist_s cn68xxp1; + struct cvmx_ciu_soft_bist_s cnf71xx; }; union cvmx_ciu_soft_prst { uint64_t u64; struct cvmx_ciu_soft_prst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t host64:1; uint64_t npi:1; uint64_t soft_prst:1; +#else + uint64_t soft_prst:1; + uint64_t npi:1; + uint64_t host64:1; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_ciu_soft_prst_s cn30xx; struct cvmx_ciu_soft_prst_s cn31xx; @@ -2199,37 +8462,90 @@ union cvmx_ciu_soft_prst { struct cvmx_ciu_soft_prst_s cn38xxp2; struct cvmx_ciu_soft_prst_s cn50xx; struct cvmx_ciu_soft_prst_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t soft_prst:1; +#else + uint64_t soft_prst:1; + uint64_t reserved_1_63:63; +#endif } cn52xx; struct cvmx_ciu_soft_prst_cn52xx cn52xxp1; struct cvmx_ciu_soft_prst_cn52xx cn56xx; struct cvmx_ciu_soft_prst_cn52xx cn56xxp1; struct cvmx_ciu_soft_prst_s cn58xx; struct cvmx_ciu_soft_prst_s cn58xxp1; + struct cvmx_ciu_soft_prst_cn52xx cn61xx; struct cvmx_ciu_soft_prst_cn52xx cn63xx; struct cvmx_ciu_soft_prst_cn52xx cn63xxp1; + struct cvmx_ciu_soft_prst_cn52xx cn66xx; + struct cvmx_ciu_soft_prst_cn52xx cn68xx; + struct cvmx_ciu_soft_prst_cn52xx cn68xxp1; + struct cvmx_ciu_soft_prst_cn52xx cnf71xx; }; union cvmx_ciu_soft_prst1 { uint64_t u64; struct cvmx_ciu_soft_prst1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t soft_prst:1; +#else + uint64_t soft_prst:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_ciu_soft_prst1_s cn52xx; struct cvmx_ciu_soft_prst1_s cn52xxp1; struct cvmx_ciu_soft_prst1_s cn56xx; struct cvmx_ciu_soft_prst1_s cn56xxp1; + struct cvmx_ciu_soft_prst1_s cn61xx; struct cvmx_ciu_soft_prst1_s cn63xx; struct cvmx_ciu_soft_prst1_s cn63xxp1; + struct cvmx_ciu_soft_prst1_s cn66xx; + struct cvmx_ciu_soft_prst1_s cn68xx; + struct cvmx_ciu_soft_prst1_s cn68xxp1; + struct cvmx_ciu_soft_prst1_s cnf71xx; +}; + +union cvmx_ciu_soft_prst2 { + uint64_t u64; + struct cvmx_ciu_soft_prst2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t soft_prst:1; +#else + uint64_t soft_prst:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu_soft_prst2_s cn66xx; +}; + +union cvmx_ciu_soft_prst3 { + uint64_t u64; + struct cvmx_ciu_soft_prst3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t soft_prst:1; +#else + uint64_t soft_prst:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu_soft_prst3_s cn66xx; }; union cvmx_ciu_soft_rst { uint64_t u64; struct cvmx_ciu_soft_rst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t soft_rst:1; +#else + uint64_t soft_rst:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_ciu_soft_rst_s cn30xx; struct cvmx_ciu_soft_rst_s cn31xx; @@ -2242,16 +8558,1371 @@ union cvmx_ciu_soft_rst { struct cvmx_ciu_soft_rst_s cn56xxp1; struct cvmx_ciu_soft_rst_s cn58xx; struct cvmx_ciu_soft_rst_s cn58xxp1; + struct cvmx_ciu_soft_rst_s cn61xx; struct cvmx_ciu_soft_rst_s cn63xx; struct cvmx_ciu_soft_rst_s cn63xxp1; + struct cvmx_ciu_soft_rst_s cn66xx; + struct cvmx_ciu_soft_rst_s cn68xx; + struct cvmx_ciu_soft_rst_s cn68xxp1; + struct cvmx_ciu_soft_rst_s cnf71xx; +}; + +union cvmx_ciu_sum1_iox_int { + uint64_t u64; + struct cvmx_ciu_sum1_iox_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu_sum1_iox_int_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; + struct cvmx_ciu_sum1_iox_int_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_sum1_iox_int_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; +}; + +union cvmx_ciu_sum1_ppx_ip2 { + uint64_t u64; + struct cvmx_ciu_sum1_ppx_ip2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu_sum1_ppx_ip2_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; + struct cvmx_ciu_sum1_ppx_ip2_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_sum1_ppx_ip2_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; +}; + +union cvmx_ciu_sum1_ppx_ip3 { + uint64_t u64; + struct cvmx_ciu_sum1_ppx_ip3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu_sum1_ppx_ip3_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; + struct cvmx_ciu_sum1_ppx_ip3_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_sum1_ppx_ip3_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; +}; + +union cvmx_ciu_sum1_ppx_ip4 { + uint64_t u64; + struct cvmx_ciu_sum1_ppx_ip4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu_sum1_ppx_ip4_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; + struct cvmx_ciu_sum1_ppx_ip4_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_sum1_ppx_ip4_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; +}; + +union cvmx_ciu_sum2_iox_int { + uint64_t u64; + struct cvmx_ciu_sum2_iox_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_sum2_iox_int_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_sum2_iox_int_cn61xx cn66xx; + struct cvmx_ciu_sum2_iox_int_s cnf71xx; +}; + +union cvmx_ciu_sum2_ppx_ip2 { + uint64_t u64; + struct cvmx_ciu_sum2_ppx_ip2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_sum2_ppx_ip2_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_sum2_ppx_ip2_cn61xx cn66xx; + struct cvmx_ciu_sum2_ppx_ip2_s cnf71xx; +}; + +union cvmx_ciu_sum2_ppx_ip3 { + uint64_t u64; + struct cvmx_ciu_sum2_ppx_ip3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_sum2_ppx_ip3_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_sum2_ppx_ip3_cn61xx cn66xx; + struct cvmx_ciu_sum2_ppx_ip3_s cnf71xx; +}; + +union cvmx_ciu_sum2_ppx_ip4 { + uint64_t u64; + struct cvmx_ciu_sum2_ppx_ip4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_sum2_ppx_ip4_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_sum2_ppx_ip4_cn61xx cn66xx; + struct cvmx_ciu_sum2_ppx_ip4_s cnf71xx; }; union cvmx_ciu_timx { uint64_t u64; struct cvmx_ciu_timx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t one_shot:1; uint64_t len:36; +#else + uint64_t len:36; + uint64_t one_shot:1; + uint64_t reserved_37_63:27; +#endif } s; struct cvmx_ciu_timx_s cn30xx; struct cvmx_ciu_timx_s cn31xx; @@ -2264,13 +9935,35 @@ union cvmx_ciu_timx { struct cvmx_ciu_timx_s cn56xxp1; struct cvmx_ciu_timx_s cn58xx; struct cvmx_ciu_timx_s cn58xxp1; + struct cvmx_ciu_timx_s cn61xx; struct cvmx_ciu_timx_s cn63xx; struct cvmx_ciu_timx_s cn63xxp1; + struct cvmx_ciu_timx_s cn66xx; + struct cvmx_ciu_timx_s cn68xx; + struct cvmx_ciu_timx_s cn68xxp1; + struct cvmx_ciu_timx_s cnf71xx; +}; + +union cvmx_ciu_tim_multi_cast { + uint64_t u64; + struct cvmx_ciu_tim_multi_cast_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t en:1; +#else + uint64_t en:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu_tim_multi_cast_s cn61xx; + struct cvmx_ciu_tim_multi_cast_s cn66xx; + struct cvmx_ciu_tim_multi_cast_s cnf71xx; }; union cvmx_ciu_wdogx { uint64_t u64; struct cvmx_ciu_wdogx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_46_63:18; uint64_t gstopen:1; uint64_t dstop:1; @@ -2278,6 +9971,15 @@ union cvmx_ciu_wdogx { uint64_t len:16; uint64_t state:2; uint64_t mode:2; +#else + uint64_t mode:2; + uint64_t state:2; + uint64_t len:16; + uint64_t cnt:24; + uint64_t dstop:1; + uint64_t gstopen:1; + uint64_t reserved_46_63:18; +#endif } s; struct cvmx_ciu_wdogx_s cn30xx; struct cvmx_ciu_wdogx_s cn31xx; @@ -2290,8 +9992,13 @@ union cvmx_ciu_wdogx { struct cvmx_ciu_wdogx_s cn56xxp1; struct cvmx_ciu_wdogx_s cn58xx; struct cvmx_ciu_wdogx_s cn58xxp1; + struct cvmx_ciu_wdogx_s cn61xx; struct cvmx_ciu_wdogx_s cn63xx; struct cvmx_ciu_wdogx_s cn63xxp1; + struct cvmx_ciu_wdogx_s cn66xx; + struct cvmx_ciu_wdogx_s cn68xx; + struct cvmx_ciu_wdogx_s cn68xxp1; + struct cvmx_ciu_wdogx_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h new file mode 100644 index 000000000000..148bc9a0085d --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h @@ -0,0 +1,7108 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_CIU2_DEFS_H__ +#define __CVMX_CIU2_DEFS_H__ + +#define CVMX_CIU2_ACK_IOX_INT(block_id) (CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_ACK_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B7800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A7800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108094800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B4800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A4800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108098800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B8800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A8800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108095800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B5800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A5800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108093800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B3800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A3800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108096800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B6800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A6800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108092800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B2800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A2800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108091800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B1800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A1800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108090800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B0800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A0800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_INTR_CIU_READY (CVMX_ADD_IO_SEG(0x0001070100102008ull)) +#define CVMX_CIU2_INTR_RAM_ECC_CTL (CVMX_ADD_IO_SEG(0x0001070100102010ull)) +#define CVMX_CIU2_INTR_RAM_ECC_ST (CVMX_ADD_IO_SEG(0x0001070100102018ull)) +#define CVMX_CIU2_INTR_SLOWDOWN (CVMX_ADD_IO_SEG(0x0001070100102000ull)) +#define CVMX_CIU2_MSIRED_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_MSIRED_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_MSIRED_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_MSI_RCVX(offset) (CVMX_ADD_IO_SEG(0x00010701000C2000ull) + ((offset) & 255) * 8) +#define CVMX_CIU2_MSI_SELX(offset) (CVMX_ADD_IO_SEG(0x00010701000C3000ull) + ((offset) & 255) * 8) +#define CVMX_CIU2_RAW_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108047800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108044800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108045800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108043800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108046800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108042800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108041800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108040800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108087800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108084800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108088800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108085800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108083800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108086800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108082800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108081800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108080800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SUM_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070100000800ull) + ((offset) & 1) * 8) +#define CVMX_CIU2_SUM_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8) +#define CVMX_CIU2_SUM_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8) +#define CVMX_CIU2_SUM_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070100000400ull) + ((offset) & 31) * 8) + +union cvmx_ciu2_ack_iox_int { + uint64_t u64; + struct cvmx_ciu2_ack_iox_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t ack:1; +#else + uint64_t ack:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu2_ack_iox_int_s cn68xx; + struct cvmx_ciu2_ack_iox_int_s cn68xxp1; +}; + +union cvmx_ciu2_ack_ppx_ip2 { + uint64_t u64; + struct cvmx_ciu2_ack_ppx_ip2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t ack:1; +#else + uint64_t ack:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu2_ack_ppx_ip2_s cn68xx; + struct cvmx_ciu2_ack_ppx_ip2_s cn68xxp1; +}; + +union cvmx_ciu2_ack_ppx_ip3 { + uint64_t u64; + struct cvmx_ciu2_ack_ppx_ip3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t ack:1; +#else + uint64_t ack:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu2_ack_ppx_ip3_s cn68xx; + struct cvmx_ciu2_ack_ppx_ip3_s cn68xxp1; +}; + +union cvmx_ciu2_ack_ppx_ip4 { + uint64_t u64; + struct cvmx_ciu2_ack_ppx_ip4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t ack:1; +#else + uint64_t ack:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu2_ack_ppx_ip4_s cn68xx; + struct cvmx_ciu2_ack_ppx_ip4_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_gpio { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_iox_int_gpio_s cn68xx; + struct cvmx_ciu2_en_iox_int_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_gpio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_gpio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_gpio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_gpio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_io { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_iox_int_io_s cn68xx; + struct cvmx_ciu2_en_iox_int_io_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_io_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_io_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_io_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_io_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mbox { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mbox_s cn68xx; + struct cvmx_ciu2_en_iox_int_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mbox_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mbox_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mbox_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mbox_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mem { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mem_s cn68xx; + struct cvmx_ciu2_en_iox_int_mem_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mem_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mem_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mem_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mem_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mio { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mio_s cn68xx; + struct cvmx_ciu2_en_iox_int_mio_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_pkt { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_iox_int_pkt_s cn68xx; + struct cvmx_ciu2_en_iox_int_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_pkt_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_pkt_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_iox_int_pkt_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_pkt_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_pkt_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_pkt_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_iox_int_pkt_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_pkt_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_rml { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_iox_int_rml_s cn68xx; + struct cvmx_ciu2_en_iox_int_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_rml_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_rml_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_iox_int_rml_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_rml_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_rml_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_rml_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_iox_int_rml_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_rml_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_wdog { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_iox_int_wdog_s cn68xx; + struct cvmx_ciu2_en_iox_int_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_wdog_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_wdog_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_wdog_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_wdog_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_wrkq { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_iox_int_wrkq_s cn68xx; + struct cvmx_ciu2_en_iox_int_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_wrkq_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_wrkq_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_wrkq_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_wrkq_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_gpio { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_gpio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_gpio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_io { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_io_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_io_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_io_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_io_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_io_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_io_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mbox { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mbox_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mbox_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mem { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mem_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mem_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mio { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_pkt { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_pkt_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_pkt_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_pkt_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_rml { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_rml_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_rml_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_rml_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_rml_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_rml_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_wdog { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_wdog_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_wdog_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_wrkq { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_wrkq_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_wrkq_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_gpio { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_gpio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_gpio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_io { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_io_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_io_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_io_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_io_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_io_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_io_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mbox { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mbox_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mbox_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mem { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mem_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mem_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mio { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_pkt { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_pkt_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_pkt_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_pkt_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_rml { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_rml_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_rml_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_rml_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_rml_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_rml_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_wdog { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_wdog_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_wdog_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_wrkq { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_wrkq_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_wrkq_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_gpio { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_gpio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_gpio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_io { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_io_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_io_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_io_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_io_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_io_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_io_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mbox { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mbox_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mbox_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mem { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mem_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mem_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mio { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_pkt { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_pkt_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_pkt_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_pkt_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_rml { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_rml_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_rml_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_rml_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_rml_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_rml_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_wdog { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_wdog_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_wdog_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_wrkq { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_wrkq_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_wrkq_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_intr_ciu_ready { + uint64_t u64; + struct cvmx_ciu2_intr_ciu_ready_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t ready:1; +#else + uint64_t ready:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu2_intr_ciu_ready_s cn68xx; + struct cvmx_ciu2_intr_ciu_ready_s cn68xxp1; +}; + +union cvmx_ciu2_intr_ram_ecc_ctl { + uint64_t u64; + struct cvmx_ciu2_intr_ram_ecc_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t flip_synd:2; + uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t flip_synd:2; + uint64_t reserved_3_63:61; +#endif + } s; + struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xx; + struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xxp1; +}; + +union cvmx_ciu2_intr_ram_ecc_st { + uint64_t u64; + struct cvmx_ciu2_intr_ram_ecc_st_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_23_63:41; + uint64_t addr:7; + uint64_t reserved_13_15:3; + uint64_t syndrom:9; + uint64_t reserved_2_3:2; + uint64_t dbe:1; + uint64_t sbe:1; +#else + uint64_t sbe:1; + uint64_t dbe:1; + uint64_t reserved_2_3:2; + uint64_t syndrom:9; + uint64_t reserved_13_15:3; + uint64_t addr:7; + uint64_t reserved_23_63:41; +#endif + } s; + struct cvmx_ciu2_intr_ram_ecc_st_s cn68xx; + struct cvmx_ciu2_intr_ram_ecc_st_s cn68xxp1; +}; + +union cvmx_ciu2_intr_slowdown { + uint64_t u64; + struct cvmx_ciu2_intr_slowdown_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t ctl:3; +#else + uint64_t ctl:3; + uint64_t reserved_3_63:61; +#endif + } s; + struct cvmx_ciu2_intr_slowdown_s cn68xx; + struct cvmx_ciu2_intr_slowdown_s cn68xxp1; +}; + +union cvmx_ciu2_msi_rcvx { + uint64_t u64; + struct cvmx_ciu2_msi_rcvx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t msi_rcv:1; +#else + uint64_t msi_rcv:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu2_msi_rcvx_s cn68xx; + struct cvmx_ciu2_msi_rcvx_s cn68xxp1; +}; + +union cvmx_ciu2_msi_selx { + uint64_t u64; + struct cvmx_ciu2_msi_selx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_13_63:51; + uint64_t pp_num:5; + uint64_t reserved_6_7:2; + uint64_t ip_num:2; + uint64_t reserved_1_3:3; + uint64_t en:1; +#else + uint64_t en:1; + uint64_t reserved_1_3:3; + uint64_t ip_num:2; + uint64_t reserved_6_7:2; + uint64_t pp_num:5; + uint64_t reserved_13_63:51; +#endif + } s; + struct cvmx_ciu2_msi_selx_s cn68xx; + struct cvmx_ciu2_msi_selx_s cn68xxp1; +}; + +union cvmx_ciu2_msired_ppx_ip2 { + uint64_t u64; + struct cvmx_ciu2_msired_ppx_ip2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_21_63:43; + uint64_t intr:1; + uint64_t reserved_17_19:3; + uint64_t newint:1; + uint64_t reserved_8_15:8; + uint64_t msi_num:8; +#else + uint64_t msi_num:8; + uint64_t reserved_8_15:8; + uint64_t newint:1; + uint64_t reserved_17_19:3; + uint64_t intr:1; + uint64_t reserved_21_63:43; +#endif + } s; + struct cvmx_ciu2_msired_ppx_ip2_s cn68xx; + struct cvmx_ciu2_msired_ppx_ip2_s cn68xxp1; +}; + +union cvmx_ciu2_msired_ppx_ip3 { + uint64_t u64; + struct cvmx_ciu2_msired_ppx_ip3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_21_63:43; + uint64_t intr:1; + uint64_t reserved_17_19:3; + uint64_t newint:1; + uint64_t reserved_8_15:8; + uint64_t msi_num:8; +#else + uint64_t msi_num:8; + uint64_t reserved_8_15:8; + uint64_t newint:1; + uint64_t reserved_17_19:3; + uint64_t intr:1; + uint64_t reserved_21_63:43; +#endif + } s; + struct cvmx_ciu2_msired_ppx_ip3_s cn68xx; + struct cvmx_ciu2_msired_ppx_ip3_s cn68xxp1; +}; + +union cvmx_ciu2_msired_ppx_ip4 { + uint64_t u64; + struct cvmx_ciu2_msired_ppx_ip4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_21_63:43; + uint64_t intr:1; + uint64_t reserved_17_19:3; + uint64_t newint:1; + uint64_t reserved_8_15:8; + uint64_t msi_num:8; +#else + uint64_t msi_num:8; + uint64_t reserved_8_15:8; + uint64_t newint:1; + uint64_t reserved_17_19:3; + uint64_t intr:1; + uint64_t reserved_21_63:43; +#endif + } s; + struct cvmx_ciu2_msired_ppx_ip4_s cn68xx; + struct cvmx_ciu2_msired_ppx_ip4_s cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_gpio { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_gpio_s cn68xx; + struct cvmx_ciu2_raw_iox_int_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_io { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_io_s cn68xx; + struct cvmx_ciu2_raw_iox_int_io_s cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_mem { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_mem_s cn68xx; + struct cvmx_ciu2_raw_iox_int_mem_s cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_mio { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_mio_s cn68xx; + struct cvmx_ciu2_raw_iox_int_mio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_pkt { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_pkt_s cn68xx; + struct cvmx_ciu2_raw_iox_int_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_rml { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_rml_s cn68xx; + struct cvmx_ciu2_raw_iox_int_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_wdog { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_wdog_s cn68xx; + struct cvmx_ciu2_raw_iox_int_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_wrkq { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xx; + struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_gpio { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_io { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_mem { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_mio { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_pkt { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_pkt_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_rml { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_rml_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_wdog { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_wrkq { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_gpio { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_io { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_mem { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_mio { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_pkt { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_pkt_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_rml { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_rml_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_wdog { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_wrkq { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_gpio { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_io { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_mem { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_mio { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_pkt { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_pkt_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_rml { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_rml_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_wdog { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_wrkq { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_gpio { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_src_iox_int_gpio_s cn68xx; + struct cvmx_ciu2_src_iox_int_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_io { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_src_iox_int_io_s cn68xx; + struct cvmx_ciu2_src_iox_int_io_s cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_mbox { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_iox_int_mbox_s cn68xx; + struct cvmx_ciu2_src_iox_int_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_mem { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_iox_int_mem_s cn68xx; + struct cvmx_ciu2_src_iox_int_mem_s cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_mio { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_src_iox_int_mio_s cn68xx; + struct cvmx_ciu2_src_iox_int_mio_s cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_pkt { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_src_iox_int_pkt_s cn68xx; + struct cvmx_ciu2_src_iox_int_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_rml { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_src_iox_int_rml_s cn68xx; + struct cvmx_ciu2_src_iox_int_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_wdog { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_src_iox_int_wdog_s cn68xx; + struct cvmx_ciu2_src_iox_int_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_wrkq { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_src_iox_int_wrkq_s cn68xx; + struct cvmx_ciu2_src_iox_int_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_gpio { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_io { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_io_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_io_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_mbox { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_mem { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_mio { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_pkt { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_pkt_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_rml { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_rml_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_wdog { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_wrkq { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_gpio { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_io { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_io_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_io_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_mbox { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_mem { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_mio { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_pkt { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_pkt_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_rml { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_rml_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_wdog { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_wrkq { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_gpio { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_io { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_io_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_io_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_mbox { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_mem { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_mio { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_pkt { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_pkt_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_rml { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_rml_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_wdog { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_wrkq { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_sum_iox_int { + uint64_t u64; + struct cvmx_ciu2_sum_iox_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t mbox:4; + uint64_t reserved_8_59:52; + uint64_t gpio:1; + uint64_t pkt:1; + uint64_t mem:1; + uint64_t io:1; + uint64_t mio:1; + uint64_t rml:1; + uint64_t wdog:1; + uint64_t workq:1; +#else + uint64_t workq:1; + uint64_t wdog:1; + uint64_t rml:1; + uint64_t mio:1; + uint64_t io:1; + uint64_t mem:1; + uint64_t pkt:1; + uint64_t gpio:1; + uint64_t reserved_8_59:52; + uint64_t mbox:4; +#endif + } s; + struct cvmx_ciu2_sum_iox_int_s cn68xx; + struct cvmx_ciu2_sum_iox_int_s cn68xxp1; +}; + +union cvmx_ciu2_sum_ppx_ip2 { + uint64_t u64; + struct cvmx_ciu2_sum_ppx_ip2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t mbox:4; + uint64_t reserved_8_59:52; + uint64_t gpio:1; + uint64_t pkt:1; + uint64_t mem:1; + uint64_t io:1; + uint64_t mio:1; + uint64_t rml:1; + uint64_t wdog:1; + uint64_t workq:1; +#else + uint64_t workq:1; + uint64_t wdog:1; + uint64_t rml:1; + uint64_t mio:1; + uint64_t io:1; + uint64_t mem:1; + uint64_t pkt:1; + uint64_t gpio:1; + uint64_t reserved_8_59:52; + uint64_t mbox:4; +#endif + } s; + struct cvmx_ciu2_sum_ppx_ip2_s cn68xx; + struct cvmx_ciu2_sum_ppx_ip2_s cn68xxp1; +}; + +union cvmx_ciu2_sum_ppx_ip3 { + uint64_t u64; + struct cvmx_ciu2_sum_ppx_ip3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t mbox:4; + uint64_t reserved_8_59:52; + uint64_t gpio:1; + uint64_t pkt:1; + uint64_t mem:1; + uint64_t io:1; + uint64_t mio:1; + uint64_t rml:1; + uint64_t wdog:1; + uint64_t workq:1; +#else + uint64_t workq:1; + uint64_t wdog:1; + uint64_t rml:1; + uint64_t mio:1; + uint64_t io:1; + uint64_t mem:1; + uint64_t pkt:1; + uint64_t gpio:1; + uint64_t reserved_8_59:52; + uint64_t mbox:4; +#endif + } s; + struct cvmx_ciu2_sum_ppx_ip3_s cn68xx; + struct cvmx_ciu2_sum_ppx_ip3_s cn68xxp1; +}; + +union cvmx_ciu2_sum_ppx_ip4 { + uint64_t u64; + struct cvmx_ciu2_sum_ppx_ip4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t mbox:4; + uint64_t reserved_8_59:52; + uint64_t gpio:1; + uint64_t pkt:1; + uint64_t mem:1; + uint64_t io:1; + uint64_t mio:1; + uint64_t rml:1; + uint64_t wdog:1; + uint64_t workq:1; +#else + uint64_t workq:1; + uint64_t wdog:1; + uint64_t rml:1; + uint64_t mio:1; + uint64_t io:1; + uint64_t mem:1; + uint64_t pkt:1; + uint64_t gpio:1; + uint64_t reserved_8_59:52; + uint64_t mbox:4; +#endif + } s; + struct cvmx_ciu2_sum_ppx_ip4_s cn68xx; + struct cvmx_ciu2_sum_ppx_ip4_s cn68xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-dbg-defs.h b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h index abbf42d05e5a..40799cdae695 100644 --- a/arch/mips/include/asm/octeon/cvmx-dbg-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,27 +28,43 @@ #ifndef __CVMX_DBG_DEFS_H__ #define __CVMX_DBG_DEFS_H__ -#define CVMX_DBG_DATA \ - CVMX_ADD_IO_SEG(0x00011F00000001E8ull) +#define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull)) union cvmx_dbg_data { uint64_t u64; struct cvmx_dbg_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t c_mul:5; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_dbg_data_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t pll_mul:3; uint64_t reserved_23_27:5; uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t c_mul:5; + uint64_t reserved_23_27:5; + uint64_t pll_mul:3; + uint64_t reserved_31_63:33; +#endif } cn30xx; struct cvmx_dbg_data_cn30xx cn31xx; struct cvmx_dbg_data_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t d_mul:4; uint64_t dclk_mul2:1; @@ -56,15 +72,32 @@ union cvmx_dbg_data { uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t c_mul:5; + uint64_t cclk_div2:1; + uint64_t dclk_mul2:1; + uint64_t d_mul:4; + uint64_t reserved_29_63:35; +#endif } cn38xx; struct cvmx_dbg_data_cn38xx cn38xxp2; struct cvmx_dbg_data_cn30xx cn50xx; struct cvmx_dbg_data_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t rem:6; uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t c_mul:5; + uint64_t rem:6; + uint64_t reserved_29_63:35; +#endif } cn58xx; struct cvmx_dbg_data_cn58xx cn58xxp1; }; diff --git a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h index c34ad04789ce..dd5b0428de35 100644 --- a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2011 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -55,52 +55,107 @@ #define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull)) #define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull)) #define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8) +static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + + if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1)) + return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8; + + if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2)) + return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; + return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8; + } + return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; +} + #define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8) union cvmx_dpi_bist_status { uint64_t u64; struct cvmx_dpi_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_47_63:17; uint64_t bist:47; +#else + uint64_t bist:47; + uint64_t reserved_47_63:17; +#endif } s; struct cvmx_dpi_bist_status_s cn61xx; struct cvmx_dpi_bist_status_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t bist:45; +#else + uint64_t bist:45; + uint64_t reserved_45_63:19; +#endif } cn63xx; struct cvmx_dpi_bist_status_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t bist:37; +#else + uint64_t bist:37; + uint64_t reserved_37_63:27; +#endif } cn63xxp1; struct cvmx_dpi_bist_status_s cn66xx; struct cvmx_dpi_bist_status_cn63xx cn68xx; struct cvmx_dpi_bist_status_cn63xx cn68xxp1; + struct cvmx_dpi_bist_status_s cnf71xx; }; union cvmx_dpi_ctl { uint64_t u64; struct cvmx_dpi_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t clk:1; uint64_t en:1; +#else + uint64_t en:1; + uint64_t clk:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_dpi_ctl_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t en:1; +#else + uint64_t en:1; + uint64_t reserved_1_63:63; +#endif } cn61xx; struct cvmx_dpi_ctl_s cn63xx; struct cvmx_dpi_ctl_s cn63xxp1; struct cvmx_dpi_ctl_s cn66xx; struct cvmx_dpi_ctl_s cn68xx; struct cvmx_dpi_ctl_s cn68xxp1; + struct cvmx_dpi_ctl_cn61xx cnf71xx; }; union cvmx_dpi_dmax_counts { uint64_t u64; struct cvmx_dpi_dmax_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t fcnt:7; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t fcnt:7; + uint64_t reserved_39_63:25; +#endif } s; struct cvmx_dpi_dmax_counts_s cn61xx; struct cvmx_dpi_dmax_counts_s cn63xx; @@ -108,13 +163,19 @@ union cvmx_dpi_dmax_counts { struct cvmx_dpi_dmax_counts_s cn66xx; struct cvmx_dpi_dmax_counts_s cn68xx; struct cvmx_dpi_dmax_counts_s cn68xxp1; + struct cvmx_dpi_dmax_counts_s cnf71xx; }; union cvmx_dpi_dmax_dbell { uint64_t u64; struct cvmx_dpi_dmax_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dbell:16; +#else + uint64_t dbell:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_dpi_dmax_dbell_s cn61xx; struct cvmx_dpi_dmax_dbell_s cn63xx; @@ -122,31 +183,48 @@ union cvmx_dpi_dmax_dbell { struct cvmx_dpi_dmax_dbell_s cn66xx; struct cvmx_dpi_dmax_dbell_s cn68xx; struct cvmx_dpi_dmax_dbell_s cn68xxp1; + struct cvmx_dpi_dmax_dbell_s cnf71xx; }; union cvmx_dpi_dmax_err_rsp_status { uint64_t u64; struct cvmx_dpi_dmax_err_rsp_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t status:6; +#else + uint64_t status:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_dpi_dmax_err_rsp_status_s cn61xx; struct cvmx_dpi_dmax_err_rsp_status_s cn66xx; struct cvmx_dpi_dmax_err_rsp_status_s cn68xx; struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1; + struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx; }; union cvmx_dpi_dmax_ibuff_saddr { uint64_t u64; struct cvmx_dpi_dmax_ibuff_saddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t csize:14; uint64_t reserved_41_47:7; uint64_t idle:1; uint64_t saddr:33; uint64_t reserved_0_6:7; +#else + uint64_t reserved_0_6:7; + uint64_t saddr:33; + uint64_t idle:1; + uint64_t reserved_41_47:7; + uint64_t csize:14; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_dpi_dmax_ibuff_saddr_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t csize:14; uint64_t reserved_41_47:7; @@ -154,47 +232,78 @@ union cvmx_dpi_dmax_ibuff_saddr { uint64_t reserved_36_39:4; uint64_t saddr:29; uint64_t reserved_0_6:7; +#else + uint64_t reserved_0_6:7; + uint64_t saddr:29; + uint64_t reserved_36_39:4; + uint64_t idle:1; + uint64_t reserved_41_47:7; + uint64_t csize:14; + uint64_t reserved_62_63:2; +#endif } cn61xx; struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx; struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1; struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx; struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx; struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1; + struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx; }; union cvmx_dpi_dmax_iflight { uint64_t u64; struct cvmx_dpi_dmax_iflight_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t cnt:3; +#else + uint64_t cnt:3; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_dpi_dmax_iflight_s cn61xx; struct cvmx_dpi_dmax_iflight_s cn66xx; struct cvmx_dpi_dmax_iflight_s cn68xx; struct cvmx_dpi_dmax_iflight_s cn68xxp1; + struct cvmx_dpi_dmax_iflight_s cnf71xx; }; union cvmx_dpi_dmax_naddr { uint64_t u64; struct cvmx_dpi_dmax_naddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t addr:40; +#else + uint64_t addr:40; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_dpi_dmax_naddr_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t addr:36; +#else + uint64_t addr:36; + uint64_t reserved_36_63:28; +#endif } cn61xx; struct cvmx_dpi_dmax_naddr_cn61xx cn63xx; struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1; struct cvmx_dpi_dmax_naddr_cn61xx cn66xx; struct cvmx_dpi_dmax_naddr_s cn68xx; struct cvmx_dpi_dmax_naddr_s cn68xxp1; + struct cvmx_dpi_dmax_naddr_cn61xx cnf71xx; }; union cvmx_dpi_dmax_reqbnk0 { uint64_t u64; struct cvmx_dpi_dmax_reqbnk0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t state:64; +#else + uint64_t state:64; +#endif } s; struct cvmx_dpi_dmax_reqbnk0_s cn61xx; struct cvmx_dpi_dmax_reqbnk0_s cn63xx; @@ -202,12 +311,17 @@ union cvmx_dpi_dmax_reqbnk0 { struct cvmx_dpi_dmax_reqbnk0_s cn66xx; struct cvmx_dpi_dmax_reqbnk0_s cn68xx; struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1; + struct cvmx_dpi_dmax_reqbnk0_s cnf71xx; }; union cvmx_dpi_dmax_reqbnk1 { uint64_t u64; struct cvmx_dpi_dmax_reqbnk1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t state:64; +#else uint64_t state:64; +#endif } s; struct cvmx_dpi_dmax_reqbnk1_s cn61xx; struct cvmx_dpi_dmax_reqbnk1_s cn63xx; @@ -215,11 +329,13 @@ union cvmx_dpi_dmax_reqbnk1 { struct cvmx_dpi_dmax_reqbnk1_s cn66xx; struct cvmx_dpi_dmax_reqbnk1_s cn68xx; struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1; + struct cvmx_dpi_dmax_reqbnk1_s cnf71xx; }; union cvmx_dpi_dma_control { uint64_t u64; struct cvmx_dpi_dma_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t dici_mode:1; uint64_t pkt_en1:1; @@ -240,9 +356,32 @@ union cvmx_dpi_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t reserved_0_13:14; +#else + uint64_t reserved_0_13:14; + uint64_t o_mode:1; + uint64_t o_es:2; + uint64_t o_ns:1; + uint64_t o_ro:1; + uint64_t o_add1:1; + uint64_t fpa_que:3; + uint64_t dwb_ichk:9; + uint64_t dwb_denb:1; + uint64_t b0_lend:1; + uint64_t reserved_34_47:14; + uint64_t dma_enb:6; + uint64_t reserved_54_55:2; + uint64_t pkt_en:1; + uint64_t pkt_hp:1; + uint64_t commit_mode:1; + uint64_t ffp_dis:1; + uint64_t pkt_en1:1; + uint64_t dici_mode:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_dpi_dma_control_s cn61xx; struct cvmx_dpi_dma_control_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t pkt_en1:1; uint64_t ffp_dis:1; @@ -262,8 +401,30 @@ union cvmx_dpi_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t reserved_0_13:14; +#else + uint64_t reserved_0_13:14; + uint64_t o_mode:1; + uint64_t o_es:2; + uint64_t o_ns:1; + uint64_t o_ro:1; + uint64_t o_add1:1; + uint64_t fpa_que:3; + uint64_t dwb_ichk:9; + uint64_t dwb_denb:1; + uint64_t b0_lend:1; + uint64_t reserved_34_47:14; + uint64_t dma_enb:6; + uint64_t reserved_54_55:2; + uint64_t pkt_en:1; + uint64_t pkt_hp:1; + uint64_t commit_mode:1; + uint64_t ffp_dis:1; + uint64_t pkt_en1:1; + uint64_t reserved_61_63:3; +#endif } cn63xx; struct cvmx_dpi_dma_control_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t commit_mode:1; uint64_t pkt_hp:1; @@ -281,17 +442,42 @@ union cvmx_dpi_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t reserved_0_13:14; +#else + uint64_t reserved_0_13:14; + uint64_t o_mode:1; + uint64_t o_es:2; + uint64_t o_ns:1; + uint64_t o_ro:1; + uint64_t o_add1:1; + uint64_t fpa_que:3; + uint64_t dwb_ichk:9; + uint64_t dwb_denb:1; + uint64_t b0_lend:1; + uint64_t reserved_34_47:14; + uint64_t dma_enb:6; + uint64_t reserved_54_55:2; + uint64_t pkt_en:1; + uint64_t pkt_hp:1; + uint64_t commit_mode:1; + uint64_t reserved_59_63:5; +#endif } cn63xxp1; struct cvmx_dpi_dma_control_cn63xx cn66xx; struct cvmx_dpi_dma_control_s cn68xx; struct cvmx_dpi_dma_control_cn63xx cn68xxp1; + struct cvmx_dpi_dma_control_s cnf71xx; }; union cvmx_dpi_dma_engx_en { uint64_t u64; struct cvmx_dpi_dma_engx_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t qen:8; +#else + uint64_t qen:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_dpi_dma_engx_en_s cn61xx; struct cvmx_dpi_dma_engx_en_s cn63xx; @@ -299,63 +485,101 @@ union cvmx_dpi_dma_engx_en { struct cvmx_dpi_dma_engx_en_s cn66xx; struct cvmx_dpi_dma_engx_en_s cn68xx; struct cvmx_dpi_dma_engx_en_s cn68xxp1; + struct cvmx_dpi_dma_engx_en_s cnf71xx; }; union cvmx_dpi_dma_ppx_cnt { uint64_t u64; struct cvmx_dpi_dma_ppx_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt:16; +#else + uint64_t cnt:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_dpi_dma_ppx_cnt_s cn61xx; struct cvmx_dpi_dma_ppx_cnt_s cn68xx; + struct cvmx_dpi_dma_ppx_cnt_s cnf71xx; }; union cvmx_dpi_engx_buf { uint64_t u64; struct cvmx_dpi_engx_buf_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t compblks:5; uint64_t reserved_9_31:23; uint64_t base:5; uint64_t blks:4; +#else + uint64_t blks:4; + uint64_t base:5; + uint64_t reserved_9_31:23; + uint64_t compblks:5; + uint64_t reserved_37_63:27; +#endif } s; struct cvmx_dpi_engx_buf_s cn61xx; struct cvmx_dpi_engx_buf_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t base:4; uint64_t blks:4; +#else + uint64_t blks:4; + uint64_t base:4; + uint64_t reserved_8_63:56; +#endif } cn63xx; struct cvmx_dpi_engx_buf_cn63xx cn63xxp1; struct cvmx_dpi_engx_buf_s cn66xx; struct cvmx_dpi_engx_buf_s cn68xx; struct cvmx_dpi_engx_buf_s cn68xxp1; + struct cvmx_dpi_engx_buf_s cnf71xx; }; union cvmx_dpi_info_reg { uint64_t u64; struct cvmx_dpi_info_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ffp:4; uint64_t reserved_2_3:2; uint64_t ncb:1; uint64_t rsl:1; +#else + uint64_t rsl:1; + uint64_t ncb:1; + uint64_t reserved_2_3:2; + uint64_t ffp:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_dpi_info_reg_s cn61xx; struct cvmx_dpi_info_reg_s cn63xx; struct cvmx_dpi_info_reg_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t ncb:1; uint64_t rsl:1; +#else + uint64_t rsl:1; + uint64_t ncb:1; + uint64_t reserved_2_63:62; +#endif } cn63xxp1; struct cvmx_dpi_info_reg_s cn66xx; struct cvmx_dpi_info_reg_s cn68xx; struct cvmx_dpi_info_reg_s cn68xxp1; + struct cvmx_dpi_info_reg_s cnf71xx; }; union cvmx_dpi_int_en { uint64_t u64; struct cvmx_dpi_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t sprt3_rst:1; uint64_t sprt2_rst:1; @@ -373,9 +597,29 @@ union cvmx_dpi_int_en { uint64_t reserved_2_7:6; uint64_t nfovr:1; uint64_t nderr:1; +#else + uint64_t nderr:1; + uint64_t nfovr:1; + uint64_t reserved_2_7:6; + uint64_t dmadbo:8; + uint64_t req_badadr:1; + uint64_t req_badlen:1; + uint64_t req_ovrflw:1; + uint64_t req_undflw:1; + uint64_t req_anull:1; + uint64_t req_inull:1; + uint64_t req_badfil:1; + uint64_t reserved_23_23:1; + uint64_t sprt0_rst:1; + uint64_t sprt1_rst:1; + uint64_t sprt2_rst:1; + uint64_t sprt3_rst:1; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_dpi_int_en_s cn61xx; struct cvmx_dpi_int_en_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t sprt1_rst:1; uint64_t sprt0_rst:1; @@ -391,16 +635,35 @@ union cvmx_dpi_int_en { uint64_t reserved_2_7:6; uint64_t nfovr:1; uint64_t nderr:1; +#else + uint64_t nderr:1; + uint64_t nfovr:1; + uint64_t reserved_2_7:6; + uint64_t dmadbo:8; + uint64_t req_badadr:1; + uint64_t req_badlen:1; + uint64_t req_ovrflw:1; + uint64_t req_undflw:1; + uint64_t req_anull:1; + uint64_t req_inull:1; + uint64_t req_badfil:1; + uint64_t reserved_23_23:1; + uint64_t sprt0_rst:1; + uint64_t sprt1_rst:1; + uint64_t reserved_26_63:38; +#endif } cn63xx; struct cvmx_dpi_int_en_cn63xx cn63xxp1; struct cvmx_dpi_int_en_s cn66xx; struct cvmx_dpi_int_en_cn63xx cn68xx; struct cvmx_dpi_int_en_cn63xx cn68xxp1; + struct cvmx_dpi_int_en_s cnf71xx; }; union cvmx_dpi_int_reg { uint64_t u64; struct cvmx_dpi_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t sprt3_rst:1; uint64_t sprt2_rst:1; @@ -418,9 +681,29 @@ union cvmx_dpi_int_reg { uint64_t reserved_2_7:6; uint64_t nfovr:1; uint64_t nderr:1; +#else + uint64_t nderr:1; + uint64_t nfovr:1; + uint64_t reserved_2_7:6; + uint64_t dmadbo:8; + uint64_t req_badadr:1; + uint64_t req_badlen:1; + uint64_t req_ovrflw:1; + uint64_t req_undflw:1; + uint64_t req_anull:1; + uint64_t req_inull:1; + uint64_t req_badfil:1; + uint64_t reserved_23_23:1; + uint64_t sprt0_rst:1; + uint64_t sprt1_rst:1; + uint64_t sprt2_rst:1; + uint64_t sprt3_rst:1; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_dpi_int_reg_s cn61xx; struct cvmx_dpi_int_reg_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t sprt1_rst:1; uint64_t sprt0_rst:1; @@ -436,31 +719,62 @@ union cvmx_dpi_int_reg { uint64_t reserved_2_7:6; uint64_t nfovr:1; uint64_t nderr:1; +#else + uint64_t nderr:1; + uint64_t nfovr:1; + uint64_t reserved_2_7:6; + uint64_t dmadbo:8; + uint64_t req_badadr:1; + uint64_t req_badlen:1; + uint64_t req_ovrflw:1; + uint64_t req_undflw:1; + uint64_t req_anull:1; + uint64_t req_inull:1; + uint64_t req_badfil:1; + uint64_t reserved_23_23:1; + uint64_t sprt0_rst:1; + uint64_t sprt1_rst:1; + uint64_t reserved_26_63:38; +#endif } cn63xx; struct cvmx_dpi_int_reg_cn63xx cn63xxp1; struct cvmx_dpi_int_reg_s cn66xx; struct cvmx_dpi_int_reg_cn63xx cn68xx; struct cvmx_dpi_int_reg_cn63xx cn68xxp1; + struct cvmx_dpi_int_reg_s cnf71xx; }; union cvmx_dpi_ncbx_cfg { uint64_t u64; struct cvmx_dpi_ncbx_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t molr:6; +#else + uint64_t molr:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_dpi_ncbx_cfg_s cn61xx; struct cvmx_dpi_ncbx_cfg_s cn66xx; struct cvmx_dpi_ncbx_cfg_s cn68xx; + struct cvmx_dpi_ncbx_cfg_s cnf71xx; }; union cvmx_dpi_pint_info { uint64_t u64; struct cvmx_dpi_pint_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t iinfo:6; uint64_t reserved_6_7:2; uint64_t sinfo:6; +#else + uint64_t sinfo:6; + uint64_t reserved_6_7:2; + uint64_t iinfo:6; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_dpi_pint_info_s cn61xx; struct cvmx_dpi_pint_info_s cn63xx; @@ -468,13 +782,19 @@ union cvmx_dpi_pint_info { struct cvmx_dpi_pint_info_s cn66xx; struct cvmx_dpi_pint_info_s cn68xx; struct cvmx_dpi_pint_info_s cn68xxp1; + struct cvmx_dpi_pint_info_s cnf71xx; }; union cvmx_dpi_pkt_err_rsp { uint64_t u64; struct cvmx_dpi_pkt_err_rsp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t pkterr:1; +#else + uint64_t pkterr:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_dpi_pkt_err_rsp_s cn61xx; struct cvmx_dpi_pkt_err_rsp_s cn63xx; @@ -482,13 +802,19 @@ union cvmx_dpi_pkt_err_rsp { struct cvmx_dpi_pkt_err_rsp_s cn66xx; struct cvmx_dpi_pkt_err_rsp_s cn68xx; struct cvmx_dpi_pkt_err_rsp_s cn68xxp1; + struct cvmx_dpi_pkt_err_rsp_s cnf71xx; }; union cvmx_dpi_req_err_rsp { uint64_t u64; struct cvmx_dpi_req_err_rsp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t qerr:8; +#else + uint64_t qerr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_dpi_req_err_rsp_s cn61xx; struct cvmx_dpi_req_err_rsp_s cn63xx; @@ -496,13 +822,19 @@ union cvmx_dpi_req_err_rsp { struct cvmx_dpi_req_err_rsp_s cn66xx; struct cvmx_dpi_req_err_rsp_s cn68xx; struct cvmx_dpi_req_err_rsp_s cn68xxp1; + struct cvmx_dpi_req_err_rsp_s cnf71xx; }; union cvmx_dpi_req_err_rsp_en { uint64_t u64; struct cvmx_dpi_req_err_rsp_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t en:8; +#else + uint64_t en:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_dpi_req_err_rsp_en_s cn61xx; struct cvmx_dpi_req_err_rsp_en_s cn63xx; @@ -510,13 +842,19 @@ union cvmx_dpi_req_err_rsp_en { struct cvmx_dpi_req_err_rsp_en_s cn66xx; struct cvmx_dpi_req_err_rsp_en_s cn68xx; struct cvmx_dpi_req_err_rsp_en_s cn68xxp1; + struct cvmx_dpi_req_err_rsp_en_s cnf71xx; }; union cvmx_dpi_req_err_rst { uint64_t u64; struct cvmx_dpi_req_err_rst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t qerr:8; +#else + uint64_t qerr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_dpi_req_err_rst_s cn61xx; struct cvmx_dpi_req_err_rst_s cn63xx; @@ -524,13 +862,19 @@ union cvmx_dpi_req_err_rst { struct cvmx_dpi_req_err_rst_s cn66xx; struct cvmx_dpi_req_err_rst_s cn68xx; struct cvmx_dpi_req_err_rst_s cn68xxp1; + struct cvmx_dpi_req_err_rst_s cnf71xx; }; union cvmx_dpi_req_err_rst_en { uint64_t u64; struct cvmx_dpi_req_err_rst_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t en:8; +#else + uint64_t en:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_dpi_req_err_rst_en_s cn61xx; struct cvmx_dpi_req_err_rst_en_s cn63xx; @@ -538,27 +882,41 @@ union cvmx_dpi_req_err_rst_en { struct cvmx_dpi_req_err_rst_en_s cn66xx; struct cvmx_dpi_req_err_rst_en_s cn68xx; struct cvmx_dpi_req_err_rst_en_s cn68xxp1; + struct cvmx_dpi_req_err_rst_en_s cnf71xx; }; union cvmx_dpi_req_err_skip_comp { uint64_t u64; struct cvmx_dpi_req_err_skip_comp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t en_rst:8; uint64_t reserved_8_15:8; uint64_t en_rsp:8; +#else + uint64_t en_rsp:8; + uint64_t reserved_8_15:8; + uint64_t en_rst:8; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_dpi_req_err_skip_comp_s cn61xx; struct cvmx_dpi_req_err_skip_comp_s cn66xx; struct cvmx_dpi_req_err_skip_comp_s cn68xx; struct cvmx_dpi_req_err_skip_comp_s cn68xxp1; + struct cvmx_dpi_req_err_skip_comp_s cnf71xx; }; union cvmx_dpi_req_gbl_en { uint64_t u64; struct cvmx_dpi_req_gbl_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t qen:8; +#else + uint64_t qen:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_dpi_req_gbl_en_s cn61xx; struct cvmx_dpi_req_gbl_en_s cn63xx; @@ -566,11 +924,13 @@ union cvmx_dpi_req_gbl_en { struct cvmx_dpi_req_gbl_en_s cn66xx; struct cvmx_dpi_req_gbl_en_s cn68xx; struct cvmx_dpi_req_gbl_en_s cn68xxp1; + struct cvmx_dpi_req_gbl_en_s cnf71xx; }; union cvmx_dpi_sli_prtx_cfg { uint64_t u64; struct cvmx_dpi_sli_prtx_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t halt:1; uint64_t qlm_cfg:4; @@ -584,9 +944,25 @@ union cvmx_dpi_sli_prtx_cfg { uint64_t mrrs_lim:1; uint64_t reserved_2_2:1; uint64_t mrrs:2; +#else + uint64_t mrrs:2; + uint64_t reserved_2_2:1; + uint64_t mrrs_lim:1; + uint64_t mps:1; + uint64_t reserved_5_6:2; + uint64_t mps_lim:1; + uint64_t molr:6; + uint64_t reserved_14_15:2; + uint64_t rd_mode:1; + uint64_t reserved_17_19:3; + uint64_t qlm_cfg:4; + uint64_t halt:1; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_dpi_sli_prtx_cfg_s cn61xx; struct cvmx_dpi_sli_prtx_cfg_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t halt:1; uint64_t reserved_21_23:3; @@ -601,18 +977,40 @@ union cvmx_dpi_sli_prtx_cfg { uint64_t mrrs_lim:1; uint64_t reserved_2_2:1; uint64_t mrrs:2; +#else + uint64_t mrrs:2; + uint64_t reserved_2_2:1; + uint64_t mrrs_lim:1; + uint64_t mps:1; + uint64_t reserved_5_6:2; + uint64_t mps_lim:1; + uint64_t molr:6; + uint64_t reserved_14_15:2; + uint64_t rd_mode:1; + uint64_t reserved_17_19:3; + uint64_t qlm_cfg:1; + uint64_t reserved_21_23:3; + uint64_t halt:1; + uint64_t reserved_25_63:39; +#endif } cn63xx; struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1; struct cvmx_dpi_sli_prtx_cfg_s cn66xx; struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx; struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1; + struct cvmx_dpi_sli_prtx_cfg_s cnf71xx; }; union cvmx_dpi_sli_prtx_err { uint64_t u64; struct cvmx_dpi_sli_prtx_err_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:61; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t addr:61; +#endif } s; struct cvmx_dpi_sli_prtx_err_s cn61xx; struct cvmx_dpi_sli_prtx_err_s cn63xx; @@ -620,17 +1018,27 @@ union cvmx_dpi_sli_prtx_err { struct cvmx_dpi_sli_prtx_err_s cn66xx; struct cvmx_dpi_sli_prtx_err_s cn68xx; struct cvmx_dpi_sli_prtx_err_s cn68xxp1; + struct cvmx_dpi_sli_prtx_err_s cnf71xx; }; union cvmx_dpi_sli_prtx_err_info { uint64_t u64; struct cvmx_dpi_sli_prtx_err_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t lock:1; uint64_t reserved_5_7:3; uint64_t type:1; uint64_t reserved_3_3:1; uint64_t reqq:3; +#else + uint64_t reqq:3; + uint64_t reserved_3_3:1; + uint64_t type:1; + uint64_t reserved_5_7:3; + uint64_t lock:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_dpi_sli_prtx_err_info_s cn61xx; struct cvmx_dpi_sli_prtx_err_info_s cn63xx; @@ -638,6 +1046,7 @@ union cvmx_dpi_sli_prtx_err_info { struct cvmx_dpi_sli_prtx_err_info_s cn66xx; struct cvmx_dpi_sli_prtx_err_info_s cn68xx; struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1; + struct cvmx_dpi_sli_prtx_err_info_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-fpa-defs.h b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h index bf5546b90110..1d79e3c7040d 100644 --- a/arch/mips/include/asm/octeon/cvmx-fpa-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,74 +28,83 @@ #ifndef __CVMX_FPA_DEFS_H__ #define __CVMX_FPA_DEFS_H__ -#define CVMX_FPA_BIST_STATUS \ - CVMX_ADD_IO_SEG(0x00011800280000E8ull) -#define CVMX_FPA_CTL_STATUS \ - CVMX_ADD_IO_SEG(0x0001180028000050ull) -#define CVMX_FPA_FPF0_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000000ull) -#define CVMX_FPA_FPF0_SIZE \ - CVMX_ADD_IO_SEG(0x0001180028000058ull) -#define CVMX_FPA_FPF1_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000008ull) -#define CVMX_FPA_FPF2_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000010ull) -#define CVMX_FPA_FPF3_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000018ull) -#define CVMX_FPA_FPF4_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000020ull) -#define CVMX_FPA_FPF5_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000028ull) -#define CVMX_FPA_FPF6_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000030ull) -#define CVMX_FPA_FPF7_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000038ull) -#define CVMX_FPA_FPFX_MARKS(offset) \ - CVMX_ADD_IO_SEG(0x0001180028000008ull + (((offset) & 7) * 8) - 8 * 1) -#define CVMX_FPA_FPFX_SIZE(offset) \ - CVMX_ADD_IO_SEG(0x0001180028000060ull + (((offset) & 7) * 8) - 8 * 1) -#define CVMX_FPA_INT_ENB \ - CVMX_ADD_IO_SEG(0x0001180028000048ull) -#define CVMX_FPA_INT_SUM \ - CVMX_ADD_IO_SEG(0x0001180028000040ull) -#define CVMX_FPA_QUE0_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x00011800280000F0ull) -#define CVMX_FPA_QUE1_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x00011800280000F8ull) -#define CVMX_FPA_QUE2_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000100ull) -#define CVMX_FPA_QUE3_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000108ull) -#define CVMX_FPA_QUE4_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000110ull) -#define CVMX_FPA_QUE5_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000118ull) -#define CVMX_FPA_QUE6_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000120ull) -#define CVMX_FPA_QUE7_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000128ull) -#define CVMX_FPA_QUEX_AVAILABLE(offset) \ - CVMX_ADD_IO_SEG(0x0001180028000098ull + (((offset) & 7) * 8)) -#define CVMX_FPA_QUEX_PAGE_INDEX(offset) \ - CVMX_ADD_IO_SEG(0x00011800280000F0ull + (((offset) & 7) * 8)) -#define CVMX_FPA_QUE_ACT \ - CVMX_ADD_IO_SEG(0x0001180028000138ull) -#define CVMX_FPA_QUE_EXP \ - CVMX_ADD_IO_SEG(0x0001180028000130ull) -#define CVMX_FPA_WART_CTL \ - CVMX_ADD_IO_SEG(0x00011800280000D8ull) -#define CVMX_FPA_WART_STATUS \ - CVMX_ADD_IO_SEG(0x00011800280000E0ull) +#define CVMX_FPA_ADDR_RANGE_ERROR (CVMX_ADD_IO_SEG(0x0001180028000458ull)) +#define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull)) +#define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull)) +#define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull)) +#define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull)) +#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1) +#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2) +#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3) +#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4) +#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5) +#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6) +#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7) +#define CVMX_FPA_FPF8_MARKS (CVMX_ADD_IO_SEG(0x0001180028000240ull)) +#define CVMX_FPA_FPF8_SIZE (CVMX_ADD_IO_SEG(0x0001180028000248ull)) +#define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1) +#define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1) +#define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull)) +#define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull)) +#define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull)) +#define CVMX_FPA_POOLX_END_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8) +#define CVMX_FPA_POOLX_START_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8) +#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8) +#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0) +#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1) +#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2) +#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3) +#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4) +#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5) +#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6) +#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7) +#define CVMX_FPA_QUE8_PAGE_INDEX (CVMX_ADD_IO_SEG(0x0001180028000250ull)) +#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8) +#define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8) +#define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull)) +#define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull)) +#define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull)) +#define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull)) +#define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull)) + +union cvmx_fpa_addr_range_error { + uint64_t u64; + struct cvmx_fpa_addr_range_error_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_38_63:26; + uint64_t pool:5; + uint64_t addr:33; +#else + uint64_t addr:33; + uint64_t pool:5; + uint64_t reserved_38_63:26; +#endif + } s; + struct cvmx_fpa_addr_range_error_s cn61xx; + struct cvmx_fpa_addr_range_error_s cn66xx; + struct cvmx_fpa_addr_range_error_s cn68xx; + struct cvmx_fpa_addr_range_error_s cn68xxp1; + struct cvmx_fpa_addr_range_error_s cnf71xx; +}; union cvmx_fpa_bist_status { uint64_t u64; struct cvmx_fpa_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t frd:1; uint64_t fpf0:1; uint64_t fpf1:1; uint64_t ffr:1; uint64_t fdr:1; +#else + uint64_t fdr:1; + uint64_t ffr:1; + uint64_t fpf1:1; + uint64_t fpf0:1; + uint64_t frd:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_fpa_bist_status_s cn30xx; struct cvmx_fpa_bist_status_s cn31xx; @@ -108,38 +117,92 @@ union cvmx_fpa_bist_status { struct cvmx_fpa_bist_status_s cn56xxp1; struct cvmx_fpa_bist_status_s cn58xx; struct cvmx_fpa_bist_status_s cn58xxp1; + struct cvmx_fpa_bist_status_s cn61xx; + struct cvmx_fpa_bist_status_s cn63xx; + struct cvmx_fpa_bist_status_s cn63xxp1; + struct cvmx_fpa_bist_status_s cn66xx; + struct cvmx_fpa_bist_status_s cn68xx; + struct cvmx_fpa_bist_status_s cn68xxp1; + struct cvmx_fpa_bist_status_s cnf71xx; }; union cvmx_fpa_ctl_status { uint64_t u64; struct cvmx_fpa_ctl_status_s { - uint64_t reserved_18_63:46; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_21_63:43; + uint64_t free_en:1; + uint64_t ret_off:1; + uint64_t req_off:1; uint64_t reset:1; uint64_t use_ldt:1; uint64_t use_stt:1; uint64_t enb:1; uint64_t mem1_err:7; uint64_t mem0_err:7; +#else + uint64_t mem0_err:7; + uint64_t mem1_err:7; + uint64_t enb:1; + uint64_t use_stt:1; + uint64_t use_ldt:1; + uint64_t reset:1; + uint64_t req_off:1; + uint64_t ret_off:1; + uint64_t free_en:1; + uint64_t reserved_21_63:43; +#endif } s; - struct cvmx_fpa_ctl_status_s cn30xx; - struct cvmx_fpa_ctl_status_s cn31xx; - struct cvmx_fpa_ctl_status_s cn38xx; - struct cvmx_fpa_ctl_status_s cn38xxp2; - struct cvmx_fpa_ctl_status_s cn50xx; - struct cvmx_fpa_ctl_status_s cn52xx; - struct cvmx_fpa_ctl_status_s cn52xxp1; - struct cvmx_fpa_ctl_status_s cn56xx; - struct cvmx_fpa_ctl_status_s cn56xxp1; - struct cvmx_fpa_ctl_status_s cn58xx; - struct cvmx_fpa_ctl_status_s cn58xxp1; + struct cvmx_fpa_ctl_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t reset:1; + uint64_t use_ldt:1; + uint64_t use_stt:1; + uint64_t enb:1; + uint64_t mem1_err:7; + uint64_t mem0_err:7; +#else + uint64_t mem0_err:7; + uint64_t mem1_err:7; + uint64_t enb:1; + uint64_t use_stt:1; + uint64_t use_ldt:1; + uint64_t reset:1; + uint64_t reserved_18_63:46; +#endif + } cn30xx; + struct cvmx_fpa_ctl_status_cn30xx cn31xx; + struct cvmx_fpa_ctl_status_cn30xx cn38xx; + struct cvmx_fpa_ctl_status_cn30xx cn38xxp2; + struct cvmx_fpa_ctl_status_cn30xx cn50xx; + struct cvmx_fpa_ctl_status_cn30xx cn52xx; + struct cvmx_fpa_ctl_status_cn30xx cn52xxp1; + struct cvmx_fpa_ctl_status_cn30xx cn56xx; + struct cvmx_fpa_ctl_status_cn30xx cn56xxp1; + struct cvmx_fpa_ctl_status_cn30xx cn58xx; + struct cvmx_fpa_ctl_status_cn30xx cn58xxp1; + struct cvmx_fpa_ctl_status_s cn61xx; + struct cvmx_fpa_ctl_status_s cn63xx; + struct cvmx_fpa_ctl_status_cn30xx cn63xxp1; + struct cvmx_fpa_ctl_status_s cn66xx; + struct cvmx_fpa_ctl_status_s cn68xx; + struct cvmx_fpa_ctl_status_s cn68xxp1; + struct cvmx_fpa_ctl_status_s cnf71xx; }; union cvmx_fpa_fpfx_marks { uint64_t u64; struct cvmx_fpa_fpfx_marks_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t fpf_wr:11; uint64_t fpf_rd:11; +#else + uint64_t fpf_rd:11; + uint64_t fpf_wr:11; + uint64_t reserved_22_63:42; +#endif } s; struct cvmx_fpa_fpfx_marks_s cn38xx; struct cvmx_fpa_fpfx_marks_s cn38xxp2; @@ -147,13 +210,25 @@ union cvmx_fpa_fpfx_marks { struct cvmx_fpa_fpfx_marks_s cn56xxp1; struct cvmx_fpa_fpfx_marks_s cn58xx; struct cvmx_fpa_fpfx_marks_s cn58xxp1; + struct cvmx_fpa_fpfx_marks_s cn61xx; + struct cvmx_fpa_fpfx_marks_s cn63xx; + struct cvmx_fpa_fpfx_marks_s cn63xxp1; + struct cvmx_fpa_fpfx_marks_s cn66xx; + struct cvmx_fpa_fpfx_marks_s cn68xx; + struct cvmx_fpa_fpfx_marks_s cn68xxp1; + struct cvmx_fpa_fpfx_marks_s cnf71xx; }; union cvmx_fpa_fpfx_size { uint64_t u64; struct cvmx_fpa_fpfx_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t fpf_siz:11; +#else + uint64_t fpf_siz:11; + uint64_t reserved_11_63:53; +#endif } s; struct cvmx_fpa_fpfx_size_s cn38xx; struct cvmx_fpa_fpfx_size_s cn38xxp2; @@ -161,14 +236,27 @@ union cvmx_fpa_fpfx_size { struct cvmx_fpa_fpfx_size_s cn56xxp1; struct cvmx_fpa_fpfx_size_s cn58xx; struct cvmx_fpa_fpfx_size_s cn58xxp1; + struct cvmx_fpa_fpfx_size_s cn61xx; + struct cvmx_fpa_fpfx_size_s cn63xx; + struct cvmx_fpa_fpfx_size_s cn63xxp1; + struct cvmx_fpa_fpfx_size_s cn66xx; + struct cvmx_fpa_fpfx_size_s cn68xx; + struct cvmx_fpa_fpfx_size_s cn68xxp1; + struct cvmx_fpa_fpfx_size_s cnf71xx; }; union cvmx_fpa_fpf0_marks { uint64_t u64; struct cvmx_fpa_fpf0_marks_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t fpf_wr:12; uint64_t fpf_rd:12; +#else + uint64_t fpf_rd:12; + uint64_t fpf_wr:12; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_fpa_fpf0_marks_s cn38xx; struct cvmx_fpa_fpf0_marks_s cn38xxp2; @@ -176,13 +264,25 @@ union cvmx_fpa_fpf0_marks { struct cvmx_fpa_fpf0_marks_s cn56xxp1; struct cvmx_fpa_fpf0_marks_s cn58xx; struct cvmx_fpa_fpf0_marks_s cn58xxp1; + struct cvmx_fpa_fpf0_marks_s cn61xx; + struct cvmx_fpa_fpf0_marks_s cn63xx; + struct cvmx_fpa_fpf0_marks_s cn63xxp1; + struct cvmx_fpa_fpf0_marks_s cn66xx; + struct cvmx_fpa_fpf0_marks_s cn68xx; + struct cvmx_fpa_fpf0_marks_s cn68xxp1; + struct cvmx_fpa_fpf0_marks_s cnf71xx; }; union cvmx_fpa_fpf0_size { uint64_t u64; struct cvmx_fpa_fpf0_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t fpf_siz:12; +#else + uint64_t fpf_siz:12; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_fpa_fpf0_size_s cn38xx; struct cvmx_fpa_fpf0_size_s cn38xxp2; @@ -190,12 +290,70 @@ union cvmx_fpa_fpf0_size { struct cvmx_fpa_fpf0_size_s cn56xxp1; struct cvmx_fpa_fpf0_size_s cn58xx; struct cvmx_fpa_fpf0_size_s cn58xxp1; + struct cvmx_fpa_fpf0_size_s cn61xx; + struct cvmx_fpa_fpf0_size_s cn63xx; + struct cvmx_fpa_fpf0_size_s cn63xxp1; + struct cvmx_fpa_fpf0_size_s cn66xx; + struct cvmx_fpa_fpf0_size_s cn68xx; + struct cvmx_fpa_fpf0_size_s cn68xxp1; + struct cvmx_fpa_fpf0_size_s cnf71xx; +}; + +union cvmx_fpa_fpf8_marks { + uint64_t u64; + struct cvmx_fpa_fpf8_marks_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_22_63:42; + uint64_t fpf_wr:11; + uint64_t fpf_rd:11; +#else + uint64_t fpf_rd:11; + uint64_t fpf_wr:11; + uint64_t reserved_22_63:42; +#endif + } s; + struct cvmx_fpa_fpf8_marks_s cn68xx; + struct cvmx_fpa_fpf8_marks_s cn68xxp1; +}; + +union cvmx_fpa_fpf8_size { + uint64_t u64; + struct cvmx_fpa_fpf8_size_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t fpf_siz:12; +#else + uint64_t fpf_siz:12; + uint64_t reserved_12_63:52; +#endif + } s; + struct cvmx_fpa_fpf8_size_s cn68xx; + struct cvmx_fpa_fpf8_size_s cn68xxp1; }; union cvmx_fpa_int_enb { uint64_t u64; struct cvmx_fpa_int_enb_s { - uint64_t reserved_28_63:36; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_50_63:14; + uint64_t paddr_e:1; + uint64_t reserved_44_48:5; + uint64_t free7:1; + uint64_t free6:1; + uint64_t free5:1; + uint64_t free4:1; + uint64_t free3:1; + uint64_t free2:1; + uint64_t free1:1; + uint64_t free0:1; + uint64_t pool7th:1; + uint64_t pool6th:1; + uint64_t pool5th:1; + uint64_t pool4th:1; + uint64_t pool3th:1; + uint64_t pool2th:1; + uint64_t pool1th:1; + uint64_t pool0th:1; uint64_t q7_perr:1; uint64_t q7_coff:1; uint64_t q7_und:1; @@ -224,23 +382,547 @@ union cvmx_fpa_int_enb { uint64_t fed1_sbe:1; uint64_t fed0_dbe:1; uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t pool0th:1; + uint64_t pool1th:1; + uint64_t pool2th:1; + uint64_t pool3th:1; + uint64_t pool4th:1; + uint64_t pool5th:1; + uint64_t pool6th:1; + uint64_t pool7th:1; + uint64_t free0:1; + uint64_t free1:1; + uint64_t free2:1; + uint64_t free3:1; + uint64_t free4:1; + uint64_t free5:1; + uint64_t free6:1; + uint64_t free7:1; + uint64_t reserved_44_48:5; + uint64_t paddr_e:1; + uint64_t reserved_50_63:14; +#endif } s; - struct cvmx_fpa_int_enb_s cn30xx; - struct cvmx_fpa_int_enb_s cn31xx; - struct cvmx_fpa_int_enb_s cn38xx; - struct cvmx_fpa_int_enb_s cn38xxp2; - struct cvmx_fpa_int_enb_s cn50xx; - struct cvmx_fpa_int_enb_s cn52xx; - struct cvmx_fpa_int_enb_s cn52xxp1; - struct cvmx_fpa_int_enb_s cn56xx; - struct cvmx_fpa_int_enb_s cn56xxp1; - struct cvmx_fpa_int_enb_s cn58xx; - struct cvmx_fpa_int_enb_s cn58xxp1; + struct cvmx_fpa_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_28_63:36; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t reserved_28_63:36; +#endif + } cn30xx; + struct cvmx_fpa_int_enb_cn30xx cn31xx; + struct cvmx_fpa_int_enb_cn30xx cn38xx; + struct cvmx_fpa_int_enb_cn30xx cn38xxp2; + struct cvmx_fpa_int_enb_cn30xx cn50xx; + struct cvmx_fpa_int_enb_cn30xx cn52xx; + struct cvmx_fpa_int_enb_cn30xx cn52xxp1; + struct cvmx_fpa_int_enb_cn30xx cn56xx; + struct cvmx_fpa_int_enb_cn30xx cn56xxp1; + struct cvmx_fpa_int_enb_cn30xx cn58xx; + struct cvmx_fpa_int_enb_cn30xx cn58xxp1; + struct cvmx_fpa_int_enb_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_50_63:14; + uint64_t paddr_e:1; + uint64_t res_44:5; + uint64_t free7:1; + uint64_t free6:1; + uint64_t free5:1; + uint64_t free4:1; + uint64_t free3:1; + uint64_t free2:1; + uint64_t free1:1; + uint64_t free0:1; + uint64_t pool7th:1; + uint64_t pool6th:1; + uint64_t pool5th:1; + uint64_t pool4th:1; + uint64_t pool3th:1; + uint64_t pool2th:1; + uint64_t pool1th:1; + uint64_t pool0th:1; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t pool0th:1; + uint64_t pool1th:1; + uint64_t pool2th:1; + uint64_t pool3th:1; + uint64_t pool4th:1; + uint64_t pool5th:1; + uint64_t pool6th:1; + uint64_t pool7th:1; + uint64_t free0:1; + uint64_t free1:1; + uint64_t free2:1; + uint64_t free3:1; + uint64_t free4:1; + uint64_t free5:1; + uint64_t free6:1; + uint64_t free7:1; + uint64_t res_44:5; + uint64_t paddr_e:1; + uint64_t reserved_50_63:14; +#endif + } cn61xx; + struct cvmx_fpa_int_enb_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_44_63:20; + uint64_t free7:1; + uint64_t free6:1; + uint64_t free5:1; + uint64_t free4:1; + uint64_t free3:1; + uint64_t free2:1; + uint64_t free1:1; + uint64_t free0:1; + uint64_t pool7th:1; + uint64_t pool6th:1; + uint64_t pool5th:1; + uint64_t pool4th:1; + uint64_t pool3th:1; + uint64_t pool2th:1; + uint64_t pool1th:1; + uint64_t pool0th:1; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t pool0th:1; + uint64_t pool1th:1; + uint64_t pool2th:1; + uint64_t pool3th:1; + uint64_t pool4th:1; + uint64_t pool5th:1; + uint64_t pool6th:1; + uint64_t pool7th:1; + uint64_t free0:1; + uint64_t free1:1; + uint64_t free2:1; + uint64_t free3:1; + uint64_t free4:1; + uint64_t free5:1; + uint64_t free6:1; + uint64_t free7:1; + uint64_t reserved_44_63:20; +#endif + } cn63xx; + struct cvmx_fpa_int_enb_cn30xx cn63xxp1; + struct cvmx_fpa_int_enb_cn61xx cn66xx; + struct cvmx_fpa_int_enb_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_50_63:14; + uint64_t paddr_e:1; + uint64_t pool8th:1; + uint64_t q8_perr:1; + uint64_t q8_coff:1; + uint64_t q8_und:1; + uint64_t free8:1; + uint64_t free7:1; + uint64_t free6:1; + uint64_t free5:1; + uint64_t free4:1; + uint64_t free3:1; + uint64_t free2:1; + uint64_t free1:1; + uint64_t free0:1; + uint64_t pool7th:1; + uint64_t pool6th:1; + uint64_t pool5th:1; + uint64_t pool4th:1; + uint64_t pool3th:1; + uint64_t pool2th:1; + uint64_t pool1th:1; + uint64_t pool0th:1; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t pool0th:1; + uint64_t pool1th:1; + uint64_t pool2th:1; + uint64_t pool3th:1; + uint64_t pool4th:1; + uint64_t pool5th:1; + uint64_t pool6th:1; + uint64_t pool7th:1; + uint64_t free0:1; + uint64_t free1:1; + uint64_t free2:1; + uint64_t free3:1; + uint64_t free4:1; + uint64_t free5:1; + uint64_t free6:1; + uint64_t free7:1; + uint64_t free8:1; + uint64_t q8_und:1; + uint64_t q8_coff:1; + uint64_t q8_perr:1; + uint64_t pool8th:1; + uint64_t paddr_e:1; + uint64_t reserved_50_63:14; +#endif + } cn68xx; + struct cvmx_fpa_int_enb_cn68xx cn68xxp1; + struct cvmx_fpa_int_enb_cn61xx cnf71xx; }; union cvmx_fpa_int_sum { uint64_t u64; struct cvmx_fpa_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_50_63:14; + uint64_t paddr_e:1; + uint64_t pool8th:1; + uint64_t q8_perr:1; + uint64_t q8_coff:1; + uint64_t q8_und:1; + uint64_t free8:1; + uint64_t free7:1; + uint64_t free6:1; + uint64_t free5:1; + uint64_t free4:1; + uint64_t free3:1; + uint64_t free2:1; + uint64_t free1:1; + uint64_t free0:1; + uint64_t pool7th:1; + uint64_t pool6th:1; + uint64_t pool5th:1; + uint64_t pool4th:1; + uint64_t pool3th:1; + uint64_t pool2th:1; + uint64_t pool1th:1; + uint64_t pool0th:1; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t pool0th:1; + uint64_t pool1th:1; + uint64_t pool2th:1; + uint64_t pool3th:1; + uint64_t pool4th:1; + uint64_t pool5th:1; + uint64_t pool6th:1; + uint64_t pool7th:1; + uint64_t free0:1; + uint64_t free1:1; + uint64_t free2:1; + uint64_t free3:1; + uint64_t free4:1; + uint64_t free5:1; + uint64_t free6:1; + uint64_t free7:1; + uint64_t free8:1; + uint64_t q8_und:1; + uint64_t q8_coff:1; + uint64_t q8_perr:1; + uint64_t pool8th:1; + uint64_t paddr_e:1; + uint64_t reserved_50_63:14; +#endif + } s; + struct cvmx_fpa_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t q7_perr:1; uint64_t q7_coff:1; @@ -270,44 +952,380 @@ union cvmx_fpa_int_sum { uint64_t fed1_sbe:1; uint64_t fed0_dbe:1; uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t reserved_28_63:36; +#endif + } cn30xx; + struct cvmx_fpa_int_sum_cn30xx cn31xx; + struct cvmx_fpa_int_sum_cn30xx cn38xx; + struct cvmx_fpa_int_sum_cn30xx cn38xxp2; + struct cvmx_fpa_int_sum_cn30xx cn50xx; + struct cvmx_fpa_int_sum_cn30xx cn52xx; + struct cvmx_fpa_int_sum_cn30xx cn52xxp1; + struct cvmx_fpa_int_sum_cn30xx cn56xx; + struct cvmx_fpa_int_sum_cn30xx cn56xxp1; + struct cvmx_fpa_int_sum_cn30xx cn58xx; + struct cvmx_fpa_int_sum_cn30xx cn58xxp1; + struct cvmx_fpa_int_sum_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_50_63:14; + uint64_t paddr_e:1; + uint64_t reserved_44_48:5; + uint64_t free7:1; + uint64_t free6:1; + uint64_t free5:1; + uint64_t free4:1; + uint64_t free3:1; + uint64_t free2:1; + uint64_t free1:1; + uint64_t free0:1; + uint64_t pool7th:1; + uint64_t pool6th:1; + uint64_t pool5th:1; + uint64_t pool4th:1; + uint64_t pool3th:1; + uint64_t pool2th:1; + uint64_t pool1th:1; + uint64_t pool0th:1; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t pool0th:1; + uint64_t pool1th:1; + uint64_t pool2th:1; + uint64_t pool3th:1; + uint64_t pool4th:1; + uint64_t pool5th:1; + uint64_t pool6th:1; + uint64_t pool7th:1; + uint64_t free0:1; + uint64_t free1:1; + uint64_t free2:1; + uint64_t free3:1; + uint64_t free4:1; + uint64_t free5:1; + uint64_t free6:1; + uint64_t free7:1; + uint64_t reserved_44_48:5; + uint64_t paddr_e:1; + uint64_t reserved_50_63:14; +#endif + } cn61xx; + struct cvmx_fpa_int_sum_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_44_63:20; + uint64_t free7:1; + uint64_t free6:1; + uint64_t free5:1; + uint64_t free4:1; + uint64_t free3:1; + uint64_t free2:1; + uint64_t free1:1; + uint64_t free0:1; + uint64_t pool7th:1; + uint64_t pool6th:1; + uint64_t pool5th:1; + uint64_t pool4th:1; + uint64_t pool3th:1; + uint64_t pool2th:1; + uint64_t pool1th:1; + uint64_t pool0th:1; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t pool0th:1; + uint64_t pool1th:1; + uint64_t pool2th:1; + uint64_t pool3th:1; + uint64_t pool4th:1; + uint64_t pool5th:1; + uint64_t pool6th:1; + uint64_t pool7th:1; + uint64_t free0:1; + uint64_t free1:1; + uint64_t free2:1; + uint64_t free3:1; + uint64_t free4:1; + uint64_t free5:1; + uint64_t free6:1; + uint64_t free7:1; + uint64_t reserved_44_63:20; +#endif + } cn63xx; + struct cvmx_fpa_int_sum_cn30xx cn63xxp1; + struct cvmx_fpa_int_sum_cn61xx cn66xx; + struct cvmx_fpa_int_sum_s cn68xx; + struct cvmx_fpa_int_sum_s cn68xxp1; + struct cvmx_fpa_int_sum_cn61xx cnf71xx; +}; + +union cvmx_fpa_packet_threshold { + uint64_t u64; + struct cvmx_fpa_packet_threshold_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t thresh:32; +#else + uint64_t thresh:32; + uint64_t reserved_32_63:32; +#endif } s; - struct cvmx_fpa_int_sum_s cn30xx; - struct cvmx_fpa_int_sum_s cn31xx; - struct cvmx_fpa_int_sum_s cn38xx; - struct cvmx_fpa_int_sum_s cn38xxp2; - struct cvmx_fpa_int_sum_s cn50xx; - struct cvmx_fpa_int_sum_s cn52xx; - struct cvmx_fpa_int_sum_s cn52xxp1; - struct cvmx_fpa_int_sum_s cn56xx; - struct cvmx_fpa_int_sum_s cn56xxp1; - struct cvmx_fpa_int_sum_s cn58xx; - struct cvmx_fpa_int_sum_s cn58xxp1; + struct cvmx_fpa_packet_threshold_s cn61xx; + struct cvmx_fpa_packet_threshold_s cn63xx; + struct cvmx_fpa_packet_threshold_s cn66xx; + struct cvmx_fpa_packet_threshold_s cn68xx; + struct cvmx_fpa_packet_threshold_s cn68xxp1; + struct cvmx_fpa_packet_threshold_s cnf71xx; +}; + +union cvmx_fpa_poolx_end_addr { + uint64_t u64; + struct cvmx_fpa_poolx_end_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t addr:33; +#else + uint64_t addr:33; + uint64_t reserved_33_63:31; +#endif + } s; + struct cvmx_fpa_poolx_end_addr_s cn61xx; + struct cvmx_fpa_poolx_end_addr_s cn66xx; + struct cvmx_fpa_poolx_end_addr_s cn68xx; + struct cvmx_fpa_poolx_end_addr_s cn68xxp1; + struct cvmx_fpa_poolx_end_addr_s cnf71xx; +}; + +union cvmx_fpa_poolx_start_addr { + uint64_t u64; + struct cvmx_fpa_poolx_start_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t addr:33; +#else + uint64_t addr:33; + uint64_t reserved_33_63:31; +#endif + } s; + struct cvmx_fpa_poolx_start_addr_s cn61xx; + struct cvmx_fpa_poolx_start_addr_s cn66xx; + struct cvmx_fpa_poolx_start_addr_s cn68xx; + struct cvmx_fpa_poolx_start_addr_s cn68xxp1; + struct cvmx_fpa_poolx_start_addr_s cnf71xx; +}; + +union cvmx_fpa_poolx_threshold { + uint64_t u64; + struct cvmx_fpa_poolx_threshold_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t thresh:32; +#else + uint64_t thresh:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_fpa_poolx_threshold_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t thresh:29; +#else + uint64_t thresh:29; + uint64_t reserved_29_63:35; +#endif + } cn61xx; + struct cvmx_fpa_poolx_threshold_cn61xx cn63xx; + struct cvmx_fpa_poolx_threshold_cn61xx cn66xx; + struct cvmx_fpa_poolx_threshold_s cn68xx; + struct cvmx_fpa_poolx_threshold_s cn68xxp1; + struct cvmx_fpa_poolx_threshold_cn61xx cnf71xx; }; union cvmx_fpa_quex_available { uint64_t u64; struct cvmx_fpa_quex_available_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t que_siz:32; +#else + uint64_t que_siz:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_fpa_quex_available_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t que_siz:29; - } s; - struct cvmx_fpa_quex_available_s cn30xx; - struct cvmx_fpa_quex_available_s cn31xx; - struct cvmx_fpa_quex_available_s cn38xx; - struct cvmx_fpa_quex_available_s cn38xxp2; - struct cvmx_fpa_quex_available_s cn50xx; - struct cvmx_fpa_quex_available_s cn52xx; - struct cvmx_fpa_quex_available_s cn52xxp1; - struct cvmx_fpa_quex_available_s cn56xx; - struct cvmx_fpa_quex_available_s cn56xxp1; - struct cvmx_fpa_quex_available_s cn58xx; - struct cvmx_fpa_quex_available_s cn58xxp1; +#else + uint64_t que_siz:29; + uint64_t reserved_29_63:35; +#endif + } cn30xx; + struct cvmx_fpa_quex_available_cn30xx cn31xx; + struct cvmx_fpa_quex_available_cn30xx cn38xx; + struct cvmx_fpa_quex_available_cn30xx cn38xxp2; + struct cvmx_fpa_quex_available_cn30xx cn50xx; + struct cvmx_fpa_quex_available_cn30xx cn52xx; + struct cvmx_fpa_quex_available_cn30xx cn52xxp1; + struct cvmx_fpa_quex_available_cn30xx cn56xx; + struct cvmx_fpa_quex_available_cn30xx cn56xxp1; + struct cvmx_fpa_quex_available_cn30xx cn58xx; + struct cvmx_fpa_quex_available_cn30xx cn58xxp1; + struct cvmx_fpa_quex_available_cn30xx cn61xx; + struct cvmx_fpa_quex_available_cn30xx cn63xx; + struct cvmx_fpa_quex_available_cn30xx cn63xxp1; + struct cvmx_fpa_quex_available_cn30xx cn66xx; + struct cvmx_fpa_quex_available_s cn68xx; + struct cvmx_fpa_quex_available_s cn68xxp1; + struct cvmx_fpa_quex_available_cn30xx cnf71xx; }; union cvmx_fpa_quex_page_index { uint64_t u64; struct cvmx_fpa_quex_page_index_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t pg_num:25; +#else + uint64_t pg_num:25; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_fpa_quex_page_index_s cn30xx; struct cvmx_fpa_quex_page_index_s cn31xx; @@ -320,14 +1338,42 @@ union cvmx_fpa_quex_page_index { struct cvmx_fpa_quex_page_index_s cn56xxp1; struct cvmx_fpa_quex_page_index_s cn58xx; struct cvmx_fpa_quex_page_index_s cn58xxp1; + struct cvmx_fpa_quex_page_index_s cn61xx; + struct cvmx_fpa_quex_page_index_s cn63xx; + struct cvmx_fpa_quex_page_index_s cn63xxp1; + struct cvmx_fpa_quex_page_index_s cn66xx; + struct cvmx_fpa_quex_page_index_s cn68xx; + struct cvmx_fpa_quex_page_index_s cn68xxp1; + struct cvmx_fpa_quex_page_index_s cnf71xx; +}; + +union cvmx_fpa_que8_page_index { + uint64_t u64; + struct cvmx_fpa_que8_page_index_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t pg_num:25; +#else + uint64_t pg_num:25; + uint64_t reserved_25_63:39; +#endif + } s; + struct cvmx_fpa_que8_page_index_s cn68xx; + struct cvmx_fpa_que8_page_index_s cn68xxp1; }; union cvmx_fpa_que_act { uint64_t u64; struct cvmx_fpa_que_act_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t act_que:3; uint64_t act_indx:26; +#else + uint64_t act_indx:26; + uint64_t act_que:3; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_fpa_que_act_s cn30xx; struct cvmx_fpa_que_act_s cn31xx; @@ -340,14 +1386,27 @@ union cvmx_fpa_que_act { struct cvmx_fpa_que_act_s cn56xxp1; struct cvmx_fpa_que_act_s cn58xx; struct cvmx_fpa_que_act_s cn58xxp1; + struct cvmx_fpa_que_act_s cn61xx; + struct cvmx_fpa_que_act_s cn63xx; + struct cvmx_fpa_que_act_s cn63xxp1; + struct cvmx_fpa_que_act_s cn66xx; + struct cvmx_fpa_que_act_s cn68xx; + struct cvmx_fpa_que_act_s cn68xxp1; + struct cvmx_fpa_que_act_s cnf71xx; }; union cvmx_fpa_que_exp { uint64_t u64; struct cvmx_fpa_que_exp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t exp_que:3; uint64_t exp_indx:26; +#else + uint64_t exp_indx:26; + uint64_t exp_que:3; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_fpa_que_exp_s cn30xx; struct cvmx_fpa_que_exp_s cn31xx; @@ -360,13 +1419,25 @@ union cvmx_fpa_que_exp { struct cvmx_fpa_que_exp_s cn56xxp1; struct cvmx_fpa_que_exp_s cn58xx; struct cvmx_fpa_que_exp_s cn58xxp1; + struct cvmx_fpa_que_exp_s cn61xx; + struct cvmx_fpa_que_exp_s cn63xx; + struct cvmx_fpa_que_exp_s cn63xxp1; + struct cvmx_fpa_que_exp_s cn66xx; + struct cvmx_fpa_que_exp_s cn68xx; + struct cvmx_fpa_que_exp_s cn68xxp1; + struct cvmx_fpa_que_exp_s cnf71xx; }; union cvmx_fpa_wart_ctl { uint64_t u64; struct cvmx_fpa_wart_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ctl:16; +#else + uint64_t ctl:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_fpa_wart_ctl_s cn30xx; struct cvmx_fpa_wart_ctl_s cn31xx; @@ -384,8 +1455,13 @@ union cvmx_fpa_wart_ctl { union cvmx_fpa_wart_status { uint64_t u64; struct cvmx_fpa_wart_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t status:32; +#else + uint64_t status:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_fpa_wart_status_s cn30xx; struct cvmx_fpa_wart_status_s cn31xx; @@ -400,4 +1476,23 @@ union cvmx_fpa_wart_status { struct cvmx_fpa_wart_status_s cn58xxp1; }; +union cvmx_fpa_wqe_threshold { + uint64_t u64; + struct cvmx_fpa_wqe_threshold_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t thresh:32; +#else + uint64_t thresh:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_fpa_wqe_threshold_s cn61xx; + struct cvmx_fpa_wqe_threshold_s cn63xx; + struct cvmx_fpa_wqe_threshold_s cn66xx; + struct cvmx_fpa_wqe_threshold_s cn68xx; + struct cvmx_fpa_wqe_threshold_s cn68xxp1; + struct cvmx_fpa_wqe_threshold_s cnf71xx; +}; + #endif diff --git a/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h index 946a43a73fd7..e347496a33c3 100644 --- a/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,208 +28,2052 @@ #ifndef __CVMX_GMXX_DEFS_H__ #define __CVMX_GMXX_DEFS_H__ -#define CVMX_GMXX_BAD_REG(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000518ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_BIST(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000400ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_CLK_EN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080007F0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_HG2_CONTROL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000550ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_INF_MODE(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080007F8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_NXA_ADR(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000510ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000580ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_PRTX_CFG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000010ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000180ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000188ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000190ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000198ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080001A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080001A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000108ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000100ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_DECISION(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000040ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000020ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000018ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000030ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000028ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_IFG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000058ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_INT_EN(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000008ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_INT_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000000ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_JABBER(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000038ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000068ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000060ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000050ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000088ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000098ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080000A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080000B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000080ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080000C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000090ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080000A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080000B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000048ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_BP_DROPX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000420ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_BP_OFFX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000460ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_BP_ONX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000440ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_HG2_STATUS(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000548ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_PASS_EN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080005F8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000600ull + (((offset) & 15) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_PRTS(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000410ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_PRT_INFO(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004E8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_TX_STATUS(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080007E8ull + (((block_id) & 0) * 0x8000000ull)) -#define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000538ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_XAUI_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000530ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_SMACX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000230ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_STAT_BP(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000520ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_APPEND(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000218ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_BURST(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000228ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080005A0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080005C0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_CLK(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000208ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000270ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000240ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000248ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000238ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000258ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000260ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000300ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_SLOT(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000220ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000250ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT0(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000280ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT1(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000288ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT2(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000290ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT3(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000298ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT4(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT5(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT6(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT7(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT8(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT9(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002C8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000268ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_THRESH(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000210ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_BP(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004D0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000780ull + (((offset) & 1) * 8) + (((block_id) & 0) * 0x0ull)) -#define CVMX_GMXX_TX_COL_ATTEMPT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000498ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_CORRUPT(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004D8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_HG2_REG1(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000558ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_HG2_REG2(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000560ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_IFG(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000488ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_INT_EN(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000508ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_INT_REG(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000500ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_JAM(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000490ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_LFSR(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004F8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_OVR_BP(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004C8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004A0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004A8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_PRTS(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000480ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_SPI_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004C0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_SPI_DRAIN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004E0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_SPI_MAX(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004B0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000680ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_SPI_THRESH(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004B8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_XAUI_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000528ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000540ull + (((block_id) & 1) * 0x8000000ull)) +static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_BPID_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8) +#define CVMX_GMXX_BPID_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000700ull) + ((block_id) & 7) * 0x1000000ull) +static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_EBP_DIS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000608ull) + ((block_id) & 7) * 0x1000000ull) +#define CVMX_GMXX_EBP_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((block_id) & 7) * 0x1000000ull) +static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_PIPE_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000760ull) + ((block_id) & 7) * 0x1000000ull) +static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +#define CVMX_GMXX_RXAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000740ull) + ((block_id) & 7) * 0x1000000ull) +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_ALL_EN(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) +#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) +static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) +static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x0ull) * 8; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x200000ull) * 8; + } + return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; +} + +static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x0ull) * 8; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x200000ull) * 8; + } + return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; +} + +static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x0ull) * 8; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x200000ull) * 8; + } + return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; +} + +static inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_RX_PASS_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800080005F8ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8) +static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_RX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800080007E8ull)) +static inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_SOFT_BIST(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TB_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) +static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +#define CVMX_GMXX_TXX_PIPE(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048) +static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8) +static inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_GMXX_TX_SPI_DRAIN(block_id) (CVMX_ADD_IO_SEG(0x00011800080004E0ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull) +static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull; +} union cvmx_gmxx_bad_reg { uint64_t u64; struct cvmx_gmxx_bad_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t inb_nxa:4; uint64_t statovr:1; @@ -238,8 +2082,19 @@ union cvmx_gmxx_bad_reg { uint64_t out_ovr:16; uint64_t ncb_ovr:1; uint64_t out_col:1; +#else + uint64_t out_col:1; + uint64_t ncb_ovr:1; + uint64_t out_ovr:16; + uint64_t reserved_18_21:4; + uint64_t loststat:4; + uint64_t statovr:1; + uint64_t inb_nxa:4; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_gmxx_bad_reg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t inb_nxa:4; uint64_t statovr:1; @@ -248,12 +2103,23 @@ union cvmx_gmxx_bad_reg { uint64_t reserved_5_21:17; uint64_t out_ovr:3; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t out_ovr:3; + uint64_t reserved_5_21:17; + uint64_t loststat:3; + uint64_t reserved_25_25:1; + uint64_t statovr:1; + uint64_t inb_nxa:4; + uint64_t reserved_31_63:33; +#endif } cn30xx; struct cvmx_gmxx_bad_reg_cn30xx cn31xx; struct cvmx_gmxx_bad_reg_s cn38xx; struct cvmx_gmxx_bad_reg_s cn38xxp2; struct cvmx_gmxx_bad_reg_cn30xx cn50xx; struct cvmx_gmxx_bad_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t inb_nxa:4; uint64_t statovr:1; @@ -261,95 +2127,274 @@ union cvmx_gmxx_bad_reg { uint64_t reserved_6_21:16; uint64_t out_ovr:4; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t out_ovr:4; + uint64_t reserved_6_21:16; + uint64_t loststat:4; + uint64_t statovr:1; + uint64_t inb_nxa:4; + uint64_t reserved_31_63:33; +#endif } cn52xx; struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1; struct cvmx_gmxx_bad_reg_cn52xx cn56xx; struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1; struct cvmx_gmxx_bad_reg_s cn58xx; struct cvmx_gmxx_bad_reg_s cn58xxp1; + struct cvmx_gmxx_bad_reg_cn52xx cn61xx; + struct cvmx_gmxx_bad_reg_cn52xx cn63xx; + struct cvmx_gmxx_bad_reg_cn52xx cn63xxp1; + struct cvmx_gmxx_bad_reg_cn52xx cn66xx; + struct cvmx_gmxx_bad_reg_cn52xx cn68xx; + struct cvmx_gmxx_bad_reg_cn52xx cn68xxp1; + struct cvmx_gmxx_bad_reg_cn52xx cnf71xx; }; union cvmx_gmxx_bist { uint64_t u64; struct cvmx_gmxx_bist_s { - uint64_t reserved_17_63:47; - uint64_t status:17; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t status:25; +#else + uint64_t status:25; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_gmxx_bist_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t status:10; +#else + uint64_t status:10; + uint64_t reserved_10_63:54; +#endif } cn30xx; struct cvmx_gmxx_bist_cn30xx cn31xx; struct cvmx_gmxx_bist_cn30xx cn38xx; struct cvmx_gmxx_bist_cn30xx cn38xxp2; struct cvmx_gmxx_bist_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t status:12; +#else + uint64_t status:12; + uint64_t reserved_12_63:52; +#endif } cn50xx; struct cvmx_gmxx_bist_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t status:16; +#else + uint64_t status:16; + uint64_t reserved_16_63:48; +#endif } cn52xx; struct cvmx_gmxx_bist_cn52xx cn52xxp1; struct cvmx_gmxx_bist_cn52xx cn56xx; struct cvmx_gmxx_bist_cn52xx cn56xxp1; - struct cvmx_gmxx_bist_s cn58xx; - struct cvmx_gmxx_bist_s cn58xxp1; + struct cvmx_gmxx_bist_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_17_63:47; + uint64_t status:17; +#else + uint64_t status:17; + uint64_t reserved_17_63:47; +#endif + } cn58xx; + struct cvmx_gmxx_bist_cn58xx cn58xxp1; + struct cvmx_gmxx_bist_s cn61xx; + struct cvmx_gmxx_bist_s cn63xx; + struct cvmx_gmxx_bist_s cn63xxp1; + struct cvmx_gmxx_bist_s cn66xx; + struct cvmx_gmxx_bist_s cn68xx; + struct cvmx_gmxx_bist_s cn68xxp1; + struct cvmx_gmxx_bist_s cnf71xx; +}; + +union cvmx_gmxx_bpid_mapx { + uint64_t u64; + struct cvmx_gmxx_bpid_mapx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_17_63:47; + uint64_t status:1; + uint64_t reserved_9_15:7; + uint64_t val:1; + uint64_t reserved_6_7:2; + uint64_t bpid:6; +#else + uint64_t bpid:6; + uint64_t reserved_6_7:2; + uint64_t val:1; + uint64_t reserved_9_15:7; + uint64_t status:1; + uint64_t reserved_17_63:47; +#endif + } s; + struct cvmx_gmxx_bpid_mapx_s cn68xx; + struct cvmx_gmxx_bpid_mapx_s cn68xxp1; +}; + +union cvmx_gmxx_bpid_msk { + uint64_t u64; + struct cvmx_gmxx_bpid_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t msk_or:16; + uint64_t reserved_16_31:16; + uint64_t msk_and:16; +#else + uint64_t msk_and:16; + uint64_t reserved_16_31:16; + uint64_t msk_or:16; + uint64_t reserved_48_63:16; +#endif + } s; + struct cvmx_gmxx_bpid_msk_s cn68xx; + struct cvmx_gmxx_bpid_msk_s cn68xxp1; }; union cvmx_gmxx_clk_en { uint64_t u64; struct cvmx_gmxx_clk_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t clk_en:1; +#else + uint64_t clk_en:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_gmxx_clk_en_s cn52xx; struct cvmx_gmxx_clk_en_s cn52xxp1; struct cvmx_gmxx_clk_en_s cn56xx; struct cvmx_gmxx_clk_en_s cn56xxp1; + struct cvmx_gmxx_clk_en_s cn61xx; + struct cvmx_gmxx_clk_en_s cn63xx; + struct cvmx_gmxx_clk_en_s cn63xxp1; + struct cvmx_gmxx_clk_en_s cn66xx; + struct cvmx_gmxx_clk_en_s cn68xx; + struct cvmx_gmxx_clk_en_s cn68xxp1; + struct cvmx_gmxx_clk_en_s cnf71xx; +}; + +union cvmx_gmxx_ebp_dis { + uint64_t u64; + struct cvmx_gmxx_ebp_dis_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t dis:16; +#else + uint64_t dis:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_gmxx_ebp_dis_s cn68xx; + struct cvmx_gmxx_ebp_dis_s cn68xxp1; +}; + +union cvmx_gmxx_ebp_msk { + uint64_t u64; + struct cvmx_gmxx_ebp_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t msk:16; +#else + uint64_t msk:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_gmxx_ebp_msk_s cn68xx; + struct cvmx_gmxx_ebp_msk_s cn68xxp1; }; union cvmx_gmxx_hg2_control { uint64_t u64; struct cvmx_gmxx_hg2_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t hg2tx_en:1; uint64_t hg2rx_en:1; uint64_t phys_en:1; uint64_t logl_en:16; +#else + uint64_t logl_en:16; + uint64_t phys_en:1; + uint64_t hg2rx_en:1; + uint64_t hg2tx_en:1; + uint64_t reserved_19_63:45; +#endif } s; struct cvmx_gmxx_hg2_control_s cn52xx; struct cvmx_gmxx_hg2_control_s cn52xxp1; struct cvmx_gmxx_hg2_control_s cn56xx; + struct cvmx_gmxx_hg2_control_s cn61xx; + struct cvmx_gmxx_hg2_control_s cn63xx; + struct cvmx_gmxx_hg2_control_s cn63xxp1; + struct cvmx_gmxx_hg2_control_s cn66xx; + struct cvmx_gmxx_hg2_control_s cn68xx; + struct cvmx_gmxx_hg2_control_s cn68xxp1; + struct cvmx_gmxx_hg2_control_s cnf71xx; }; union cvmx_gmxx_inf_mode { uint64_t u64; struct cvmx_gmxx_inf_mode_s { - uint64_t reserved_10_63:54; - uint64_t speed:2; - uint64_t reserved_6_7:2; - uint64_t mode:2; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t rate:4; + uint64_t reserved_12_15:4; + uint64_t speed:4; + uint64_t reserved_7_7:1; + uint64_t mode:3; uint64_t reserved_3_3:1; uint64_t p0mii:1; uint64_t en:1; uint64_t type:1; +#else + uint64_t type:1; + uint64_t en:1; + uint64_t p0mii:1; + uint64_t reserved_3_3:1; + uint64_t mode:3; + uint64_t reserved_7_7:1; + uint64_t speed:4; + uint64_t reserved_12_15:4; + uint64_t rate:4; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_gmxx_inf_mode_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t p0mii:1; uint64_t en:1; uint64_t type:1; +#else + uint64_t type:1; + uint64_t en:1; + uint64_t p0mii:1; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_gmxx_inf_mode_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t en:1; uint64_t type:1; +#else + uint64_t type:1; + uint64_t en:1; + uint64_t reserved_2_63:62; +#endif } cn31xx; struct cvmx_gmxx_inf_mode_cn31xx cn38xx; struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2; struct cvmx_gmxx_inf_mode_cn30xx cn50xx; struct cvmx_gmxx_inf_mode_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t speed:2; uint64_t reserved_6_7:2; @@ -357,36 +2402,158 @@ union cvmx_gmxx_inf_mode { uint64_t reserved_2_3:2; uint64_t en:1; uint64_t type:1; +#else + uint64_t type:1; + uint64_t en:1; + uint64_t reserved_2_3:2; + uint64_t mode:2; + uint64_t reserved_6_7:2; + uint64_t speed:2; + uint64_t reserved_10_63:54; +#endif } cn52xx; struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1; struct cvmx_gmxx_inf_mode_cn52xx cn56xx; struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1; struct cvmx_gmxx_inf_mode_cn31xx cn58xx; struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1; + struct cvmx_gmxx_inf_mode_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t speed:4; + uint64_t reserved_5_7:3; + uint64_t mode:1; + uint64_t reserved_2_3:2; + uint64_t en:1; + uint64_t type:1; +#else + uint64_t type:1; + uint64_t en:1; + uint64_t reserved_2_3:2; + uint64_t mode:1; + uint64_t reserved_5_7:3; + uint64_t speed:4; + uint64_t reserved_12_63:52; +#endif + } cn61xx; + struct cvmx_gmxx_inf_mode_cn61xx cn63xx; + struct cvmx_gmxx_inf_mode_cn61xx cn63xxp1; + struct cvmx_gmxx_inf_mode_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t rate:4; + uint64_t reserved_12_15:4; + uint64_t speed:4; + uint64_t reserved_5_7:3; + uint64_t mode:1; + uint64_t reserved_2_3:2; + uint64_t en:1; + uint64_t type:1; +#else + uint64_t type:1; + uint64_t en:1; + uint64_t reserved_2_3:2; + uint64_t mode:1; + uint64_t reserved_5_7:3; + uint64_t speed:4; + uint64_t reserved_12_15:4; + uint64_t rate:4; + uint64_t reserved_20_63:44; +#endif + } cn66xx; + struct cvmx_gmxx_inf_mode_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t speed:4; + uint64_t reserved_7_7:1; + uint64_t mode:3; + uint64_t reserved_2_3:2; + uint64_t en:1; + uint64_t type:1; +#else + uint64_t type:1; + uint64_t en:1; + uint64_t reserved_2_3:2; + uint64_t mode:3; + uint64_t reserved_7_7:1; + uint64_t speed:4; + uint64_t reserved_12_63:52; +#endif + } cn68xx; + struct cvmx_gmxx_inf_mode_cn68xx cn68xxp1; + struct cvmx_gmxx_inf_mode_cn61xx cnf71xx; }; union cvmx_gmxx_nxa_adr { uint64_t u64; struct cvmx_gmxx_nxa_adr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_23_63:41; + uint64_t pipe:7; + uint64_t reserved_6_15:10; + uint64_t prt:6; +#else + uint64_t prt:6; + uint64_t reserved_6_15:10; + uint64_t pipe:7; + uint64_t reserved_23_63:41; +#endif + } s; + struct cvmx_gmxx_nxa_adr_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t prt:6; +#else + uint64_t prt:6; + uint64_t reserved_6_63:58; +#endif + } cn30xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn31xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn38xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn38xxp2; + struct cvmx_gmxx_nxa_adr_cn30xx cn50xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn52xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn52xxp1; + struct cvmx_gmxx_nxa_adr_cn30xx cn56xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn56xxp1; + struct cvmx_gmxx_nxa_adr_cn30xx cn58xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn58xxp1; + struct cvmx_gmxx_nxa_adr_cn30xx cn61xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn63xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn63xxp1; + struct cvmx_gmxx_nxa_adr_cn30xx cn66xx; + struct cvmx_gmxx_nxa_adr_s cn68xx; + struct cvmx_gmxx_nxa_adr_s cn68xxp1; + struct cvmx_gmxx_nxa_adr_cn30xx cnf71xx; +}; + +union cvmx_gmxx_pipe_status { + uint64_t u64; + struct cvmx_gmxx_pipe_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t ovr:4; + uint64_t reserved_12_15:4; + uint64_t bp:4; + uint64_t reserved_4_7:4; + uint64_t stop:4; +#else + uint64_t stop:4; + uint64_t reserved_4_7:4; + uint64_t bp:4; + uint64_t reserved_12_15:4; + uint64_t ovr:4; + uint64_t reserved_20_63:44; +#endif } s; - struct cvmx_gmxx_nxa_adr_s cn30xx; - struct cvmx_gmxx_nxa_adr_s cn31xx; - struct cvmx_gmxx_nxa_adr_s cn38xx; - struct cvmx_gmxx_nxa_adr_s cn38xxp2; - struct cvmx_gmxx_nxa_adr_s cn50xx; - struct cvmx_gmxx_nxa_adr_s cn52xx; - struct cvmx_gmxx_nxa_adr_s cn52xxp1; - struct cvmx_gmxx_nxa_adr_s cn56xx; - struct cvmx_gmxx_nxa_adr_s cn56xxp1; - struct cvmx_gmxx_nxa_adr_s cn58xx; - struct cvmx_gmxx_nxa_adr_s cn58xxp1; + struct cvmx_gmxx_pipe_status_s cn68xx; + struct cvmx_gmxx_pipe_status_s cn68xxp1; }; union cvmx_gmxx_prtx_cbfc_ctl { uint64_t u64; struct cvmx_gmxx_prtx_cbfc_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t phys_en:16; uint64_t logl_en:16; uint64_t phys_bp:16; @@ -395,15 +2562,35 @@ union cvmx_gmxx_prtx_cbfc_ctl { uint64_t drp_en:1; uint64_t tx_en:1; uint64_t rx_en:1; +#else + uint64_t rx_en:1; + uint64_t tx_en:1; + uint64_t drp_en:1; + uint64_t bck_en:1; + uint64_t reserved_4_15:12; + uint64_t phys_bp:16; + uint64_t logl_en:16; + uint64_t phys_en:16; +#endif } s; struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx; struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn61xx; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xx; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xxp1; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn66xx; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xx; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xxp1; + struct cvmx_gmxx_prtx_cbfc_ctl_s cnf71xx; }; union cvmx_gmxx_prtx_cfg { uint64_t u64; struct cvmx_gmxx_prtx_cfg_s { - uint64_t reserved_14_63:50; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_22_63:42; + uint64_t pknd:6; + uint64_t reserved_14_15:2; uint64_t tx_idle:1; uint64_t rx_idle:1; uint64_t reserved_9_11:3; @@ -413,30 +2600,87 @@ union cvmx_gmxx_prtx_cfg { uint64_t duplex:1; uint64_t speed:1; uint64_t en:1; +#else + uint64_t en:1; + uint64_t speed:1; + uint64_t duplex:1; + uint64_t slottime:1; + uint64_t reserved_4_7:4; + uint64_t speed_msb:1; + uint64_t reserved_9_11:3; + uint64_t rx_idle:1; + uint64_t tx_idle:1; + uint64_t reserved_14_15:2; + uint64_t pknd:6; + uint64_t reserved_22_63:42; +#endif } s; struct cvmx_gmxx_prtx_cfg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t slottime:1; uint64_t duplex:1; uint64_t speed:1; uint64_t en:1; +#else + uint64_t en:1; + uint64_t speed:1; + uint64_t duplex:1; + uint64_t slottime:1; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx; struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx; struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2; struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx; - struct cvmx_gmxx_prtx_cfg_s cn52xx; - struct cvmx_gmxx_prtx_cfg_s cn52xxp1; - struct cvmx_gmxx_prtx_cfg_s cn56xx; - struct cvmx_gmxx_prtx_cfg_s cn56xxp1; + struct cvmx_gmxx_prtx_cfg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_14_63:50; + uint64_t tx_idle:1; + uint64_t rx_idle:1; + uint64_t reserved_9_11:3; + uint64_t speed_msb:1; + uint64_t reserved_4_7:4; + uint64_t slottime:1; + uint64_t duplex:1; + uint64_t speed:1; + uint64_t en:1; +#else + uint64_t en:1; + uint64_t speed:1; + uint64_t duplex:1; + uint64_t slottime:1; + uint64_t reserved_4_7:4; + uint64_t speed_msb:1; + uint64_t reserved_9_11:3; + uint64_t rx_idle:1; + uint64_t tx_idle:1; + uint64_t reserved_14_63:50; +#endif + } cn52xx; + struct cvmx_gmxx_prtx_cfg_cn52xx cn52xxp1; + struct cvmx_gmxx_prtx_cfg_cn52xx cn56xx; + struct cvmx_gmxx_prtx_cfg_cn52xx cn56xxp1; struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx; struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1; + struct cvmx_gmxx_prtx_cfg_cn52xx cn61xx; + struct cvmx_gmxx_prtx_cfg_cn52xx cn63xx; + struct cvmx_gmxx_prtx_cfg_cn52xx cn63xxp1; + struct cvmx_gmxx_prtx_cfg_cn52xx cn66xx; + struct cvmx_gmxx_prtx_cfg_s cn68xx; + struct cvmx_gmxx_prtx_cfg_s cn68xxp1; + struct cvmx_gmxx_prtx_cfg_cn52xx cnf71xx; }; union cvmx_gmxx_rxx_adr_cam0 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t adr:64; +#else uint64_t adr:64; +#endif } s; struct cvmx_gmxx_rxx_adr_cam0_s cn30xx; struct cvmx_gmxx_rxx_adr_cam0_s cn31xx; @@ -449,12 +2693,23 @@ union cvmx_gmxx_rxx_adr_cam0 { struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam0_s cn58xx; struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_cam0_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn63xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_cam0_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_cam0_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam1 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; +#else + uint64_t adr:64; +#endif } s; struct cvmx_gmxx_rxx_adr_cam1_s cn30xx; struct cvmx_gmxx_rxx_adr_cam1_s cn31xx; @@ -467,12 +2722,23 @@ union cvmx_gmxx_rxx_adr_cam1 { struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam1_s cn58xx; struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_cam1_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn63xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_cam1_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_cam1_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam2 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t adr:64; +#else uint64_t adr:64; +#endif } s; struct cvmx_gmxx_rxx_adr_cam2_s cn30xx; struct cvmx_gmxx_rxx_adr_cam2_s cn31xx; @@ -485,12 +2751,23 @@ union cvmx_gmxx_rxx_adr_cam2 { struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam2_s cn58xx; struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_cam2_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn63xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_cam2_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_cam2_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam3 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t adr:64; +#else uint64_t adr:64; +#endif } s; struct cvmx_gmxx_rxx_adr_cam3_s cn30xx; struct cvmx_gmxx_rxx_adr_cam3_s cn31xx; @@ -503,12 +2780,23 @@ union cvmx_gmxx_rxx_adr_cam3 { struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam3_s cn58xx; struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_cam3_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn63xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_cam3_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_cam3_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam4 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam4_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; +#else + uint64_t adr:64; +#endif } s; struct cvmx_gmxx_rxx_adr_cam4_s cn30xx; struct cvmx_gmxx_rxx_adr_cam4_s cn31xx; @@ -521,12 +2809,23 @@ union cvmx_gmxx_rxx_adr_cam4 { struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam4_s cn58xx; struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_cam4_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn63xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_cam4_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_cam4_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam5 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam5_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t adr:64; +#else uint64_t adr:64; +#endif } s; struct cvmx_gmxx_rxx_adr_cam5_s cn30xx; struct cvmx_gmxx_rxx_adr_cam5_s cn31xx; @@ -539,13 +2838,42 @@ union cvmx_gmxx_rxx_adr_cam5 { struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam5_s cn58xx; struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_cam5_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn63xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_cam5_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_cam5_s cnf71xx; +}; + +union cvmx_gmxx_rxx_adr_cam_all_en { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam_all_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t en:32; +#else + uint64_t en:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_gmxx_rxx_adr_cam_all_en_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam_all_en_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam_all_en_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam_all_en_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam_en { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t en:8; +#else + uint64_t en:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx; struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx; @@ -558,15 +2886,29 @@ union cvmx_gmxx_rxx_adr_cam_en { struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx; struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_cam_en_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn63xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_cam_en_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_cam_en_s cnf71xx; }; union cvmx_gmxx_rxx_adr_ctl { uint64_t u64; struct cvmx_gmxx_rxx_adr_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t cam_mode:1; uint64_t mcst:2; uint64_t bcst:1; +#else + uint64_t bcst:1; + uint64_t mcst:2; + uint64_t cam_mode:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_gmxx_rxx_adr_ctl_s cn30xx; struct cvmx_gmxx_rxx_adr_ctl_s cn31xx; @@ -579,13 +2921,25 @@ union cvmx_gmxx_rxx_adr_ctl { struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1; struct cvmx_gmxx_rxx_adr_ctl_s cn58xx; struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_ctl_s cn61xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn63xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_ctl_s cn66xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn68xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_ctl_s cnf71xx; }; union cvmx_gmxx_rxx_decision { uint64_t u64; struct cvmx_gmxx_rxx_decision_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t cnt:5; +#else + uint64_t cnt:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_gmxx_rxx_decision_s cn30xx; struct cvmx_gmxx_rxx_decision_s cn31xx; @@ -598,11 +2952,19 @@ union cvmx_gmxx_rxx_decision { struct cvmx_gmxx_rxx_decision_s cn56xxp1; struct cvmx_gmxx_rxx_decision_s cn58xx; struct cvmx_gmxx_rxx_decision_s cn58xxp1; + struct cvmx_gmxx_rxx_decision_s cn61xx; + struct cvmx_gmxx_rxx_decision_s cn63xx; + struct cvmx_gmxx_rxx_decision_s cn63xxp1; + struct cvmx_gmxx_rxx_decision_s cn66xx; + struct cvmx_gmxx_rxx_decision_s cn68xx; + struct cvmx_gmxx_rxx_decision_s cn68xxp1; + struct cvmx_gmxx_rxx_decision_s cnf71xx; }; union cvmx_gmxx_rxx_frm_chk { uint64_t u64; struct cvmx_gmxx_rxx_frm_chk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t niberr:1; uint64_t skperr:1; @@ -614,12 +2976,26 @@ union cvmx_gmxx_rxx_frm_chk { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_gmxx_rxx_frm_chk_s cn30xx; struct cvmx_gmxx_rxx_frm_chk_s cn31xx; struct cvmx_gmxx_rxx_frm_chk_s cn38xx; struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2; struct cvmx_gmxx_rxx_frm_chk_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t niberr:1; uint64_t skperr:1; @@ -631,8 +3007,22 @@ union cvmx_gmxx_rxx_frm_chk { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t reserved_6_6:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t reserved_10_63:54; +#endif } cn50xx; struct cvmx_gmxx_rxx_frm_chk_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t skperr:1; uint64_t rcverr:1; @@ -642,18 +3032,61 @@ union cvmx_gmxx_rxx_frm_chk { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_63:55; +#endif } cn52xx; struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1; struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx; struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1; struct cvmx_gmxx_rxx_frm_chk_s cn58xx; struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1; + struct cvmx_gmxx_rxx_frm_chk_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_63:55; +#endif + } cn61xx; + struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xx; + struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xxp1; + struct cvmx_gmxx_rxx_frm_chk_cn61xx cn66xx; + struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xx; + struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xxp1; + struct cvmx_gmxx_rxx_frm_chk_cn61xx cnf71xx; }; union cvmx_gmxx_rxx_frm_ctl { uint64_t u64; struct cvmx_gmxx_rxx_frm_ctl_s { - uint64_t reserved_11_63:53; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_13_63:51; + uint64_t ptp_mode:1; + uint64_t reserved_11_11:1; uint64_t null_dis:1; uint64_t pre_align:1; uint64_t pad_len:1; @@ -665,8 +3098,25 @@ union cvmx_gmxx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t pre_align:1; + uint64_t null_dis:1; + uint64_t reserved_11_11:1; + uint64_t ptp_mode:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_gmxx_rxx_frm_ctl_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t pad_len:1; uint64_t vlan_len:1; @@ -677,8 +3127,21 @@ union cvmx_gmxx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t reserved_9_63:55; +#endif } cn30xx; struct cvmx_gmxx_rxx_frm_ctl_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t vlan_len:1; uint64_t pre_free:1; @@ -688,10 +3151,22 @@ union cvmx_gmxx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t vlan_len:1; + uint64_t reserved_8_63:56; +#endif } cn31xx; struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx; struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2; struct cvmx_gmxx_rxx_frm_ctl_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t null_dis:1; uint64_t pre_align:1; @@ -703,11 +3178,25 @@ union cvmx_gmxx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t reserved_7_8:2; + uint64_t pre_align:1; + uint64_t null_dis:1; + uint64_t reserved_11_63:53; +#endif } cn50xx; struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx; struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1; struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx; struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pre_align:1; uint64_t reserved_7_8:2; @@ -718,16 +3207,98 @@ union cvmx_gmxx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t reserved_7_8:2; + uint64_t pre_align:1; + uint64_t reserved_10_63:54; +#endif } cn56xxp1; - struct cvmx_gmxx_rxx_frm_ctl_s cn58xx; + struct cvmx_gmxx_rxx_frm_ctl_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t null_dis:1; + uint64_t pre_align:1; + uint64_t pad_len:1; + uint64_t vlan_len:1; + uint64_t pre_free:1; + uint64_t ctl_smac:1; + uint64_t ctl_mcst:1; + uint64_t ctl_bck:1; + uint64_t ctl_drp:1; + uint64_t pre_strp:1; + uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t pre_align:1; + uint64_t null_dis:1; + uint64_t reserved_11_63:53; +#endif + } cn58xx; struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1; + struct cvmx_gmxx_rxx_frm_ctl_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_13_63:51; + uint64_t ptp_mode:1; + uint64_t reserved_11_11:1; + uint64_t null_dis:1; + uint64_t pre_align:1; + uint64_t reserved_7_8:2; + uint64_t pre_free:1; + uint64_t ctl_smac:1; + uint64_t ctl_mcst:1; + uint64_t ctl_bck:1; + uint64_t ctl_drp:1; + uint64_t pre_strp:1; + uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t reserved_7_8:2; + uint64_t pre_align:1; + uint64_t null_dis:1; + uint64_t reserved_11_11:1; + uint64_t ptp_mode:1; + uint64_t reserved_13_63:51; +#endif + } cn61xx; + struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xx; + struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xxp1; + struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn66xx; + struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xx; + struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xxp1; + struct cvmx_gmxx_rxx_frm_ctl_cn61xx cnf71xx; }; union cvmx_gmxx_rxx_frm_max { uint64_t u64; struct cvmx_gmxx_rxx_frm_max_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t len:16; +#else + uint64_t len:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_rxx_frm_max_s cn30xx; struct cvmx_gmxx_rxx_frm_max_s cn31xx; @@ -740,8 +3311,13 @@ union cvmx_gmxx_rxx_frm_max { union cvmx_gmxx_rxx_frm_min { uint64_t u64; struct cvmx_gmxx_rxx_frm_min_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t len:16; +#else + uint64_t len:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_rxx_frm_min_s cn30xx; struct cvmx_gmxx_rxx_frm_min_s cn31xx; @@ -754,8 +3330,13 @@ union cvmx_gmxx_rxx_frm_min { union cvmx_gmxx_rxx_ifg { uint64_t u64; struct cvmx_gmxx_rxx_ifg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t ifg:4; +#else + uint64_t ifg:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_gmxx_rxx_ifg_s cn30xx; struct cvmx_gmxx_rxx_ifg_s cn31xx; @@ -768,11 +3349,19 @@ union cvmx_gmxx_rxx_ifg { struct cvmx_gmxx_rxx_ifg_s cn56xxp1; struct cvmx_gmxx_rxx_ifg_s cn58xx; struct cvmx_gmxx_rxx_ifg_s cn58xxp1; + struct cvmx_gmxx_rxx_ifg_s cn61xx; + struct cvmx_gmxx_rxx_ifg_s cn63xx; + struct cvmx_gmxx_rxx_ifg_s cn63xxp1; + struct cvmx_gmxx_rxx_ifg_s cn66xx; + struct cvmx_gmxx_rxx_ifg_s cn68xx; + struct cvmx_gmxx_rxx_ifg_s cn68xxp1; + struct cvmx_gmxx_rxx_ifg_s cnf71xx; }; union cvmx_gmxx_rxx_int_en { uint64_t u64; struct cvmx_gmxx_rxx_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t hg2cc:1; uint64_t hg2fld:1; @@ -803,8 +3392,41 @@ union cvmx_gmxx_rxx_int_en { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t hg2fld:1; + uint64_t hg2cc:1; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_gmxx_rxx_int_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t phy_dupx:1; uint64_t phy_spd:1; @@ -825,11 +3447,34 @@ union cvmx_gmxx_rxx_int_en { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t reserved_19_63:45; +#endif } cn30xx; struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx; struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx; struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2; struct cvmx_gmxx_rxx_int_en_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -851,8 +3496,32 @@ union cvmx_gmxx_rxx_int_en { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t reserved_6_6:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } cn50xx; struct cvmx_gmxx_rxx_int_en_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t hg2cc:1; uint64_t hg2fld:1; @@ -880,10 +3549,40 @@ union cvmx_gmxx_rxx_int_en { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t hg2fld:1; + uint64_t hg2cc:1; + uint64_t reserved_29_63:35; +#endif } cn52xx; struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1; struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx; struct cvmx_gmxx_rxx_int_en_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t undat:1; uint64_t uneop:1; @@ -909,8 +3608,36 @@ union cvmx_gmxx_rxx_int_en { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t reserved_27_63:37; +#endif } cn56xxp1; struct cvmx_gmxx_rxx_int_en_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -932,13 +3659,102 @@ union cvmx_gmxx_rxx_int_en { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } cn58xx; struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1; + struct cvmx_gmxx_rxx_int_en_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t hg2cc:1; + uint64_t hg2fld:1; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t reserved_16_18:3; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t reserved_9_9:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t hg2fld:1; + uint64_t hg2cc:1; + uint64_t reserved_29_63:35; +#endif + } cn61xx; + struct cvmx_gmxx_rxx_int_en_cn61xx cn63xx; + struct cvmx_gmxx_rxx_int_en_cn61xx cn63xxp1; + struct cvmx_gmxx_rxx_int_en_cn61xx cn66xx; + struct cvmx_gmxx_rxx_int_en_cn61xx cn68xx; + struct cvmx_gmxx_rxx_int_en_cn61xx cn68xxp1; + struct cvmx_gmxx_rxx_int_en_cn61xx cnf71xx; }; union cvmx_gmxx_rxx_int_reg { uint64_t u64; struct cvmx_gmxx_rxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t hg2cc:1; uint64_t hg2fld:1; @@ -969,8 +3785,41 @@ union cvmx_gmxx_rxx_int_reg { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t hg2fld:1; + uint64_t hg2cc:1; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_gmxx_rxx_int_reg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t phy_dupx:1; uint64_t phy_spd:1; @@ -991,11 +3840,34 @@ union cvmx_gmxx_rxx_int_reg { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t reserved_19_63:45; +#endif } cn30xx; struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx; struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx; struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2; struct cvmx_gmxx_rxx_int_reg_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -1017,8 +3889,32 @@ union cvmx_gmxx_rxx_int_reg { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t reserved_6_6:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } cn50xx; struct cvmx_gmxx_rxx_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t hg2cc:1; uint64_t hg2fld:1; @@ -1046,10 +3942,40 @@ union cvmx_gmxx_rxx_int_reg { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t hg2fld:1; + uint64_t hg2cc:1; + uint64_t reserved_29_63:35; +#endif } cn52xx; struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1; struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx; struct cvmx_gmxx_rxx_int_reg_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t undat:1; uint64_t uneop:1; @@ -1075,8 +4001,36 @@ union cvmx_gmxx_rxx_int_reg { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t reserved_27_63:37; +#endif } cn56xxp1; struct cvmx_gmxx_rxx_int_reg_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -1098,15 +4052,108 @@ union cvmx_gmxx_rxx_int_reg { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } cn58xx; struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1; + struct cvmx_gmxx_rxx_int_reg_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t hg2cc:1; + uint64_t hg2fld:1; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t reserved_16_18:3; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t reserved_9_9:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t hg2fld:1; + uint64_t hg2cc:1; + uint64_t reserved_29_63:35; +#endif + } cn61xx; + struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xx; + struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xxp1; + struct cvmx_gmxx_rxx_int_reg_cn61xx cn66xx; + struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xx; + struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xxp1; + struct cvmx_gmxx_rxx_int_reg_cn61xx cnf71xx; }; union cvmx_gmxx_rxx_jabber { uint64_t u64; struct cvmx_gmxx_rxx_jabber_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt:16; +#else + uint64_t cnt:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_rxx_jabber_s cn30xx; struct cvmx_gmxx_rxx_jabber_s cn31xx; @@ -1119,13 +4166,25 @@ union cvmx_gmxx_rxx_jabber { struct cvmx_gmxx_rxx_jabber_s cn56xxp1; struct cvmx_gmxx_rxx_jabber_s cn58xx; struct cvmx_gmxx_rxx_jabber_s cn58xxp1; + struct cvmx_gmxx_rxx_jabber_s cn61xx; + struct cvmx_gmxx_rxx_jabber_s cn63xx; + struct cvmx_gmxx_rxx_jabber_s cn63xxp1; + struct cvmx_gmxx_rxx_jabber_s cn66xx; + struct cvmx_gmxx_rxx_jabber_s cn68xx; + struct cvmx_gmxx_rxx_jabber_s cn68xxp1; + struct cvmx_gmxx_rxx_jabber_s cnf71xx; }; union cvmx_gmxx_rxx_pause_drop_time { uint64_t u64; struct cvmx_gmxx_rxx_pause_drop_time_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t status:16; +#else + uint64_t status:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx; struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx; @@ -1134,15 +4193,29 @@ union cvmx_gmxx_rxx_pause_drop_time { struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1; struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx; struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1; + struct cvmx_gmxx_rxx_pause_drop_time_s cn61xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn63xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn63xxp1; + struct cvmx_gmxx_rxx_pause_drop_time_s cn66xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn68xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn68xxp1; + struct cvmx_gmxx_rxx_pause_drop_time_s cnf71xx; }; union cvmx_gmxx_rxx_rx_inbnd { uint64_t u64; struct cvmx_gmxx_rxx_rx_inbnd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t duplex:1; uint64_t speed:2; uint64_t status:1; +#else + uint64_t status:1; + uint64_t speed:2; + uint64_t duplex:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx; struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx; @@ -1156,8 +4229,13 @@ union cvmx_gmxx_rxx_rx_inbnd { union cvmx_gmxx_rxx_stats_ctl { uint64_t u64; struct cvmx_gmxx_rxx_stats_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rd_clr:1; +#else + uint64_t rd_clr:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_gmxx_rxx_stats_ctl_s cn30xx; struct cvmx_gmxx_rxx_stats_ctl_s cn31xx; @@ -1170,13 +4248,25 @@ union cvmx_gmxx_rxx_stats_ctl { struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1; struct cvmx_gmxx_rxx_stats_ctl_s cn58xx; struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_ctl_s cn61xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn63xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_ctl_s cn66xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn68xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_ctl_s cnf71xx; }; union cvmx_gmxx_rxx_stats_octs { uint64_t u64; struct cvmx_gmxx_rxx_stats_octs_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_rxx_stats_octs_s cn30xx; struct cvmx_gmxx_rxx_stats_octs_s cn31xx; @@ -1189,13 +4279,25 @@ union cvmx_gmxx_rxx_stats_octs { struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1; struct cvmx_gmxx_rxx_stats_octs_s cn58xx; struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_octs_s cn61xx; + struct cvmx_gmxx_rxx_stats_octs_s cn63xx; + struct cvmx_gmxx_rxx_stats_octs_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_octs_s cn66xx; + struct cvmx_gmxx_rxx_stats_octs_s cn68xx; + struct cvmx_gmxx_rxx_stats_octs_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_octs_s cnf71xx; }; union cvmx_gmxx_rxx_stats_octs_ctl { uint64_t u64; struct cvmx_gmxx_rxx_stats_octs_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx; struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx; @@ -1208,13 +4310,25 @@ union cvmx_gmxx_rxx_stats_octs_ctl { struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1; struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx; struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn61xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn66xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cnf71xx; }; union cvmx_gmxx_rxx_stats_octs_dmac { uint64_t u64; struct cvmx_gmxx_rxx_stats_octs_dmac_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx; struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx; @@ -1227,13 +4341,25 @@ union cvmx_gmxx_rxx_stats_octs_dmac { struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1; struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx; struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn61xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn66xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cnf71xx; }; union cvmx_gmxx_rxx_stats_octs_drp { uint64_t u64; struct cvmx_gmxx_rxx_stats_octs_drp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx; struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx; @@ -1246,13 +4372,25 @@ union cvmx_gmxx_rxx_stats_octs_drp { struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1; struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx; struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn61xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn66xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_octs_drp_s cnf71xx; }; union cvmx_gmxx_rxx_stats_pkts { uint64_t u64; struct cvmx_gmxx_rxx_stats_pkts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_rxx_stats_pkts_s cn30xx; struct cvmx_gmxx_rxx_stats_pkts_s cn31xx; @@ -1265,13 +4403,25 @@ union cvmx_gmxx_rxx_stats_pkts { struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1; struct cvmx_gmxx_rxx_stats_pkts_s cn58xx; struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_pkts_s cn61xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn63xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_pkts_s cn66xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn68xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_pkts_s cnf71xx; }; union cvmx_gmxx_rxx_stats_pkts_bad { uint64_t u64; struct cvmx_gmxx_rxx_stats_pkts_bad_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx; struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx; @@ -1284,13 +4434,25 @@ union cvmx_gmxx_rxx_stats_pkts_bad { struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1; struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx; struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn61xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn66xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cnf71xx; }; union cvmx_gmxx_rxx_stats_pkts_ctl { uint64_t u64; struct cvmx_gmxx_rxx_stats_pkts_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx; struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx; @@ -1303,13 +4465,25 @@ union cvmx_gmxx_rxx_stats_pkts_ctl { struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1; struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx; struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn61xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn66xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cnf71xx; }; union cvmx_gmxx_rxx_stats_pkts_dmac { uint64_t u64; struct cvmx_gmxx_rxx_stats_pkts_dmac_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx; struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx; @@ -1322,13 +4496,25 @@ union cvmx_gmxx_rxx_stats_pkts_dmac { struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1; struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx; struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn61xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn66xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cnf71xx; }; union cvmx_gmxx_rxx_stats_pkts_drp { uint64_t u64; struct cvmx_gmxx_rxx_stats_pkts_drp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx; struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx; @@ -1341,15 +4527,29 @@ union cvmx_gmxx_rxx_stats_pkts_drp { struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1; struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx; struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn61xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn66xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cnf71xx; }; union cvmx_gmxx_rxx_udd_skp { uint64_t u64; struct cvmx_gmxx_rxx_udd_skp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t fcssel:1; uint64_t reserved_7_7:1; uint64_t len:7; +#else + uint64_t len:7; + uint64_t reserved_7_7:1; + uint64_t fcssel:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_gmxx_rxx_udd_skp_s cn30xx; struct cvmx_gmxx_rxx_udd_skp_s cn31xx; @@ -1362,13 +4562,25 @@ union cvmx_gmxx_rxx_udd_skp { struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1; struct cvmx_gmxx_rxx_udd_skp_s cn58xx; struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1; + struct cvmx_gmxx_rxx_udd_skp_s cn61xx; + struct cvmx_gmxx_rxx_udd_skp_s cn63xx; + struct cvmx_gmxx_rxx_udd_skp_s cn63xxp1; + struct cvmx_gmxx_rxx_udd_skp_s cn66xx; + struct cvmx_gmxx_rxx_udd_skp_s cn68xx; + struct cvmx_gmxx_rxx_udd_skp_s cn68xxp1; + struct cvmx_gmxx_rxx_udd_skp_s cnf71xx; }; union cvmx_gmxx_rx_bp_dropx { uint64_t u64; struct cvmx_gmxx_rx_bp_dropx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mark:6; +#else + uint64_t mark:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_gmxx_rx_bp_dropx_s cn30xx; struct cvmx_gmxx_rx_bp_dropx_s cn31xx; @@ -1381,13 +4593,25 @@ union cvmx_gmxx_rx_bp_dropx { struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1; struct cvmx_gmxx_rx_bp_dropx_s cn58xx; struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1; + struct cvmx_gmxx_rx_bp_dropx_s cn61xx; + struct cvmx_gmxx_rx_bp_dropx_s cn63xx; + struct cvmx_gmxx_rx_bp_dropx_s cn63xxp1; + struct cvmx_gmxx_rx_bp_dropx_s cn66xx; + struct cvmx_gmxx_rx_bp_dropx_s cn68xx; + struct cvmx_gmxx_rx_bp_dropx_s cn68xxp1; + struct cvmx_gmxx_rx_bp_dropx_s cnf71xx; }; union cvmx_gmxx_rx_bp_offx { uint64_t u64; struct cvmx_gmxx_rx_bp_offx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mark:6; +#else + uint64_t mark:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_gmxx_rx_bp_offx_s cn30xx; struct cvmx_gmxx_rx_bp_offx_s cn31xx; @@ -1400,45 +4624,91 @@ union cvmx_gmxx_rx_bp_offx { struct cvmx_gmxx_rx_bp_offx_s cn56xxp1; struct cvmx_gmxx_rx_bp_offx_s cn58xx; struct cvmx_gmxx_rx_bp_offx_s cn58xxp1; + struct cvmx_gmxx_rx_bp_offx_s cn61xx; + struct cvmx_gmxx_rx_bp_offx_s cn63xx; + struct cvmx_gmxx_rx_bp_offx_s cn63xxp1; + struct cvmx_gmxx_rx_bp_offx_s cn66xx; + struct cvmx_gmxx_rx_bp_offx_s cn68xx; + struct cvmx_gmxx_rx_bp_offx_s cn68xxp1; + struct cvmx_gmxx_rx_bp_offx_s cnf71xx; }; union cvmx_gmxx_rx_bp_onx { uint64_t u64; struct cvmx_gmxx_rx_bp_onx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t mark:11; +#else + uint64_t mark:11; + uint64_t reserved_11_63:53; +#endif + } s; + struct cvmx_gmxx_rx_bp_onx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t mark:9; - } s; - struct cvmx_gmxx_rx_bp_onx_s cn30xx; - struct cvmx_gmxx_rx_bp_onx_s cn31xx; - struct cvmx_gmxx_rx_bp_onx_s cn38xx; - struct cvmx_gmxx_rx_bp_onx_s cn38xxp2; - struct cvmx_gmxx_rx_bp_onx_s cn50xx; - struct cvmx_gmxx_rx_bp_onx_s cn52xx; - struct cvmx_gmxx_rx_bp_onx_s cn52xxp1; - struct cvmx_gmxx_rx_bp_onx_s cn56xx; - struct cvmx_gmxx_rx_bp_onx_s cn56xxp1; - struct cvmx_gmxx_rx_bp_onx_s cn58xx; - struct cvmx_gmxx_rx_bp_onx_s cn58xxp1; +#else + uint64_t mark:9; + uint64_t reserved_9_63:55; +#endif + } cn30xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn31xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xxp2; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn50xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xxp1; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xxp1; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xxp1; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn61xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xxp1; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn66xx; + struct cvmx_gmxx_rx_bp_onx_s cn68xx; + struct cvmx_gmxx_rx_bp_onx_s cn68xxp1; + struct cvmx_gmxx_rx_bp_onx_cn30xx cnf71xx; }; union cvmx_gmxx_rx_hg2_status { uint64_t u64; struct cvmx_gmxx_rx_hg2_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t phtim2go:16; uint64_t xof:16; uint64_t lgtim2go:16; +#else + uint64_t lgtim2go:16; + uint64_t xof:16; + uint64_t phtim2go:16; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_rx_hg2_status_s cn52xx; struct cvmx_gmxx_rx_hg2_status_s cn52xxp1; struct cvmx_gmxx_rx_hg2_status_s cn56xx; + struct cvmx_gmxx_rx_hg2_status_s cn61xx; + struct cvmx_gmxx_rx_hg2_status_s cn63xx; + struct cvmx_gmxx_rx_hg2_status_s cn63xxp1; + struct cvmx_gmxx_rx_hg2_status_s cn66xx; + struct cvmx_gmxx_rx_hg2_status_s cn68xx; + struct cvmx_gmxx_rx_hg2_status_s cn68xxp1; + struct cvmx_gmxx_rx_hg2_status_s cnf71xx; }; union cvmx_gmxx_rx_pass_en { uint64_t u64; struct cvmx_gmxx_rx_pass_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t en:16; +#else + uint64_t en:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_rx_pass_en_s cn38xx; struct cvmx_gmxx_rx_pass_en_s cn38xxp2; @@ -1449,8 +4719,13 @@ union cvmx_gmxx_rx_pass_en { union cvmx_gmxx_rx_pass_mapx { uint64_t u64; struct cvmx_gmxx_rx_pass_mapx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t dprt:4; +#else + uint64_t dprt:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_gmxx_rx_pass_mapx_s cn38xx; struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2; @@ -1461,37 +4736,81 @@ union cvmx_gmxx_rx_pass_mapx { union cvmx_gmxx_rx_prt_info { uint64_t u64; struct cvmx_gmxx_rx_prt_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t drop:16; uint64_t commit:16; +#else + uint64_t commit:16; + uint64_t drop:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_rx_prt_info_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t drop:3; uint64_t reserved_3_15:13; uint64_t commit:3; +#else + uint64_t commit:3; + uint64_t reserved_3_15:13; + uint64_t drop:3; + uint64_t reserved_19_63:45; +#endif } cn30xx; struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx; struct cvmx_gmxx_rx_prt_info_s cn38xx; struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx; struct cvmx_gmxx_rx_prt_info_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t drop:4; uint64_t reserved_4_15:12; uint64_t commit:4; +#else + uint64_t commit:4; + uint64_t reserved_4_15:12; + uint64_t drop:4; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1; struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx; struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1; struct cvmx_gmxx_rx_prt_info_s cn58xx; struct cvmx_gmxx_rx_prt_info_s cn58xxp1; + struct cvmx_gmxx_rx_prt_info_cn52xx cn61xx; + struct cvmx_gmxx_rx_prt_info_cn52xx cn63xx; + struct cvmx_gmxx_rx_prt_info_cn52xx cn63xxp1; + struct cvmx_gmxx_rx_prt_info_cn52xx cn66xx; + struct cvmx_gmxx_rx_prt_info_cn52xx cn68xx; + struct cvmx_gmxx_rx_prt_info_cn52xx cn68xxp1; + struct cvmx_gmxx_rx_prt_info_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t drop:2; + uint64_t reserved_2_15:14; + uint64_t commit:2; +#else + uint64_t commit:2; + uint64_t reserved_2_15:14; + uint64_t drop:2; + uint64_t reserved_18_63:46; +#endif + } cnf71xx; }; union cvmx_gmxx_rx_prts { uint64_t u64; struct cvmx_gmxx_rx_prts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t prts:3; +#else + uint64_t prts:3; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_gmxx_rx_prts_s cn30xx; struct cvmx_gmxx_rx_prts_s cn31xx; @@ -1504,15 +4823,29 @@ union cvmx_gmxx_rx_prts { struct cvmx_gmxx_rx_prts_s cn56xxp1; struct cvmx_gmxx_rx_prts_s cn58xx; struct cvmx_gmxx_rx_prts_s cn58xxp1; + struct cvmx_gmxx_rx_prts_s cn61xx; + struct cvmx_gmxx_rx_prts_s cn63xx; + struct cvmx_gmxx_rx_prts_s cn63xxp1; + struct cvmx_gmxx_rx_prts_s cn66xx; + struct cvmx_gmxx_rx_prts_s cn68xx; + struct cvmx_gmxx_rx_prts_s cn68xxp1; + struct cvmx_gmxx_rx_prts_s cnf71xx; }; union cvmx_gmxx_rx_tx_status { uint64_t u64; struct cvmx_gmxx_rx_tx_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t tx:3; uint64_t reserved_3_3:1; uint64_t rx:3; +#else + uint64_t rx:3; + uint64_t reserved_3_3:1; + uint64_t tx:3; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_gmxx_rx_tx_status_s cn30xx; struct cvmx_gmxx_rx_tx_status_s cn31xx; @@ -1522,35 +4855,82 @@ union cvmx_gmxx_rx_tx_status { union cvmx_gmxx_rx_xaui_bad_col { uint64_t u64; struct cvmx_gmxx_rx_xaui_bad_col_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t val:1; uint64_t state:3; uint64_t lane_rxc:4; uint64_t lane_rxd:32; +#else + uint64_t lane_rxd:32; + uint64_t lane_rxc:4; + uint64_t state:3; + uint64_t val:1; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx; struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1; struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx; struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1; + struct cvmx_gmxx_rx_xaui_bad_col_s cn61xx; + struct cvmx_gmxx_rx_xaui_bad_col_s cn63xx; + struct cvmx_gmxx_rx_xaui_bad_col_s cn63xxp1; + struct cvmx_gmxx_rx_xaui_bad_col_s cn66xx; + struct cvmx_gmxx_rx_xaui_bad_col_s cn68xx; + struct cvmx_gmxx_rx_xaui_bad_col_s cn68xxp1; + struct cvmx_gmxx_rx_xaui_bad_col_s cnf71xx; }; union cvmx_gmxx_rx_xaui_ctl { uint64_t u64; struct cvmx_gmxx_rx_xaui_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t status:2; +#else + uint64_t status:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_gmxx_rx_xaui_ctl_s cn52xx; struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1; struct cvmx_gmxx_rx_xaui_ctl_s cn56xx; struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1; + struct cvmx_gmxx_rx_xaui_ctl_s cn61xx; + struct cvmx_gmxx_rx_xaui_ctl_s cn63xx; + struct cvmx_gmxx_rx_xaui_ctl_s cn63xxp1; + struct cvmx_gmxx_rx_xaui_ctl_s cn66xx; + struct cvmx_gmxx_rx_xaui_ctl_s cn68xx; + struct cvmx_gmxx_rx_xaui_ctl_s cn68xxp1; + struct cvmx_gmxx_rx_xaui_ctl_s cnf71xx; +}; + +union cvmx_gmxx_rxaui_ctl { + uint64_t u64; + struct cvmx_gmxx_rxaui_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t disparity:1; +#else + uint64_t disparity:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_gmxx_rxaui_ctl_s cn68xx; + struct cvmx_gmxx_rxaui_ctl_s cn68xxp1; }; union cvmx_gmxx_smacx { uint64_t u64; struct cvmx_gmxx_smacx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t smac:48; +#else + uint64_t smac:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_smacx_s cn30xx; struct cvmx_gmxx_smacx_s cn31xx; @@ -1563,14 +4943,47 @@ union cvmx_gmxx_smacx { struct cvmx_gmxx_smacx_s cn56xxp1; struct cvmx_gmxx_smacx_s cn58xx; struct cvmx_gmxx_smacx_s cn58xxp1; + struct cvmx_gmxx_smacx_s cn61xx; + struct cvmx_gmxx_smacx_s cn63xx; + struct cvmx_gmxx_smacx_s cn63xxp1; + struct cvmx_gmxx_smacx_s cn66xx; + struct cvmx_gmxx_smacx_s cn68xx; + struct cvmx_gmxx_smacx_s cn68xxp1; + struct cvmx_gmxx_smacx_s cnf71xx; +}; + +union cvmx_gmxx_soft_bist { + uint64_t u64; + struct cvmx_gmxx_soft_bist_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_2_63:62; + uint64_t start_bist:1; + uint64_t clear_bist:1; +#else + uint64_t clear_bist:1; + uint64_t start_bist:1; + uint64_t reserved_2_63:62; +#endif + } s; + struct cvmx_gmxx_soft_bist_s cn63xx; + struct cvmx_gmxx_soft_bist_s cn63xxp1; + struct cvmx_gmxx_soft_bist_s cn66xx; + struct cvmx_gmxx_soft_bist_s cn68xx; + struct cvmx_gmxx_soft_bist_s cn68xxp1; }; union cvmx_gmxx_stat_bp { uint64_t u64; struct cvmx_gmxx_stat_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t bp:1; uint64_t cnt:16; +#else + uint64_t cnt:16; + uint64_t bp:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_gmxx_stat_bp_s cn30xx; struct cvmx_gmxx_stat_bp_s cn31xx; @@ -1583,16 +4996,48 @@ union cvmx_gmxx_stat_bp { struct cvmx_gmxx_stat_bp_s cn56xxp1; struct cvmx_gmxx_stat_bp_s cn58xx; struct cvmx_gmxx_stat_bp_s cn58xxp1; + struct cvmx_gmxx_stat_bp_s cn61xx; + struct cvmx_gmxx_stat_bp_s cn63xx; + struct cvmx_gmxx_stat_bp_s cn63xxp1; + struct cvmx_gmxx_stat_bp_s cn66xx; + struct cvmx_gmxx_stat_bp_s cn68xx; + struct cvmx_gmxx_stat_bp_s cn68xxp1; + struct cvmx_gmxx_stat_bp_s cnf71xx; +}; + +union cvmx_gmxx_tb_reg { + uint64_t u64; + struct cvmx_gmxx_tb_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t wr_magic:1; +#else + uint64_t wr_magic:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_gmxx_tb_reg_s cn61xx; + struct cvmx_gmxx_tb_reg_s cn66xx; + struct cvmx_gmxx_tb_reg_s cn68xx; + struct cvmx_gmxx_tb_reg_s cnf71xx; }; union cvmx_gmxx_txx_append { uint64_t u64; struct cvmx_gmxx_txx_append_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t force_fcs:1; uint64_t fcs:1; uint64_t pad:1; uint64_t preamble:1; +#else + uint64_t preamble:1; + uint64_t pad:1; + uint64_t fcs:1; + uint64_t force_fcs:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_gmxx_txx_append_s cn30xx; struct cvmx_gmxx_txx_append_s cn31xx; @@ -1605,13 +5050,25 @@ union cvmx_gmxx_txx_append { struct cvmx_gmxx_txx_append_s cn56xxp1; struct cvmx_gmxx_txx_append_s cn58xx; struct cvmx_gmxx_txx_append_s cn58xxp1; + struct cvmx_gmxx_txx_append_s cn61xx; + struct cvmx_gmxx_txx_append_s cn63xx; + struct cvmx_gmxx_txx_append_s cn63xxp1; + struct cvmx_gmxx_txx_append_s cn66xx; + struct cvmx_gmxx_txx_append_s cn68xx; + struct cvmx_gmxx_txx_append_s cn68xxp1; + struct cvmx_gmxx_txx_append_s cnf71xx; }; union cvmx_gmxx_txx_burst { uint64_t u64; struct cvmx_gmxx_txx_burst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t burst:16; +#else + uint64_t burst:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_txx_burst_s cn30xx; struct cvmx_gmxx_txx_burst_s cn31xx; @@ -1624,33 +5081,69 @@ union cvmx_gmxx_txx_burst { struct cvmx_gmxx_txx_burst_s cn56xxp1; struct cvmx_gmxx_txx_burst_s cn58xx; struct cvmx_gmxx_txx_burst_s cn58xxp1; + struct cvmx_gmxx_txx_burst_s cn61xx; + struct cvmx_gmxx_txx_burst_s cn63xx; + struct cvmx_gmxx_txx_burst_s cn63xxp1; + struct cvmx_gmxx_txx_burst_s cn66xx; + struct cvmx_gmxx_txx_burst_s cn68xx; + struct cvmx_gmxx_txx_burst_s cn68xxp1; + struct cvmx_gmxx_txx_burst_s cnf71xx; }; union cvmx_gmxx_txx_cbfc_xoff { uint64_t u64; struct cvmx_gmxx_txx_cbfc_xoff_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t xoff:16; +#else + uint64_t xoff:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx; struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx; + struct cvmx_gmxx_txx_cbfc_xoff_s cn61xx; + struct cvmx_gmxx_txx_cbfc_xoff_s cn63xx; + struct cvmx_gmxx_txx_cbfc_xoff_s cn63xxp1; + struct cvmx_gmxx_txx_cbfc_xoff_s cn66xx; + struct cvmx_gmxx_txx_cbfc_xoff_s cn68xx; + struct cvmx_gmxx_txx_cbfc_xoff_s cn68xxp1; + struct cvmx_gmxx_txx_cbfc_xoff_s cnf71xx; }; union cvmx_gmxx_txx_cbfc_xon { uint64_t u64; struct cvmx_gmxx_txx_cbfc_xon_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t xon:16; +#else + uint64_t xon:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_txx_cbfc_xon_s cn52xx; struct cvmx_gmxx_txx_cbfc_xon_s cn56xx; + struct cvmx_gmxx_txx_cbfc_xon_s cn61xx; + struct cvmx_gmxx_txx_cbfc_xon_s cn63xx; + struct cvmx_gmxx_txx_cbfc_xon_s cn63xxp1; + struct cvmx_gmxx_txx_cbfc_xon_s cn66xx; + struct cvmx_gmxx_txx_cbfc_xon_s cn68xx; + struct cvmx_gmxx_txx_cbfc_xon_s cn68xxp1; + struct cvmx_gmxx_txx_cbfc_xon_s cnf71xx; }; union cvmx_gmxx_txx_clk { uint64_t u64; struct cvmx_gmxx_txx_clk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t clk_cnt:6; +#else + uint64_t clk_cnt:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_gmxx_txx_clk_s cn30xx; struct cvmx_gmxx_txx_clk_s cn31xx; @@ -1664,9 +5157,15 @@ union cvmx_gmxx_txx_clk { union cvmx_gmxx_txx_ctl { uint64_t u64; struct cvmx_gmxx_txx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t xsdef_en:1; uint64_t xscol_en:1; +#else + uint64_t xscol_en:1; + uint64_t xsdef_en:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_gmxx_txx_ctl_s cn30xx; struct cvmx_gmxx_txx_ctl_s cn31xx; @@ -1679,13 +5178,25 @@ union cvmx_gmxx_txx_ctl { struct cvmx_gmxx_txx_ctl_s cn56xxp1; struct cvmx_gmxx_txx_ctl_s cn58xx; struct cvmx_gmxx_txx_ctl_s cn58xxp1; + struct cvmx_gmxx_txx_ctl_s cn61xx; + struct cvmx_gmxx_txx_ctl_s cn63xx; + struct cvmx_gmxx_txx_ctl_s cn63xxp1; + struct cvmx_gmxx_txx_ctl_s cn66xx; + struct cvmx_gmxx_txx_ctl_s cn68xx; + struct cvmx_gmxx_txx_ctl_s cn68xxp1; + struct cvmx_gmxx_txx_ctl_s cnf71xx; }; union cvmx_gmxx_txx_min_pkt { uint64_t u64; struct cvmx_gmxx_txx_min_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t min_size:8; +#else + uint64_t min_size:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_gmxx_txx_min_pkt_s cn30xx; struct cvmx_gmxx_txx_min_pkt_s cn31xx; @@ -1698,13 +5209,25 @@ union cvmx_gmxx_txx_min_pkt { struct cvmx_gmxx_txx_min_pkt_s cn56xxp1; struct cvmx_gmxx_txx_min_pkt_s cn58xx; struct cvmx_gmxx_txx_min_pkt_s cn58xxp1; + struct cvmx_gmxx_txx_min_pkt_s cn61xx; + struct cvmx_gmxx_txx_min_pkt_s cn63xx; + struct cvmx_gmxx_txx_min_pkt_s cn63xxp1; + struct cvmx_gmxx_txx_min_pkt_s cn66xx; + struct cvmx_gmxx_txx_min_pkt_s cn68xx; + struct cvmx_gmxx_txx_min_pkt_s cn68xxp1; + struct cvmx_gmxx_txx_min_pkt_s cnf71xx; }; union cvmx_gmxx_txx_pause_pkt_interval { uint64_t u64; struct cvmx_gmxx_txx_pause_pkt_interval_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t interval:16; +#else + uint64_t interval:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx; struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx; @@ -1717,13 +5240,25 @@ union cvmx_gmxx_txx_pause_pkt_interval { struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1; struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx; struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn61xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xxp1; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn66xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xxp1; + struct cvmx_gmxx_txx_pause_pkt_interval_s cnf71xx; }; union cvmx_gmxx_txx_pause_pkt_time { uint64_t u64; struct cvmx_gmxx_txx_pause_pkt_time_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; +#else + uint64_t time:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx; struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx; @@ -1736,18 +5271,36 @@ union cvmx_gmxx_txx_pause_pkt_time { struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1; struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx; struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1; + struct cvmx_gmxx_txx_pause_pkt_time_s cn61xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn63xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn63xxp1; + struct cvmx_gmxx_txx_pause_pkt_time_s cn66xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn68xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn68xxp1; + struct cvmx_gmxx_txx_pause_pkt_time_s cnf71xx; }; union cvmx_gmxx_txx_pause_togo { uint64_t u64; struct cvmx_gmxx_txx_pause_togo_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t msg_time:16; uint64_t time:16; +#else + uint64_t time:16; + uint64_t msg_time:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_txx_pause_togo_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; +#else + uint64_t time:16; + uint64_t reserved_16_63:48; +#endif } cn30xx; struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx; struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx; @@ -1759,13 +5312,25 @@ union cvmx_gmxx_txx_pause_togo { struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1; struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx; struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1; + struct cvmx_gmxx_txx_pause_togo_s cn61xx; + struct cvmx_gmxx_txx_pause_togo_s cn63xx; + struct cvmx_gmxx_txx_pause_togo_s cn63xxp1; + struct cvmx_gmxx_txx_pause_togo_s cn66xx; + struct cvmx_gmxx_txx_pause_togo_s cn68xx; + struct cvmx_gmxx_txx_pause_togo_s cn68xxp1; + struct cvmx_gmxx_txx_pause_togo_s cnf71xx; }; union cvmx_gmxx_txx_pause_zero { uint64_t u64; struct cvmx_gmxx_txx_pause_zero_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t send:1; +#else + uint64_t send:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_gmxx_txx_pause_zero_s cn30xx; struct cvmx_gmxx_txx_pause_zero_s cn31xx; @@ -1778,25 +5343,72 @@ union cvmx_gmxx_txx_pause_zero { struct cvmx_gmxx_txx_pause_zero_s cn56xxp1; struct cvmx_gmxx_txx_pause_zero_s cn58xx; struct cvmx_gmxx_txx_pause_zero_s cn58xxp1; + struct cvmx_gmxx_txx_pause_zero_s cn61xx; + struct cvmx_gmxx_txx_pause_zero_s cn63xx; + struct cvmx_gmxx_txx_pause_zero_s cn63xxp1; + struct cvmx_gmxx_txx_pause_zero_s cn66xx; + struct cvmx_gmxx_txx_pause_zero_s cn68xx; + struct cvmx_gmxx_txx_pause_zero_s cn68xxp1; + struct cvmx_gmxx_txx_pause_zero_s cnf71xx; +}; + +union cvmx_gmxx_txx_pipe { + uint64_t u64; + struct cvmx_gmxx_txx_pipe_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t ign_bp:1; + uint64_t reserved_21_31:11; + uint64_t nump:5; + uint64_t reserved_7_15:9; + uint64_t base:7; +#else + uint64_t base:7; + uint64_t reserved_7_15:9; + uint64_t nump:5; + uint64_t reserved_21_31:11; + uint64_t ign_bp:1; + uint64_t reserved_33_63:31; +#endif + } s; + struct cvmx_gmxx_txx_pipe_s cn68xx; + struct cvmx_gmxx_txx_pipe_s cn68xxp1; }; union cvmx_gmxx_txx_sgmii_ctl { uint64_t u64; struct cvmx_gmxx_txx_sgmii_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t align:1; +#else + uint64_t align:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx; struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1; struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx; struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1; + struct cvmx_gmxx_txx_sgmii_ctl_s cn61xx; + struct cvmx_gmxx_txx_sgmii_ctl_s cn63xx; + struct cvmx_gmxx_txx_sgmii_ctl_s cn63xxp1; + struct cvmx_gmxx_txx_sgmii_ctl_s cn66xx; + struct cvmx_gmxx_txx_sgmii_ctl_s cn68xx; + struct cvmx_gmxx_txx_sgmii_ctl_s cn68xxp1; + struct cvmx_gmxx_txx_sgmii_ctl_s cnf71xx; }; union cvmx_gmxx_txx_slot { uint64_t u64; struct cvmx_gmxx_txx_slot_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t slot:10; +#else + uint64_t slot:10; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_gmxx_txx_slot_s cn30xx; struct cvmx_gmxx_txx_slot_s cn31xx; @@ -1809,13 +5421,25 @@ union cvmx_gmxx_txx_slot { struct cvmx_gmxx_txx_slot_s cn56xxp1; struct cvmx_gmxx_txx_slot_s cn58xx; struct cvmx_gmxx_txx_slot_s cn58xxp1; + struct cvmx_gmxx_txx_slot_s cn61xx; + struct cvmx_gmxx_txx_slot_s cn63xx; + struct cvmx_gmxx_txx_slot_s cn63xxp1; + struct cvmx_gmxx_txx_slot_s cn66xx; + struct cvmx_gmxx_txx_slot_s cn68xx; + struct cvmx_gmxx_txx_slot_s cn68xxp1; + struct cvmx_gmxx_txx_slot_s cnf71xx; }; union cvmx_gmxx_txx_soft_pause { uint64_t u64; struct cvmx_gmxx_txx_soft_pause_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; +#else + uint64_t time:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_txx_soft_pause_s cn30xx; struct cvmx_gmxx_txx_soft_pause_s cn31xx; @@ -1828,13 +5452,25 @@ union cvmx_gmxx_txx_soft_pause { struct cvmx_gmxx_txx_soft_pause_s cn56xxp1; struct cvmx_gmxx_txx_soft_pause_s cn58xx; struct cvmx_gmxx_txx_soft_pause_s cn58xxp1; + struct cvmx_gmxx_txx_soft_pause_s cn61xx; + struct cvmx_gmxx_txx_soft_pause_s cn63xx; + struct cvmx_gmxx_txx_soft_pause_s cn63xxp1; + struct cvmx_gmxx_txx_soft_pause_s cn66xx; + struct cvmx_gmxx_txx_soft_pause_s cn68xx; + struct cvmx_gmxx_txx_soft_pause_s cn68xxp1; + struct cvmx_gmxx_txx_soft_pause_s cnf71xx; }; union cvmx_gmxx_txx_stat0 { uint64_t u64; struct cvmx_gmxx_txx_stat0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t xsdef:32; uint64_t xscol:32; +#else + uint64_t xscol:32; + uint64_t xsdef:32; +#endif } s; struct cvmx_gmxx_txx_stat0_s cn30xx; struct cvmx_gmxx_txx_stat0_s cn31xx; @@ -1847,13 +5483,25 @@ union cvmx_gmxx_txx_stat0 { struct cvmx_gmxx_txx_stat0_s cn56xxp1; struct cvmx_gmxx_txx_stat0_s cn58xx; struct cvmx_gmxx_txx_stat0_s cn58xxp1; + struct cvmx_gmxx_txx_stat0_s cn61xx; + struct cvmx_gmxx_txx_stat0_s cn63xx; + struct cvmx_gmxx_txx_stat0_s cn63xxp1; + struct cvmx_gmxx_txx_stat0_s cn66xx; + struct cvmx_gmxx_txx_stat0_s cn68xx; + struct cvmx_gmxx_txx_stat0_s cn68xxp1; + struct cvmx_gmxx_txx_stat0_s cnf71xx; }; union cvmx_gmxx_txx_stat1 { uint64_t u64; struct cvmx_gmxx_txx_stat1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t scol:32; uint64_t mcol:32; +#else + uint64_t mcol:32; + uint64_t scol:32; +#endif } s; struct cvmx_gmxx_txx_stat1_s cn30xx; struct cvmx_gmxx_txx_stat1_s cn31xx; @@ -1866,13 +5514,25 @@ union cvmx_gmxx_txx_stat1 { struct cvmx_gmxx_txx_stat1_s cn56xxp1; struct cvmx_gmxx_txx_stat1_s cn58xx; struct cvmx_gmxx_txx_stat1_s cn58xxp1; + struct cvmx_gmxx_txx_stat1_s cn61xx; + struct cvmx_gmxx_txx_stat1_s cn63xx; + struct cvmx_gmxx_txx_stat1_s cn63xxp1; + struct cvmx_gmxx_txx_stat1_s cn66xx; + struct cvmx_gmxx_txx_stat1_s cn68xx; + struct cvmx_gmxx_txx_stat1_s cn68xxp1; + struct cvmx_gmxx_txx_stat1_s cnf71xx; }; union cvmx_gmxx_txx_stat2 { uint64_t u64; struct cvmx_gmxx_txx_stat2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t octs:48; +#else + uint64_t octs:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_txx_stat2_s cn30xx; struct cvmx_gmxx_txx_stat2_s cn31xx; @@ -1885,13 +5545,25 @@ union cvmx_gmxx_txx_stat2 { struct cvmx_gmxx_txx_stat2_s cn56xxp1; struct cvmx_gmxx_txx_stat2_s cn58xx; struct cvmx_gmxx_txx_stat2_s cn58xxp1; + struct cvmx_gmxx_txx_stat2_s cn61xx; + struct cvmx_gmxx_txx_stat2_s cn63xx; + struct cvmx_gmxx_txx_stat2_s cn63xxp1; + struct cvmx_gmxx_txx_stat2_s cn66xx; + struct cvmx_gmxx_txx_stat2_s cn68xx; + struct cvmx_gmxx_txx_stat2_s cn68xxp1; + struct cvmx_gmxx_txx_stat2_s cnf71xx; }; union cvmx_gmxx_txx_stat3 { uint64_t u64; struct cvmx_gmxx_txx_stat3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pkts:32; +#else + uint64_t pkts:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_txx_stat3_s cn30xx; struct cvmx_gmxx_txx_stat3_s cn31xx; @@ -1904,13 +5576,25 @@ union cvmx_gmxx_txx_stat3 { struct cvmx_gmxx_txx_stat3_s cn56xxp1; struct cvmx_gmxx_txx_stat3_s cn58xx; struct cvmx_gmxx_txx_stat3_s cn58xxp1; + struct cvmx_gmxx_txx_stat3_s cn61xx; + struct cvmx_gmxx_txx_stat3_s cn63xx; + struct cvmx_gmxx_txx_stat3_s cn63xxp1; + struct cvmx_gmxx_txx_stat3_s cn66xx; + struct cvmx_gmxx_txx_stat3_s cn68xx; + struct cvmx_gmxx_txx_stat3_s cn68xxp1; + struct cvmx_gmxx_txx_stat3_s cnf71xx; }; union cvmx_gmxx_txx_stat4 { uint64_t u64; struct cvmx_gmxx_txx_stat4_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist1:32; uint64_t hist0:32; +#else + uint64_t hist0:32; + uint64_t hist1:32; +#endif } s; struct cvmx_gmxx_txx_stat4_s cn30xx; struct cvmx_gmxx_txx_stat4_s cn31xx; @@ -1923,13 +5607,25 @@ union cvmx_gmxx_txx_stat4 { struct cvmx_gmxx_txx_stat4_s cn56xxp1; struct cvmx_gmxx_txx_stat4_s cn58xx; struct cvmx_gmxx_txx_stat4_s cn58xxp1; + struct cvmx_gmxx_txx_stat4_s cn61xx; + struct cvmx_gmxx_txx_stat4_s cn63xx; + struct cvmx_gmxx_txx_stat4_s cn63xxp1; + struct cvmx_gmxx_txx_stat4_s cn66xx; + struct cvmx_gmxx_txx_stat4_s cn68xx; + struct cvmx_gmxx_txx_stat4_s cn68xxp1; + struct cvmx_gmxx_txx_stat4_s cnf71xx; }; union cvmx_gmxx_txx_stat5 { uint64_t u64; struct cvmx_gmxx_txx_stat5_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist3:32; uint64_t hist2:32; +#else + uint64_t hist2:32; + uint64_t hist3:32; +#endif } s; struct cvmx_gmxx_txx_stat5_s cn30xx; struct cvmx_gmxx_txx_stat5_s cn31xx; @@ -1942,13 +5638,25 @@ union cvmx_gmxx_txx_stat5 { struct cvmx_gmxx_txx_stat5_s cn56xxp1; struct cvmx_gmxx_txx_stat5_s cn58xx; struct cvmx_gmxx_txx_stat5_s cn58xxp1; + struct cvmx_gmxx_txx_stat5_s cn61xx; + struct cvmx_gmxx_txx_stat5_s cn63xx; + struct cvmx_gmxx_txx_stat5_s cn63xxp1; + struct cvmx_gmxx_txx_stat5_s cn66xx; + struct cvmx_gmxx_txx_stat5_s cn68xx; + struct cvmx_gmxx_txx_stat5_s cn68xxp1; + struct cvmx_gmxx_txx_stat5_s cnf71xx; }; union cvmx_gmxx_txx_stat6 { uint64_t u64; struct cvmx_gmxx_txx_stat6_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist5:32; uint64_t hist4:32; +#else + uint64_t hist4:32; + uint64_t hist5:32; +#endif } s; struct cvmx_gmxx_txx_stat6_s cn30xx; struct cvmx_gmxx_txx_stat6_s cn31xx; @@ -1961,13 +5669,25 @@ union cvmx_gmxx_txx_stat6 { struct cvmx_gmxx_txx_stat6_s cn56xxp1; struct cvmx_gmxx_txx_stat6_s cn58xx; struct cvmx_gmxx_txx_stat6_s cn58xxp1; + struct cvmx_gmxx_txx_stat6_s cn61xx; + struct cvmx_gmxx_txx_stat6_s cn63xx; + struct cvmx_gmxx_txx_stat6_s cn63xxp1; + struct cvmx_gmxx_txx_stat6_s cn66xx; + struct cvmx_gmxx_txx_stat6_s cn68xx; + struct cvmx_gmxx_txx_stat6_s cn68xxp1; + struct cvmx_gmxx_txx_stat6_s cnf71xx; }; union cvmx_gmxx_txx_stat7 { uint64_t u64; struct cvmx_gmxx_txx_stat7_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist7:32; uint64_t hist6:32; +#else + uint64_t hist6:32; + uint64_t hist7:32; +#endif } s; struct cvmx_gmxx_txx_stat7_s cn30xx; struct cvmx_gmxx_txx_stat7_s cn31xx; @@ -1980,13 +5700,25 @@ union cvmx_gmxx_txx_stat7 { struct cvmx_gmxx_txx_stat7_s cn56xxp1; struct cvmx_gmxx_txx_stat7_s cn58xx; struct cvmx_gmxx_txx_stat7_s cn58xxp1; + struct cvmx_gmxx_txx_stat7_s cn61xx; + struct cvmx_gmxx_txx_stat7_s cn63xx; + struct cvmx_gmxx_txx_stat7_s cn63xxp1; + struct cvmx_gmxx_txx_stat7_s cn66xx; + struct cvmx_gmxx_txx_stat7_s cn68xx; + struct cvmx_gmxx_txx_stat7_s cn68xxp1; + struct cvmx_gmxx_txx_stat7_s cnf71xx; }; union cvmx_gmxx_txx_stat8 { uint64_t u64; struct cvmx_gmxx_txx_stat8_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mcst:32; uint64_t bcst:32; +#else + uint64_t bcst:32; + uint64_t mcst:32; +#endif } s; struct cvmx_gmxx_txx_stat8_s cn30xx; struct cvmx_gmxx_txx_stat8_s cn31xx; @@ -1999,13 +5731,25 @@ union cvmx_gmxx_txx_stat8 { struct cvmx_gmxx_txx_stat8_s cn56xxp1; struct cvmx_gmxx_txx_stat8_s cn58xx; struct cvmx_gmxx_txx_stat8_s cn58xxp1; + struct cvmx_gmxx_txx_stat8_s cn61xx; + struct cvmx_gmxx_txx_stat8_s cn63xx; + struct cvmx_gmxx_txx_stat8_s cn63xxp1; + struct cvmx_gmxx_txx_stat8_s cn66xx; + struct cvmx_gmxx_txx_stat8_s cn68xx; + struct cvmx_gmxx_txx_stat8_s cn68xxp1; + struct cvmx_gmxx_txx_stat8_s cnf71xx; }; union cvmx_gmxx_txx_stat9 { uint64_t u64; struct cvmx_gmxx_txx_stat9_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t undflw:32; uint64_t ctl:32; +#else + uint64_t ctl:32; + uint64_t undflw:32; +#endif } s; struct cvmx_gmxx_txx_stat9_s cn30xx; struct cvmx_gmxx_txx_stat9_s cn31xx; @@ -2018,13 +5762,25 @@ union cvmx_gmxx_txx_stat9 { struct cvmx_gmxx_txx_stat9_s cn56xxp1; struct cvmx_gmxx_txx_stat9_s cn58xx; struct cvmx_gmxx_txx_stat9_s cn58xxp1; + struct cvmx_gmxx_txx_stat9_s cn61xx; + struct cvmx_gmxx_txx_stat9_s cn63xx; + struct cvmx_gmxx_txx_stat9_s cn63xxp1; + struct cvmx_gmxx_txx_stat9_s cn66xx; + struct cvmx_gmxx_txx_stat9_s cn68xx; + struct cvmx_gmxx_txx_stat9_s cn68xxp1; + struct cvmx_gmxx_txx_stat9_s cnf71xx; }; union cvmx_gmxx_txx_stats_ctl { uint64_t u64; struct cvmx_gmxx_txx_stats_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rd_clr:1; +#else + uint64_t rd_clr:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_gmxx_txx_stats_ctl_s cn30xx; struct cvmx_gmxx_txx_stats_ctl_s cn31xx; @@ -2037,39 +5793,81 @@ union cvmx_gmxx_txx_stats_ctl { struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1; struct cvmx_gmxx_txx_stats_ctl_s cn58xx; struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1; + struct cvmx_gmxx_txx_stats_ctl_s cn61xx; + struct cvmx_gmxx_txx_stats_ctl_s cn63xx; + struct cvmx_gmxx_txx_stats_ctl_s cn63xxp1; + struct cvmx_gmxx_txx_stats_ctl_s cn66xx; + struct cvmx_gmxx_txx_stats_ctl_s cn68xx; + struct cvmx_gmxx_txx_stats_ctl_s cn68xxp1; + struct cvmx_gmxx_txx_stats_ctl_s cnf71xx; }; union cvmx_gmxx_txx_thresh { uint64_t u64; struct cvmx_gmxx_txx_thresh_s { - uint64_t reserved_9_63:55; - uint64_t cnt:9; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t cnt:10; +#else + uint64_t cnt:10; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_gmxx_txx_thresh_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t cnt:7; +#else + uint64_t cnt:7; + uint64_t reserved_7_63:57; +#endif } cn30xx; struct cvmx_gmxx_txx_thresh_cn30xx cn31xx; - struct cvmx_gmxx_txx_thresh_s cn38xx; - struct cvmx_gmxx_txx_thresh_s cn38xxp2; + struct cvmx_gmxx_txx_thresh_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t cnt:9; +#else + uint64_t cnt:9; + uint64_t reserved_9_63:55; +#endif + } cn38xx; + struct cvmx_gmxx_txx_thresh_cn38xx cn38xxp2; struct cvmx_gmxx_txx_thresh_cn30xx cn50xx; - struct cvmx_gmxx_txx_thresh_s cn52xx; - struct cvmx_gmxx_txx_thresh_s cn52xxp1; - struct cvmx_gmxx_txx_thresh_s cn56xx; - struct cvmx_gmxx_txx_thresh_s cn56xxp1; - struct cvmx_gmxx_txx_thresh_s cn58xx; - struct cvmx_gmxx_txx_thresh_s cn58xxp1; + struct cvmx_gmxx_txx_thresh_cn38xx cn52xx; + struct cvmx_gmxx_txx_thresh_cn38xx cn52xxp1; + struct cvmx_gmxx_txx_thresh_cn38xx cn56xx; + struct cvmx_gmxx_txx_thresh_cn38xx cn56xxp1; + struct cvmx_gmxx_txx_thresh_cn38xx cn58xx; + struct cvmx_gmxx_txx_thresh_cn38xx cn58xxp1; + struct cvmx_gmxx_txx_thresh_cn38xx cn61xx; + struct cvmx_gmxx_txx_thresh_cn38xx cn63xx; + struct cvmx_gmxx_txx_thresh_cn38xx cn63xxp1; + struct cvmx_gmxx_txx_thresh_cn38xx cn66xx; + struct cvmx_gmxx_txx_thresh_s cn68xx; + struct cvmx_gmxx_txx_thresh_s cn68xxp1; + struct cvmx_gmxx_txx_thresh_cn38xx cnf71xx; }; union cvmx_gmxx_tx_bp { uint64_t u64; struct cvmx_gmxx_tx_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t bp:4; +#else + uint64_t bp:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_gmxx_tx_bp_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t bp:3; +#else + uint64_t bp:3; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_gmxx_tx_bp_cn30xx cn31xx; struct cvmx_gmxx_tx_bp_s cn38xx; @@ -2081,13 +5879,33 @@ union cvmx_gmxx_tx_bp { struct cvmx_gmxx_tx_bp_s cn56xxp1; struct cvmx_gmxx_tx_bp_s cn58xx; struct cvmx_gmxx_tx_bp_s cn58xxp1; + struct cvmx_gmxx_tx_bp_s cn61xx; + struct cvmx_gmxx_tx_bp_s cn63xx; + struct cvmx_gmxx_tx_bp_s cn63xxp1; + struct cvmx_gmxx_tx_bp_s cn66xx; + struct cvmx_gmxx_tx_bp_s cn68xx; + struct cvmx_gmxx_tx_bp_s cn68xxp1; + struct cvmx_gmxx_tx_bp_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_2_63:62; + uint64_t bp:2; +#else + uint64_t bp:2; + uint64_t reserved_2_63:62; +#endif + } cnf71xx; }; union cvmx_gmxx_tx_clk_mskx { uint64_t u64; struct cvmx_gmxx_tx_clk_mskx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t msk:1; +#else + uint64_t msk:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_gmxx_tx_clk_mskx_s cn30xx; struct cvmx_gmxx_tx_clk_mskx_s cn50xx; @@ -2096,8 +5914,13 @@ union cvmx_gmxx_tx_clk_mskx { union cvmx_gmxx_tx_col_attempt { uint64_t u64; struct cvmx_gmxx_tx_col_attempt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t limit:5; +#else + uint64_t limit:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_gmxx_tx_col_attempt_s cn30xx; struct cvmx_gmxx_tx_col_attempt_s cn31xx; @@ -2110,17 +5933,34 @@ union cvmx_gmxx_tx_col_attempt { struct cvmx_gmxx_tx_col_attempt_s cn56xxp1; struct cvmx_gmxx_tx_col_attempt_s cn58xx; struct cvmx_gmxx_tx_col_attempt_s cn58xxp1; + struct cvmx_gmxx_tx_col_attempt_s cn61xx; + struct cvmx_gmxx_tx_col_attempt_s cn63xx; + struct cvmx_gmxx_tx_col_attempt_s cn63xxp1; + struct cvmx_gmxx_tx_col_attempt_s cn66xx; + struct cvmx_gmxx_tx_col_attempt_s cn68xx; + struct cvmx_gmxx_tx_col_attempt_s cn68xxp1; + struct cvmx_gmxx_tx_col_attempt_s cnf71xx; }; union cvmx_gmxx_tx_corrupt { uint64_t u64; struct cvmx_gmxx_tx_corrupt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t corrupt:4; +#else + uint64_t corrupt:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_gmxx_tx_corrupt_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t corrupt:3; +#else + uint64_t corrupt:3; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx; struct cvmx_gmxx_tx_corrupt_s cn38xx; @@ -2132,36 +5972,81 @@ union cvmx_gmxx_tx_corrupt { struct cvmx_gmxx_tx_corrupt_s cn56xxp1; struct cvmx_gmxx_tx_corrupt_s cn58xx; struct cvmx_gmxx_tx_corrupt_s cn58xxp1; + struct cvmx_gmxx_tx_corrupt_s cn61xx; + struct cvmx_gmxx_tx_corrupt_s cn63xx; + struct cvmx_gmxx_tx_corrupt_s cn63xxp1; + struct cvmx_gmxx_tx_corrupt_s cn66xx; + struct cvmx_gmxx_tx_corrupt_s cn68xx; + struct cvmx_gmxx_tx_corrupt_s cn68xxp1; + struct cvmx_gmxx_tx_corrupt_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_2_63:62; + uint64_t corrupt:2; +#else + uint64_t corrupt:2; + uint64_t reserved_2_63:62; +#endif + } cnf71xx; }; union cvmx_gmxx_tx_hg2_reg1 { uint64_t u64; struct cvmx_gmxx_tx_hg2_reg1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t tx_xof:16; +#else + uint64_t tx_xof:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_tx_hg2_reg1_s cn52xx; struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1; struct cvmx_gmxx_tx_hg2_reg1_s cn56xx; + struct cvmx_gmxx_tx_hg2_reg1_s cn61xx; + struct cvmx_gmxx_tx_hg2_reg1_s cn63xx; + struct cvmx_gmxx_tx_hg2_reg1_s cn63xxp1; + struct cvmx_gmxx_tx_hg2_reg1_s cn66xx; + struct cvmx_gmxx_tx_hg2_reg1_s cn68xx; + struct cvmx_gmxx_tx_hg2_reg1_s cn68xxp1; + struct cvmx_gmxx_tx_hg2_reg1_s cnf71xx; }; union cvmx_gmxx_tx_hg2_reg2 { uint64_t u64; struct cvmx_gmxx_tx_hg2_reg2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t tx_xon:16; +#else + uint64_t tx_xon:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_tx_hg2_reg2_s cn52xx; struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1; struct cvmx_gmxx_tx_hg2_reg2_s cn56xx; + struct cvmx_gmxx_tx_hg2_reg2_s cn61xx; + struct cvmx_gmxx_tx_hg2_reg2_s cn63xx; + struct cvmx_gmxx_tx_hg2_reg2_s cn63xxp1; + struct cvmx_gmxx_tx_hg2_reg2_s cn66xx; + struct cvmx_gmxx_tx_hg2_reg2_s cn68xx; + struct cvmx_gmxx_tx_hg2_reg2_s cn68xxp1; + struct cvmx_gmxx_tx_hg2_reg2_s cnf71xx; }; union cvmx_gmxx_tx_ifg { uint64_t u64; struct cvmx_gmxx_tx_ifg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ifg2:4; uint64_t ifg1:4; +#else + uint64_t ifg1:4; + uint64_t ifg2:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_gmxx_tx_ifg_s cn30xx; struct cvmx_gmxx_tx_ifg_s cn31xx; @@ -2174,21 +6059,44 @@ union cvmx_gmxx_tx_ifg { struct cvmx_gmxx_tx_ifg_s cn56xxp1; struct cvmx_gmxx_tx_ifg_s cn58xx; struct cvmx_gmxx_tx_ifg_s cn58xxp1; + struct cvmx_gmxx_tx_ifg_s cn61xx; + struct cvmx_gmxx_tx_ifg_s cn63xx; + struct cvmx_gmxx_tx_ifg_s cn63xxp1; + struct cvmx_gmxx_tx_ifg_s cn66xx; + struct cvmx_gmxx_tx_ifg_s cn68xx; + struct cvmx_gmxx_tx_ifg_s cn68xxp1; + struct cvmx_gmxx_tx_ifg_s cnf71xx; }; union cvmx_gmxx_tx_int_en { uint64_t u64; struct cvmx_gmxx_tx_int_en_s { - uint64_t reserved_20_63:44; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t xchange:1; + uint64_t ptp_lost:4; uint64_t late_col:4; uint64_t xsdef:4; uint64_t xscol:4; uint64_t reserved_6_7:2; uint64_t undflw:4; - uint64_t ncb_nxa:1; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; +#else uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t ptp_lost:4; + uint64_t xchange:1; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_gmxx_tx_int_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t late_col:3; uint64_t reserved_15_15:1; @@ -2199,8 +6107,21 @@ union cvmx_gmxx_tx_int_en { uint64_t undflw:3; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:3; + uint64_t reserved_5_7:3; + uint64_t xscol:3; + uint64_t reserved_11_11:1; + uint64_t xsdef:3; + uint64_t reserved_15_15:1; + uint64_t late_col:3; + uint64_t reserved_19_63:45; +#endif } cn30xx; struct cvmx_gmxx_tx_int_en_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t xsdef:3; uint64_t reserved_11_11:1; @@ -2209,9 +6130,40 @@ union cvmx_gmxx_tx_int_en { uint64_t undflw:3; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:3; + uint64_t reserved_5_7:3; + uint64_t xscol:3; + uint64_t reserved_11_11:1; + uint64_t xsdef:3; + uint64_t reserved_15_63:49; +#endif } cn31xx; - struct cvmx_gmxx_tx_int_en_s cn38xx; + struct cvmx_gmxx_tx_int_en_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t ncb_nxa:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t ncb_nxa:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t reserved_20_63:44; +#endif + } cn38xx; struct cvmx_gmxx_tx_int_en_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t xsdef:4; uint64_t xscol:4; @@ -2219,9 +6171,19 @@ union cvmx_gmxx_tx_int_en { uint64_t undflw:4; uint64_t ncb_nxa:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t ncb_nxa:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t reserved_16_63:48; +#endif } cn38xxp2; struct cvmx_gmxx_tx_int_en_cn30xx cn50xx; struct cvmx_gmxx_tx_int_en_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t late_col:4; uint64_t xsdef:4; @@ -2230,27 +6192,138 @@ union cvmx_gmxx_tx_int_en { uint64_t undflw:4; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1; struct cvmx_gmxx_tx_int_en_cn52xx cn56xx; struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1; - struct cvmx_gmxx_tx_int_en_s cn58xx; - struct cvmx_gmxx_tx_int_en_s cn58xxp1; + struct cvmx_gmxx_tx_int_en_cn38xx cn58xx; + struct cvmx_gmxx_tx_int_en_cn38xx cn58xxp1; + struct cvmx_gmxx_tx_int_en_s cn61xx; + struct cvmx_gmxx_tx_int_en_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_24_63:40; + uint64_t ptp_lost:4; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t ptp_lost:4; + uint64_t reserved_24_63:40; +#endif + } cn63xx; + struct cvmx_gmxx_tx_int_en_cn63xx cn63xxp1; + struct cvmx_gmxx_tx_int_en_s cn66xx; + struct cvmx_gmxx_tx_int_en_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t xchange:1; + uint64_t ptp_lost:4; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t pko_nxp:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t pko_nxp:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t ptp_lost:4; + uint64_t xchange:1; + uint64_t reserved_25_63:39; +#endif + } cn68xx; + struct cvmx_gmxx_tx_int_en_cn68xx cn68xxp1; + struct cvmx_gmxx_tx_int_en_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t xchange:1; + uint64_t reserved_22_23:2; + uint64_t ptp_lost:2; + uint64_t reserved_18_19:2; + uint64_t late_col:2; + uint64_t reserved_14_15:2; + uint64_t xsdef:2; + uint64_t reserved_10_11:2; + uint64_t xscol:2; + uint64_t reserved_4_7:4; + uint64_t undflw:2; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:2; + uint64_t reserved_4_7:4; + uint64_t xscol:2; + uint64_t reserved_10_11:2; + uint64_t xsdef:2; + uint64_t reserved_14_15:2; + uint64_t late_col:2; + uint64_t reserved_18_19:2; + uint64_t ptp_lost:2; + uint64_t reserved_22_23:2; + uint64_t xchange:1; + uint64_t reserved_25_63:39; +#endif + } cnf71xx; }; union cvmx_gmxx_tx_int_reg { uint64_t u64; struct cvmx_gmxx_tx_int_reg_s { - uint64_t reserved_20_63:44; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t xchange:1; + uint64_t ptp_lost:4; uint64_t late_col:4; uint64_t xsdef:4; uint64_t xscol:4; uint64_t reserved_6_7:2; uint64_t undflw:4; - uint64_t ncb_nxa:1; + uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t ptp_lost:4; + uint64_t xchange:1; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_gmxx_tx_int_reg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t late_col:3; uint64_t reserved_15_15:1; @@ -2261,8 +6334,21 @@ union cvmx_gmxx_tx_int_reg { uint64_t undflw:3; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:3; + uint64_t reserved_5_7:3; + uint64_t xscol:3; + uint64_t reserved_11_11:1; + uint64_t xsdef:3; + uint64_t reserved_15_15:1; + uint64_t late_col:3; + uint64_t reserved_19_63:45; +#endif } cn30xx; struct cvmx_gmxx_tx_int_reg_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t xsdef:3; uint64_t reserved_11_11:1; @@ -2271,9 +6357,40 @@ union cvmx_gmxx_tx_int_reg { uint64_t undflw:3; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:3; + uint64_t reserved_5_7:3; + uint64_t xscol:3; + uint64_t reserved_11_11:1; + uint64_t xsdef:3; + uint64_t reserved_15_63:49; +#endif } cn31xx; - struct cvmx_gmxx_tx_int_reg_s cn38xx; + struct cvmx_gmxx_tx_int_reg_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t ncb_nxa:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t ncb_nxa:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t reserved_20_63:44; +#endif + } cn38xx; struct cvmx_gmxx_tx_int_reg_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t xsdef:4; uint64_t xscol:4; @@ -2281,9 +6398,19 @@ union cvmx_gmxx_tx_int_reg { uint64_t undflw:4; uint64_t ncb_nxa:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t ncb_nxa:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t reserved_16_63:48; +#endif } cn38xxp2; struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx; struct cvmx_gmxx_tx_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t late_col:4; uint64_t xsdef:4; @@ -2292,19 +6419,119 @@ union cvmx_gmxx_tx_int_reg { uint64_t undflw:4; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1; struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx; struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1; - struct cvmx_gmxx_tx_int_reg_s cn58xx; - struct cvmx_gmxx_tx_int_reg_s cn58xxp1; + struct cvmx_gmxx_tx_int_reg_cn38xx cn58xx; + struct cvmx_gmxx_tx_int_reg_cn38xx cn58xxp1; + struct cvmx_gmxx_tx_int_reg_s cn61xx; + struct cvmx_gmxx_tx_int_reg_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_24_63:40; + uint64_t ptp_lost:4; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t ptp_lost:4; + uint64_t reserved_24_63:40; +#endif + } cn63xx; + struct cvmx_gmxx_tx_int_reg_cn63xx cn63xxp1; + struct cvmx_gmxx_tx_int_reg_s cn66xx; + struct cvmx_gmxx_tx_int_reg_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t xchange:1; + uint64_t ptp_lost:4; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t pko_nxp:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t pko_nxp:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t ptp_lost:4; + uint64_t xchange:1; + uint64_t reserved_25_63:39; +#endif + } cn68xx; + struct cvmx_gmxx_tx_int_reg_cn68xx cn68xxp1; + struct cvmx_gmxx_tx_int_reg_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t xchange:1; + uint64_t reserved_22_23:2; + uint64_t ptp_lost:2; + uint64_t reserved_18_19:2; + uint64_t late_col:2; + uint64_t reserved_14_15:2; + uint64_t xsdef:2; + uint64_t reserved_10_11:2; + uint64_t xscol:2; + uint64_t reserved_4_7:4; + uint64_t undflw:2; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:2; + uint64_t reserved_4_7:4; + uint64_t xscol:2; + uint64_t reserved_10_11:2; + uint64_t xsdef:2; + uint64_t reserved_14_15:2; + uint64_t late_col:2; + uint64_t reserved_18_19:2; + uint64_t ptp_lost:2; + uint64_t reserved_22_23:2; + uint64_t xchange:1; + uint64_t reserved_25_63:39; +#endif + } cnf71xx; }; union cvmx_gmxx_tx_jam { uint64_t u64; struct cvmx_gmxx_tx_jam_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t jam:8; +#else + uint64_t jam:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_gmxx_tx_jam_s cn30xx; struct cvmx_gmxx_tx_jam_s cn31xx; @@ -2317,13 +6544,25 @@ union cvmx_gmxx_tx_jam { struct cvmx_gmxx_tx_jam_s cn56xxp1; struct cvmx_gmxx_tx_jam_s cn58xx; struct cvmx_gmxx_tx_jam_s cn58xxp1; + struct cvmx_gmxx_tx_jam_s cn61xx; + struct cvmx_gmxx_tx_jam_s cn63xx; + struct cvmx_gmxx_tx_jam_s cn63xxp1; + struct cvmx_gmxx_tx_jam_s cn66xx; + struct cvmx_gmxx_tx_jam_s cn68xx; + struct cvmx_gmxx_tx_jam_s cn68xxp1; + struct cvmx_gmxx_tx_jam_s cnf71xx; }; union cvmx_gmxx_tx_lfsr { uint64_t u64; struct cvmx_gmxx_tx_lfsr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t lfsr:16; +#else + uint64_t lfsr:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_tx_lfsr_s cn30xx; struct cvmx_gmxx_tx_lfsr_s cn31xx; @@ -2336,32 +6575,64 @@ union cvmx_gmxx_tx_lfsr { struct cvmx_gmxx_tx_lfsr_s cn56xxp1; struct cvmx_gmxx_tx_lfsr_s cn58xx; struct cvmx_gmxx_tx_lfsr_s cn58xxp1; + struct cvmx_gmxx_tx_lfsr_s cn61xx; + struct cvmx_gmxx_tx_lfsr_s cn63xx; + struct cvmx_gmxx_tx_lfsr_s cn63xxp1; + struct cvmx_gmxx_tx_lfsr_s cn66xx; + struct cvmx_gmxx_tx_lfsr_s cn68xx; + struct cvmx_gmxx_tx_lfsr_s cn68xxp1; + struct cvmx_gmxx_tx_lfsr_s cnf71xx; }; union cvmx_gmxx_tx_ovr_bp { uint64_t u64; struct cvmx_gmxx_tx_ovr_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t tx_prt_bp:16; uint64_t reserved_12_31:20; uint64_t en:4; uint64_t bp:4; uint64_t ign_full:4; +#else + uint64_t ign_full:4; + uint64_t bp:4; + uint64_t en:4; + uint64_t reserved_12_31:20; + uint64_t tx_prt_bp:16; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_tx_ovr_bp_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t en:3; uint64_t reserved_7_7:1; uint64_t bp:3; uint64_t reserved_3_3:1; uint64_t ign_full:3; +#else + uint64_t ign_full:3; + uint64_t reserved_3_3:1; + uint64_t bp:3; + uint64_t reserved_7_7:1; + uint64_t en:3; + uint64_t reserved_11_63:53; +#endif } cn30xx; struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx; struct cvmx_gmxx_tx_ovr_bp_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t en:4; uint64_t bp:4; uint64_t ign_full:4; +#else + uint64_t ign_full:4; + uint64_t bp:4; + uint64_t en:4; + uint64_t reserved_12_63:52; +#endif } cn38xx; struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2; struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx; @@ -2371,13 +6642,45 @@ union cvmx_gmxx_tx_ovr_bp { struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1; struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx; struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1; + struct cvmx_gmxx_tx_ovr_bp_s cn61xx; + struct cvmx_gmxx_tx_ovr_bp_s cn63xx; + struct cvmx_gmxx_tx_ovr_bp_s cn63xxp1; + struct cvmx_gmxx_tx_ovr_bp_s cn66xx; + struct cvmx_gmxx_tx_ovr_bp_s cn68xx; + struct cvmx_gmxx_tx_ovr_bp_s cn68xxp1; + struct cvmx_gmxx_tx_ovr_bp_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t tx_prt_bp:16; + uint64_t reserved_10_31:22; + uint64_t en:2; + uint64_t reserved_6_7:2; + uint64_t bp:2; + uint64_t reserved_2_3:2; + uint64_t ign_full:2; +#else + uint64_t ign_full:2; + uint64_t reserved_2_3:2; + uint64_t bp:2; + uint64_t reserved_6_7:2; + uint64_t en:2; + uint64_t reserved_10_31:22; + uint64_t tx_prt_bp:16; + uint64_t reserved_48_63:16; +#endif + } cnf71xx; }; union cvmx_gmxx_tx_pause_pkt_dmac { uint64_t u64; struct cvmx_gmxx_tx_pause_pkt_dmac_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t dmac:48; +#else + uint64_t dmac:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx; struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx; @@ -2390,13 +6693,25 @@ union cvmx_gmxx_tx_pause_pkt_dmac { struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1; struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx; struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn61xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xxp1; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn66xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xxp1; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cnf71xx; }; union cvmx_gmxx_tx_pause_pkt_type { uint64_t u64; struct cvmx_gmxx_tx_pause_pkt_type_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t type:16; +#else + uint64_t type:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx; struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx; @@ -2409,13 +6724,25 @@ union cvmx_gmxx_tx_pause_pkt_type { struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1; struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx; struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1; + struct cvmx_gmxx_tx_pause_pkt_type_s cn61xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn63xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn63xxp1; + struct cvmx_gmxx_tx_pause_pkt_type_s cn66xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn68xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn68xxp1; + struct cvmx_gmxx_tx_pause_pkt_type_s cnf71xx; }; union cvmx_gmxx_tx_prts { uint64_t u64; struct cvmx_gmxx_tx_prts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t prts:5; +#else + uint64_t prts:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_gmxx_tx_prts_s cn30xx; struct cvmx_gmxx_tx_prts_s cn31xx; @@ -2428,14 +6755,27 @@ union cvmx_gmxx_tx_prts { struct cvmx_gmxx_tx_prts_s cn56xxp1; struct cvmx_gmxx_tx_prts_s cn58xx; struct cvmx_gmxx_tx_prts_s cn58xxp1; + struct cvmx_gmxx_tx_prts_s cn61xx; + struct cvmx_gmxx_tx_prts_s cn63xx; + struct cvmx_gmxx_tx_prts_s cn63xxp1; + struct cvmx_gmxx_tx_prts_s cn66xx; + struct cvmx_gmxx_tx_prts_s cn68xx; + struct cvmx_gmxx_tx_prts_s cn68xxp1; + struct cvmx_gmxx_tx_prts_s cnf71xx; }; union cvmx_gmxx_tx_spi_ctl { uint64_t u64; struct cvmx_gmxx_tx_spi_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t tpa_clr:1; uint64_t cont_pkt:1; +#else + uint64_t cont_pkt:1; + uint64_t tpa_clr:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_gmxx_tx_spi_ctl_s cn38xx; struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2; @@ -2446,8 +6786,13 @@ union cvmx_gmxx_tx_spi_ctl { union cvmx_gmxx_tx_spi_drain { uint64_t u64; struct cvmx_gmxx_tx_spi_drain_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t drain:16; +#else + uint64_t drain:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_tx_spi_drain_s cn38xx; struct cvmx_gmxx_tx_spi_drain_s cn58xx; @@ -2457,15 +6802,28 @@ union cvmx_gmxx_tx_spi_drain { union cvmx_gmxx_tx_spi_max { uint64_t u64; struct cvmx_gmxx_tx_spi_max_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t slice:7; uint64_t max2:8; uint64_t max1:8; +#else + uint64_t max1:8; + uint64_t max2:8; + uint64_t slice:7; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_gmxx_tx_spi_max_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t max2:8; uint64_t max1:8; +#else + uint64_t max1:8; + uint64_t max2:8; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2; struct cvmx_gmxx_tx_spi_max_s cn58xx; @@ -2475,8 +6833,13 @@ union cvmx_gmxx_tx_spi_max { union cvmx_gmxx_tx_spi_roundx { uint64_t u64; struct cvmx_gmxx_tx_spi_roundx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t round:16; +#else + uint64_t round:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_tx_spi_roundx_s cn58xx; struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1; @@ -2485,8 +6848,13 @@ union cvmx_gmxx_tx_spi_roundx { union cvmx_gmxx_tx_spi_thresh { uint64_t u64; struct cvmx_gmxx_tx_spi_thresh_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t thresh:6; +#else + uint64_t thresh:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_gmxx_tx_spi_thresh_s cn38xx; struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2; @@ -2497,6 +6865,7 @@ union cvmx_gmxx_tx_spi_thresh { union cvmx_gmxx_tx_xaui_ctl { uint64_t u64; struct cvmx_gmxx_tx_xaui_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t hg_pause_hgi:2; uint64_t hg_en:1; @@ -2506,24 +6875,55 @@ union cvmx_gmxx_tx_xaui_ctl { uint64_t reserved_2_3:2; uint64_t uni_en:1; uint64_t dic_en:1; +#else + uint64_t dic_en:1; + uint64_t uni_en:1; + uint64_t reserved_2_3:2; + uint64_t ls:2; + uint64_t ls_byp:1; + uint64_t reserved_7_7:1; + uint64_t hg_en:1; + uint64_t hg_pause_hgi:2; + uint64_t reserved_11_63:53; +#endif } s; struct cvmx_gmxx_tx_xaui_ctl_s cn52xx; struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1; struct cvmx_gmxx_tx_xaui_ctl_s cn56xx; struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1; + struct cvmx_gmxx_tx_xaui_ctl_s cn61xx; + struct cvmx_gmxx_tx_xaui_ctl_s cn63xx; + struct cvmx_gmxx_tx_xaui_ctl_s cn63xxp1; + struct cvmx_gmxx_tx_xaui_ctl_s cn66xx; + struct cvmx_gmxx_tx_xaui_ctl_s cn68xx; + struct cvmx_gmxx_tx_xaui_ctl_s cn68xxp1; + struct cvmx_gmxx_tx_xaui_ctl_s cnf71xx; }; union cvmx_gmxx_xaui_ext_loopback { uint64_t u64; struct cvmx_gmxx_xaui_ext_loopback_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t en:1; uint64_t thresh:4; +#else + uint64_t thresh:4; + uint64_t en:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_gmxx_xaui_ext_loopback_s cn52xx; struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1; struct cvmx_gmxx_xaui_ext_loopback_s cn56xx; struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1; + struct cvmx_gmxx_xaui_ext_loopback_s cn61xx; + struct cvmx_gmxx_xaui_ext_loopback_s cn63xx; + struct cvmx_gmxx_xaui_ext_loopback_s cn63xxp1; + struct cvmx_gmxx_xaui_ext_loopback_s cn66xx; + struct cvmx_gmxx_xaui_ext_loopback_s cn68xx; + struct cvmx_gmxx_xaui_ext_loopback_s cn68xxp1; + struct cvmx_gmxx_xaui_ext_loopback_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h index 395564e8d1f0..4719fcfa8865 100644 --- a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -34,7 +34,10 @@ #define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8) #define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) #define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull)) +#define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull)) +#define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull)) #define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull)) +#define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) #define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull)) #define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull)) #define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16) @@ -42,6 +45,7 @@ union cvmx_gpio_bit_cfgx { uint64_t u64; struct cvmx_gpio_bit_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t synce_sel:2; uint64_t clk_gen:1; @@ -52,8 +56,21 @@ union cvmx_gpio_bit_cfgx { uint64_t int_en:1; uint64_t rx_xor:1; uint64_t tx_oe:1; +#else + uint64_t tx_oe:1; + uint64_t rx_xor:1; + uint64_t int_en:1; + uint64_t int_type:1; + uint64_t fil_cnt:4; + uint64_t fil_sel:4; + uint64_t clk_sel:2; + uint64_t clk_gen:1; + uint64_t synce_sel:2; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_gpio_bit_cfgx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t fil_sel:4; uint64_t fil_cnt:4; @@ -61,12 +78,22 @@ union cvmx_gpio_bit_cfgx { uint64_t int_en:1; uint64_t rx_xor:1; uint64_t tx_oe:1; +#else + uint64_t tx_oe:1; + uint64_t rx_xor:1; + uint64_t int_en:1; + uint64_t int_type:1; + uint64_t fil_cnt:4; + uint64_t fil_sel:4; + uint64_t reserved_12_63:52; +#endif } cn30xx; struct cvmx_gpio_bit_cfgx_cn30xx cn31xx; struct cvmx_gpio_bit_cfgx_cn30xx cn38xx; struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2; struct cvmx_gpio_bit_cfgx_cn30xx cn50xx; struct cvmx_gpio_bit_cfgx_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t clk_gen:1; uint64_t clk_sel:2; @@ -76,22 +103,44 @@ union cvmx_gpio_bit_cfgx { uint64_t int_en:1; uint64_t rx_xor:1; uint64_t tx_oe:1; +#else + uint64_t tx_oe:1; + uint64_t rx_xor:1; + uint64_t int_en:1; + uint64_t int_type:1; + uint64_t fil_cnt:4; + uint64_t fil_sel:4; + uint64_t clk_sel:2; + uint64_t clk_gen:1; + uint64_t reserved_15_63:49; +#endif } cn52xx; struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1; struct cvmx_gpio_bit_cfgx_cn52xx cn56xx; struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1; struct cvmx_gpio_bit_cfgx_cn30xx cn58xx; struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1; + struct cvmx_gpio_bit_cfgx_s cn61xx; struct cvmx_gpio_bit_cfgx_s cn63xx; struct cvmx_gpio_bit_cfgx_s cn63xxp1; + struct cvmx_gpio_bit_cfgx_s cn66xx; + struct cvmx_gpio_bit_cfgx_s cn68xx; + struct cvmx_gpio_bit_cfgx_s cn68xxp1; + struct cvmx_gpio_bit_cfgx_s cnf71xx; }; union cvmx_gpio_boot_ena { uint64_t u64; struct cvmx_gpio_boot_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t boot_ena:4; uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t boot_ena:4; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_gpio_boot_ena_s cn30xx; struct cvmx_gpio_boot_ena_s cn31xx; @@ -101,33 +150,87 @@ union cvmx_gpio_boot_ena { union cvmx_gpio_clk_genx { uint64_t u64; struct cvmx_gpio_clk_genx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t n:32; +#else + uint64_t n:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gpio_clk_genx_s cn52xx; struct cvmx_gpio_clk_genx_s cn52xxp1; struct cvmx_gpio_clk_genx_s cn56xx; struct cvmx_gpio_clk_genx_s cn56xxp1; + struct cvmx_gpio_clk_genx_s cn61xx; struct cvmx_gpio_clk_genx_s cn63xx; struct cvmx_gpio_clk_genx_s cn63xxp1; + struct cvmx_gpio_clk_genx_s cn66xx; + struct cvmx_gpio_clk_genx_s cn68xx; + struct cvmx_gpio_clk_genx_s cn68xxp1; + struct cvmx_gpio_clk_genx_s cnf71xx; }; union cvmx_gpio_clk_qlmx { uint64_t u64; struct cvmx_gpio_clk_qlmx_s { - uint64_t reserved_3_63:61; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t qlm_sel:3; + uint64_t reserved_3_7:5; uint64_t div:1; uint64_t lane_sel:2; +#else + uint64_t lane_sel:2; + uint64_t div:1; + uint64_t reserved_3_7:5; + uint64_t qlm_sel:3; + uint64_t reserved_11_63:53; +#endif } s; - struct cvmx_gpio_clk_qlmx_s cn63xx; - struct cvmx_gpio_clk_qlmx_s cn63xxp1; + struct cvmx_gpio_clk_qlmx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t qlm_sel:2; + uint64_t reserved_3_7:5; + uint64_t div:1; + uint64_t lane_sel:2; +#else + uint64_t lane_sel:2; + uint64_t div:1; + uint64_t reserved_3_7:5; + uint64_t qlm_sel:2; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_gpio_clk_qlmx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t div:1; + uint64_t lane_sel:2; +#else + uint64_t lane_sel:2; + uint64_t div:1; + uint64_t reserved_3_63:61; +#endif + } cn63xx; + struct cvmx_gpio_clk_qlmx_cn63xx cn63xxp1; + struct cvmx_gpio_clk_qlmx_cn61xx cn66xx; + struct cvmx_gpio_clk_qlmx_s cn68xx; + struct cvmx_gpio_clk_qlmx_s cn68xxp1; + struct cvmx_gpio_clk_qlmx_cn61xx cnf71xx; }; union cvmx_gpio_dbg_ena { uint64_t u64; struct cvmx_gpio_dbg_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t dbg_ena:21; +#else + uint64_t dbg_ena:21; + uint64_t reserved_21_63:43; +#endif } s; struct cvmx_gpio_dbg_ena_s cn30xx; struct cvmx_gpio_dbg_ena_s cn31xx; @@ -137,8 +240,13 @@ union cvmx_gpio_dbg_ena { union cvmx_gpio_int_clr { uint64_t u64; struct cvmx_gpio_int_clr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t type:16; +#else + uint64_t type:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gpio_int_clr_s cn30xx; struct cvmx_gpio_int_clr_s cn31xx; @@ -151,21 +259,69 @@ union cvmx_gpio_int_clr { struct cvmx_gpio_int_clr_s cn56xxp1; struct cvmx_gpio_int_clr_s cn58xx; struct cvmx_gpio_int_clr_s cn58xxp1; + struct cvmx_gpio_int_clr_s cn61xx; struct cvmx_gpio_int_clr_s cn63xx; struct cvmx_gpio_int_clr_s cn63xxp1; + struct cvmx_gpio_int_clr_s cn66xx; + struct cvmx_gpio_int_clr_s cn68xx; + struct cvmx_gpio_int_clr_s cn68xxp1; + struct cvmx_gpio_int_clr_s cnf71xx; +}; + +union cvmx_gpio_multi_cast { + uint64_t u64; + struct cvmx_gpio_multi_cast_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t en:1; +#else + uint64_t en:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_gpio_multi_cast_s cn61xx; + struct cvmx_gpio_multi_cast_s cnf71xx; +}; + +union cvmx_gpio_pin_ena { + uint64_t u64; + struct cvmx_gpio_pin_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t ena19:1; + uint64_t ena18:1; + uint64_t reserved_0_17:18; +#else + uint64_t reserved_0_17:18; + uint64_t ena18:1; + uint64_t ena19:1; + uint64_t reserved_20_63:44; +#endif + } s; + struct cvmx_gpio_pin_ena_s cn66xx; }; union cvmx_gpio_rx_dat { uint64_t u64; struct cvmx_gpio_rx_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t dat:24; +#else + uint64_t dat:24; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_gpio_rx_dat_s cn30xx; struct cvmx_gpio_rx_dat_s cn31xx; struct cvmx_gpio_rx_dat_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dat:16; +#else + uint64_t dat:16; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_gpio_rx_dat_cn38xx cn38xxp2; struct cvmx_gpio_rx_dat_s cn50xx; @@ -175,21 +331,59 @@ union cvmx_gpio_rx_dat { struct cvmx_gpio_rx_dat_cn38xx cn56xxp1; struct cvmx_gpio_rx_dat_cn38xx cn58xx; struct cvmx_gpio_rx_dat_cn38xx cn58xxp1; + struct cvmx_gpio_rx_dat_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t dat:20; +#else + uint64_t dat:20; + uint64_t reserved_20_63:44; +#endif + } cn61xx; struct cvmx_gpio_rx_dat_cn38xx cn63xx; struct cvmx_gpio_rx_dat_cn38xx cn63xxp1; + struct cvmx_gpio_rx_dat_cn61xx cn66xx; + struct cvmx_gpio_rx_dat_cn38xx cn68xx; + struct cvmx_gpio_rx_dat_cn38xx cn68xxp1; + struct cvmx_gpio_rx_dat_cn61xx cnf71xx; +}; + +union cvmx_gpio_tim_ctl { + uint64_t u64; + struct cvmx_gpio_tim_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t sel:4; +#else + uint64_t sel:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_gpio_tim_ctl_s cn68xx; + struct cvmx_gpio_tim_ctl_s cn68xxp1; }; union cvmx_gpio_tx_clr { uint64_t u64; struct cvmx_gpio_tx_clr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t clr:24; +#else + uint64_t clr:24; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_gpio_tx_clr_s cn30xx; struct cvmx_gpio_tx_clr_s cn31xx; struct cvmx_gpio_tx_clr_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t clr:16; +#else + uint64_t clr:16; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_gpio_tx_clr_cn38xx cn38xxp2; struct cvmx_gpio_tx_clr_s cn50xx; @@ -199,21 +393,44 @@ union cvmx_gpio_tx_clr { struct cvmx_gpio_tx_clr_cn38xx cn56xxp1; struct cvmx_gpio_tx_clr_cn38xx cn58xx; struct cvmx_gpio_tx_clr_cn38xx cn58xxp1; + struct cvmx_gpio_tx_clr_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t clr:20; +#else + uint64_t clr:20; + uint64_t reserved_20_63:44; +#endif + } cn61xx; struct cvmx_gpio_tx_clr_cn38xx cn63xx; struct cvmx_gpio_tx_clr_cn38xx cn63xxp1; + struct cvmx_gpio_tx_clr_cn61xx cn66xx; + struct cvmx_gpio_tx_clr_cn38xx cn68xx; + struct cvmx_gpio_tx_clr_cn38xx cn68xxp1; + struct cvmx_gpio_tx_clr_cn61xx cnf71xx; }; union cvmx_gpio_tx_set { uint64_t u64; struct cvmx_gpio_tx_set_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t set:24; +#else + uint64_t set:24; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_gpio_tx_set_s cn30xx; struct cvmx_gpio_tx_set_s cn31xx; struct cvmx_gpio_tx_set_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t set:16; +#else + uint64_t set:16; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_gpio_tx_set_cn38xx cn38xxp2; struct cvmx_gpio_tx_set_s cn50xx; @@ -223,23 +440,72 @@ union cvmx_gpio_tx_set { struct cvmx_gpio_tx_set_cn38xx cn56xxp1; struct cvmx_gpio_tx_set_cn38xx cn58xx; struct cvmx_gpio_tx_set_cn38xx cn58xxp1; + struct cvmx_gpio_tx_set_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t set:20; +#else + uint64_t set:20; + uint64_t reserved_20_63:44; +#endif + } cn61xx; struct cvmx_gpio_tx_set_cn38xx cn63xx; struct cvmx_gpio_tx_set_cn38xx cn63xxp1; + struct cvmx_gpio_tx_set_cn61xx cn66xx; + struct cvmx_gpio_tx_set_cn38xx cn68xx; + struct cvmx_gpio_tx_set_cn38xx cn68xxp1; + struct cvmx_gpio_tx_set_cn61xx cnf71xx; }; union cvmx_gpio_xbit_cfgx { uint64_t u64; struct cvmx_gpio_xbit_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_17_63:47; + uint64_t synce_sel:2; + uint64_t clk_gen:1; + uint64_t clk_sel:2; + uint64_t fil_sel:4; + uint64_t fil_cnt:4; + uint64_t int_type:1; + uint64_t int_en:1; + uint64_t rx_xor:1; + uint64_t tx_oe:1; +#else + uint64_t tx_oe:1; + uint64_t rx_xor:1; + uint64_t int_en:1; + uint64_t int_type:1; + uint64_t fil_cnt:4; + uint64_t fil_sel:4; + uint64_t clk_sel:2; + uint64_t clk_gen:1; + uint64_t synce_sel:2; + uint64_t reserved_17_63:47; +#endif + } s; + struct cvmx_gpio_xbit_cfgx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t fil_sel:4; uint64_t fil_cnt:4; uint64_t reserved_2_3:2; uint64_t rx_xor:1; uint64_t tx_oe:1; - } s; - struct cvmx_gpio_xbit_cfgx_s cn30xx; - struct cvmx_gpio_xbit_cfgx_s cn31xx; - struct cvmx_gpio_xbit_cfgx_s cn50xx; +#else + uint64_t tx_oe:1; + uint64_t rx_xor:1; + uint64_t reserved_2_3:2; + uint64_t fil_cnt:4; + uint64_t fil_sel:4; + uint64_t reserved_12_63:52; +#endif + } cn30xx; + struct cvmx_gpio_xbit_cfgx_cn30xx cn31xx; + struct cvmx_gpio_xbit_cfgx_cn30xx cn50xx; + struct cvmx_gpio_xbit_cfgx_s cn61xx; + struct cvmx_gpio_xbit_cfgx_s cn66xx; + struct cvmx_gpio_xbit_cfgx_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-iob-defs.h b/arch/mips/include/asm/octeon/cvmx-iob-defs.h index d7d856c2483d..7936f816e93e 100644 --- a/arch/mips/include/asm/octeon/cvmx-iob-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-iob-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -51,10 +51,86 @@ #define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull)) #define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull)) #define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull)) +#define CVMX_IOB_TO_NCB_DID_00_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000800ull)) +#define CVMX_IOB_TO_NCB_DID_111_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B78ull)) +#define CVMX_IOB_TO_NCB_DID_223_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000EF8ull)) +#define CVMX_IOB_TO_NCB_DID_24_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00008C0ull)) +#define CVMX_IOB_TO_NCB_DID_32_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000900ull)) +#define CVMX_IOB_TO_NCB_DID_40_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000940ull)) +#define CVMX_IOB_TO_NCB_DID_55_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00009B8ull)) +#define CVMX_IOB_TO_NCB_DID_64_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A00ull)) +#define CVMX_IOB_TO_NCB_DID_79_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A78ull)) +#define CVMX_IOB_TO_NCB_DID_96_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B00ull)) +#define CVMX_IOB_TO_NCB_DID_98_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B10ull)) union cvmx_iob_bist_status { uint64_t u64; struct cvmx_iob_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_2_63:62; + uint64_t ibd:1; + uint64_t icd:1; +#else + uint64_t icd:1; + uint64_t ibd:1; + uint64_t reserved_2_63:62; +#endif + } s; + struct cvmx_iob_bist_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t icnrcb:1; + uint64_t icr0:1; + uint64_t icr1:1; + uint64_t icnr1:1; + uint64_t icnr0:1; + uint64_t ibdr0:1; + uint64_t ibdr1:1; + uint64_t ibr0:1; + uint64_t ibr1:1; + uint64_t icnrt:1; + uint64_t ibrq0:1; + uint64_t ibrq1:1; + uint64_t icrn0:1; + uint64_t icrn1:1; + uint64_t icrp0:1; + uint64_t icrp1:1; + uint64_t ibd:1; + uint64_t icd:1; +#else + uint64_t icd:1; + uint64_t ibd:1; + uint64_t icrp1:1; + uint64_t icrp0:1; + uint64_t icrn1:1; + uint64_t icrn0:1; + uint64_t ibrq1:1; + uint64_t ibrq0:1; + uint64_t icnrt:1; + uint64_t ibr1:1; + uint64_t ibr0:1; + uint64_t ibdr1:1; + uint64_t ibdr0:1; + uint64_t icnr0:1; + uint64_t icnr1:1; + uint64_t icr1:1; + uint64_t icr0:1; + uint64_t icnrcb:1; + uint64_t reserved_18_63:46; +#endif + } cn30xx; + struct cvmx_iob_bist_status_cn30xx cn31xx; + struct cvmx_iob_bist_status_cn30xx cn38xx; + struct cvmx_iob_bist_status_cn30xx cn38xxp2; + struct cvmx_iob_bist_status_cn30xx cn50xx; + struct cvmx_iob_bist_status_cn30xx cn52xx; + struct cvmx_iob_bist_status_cn30xx cn52xxp1; + struct cvmx_iob_bist_status_cn30xx cn56xx; + struct cvmx_iob_bist_status_cn30xx cn56xxp1; + struct cvmx_iob_bist_status_cn30xx cn58xx; + struct cvmx_iob_bist_status_cn30xx cn58xxp1; + struct cvmx_iob_bist_status_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t xmdfif:1; uint64_t xmcfif:1; @@ -79,16 +155,48 @@ union cvmx_iob_bist_status { uint64_t icrp1:1; uint64_t ibd:1; uint64_t icd:1; - } s; - struct cvmx_iob_bist_status_cn30xx { +#else + uint64_t icd:1; + uint64_t ibd:1; + uint64_t icrp1:1; + uint64_t icrp0:1; + uint64_t icrn1:1; + uint64_t icrn0:1; + uint64_t ibrq1:1; + uint64_t ibrq0:1; + uint64_t icnrt:1; + uint64_t ibr1:1; + uint64_t ibr0:1; + uint64_t ibdr1:1; + uint64_t ibdr0:1; + uint64_t icnr0:1; + uint64_t icnr1:1; + uint64_t icr1:1; + uint64_t icr0:1; + uint64_t icnrcb:1; + uint64_t iocfif:1; + uint64_t rsdfif:1; + uint64_t iorfif:1; + uint64_t xmcfif:1; + uint64_t xmdfif:1; + uint64_t reserved_23_63:41; +#endif + } cn61xx; + struct cvmx_iob_bist_status_cn61xx cn63xx; + struct cvmx_iob_bist_status_cn61xx cn63xxp1; + struct cvmx_iob_bist_status_cn61xx cn66xx; + struct cvmx_iob_bist_status_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; + uint64_t xmdfif:1; + uint64_t xmcfif:1; + uint64_t iorfif:1; + uint64_t rsdfif:1; + uint64_t iocfif:1; uint64_t icnrcb:1; uint64_t icr0:1; uint64_t icr1:1; - uint64_t icnr1:1; uint64_t icnr0:1; - uint64_t ibdr0:1; - uint64_t ibdr1:1; uint64_t ibr0:1; uint64_t ibr1:1; uint64_t icnrt:1; @@ -96,50 +204,82 @@ union cvmx_iob_bist_status { uint64_t ibrq1:1; uint64_t icrn0:1; uint64_t icrn1:1; - uint64_t icrp0:1; - uint64_t icrp1:1; uint64_t ibd:1; uint64_t icd:1; - } cn30xx; - struct cvmx_iob_bist_status_cn30xx cn31xx; - struct cvmx_iob_bist_status_cn30xx cn38xx; - struct cvmx_iob_bist_status_cn30xx cn38xxp2; - struct cvmx_iob_bist_status_cn30xx cn50xx; - struct cvmx_iob_bist_status_cn30xx cn52xx; - struct cvmx_iob_bist_status_cn30xx cn52xxp1; - struct cvmx_iob_bist_status_cn30xx cn56xx; - struct cvmx_iob_bist_status_cn30xx cn56xxp1; - struct cvmx_iob_bist_status_cn30xx cn58xx; - struct cvmx_iob_bist_status_cn30xx cn58xxp1; - struct cvmx_iob_bist_status_s cn63xx; - struct cvmx_iob_bist_status_s cn63xxp1; +#else + uint64_t icd:1; + uint64_t ibd:1; + uint64_t icrn1:1; + uint64_t icrn0:1; + uint64_t ibrq1:1; + uint64_t ibrq0:1; + uint64_t icnrt:1; + uint64_t ibr1:1; + uint64_t ibr0:1; + uint64_t icnr0:1; + uint64_t icr1:1; + uint64_t icr0:1; + uint64_t icnrcb:1; + uint64_t iocfif:1; + uint64_t rsdfif:1; + uint64_t iorfif:1; + uint64_t xmcfif:1; + uint64_t xmdfif:1; + uint64_t reserved_18_63:46; +#endif + } cn68xx; + struct cvmx_iob_bist_status_cn68xx cn68xxp1; + struct cvmx_iob_bist_status_cn61xx cnf71xx; }; union cvmx_iob_ctl_status { uint64_t u64; struct cvmx_iob_ctl_status_s { - uint64_t reserved_10_63:54; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t fif_dly:1; uint64_t xmc_per:4; - uint64_t rr_mode:1; + uint64_t reserved_5_5:1; uint64_t outb_mat:1; uint64_t inb_mat:1; uint64_t pko_enb:1; uint64_t dwb_enb:1; uint64_t fau_end:1; +#else + uint64_t fau_end:1; + uint64_t dwb_enb:1; + uint64_t pko_enb:1; + uint64_t inb_mat:1; + uint64_t outb_mat:1; + uint64_t reserved_5_5:1; + uint64_t xmc_per:4; + uint64_t fif_dly:1; + uint64_t reserved_11_63:53; +#endif } s; struct cvmx_iob_ctl_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t outb_mat:1; uint64_t inb_mat:1; uint64_t pko_enb:1; uint64_t dwb_enb:1; uint64_t fau_end:1; +#else + uint64_t fau_end:1; + uint64_t dwb_enb:1; + uint64_t pko_enb:1; + uint64_t inb_mat:1; + uint64_t outb_mat:1; + uint64_t reserved_5_63:59; +#endif } cn30xx; struct cvmx_iob_ctl_status_cn30xx cn31xx; struct cvmx_iob_ctl_status_cn30xx cn38xx; struct cvmx_iob_ctl_status_cn30xx cn38xxp2; struct cvmx_iob_ctl_status_cn30xx cn50xx; struct cvmx_iob_ctl_status_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t rr_mode:1; uint64_t outb_mat:1; @@ -147,22 +287,106 @@ union cvmx_iob_ctl_status { uint64_t pko_enb:1; uint64_t dwb_enb:1; uint64_t fau_end:1; +#else + uint64_t fau_end:1; + uint64_t dwb_enb:1; + uint64_t pko_enb:1; + uint64_t inb_mat:1; + uint64_t outb_mat:1; + uint64_t rr_mode:1; + uint64_t reserved_6_63:58; +#endif } cn52xx; struct cvmx_iob_ctl_status_cn30xx cn52xxp1; struct cvmx_iob_ctl_status_cn30xx cn56xx; struct cvmx_iob_ctl_status_cn30xx cn56xxp1; struct cvmx_iob_ctl_status_cn30xx cn58xx; struct cvmx_iob_ctl_status_cn30xx cn58xxp1; - struct cvmx_iob_ctl_status_s cn63xx; - struct cvmx_iob_ctl_status_s cn63xxp1; + struct cvmx_iob_ctl_status_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t fif_dly:1; + uint64_t xmc_per:4; + uint64_t rr_mode:1; + uint64_t outb_mat:1; + uint64_t inb_mat:1; + uint64_t pko_enb:1; + uint64_t dwb_enb:1; + uint64_t fau_end:1; +#else + uint64_t fau_end:1; + uint64_t dwb_enb:1; + uint64_t pko_enb:1; + uint64_t inb_mat:1; + uint64_t outb_mat:1; + uint64_t rr_mode:1; + uint64_t xmc_per:4; + uint64_t fif_dly:1; + uint64_t reserved_11_63:53; +#endif + } cn61xx; + struct cvmx_iob_ctl_status_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t xmc_per:4; + uint64_t rr_mode:1; + uint64_t outb_mat:1; + uint64_t inb_mat:1; + uint64_t pko_enb:1; + uint64_t dwb_enb:1; + uint64_t fau_end:1; +#else + uint64_t fau_end:1; + uint64_t dwb_enb:1; + uint64_t pko_enb:1; + uint64_t inb_mat:1; + uint64_t outb_mat:1; + uint64_t rr_mode:1; + uint64_t xmc_per:4; + uint64_t reserved_10_63:54; +#endif + } cn63xx; + struct cvmx_iob_ctl_status_cn63xx cn63xxp1; + struct cvmx_iob_ctl_status_cn61xx cn66xx; + struct cvmx_iob_ctl_status_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t fif_dly:1; + uint64_t xmc_per:4; + uint64_t rsvr5:1; + uint64_t outb_mat:1; + uint64_t inb_mat:1; + uint64_t pko_enb:1; + uint64_t dwb_enb:1; + uint64_t fau_end:1; +#else + uint64_t fau_end:1; + uint64_t dwb_enb:1; + uint64_t pko_enb:1; + uint64_t inb_mat:1; + uint64_t outb_mat:1; + uint64_t rsvr5:1; + uint64_t xmc_per:4; + uint64_t fif_dly:1; + uint64_t reserved_11_63:53; +#endif + } cn68xx; + struct cvmx_iob_ctl_status_cn68xx cn68xxp1; + struct cvmx_iob_ctl_status_cn61xx cnf71xx; }; union cvmx_iob_dwb_pri_cnt { uint64_t u64; struct cvmx_iob_dwb_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_dwb_pri_cnt_s cn38xx; struct cvmx_iob_dwb_pri_cnt_s cn38xxp2; @@ -172,16 +396,25 @@ union cvmx_iob_dwb_pri_cnt { struct cvmx_iob_dwb_pri_cnt_s cn56xxp1; struct cvmx_iob_dwb_pri_cnt_s cn58xx; struct cvmx_iob_dwb_pri_cnt_s cn58xxp1; + struct cvmx_iob_dwb_pri_cnt_s cn61xx; struct cvmx_iob_dwb_pri_cnt_s cn63xx; struct cvmx_iob_dwb_pri_cnt_s cn63xxp1; + struct cvmx_iob_dwb_pri_cnt_s cn66xx; + struct cvmx_iob_dwb_pri_cnt_s cnf71xx; }; union cvmx_iob_fau_timeout { uint64_t u64; struct cvmx_iob_fau_timeout_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t tout_enb:1; uint64_t tout_val:12; +#else + uint64_t tout_val:12; + uint64_t tout_enb:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_iob_fau_timeout_s cn30xx; struct cvmx_iob_fau_timeout_s cn31xx; @@ -194,16 +427,27 @@ union cvmx_iob_fau_timeout { struct cvmx_iob_fau_timeout_s cn56xxp1; struct cvmx_iob_fau_timeout_s cn58xx; struct cvmx_iob_fau_timeout_s cn58xxp1; + struct cvmx_iob_fau_timeout_s cn61xx; struct cvmx_iob_fau_timeout_s cn63xx; struct cvmx_iob_fau_timeout_s cn63xxp1; + struct cvmx_iob_fau_timeout_s cn66xx; + struct cvmx_iob_fau_timeout_s cn68xx; + struct cvmx_iob_fau_timeout_s cn68xxp1; + struct cvmx_iob_fau_timeout_s cnf71xx; }; union cvmx_iob_i2c_pri_cnt { uint64_t u64; struct cvmx_iob_i2c_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_i2c_pri_cnt_s cn38xx; struct cvmx_iob_i2c_pri_cnt_s cn38xxp2; @@ -213,18 +457,29 @@ union cvmx_iob_i2c_pri_cnt { struct cvmx_iob_i2c_pri_cnt_s cn56xxp1; struct cvmx_iob_i2c_pri_cnt_s cn58xx; struct cvmx_iob_i2c_pri_cnt_s cn58xxp1; + struct cvmx_iob_i2c_pri_cnt_s cn61xx; struct cvmx_iob_i2c_pri_cnt_s cn63xx; struct cvmx_iob_i2c_pri_cnt_s cn63xxp1; + struct cvmx_iob_i2c_pri_cnt_s cn66xx; + struct cvmx_iob_i2c_pri_cnt_s cnf71xx; }; union cvmx_iob_inb_control_match { uint64_t u64; struct cvmx_iob_inb_control_match_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t mask:8; uint64_t opc:4; uint64_t dst:9; uint64_t src:8; +#else + uint64_t src:8; + uint64_t dst:9; + uint64_t opc:4; + uint64_t mask:8; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_iob_inb_control_match_s cn30xx; struct cvmx_iob_inb_control_match_s cn31xx; @@ -237,18 +492,31 @@ union cvmx_iob_inb_control_match { struct cvmx_iob_inb_control_match_s cn56xxp1; struct cvmx_iob_inb_control_match_s cn58xx; struct cvmx_iob_inb_control_match_s cn58xxp1; + struct cvmx_iob_inb_control_match_s cn61xx; struct cvmx_iob_inb_control_match_s cn63xx; struct cvmx_iob_inb_control_match_s cn63xxp1; + struct cvmx_iob_inb_control_match_s cn66xx; + struct cvmx_iob_inb_control_match_s cn68xx; + struct cvmx_iob_inb_control_match_s cn68xxp1; + struct cvmx_iob_inb_control_match_s cnf71xx; }; union cvmx_iob_inb_control_match_enb { uint64_t u64; struct cvmx_iob_inb_control_match_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t mask:8; uint64_t opc:4; uint64_t dst:9; uint64_t src:8; +#else + uint64_t src:8; + uint64_t dst:9; + uint64_t opc:4; + uint64_t mask:8; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_iob_inb_control_match_enb_s cn30xx; struct cvmx_iob_inb_control_match_enb_s cn31xx; @@ -261,14 +529,23 @@ union cvmx_iob_inb_control_match_enb { struct cvmx_iob_inb_control_match_enb_s cn56xxp1; struct cvmx_iob_inb_control_match_enb_s cn58xx; struct cvmx_iob_inb_control_match_enb_s cn58xxp1; + struct cvmx_iob_inb_control_match_enb_s cn61xx; struct cvmx_iob_inb_control_match_enb_s cn63xx; struct cvmx_iob_inb_control_match_enb_s cn63xxp1; + struct cvmx_iob_inb_control_match_enb_s cn66xx; + struct cvmx_iob_inb_control_match_enb_s cn68xx; + struct cvmx_iob_inb_control_match_enb_s cn68xxp1; + struct cvmx_iob_inb_control_match_enb_s cnf71xx; }; union cvmx_iob_inb_data_match { uint64_t u64; struct cvmx_iob_inb_data_match_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_iob_inb_data_match_s cn30xx; struct cvmx_iob_inb_data_match_s cn31xx; @@ -281,14 +558,23 @@ union cvmx_iob_inb_data_match { struct cvmx_iob_inb_data_match_s cn56xxp1; struct cvmx_iob_inb_data_match_s cn58xx; struct cvmx_iob_inb_data_match_s cn58xxp1; + struct cvmx_iob_inb_data_match_s cn61xx; struct cvmx_iob_inb_data_match_s cn63xx; struct cvmx_iob_inb_data_match_s cn63xxp1; + struct cvmx_iob_inb_data_match_s cn66xx; + struct cvmx_iob_inb_data_match_s cn68xx; + struct cvmx_iob_inb_data_match_s cn68xxp1; + struct cvmx_iob_inb_data_match_s cnf71xx; }; union cvmx_iob_inb_data_match_enb { uint64_t u64; struct cvmx_iob_inb_data_match_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; +#else + uint64_t data:64; +#endif } s; struct cvmx_iob_inb_data_match_enb_s cn30xx; struct cvmx_iob_inb_data_match_enb_s cn31xx; @@ -301,13 +587,19 @@ union cvmx_iob_inb_data_match_enb { struct cvmx_iob_inb_data_match_enb_s cn56xxp1; struct cvmx_iob_inb_data_match_enb_s cn58xx; struct cvmx_iob_inb_data_match_enb_s cn58xxp1; + struct cvmx_iob_inb_data_match_enb_s cn61xx; struct cvmx_iob_inb_data_match_enb_s cn63xx; struct cvmx_iob_inb_data_match_enb_s cn63xxp1; + struct cvmx_iob_inb_data_match_enb_s cn66xx; + struct cvmx_iob_inb_data_match_enb_s cn68xx; + struct cvmx_iob_inb_data_match_enb_s cn68xxp1; + struct cvmx_iob_inb_data_match_enb_s cnf71xx; }; union cvmx_iob_int_enb { uint64_t u64; struct cvmx_iob_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t p_dat:1; uint64_t np_dat:1; @@ -315,13 +607,30 @@ union cvmx_iob_int_enb { uint64_t p_sop:1; uint64_t np_eop:1; uint64_t np_sop:1; +#else + uint64_t np_sop:1; + uint64_t np_eop:1; + uint64_t p_sop:1; + uint64_t p_eop:1; + uint64_t np_dat:1; + uint64_t p_dat:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_iob_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t p_eop:1; uint64_t p_sop:1; uint64_t np_eop:1; uint64_t np_sop:1; +#else + uint64_t np_sop:1; + uint64_t np_eop:1; + uint64_t p_sop:1; + uint64_t p_eop:1; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_iob_int_enb_cn30xx cn31xx; struct cvmx_iob_int_enb_cn30xx cn38xx; @@ -333,13 +642,25 @@ union cvmx_iob_int_enb { struct cvmx_iob_int_enb_s cn56xxp1; struct cvmx_iob_int_enb_s cn58xx; struct cvmx_iob_int_enb_s cn58xxp1; + struct cvmx_iob_int_enb_s cn61xx; struct cvmx_iob_int_enb_s cn63xx; struct cvmx_iob_int_enb_s cn63xxp1; + struct cvmx_iob_int_enb_s cn66xx; + struct cvmx_iob_int_enb_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif + } cn68xx; + struct cvmx_iob_int_enb_cn68xx cn68xxp1; + struct cvmx_iob_int_enb_s cnf71xx; }; union cvmx_iob_int_sum { uint64_t u64; struct cvmx_iob_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t p_dat:1; uint64_t np_dat:1; @@ -347,13 +668,30 @@ union cvmx_iob_int_sum { uint64_t p_sop:1; uint64_t np_eop:1; uint64_t np_sop:1; +#else + uint64_t np_sop:1; + uint64_t np_eop:1; + uint64_t p_sop:1; + uint64_t p_eop:1; + uint64_t np_dat:1; + uint64_t p_dat:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_iob_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t p_eop:1; uint64_t p_sop:1; uint64_t np_eop:1; uint64_t np_sop:1; +#else + uint64_t np_sop:1; + uint64_t np_eop:1; + uint64_t p_sop:1; + uint64_t p_eop:1; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_iob_int_sum_cn30xx cn31xx; struct cvmx_iob_int_sum_cn30xx cn38xx; @@ -365,16 +703,33 @@ union cvmx_iob_int_sum { struct cvmx_iob_int_sum_s cn56xxp1; struct cvmx_iob_int_sum_s cn58xx; struct cvmx_iob_int_sum_s cn58xxp1; + struct cvmx_iob_int_sum_s cn61xx; struct cvmx_iob_int_sum_s cn63xx; struct cvmx_iob_int_sum_s cn63xxp1; + struct cvmx_iob_int_sum_s cn66xx; + struct cvmx_iob_int_sum_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif + } cn68xx; + struct cvmx_iob_int_sum_cn68xx cn68xxp1; + struct cvmx_iob_int_sum_s cnf71xx; }; union cvmx_iob_n2c_l2c_pri_cnt { uint64_t u64; struct cvmx_iob_n2c_l2c_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xx; struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xxp2; @@ -384,16 +739,25 @@ union cvmx_iob_n2c_l2c_pri_cnt { struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1; struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx; struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1; + struct cvmx_iob_n2c_l2c_pri_cnt_s cn61xx; struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xx; struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xxp1; + struct cvmx_iob_n2c_l2c_pri_cnt_s cn66xx; + struct cvmx_iob_n2c_l2c_pri_cnt_s cnf71xx; }; union cvmx_iob_n2c_rsp_pri_cnt { uint64_t u64; struct cvmx_iob_n2c_rsp_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xx; struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xxp2; @@ -403,16 +767,25 @@ union cvmx_iob_n2c_rsp_pri_cnt { struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1; struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx; struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1; + struct cvmx_iob_n2c_rsp_pri_cnt_s cn61xx; struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xx; struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xxp1; + struct cvmx_iob_n2c_rsp_pri_cnt_s cn66xx; + struct cvmx_iob_n2c_rsp_pri_cnt_s cnf71xx; }; union cvmx_iob_outb_com_pri_cnt { uint64_t u64; struct cvmx_iob_outb_com_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_outb_com_pri_cnt_s cn38xx; struct cvmx_iob_outb_com_pri_cnt_s cn38xxp2; @@ -422,18 +795,31 @@ union cvmx_iob_outb_com_pri_cnt { struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1; struct cvmx_iob_outb_com_pri_cnt_s cn58xx; struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1; + struct cvmx_iob_outb_com_pri_cnt_s cn61xx; struct cvmx_iob_outb_com_pri_cnt_s cn63xx; struct cvmx_iob_outb_com_pri_cnt_s cn63xxp1; + struct cvmx_iob_outb_com_pri_cnt_s cn66xx; + struct cvmx_iob_outb_com_pri_cnt_s cn68xx; + struct cvmx_iob_outb_com_pri_cnt_s cn68xxp1; + struct cvmx_iob_outb_com_pri_cnt_s cnf71xx; }; union cvmx_iob_outb_control_match { uint64_t u64; struct cvmx_iob_outb_control_match_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t mask:8; uint64_t eot:1; uint64_t dst:8; uint64_t src:9; +#else + uint64_t src:9; + uint64_t dst:8; + uint64_t eot:1; + uint64_t mask:8; + uint64_t reserved_26_63:38; +#endif } s; struct cvmx_iob_outb_control_match_s cn30xx; struct cvmx_iob_outb_control_match_s cn31xx; @@ -446,18 +832,31 @@ union cvmx_iob_outb_control_match { struct cvmx_iob_outb_control_match_s cn56xxp1; struct cvmx_iob_outb_control_match_s cn58xx; struct cvmx_iob_outb_control_match_s cn58xxp1; + struct cvmx_iob_outb_control_match_s cn61xx; struct cvmx_iob_outb_control_match_s cn63xx; struct cvmx_iob_outb_control_match_s cn63xxp1; + struct cvmx_iob_outb_control_match_s cn66xx; + struct cvmx_iob_outb_control_match_s cn68xx; + struct cvmx_iob_outb_control_match_s cn68xxp1; + struct cvmx_iob_outb_control_match_s cnf71xx; }; union cvmx_iob_outb_control_match_enb { uint64_t u64; struct cvmx_iob_outb_control_match_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t mask:8; uint64_t eot:1; uint64_t dst:8; uint64_t src:9; +#else + uint64_t src:9; + uint64_t dst:8; + uint64_t eot:1; + uint64_t mask:8; + uint64_t reserved_26_63:38; +#endif } s; struct cvmx_iob_outb_control_match_enb_s cn30xx; struct cvmx_iob_outb_control_match_enb_s cn31xx; @@ -470,14 +869,23 @@ union cvmx_iob_outb_control_match_enb { struct cvmx_iob_outb_control_match_enb_s cn56xxp1; struct cvmx_iob_outb_control_match_enb_s cn58xx; struct cvmx_iob_outb_control_match_enb_s cn58xxp1; + struct cvmx_iob_outb_control_match_enb_s cn61xx; struct cvmx_iob_outb_control_match_enb_s cn63xx; struct cvmx_iob_outb_control_match_enb_s cn63xxp1; + struct cvmx_iob_outb_control_match_enb_s cn66xx; + struct cvmx_iob_outb_control_match_enb_s cn68xx; + struct cvmx_iob_outb_control_match_enb_s cn68xxp1; + struct cvmx_iob_outb_control_match_enb_s cnf71xx; }; union cvmx_iob_outb_data_match { uint64_t u64; struct cvmx_iob_outb_data_match_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; +#else + uint64_t data:64; +#endif } s; struct cvmx_iob_outb_data_match_s cn30xx; struct cvmx_iob_outb_data_match_s cn31xx; @@ -490,14 +898,23 @@ union cvmx_iob_outb_data_match { struct cvmx_iob_outb_data_match_s cn56xxp1; struct cvmx_iob_outb_data_match_s cn58xx; struct cvmx_iob_outb_data_match_s cn58xxp1; + struct cvmx_iob_outb_data_match_s cn61xx; struct cvmx_iob_outb_data_match_s cn63xx; struct cvmx_iob_outb_data_match_s cn63xxp1; + struct cvmx_iob_outb_data_match_s cn66xx; + struct cvmx_iob_outb_data_match_s cn68xx; + struct cvmx_iob_outb_data_match_s cn68xxp1; + struct cvmx_iob_outb_data_match_s cnf71xx; }; union cvmx_iob_outb_data_match_enb { uint64_t u64; struct cvmx_iob_outb_data_match_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_iob_outb_data_match_enb_s cn30xx; struct cvmx_iob_outb_data_match_enb_s cn31xx; @@ -510,16 +927,27 @@ union cvmx_iob_outb_data_match_enb { struct cvmx_iob_outb_data_match_enb_s cn56xxp1; struct cvmx_iob_outb_data_match_enb_s cn58xx; struct cvmx_iob_outb_data_match_enb_s cn58xxp1; + struct cvmx_iob_outb_data_match_enb_s cn61xx; struct cvmx_iob_outb_data_match_enb_s cn63xx; struct cvmx_iob_outb_data_match_enb_s cn63xxp1; + struct cvmx_iob_outb_data_match_enb_s cn66xx; + struct cvmx_iob_outb_data_match_enb_s cn68xx; + struct cvmx_iob_outb_data_match_enb_s cn68xxp1; + struct cvmx_iob_outb_data_match_enb_s cnf71xx; }; union cvmx_iob_outb_fpa_pri_cnt { uint64_t u64; struct cvmx_iob_outb_fpa_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_outb_fpa_pri_cnt_s cn38xx; struct cvmx_iob_outb_fpa_pri_cnt_s cn38xxp2; @@ -529,16 +957,27 @@ union cvmx_iob_outb_fpa_pri_cnt { struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1; struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx; struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1; + struct cvmx_iob_outb_fpa_pri_cnt_s cn61xx; struct cvmx_iob_outb_fpa_pri_cnt_s cn63xx; struct cvmx_iob_outb_fpa_pri_cnt_s cn63xxp1; + struct cvmx_iob_outb_fpa_pri_cnt_s cn66xx; + struct cvmx_iob_outb_fpa_pri_cnt_s cn68xx; + struct cvmx_iob_outb_fpa_pri_cnt_s cn68xxp1; + struct cvmx_iob_outb_fpa_pri_cnt_s cnf71xx; }; union cvmx_iob_outb_req_pri_cnt { uint64_t u64; struct cvmx_iob_outb_req_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_outb_req_pri_cnt_s cn38xx; struct cvmx_iob_outb_req_pri_cnt_s cn38xxp2; @@ -548,16 +987,27 @@ union cvmx_iob_outb_req_pri_cnt { struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1; struct cvmx_iob_outb_req_pri_cnt_s cn58xx; struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1; + struct cvmx_iob_outb_req_pri_cnt_s cn61xx; struct cvmx_iob_outb_req_pri_cnt_s cn63xx; struct cvmx_iob_outb_req_pri_cnt_s cn63xxp1; + struct cvmx_iob_outb_req_pri_cnt_s cn66xx; + struct cvmx_iob_outb_req_pri_cnt_s cn68xx; + struct cvmx_iob_outb_req_pri_cnt_s cn68xxp1; + struct cvmx_iob_outb_req_pri_cnt_s cnf71xx; }; union cvmx_iob_p2c_req_pri_cnt { uint64_t u64; struct cvmx_iob_p2c_req_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_p2c_req_pri_cnt_s cn38xx; struct cvmx_iob_p2c_req_pri_cnt_s cn38xxp2; @@ -567,20 +1017,34 @@ union cvmx_iob_p2c_req_pri_cnt { struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1; struct cvmx_iob_p2c_req_pri_cnt_s cn58xx; struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1; + struct cvmx_iob_p2c_req_pri_cnt_s cn61xx; struct cvmx_iob_p2c_req_pri_cnt_s cn63xx; struct cvmx_iob_p2c_req_pri_cnt_s cn63xxp1; + struct cvmx_iob_p2c_req_pri_cnt_s cn66xx; + struct cvmx_iob_p2c_req_pri_cnt_s cnf71xx; }; union cvmx_iob_pkt_err { uint64_t u64; struct cvmx_iob_pkt_err_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t vport:6; uint64_t port:6; +#else + uint64_t port:6; + uint64_t vport:6; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_iob_pkt_err_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t port:6; +#else + uint64_t port:6; + uint64_t reserved_6_63:58; +#endif } cn30xx; struct cvmx_iob_pkt_err_cn30xx cn31xx; struct cvmx_iob_pkt_err_cn30xx cn38xx; @@ -592,21 +1056,223 @@ union cvmx_iob_pkt_err { struct cvmx_iob_pkt_err_cn30xx cn56xxp1; struct cvmx_iob_pkt_err_cn30xx cn58xx; struct cvmx_iob_pkt_err_cn30xx cn58xxp1; + struct cvmx_iob_pkt_err_s cn61xx; struct cvmx_iob_pkt_err_s cn63xx; struct cvmx_iob_pkt_err_s cn63xxp1; + struct cvmx_iob_pkt_err_s cn66xx; + struct cvmx_iob_pkt_err_s cnf71xx; }; union cvmx_iob_to_cmb_credits { uint64_t u64; struct cvmx_iob_to_cmb_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_63:58; + uint64_t ncb_rd:3; + uint64_t ncb_wr:3; +#else + uint64_t ncb_wr:3; + uint64_t ncb_rd:3; + uint64_t reserved_6_63:58; +#endif + } s; + struct cvmx_iob_to_cmb_credits_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t pko_rd:3; uint64_t ncb_rd:3; uint64_t ncb_wr:3; +#else + uint64_t ncb_wr:3; + uint64_t ncb_rd:3; + uint64_t pko_rd:3; + uint64_t reserved_9_63:55; +#endif + } cn52xx; + struct cvmx_iob_to_cmb_credits_cn52xx cn61xx; + struct cvmx_iob_to_cmb_credits_cn52xx cn63xx; + struct cvmx_iob_to_cmb_credits_cn52xx cn63xxp1; + struct cvmx_iob_to_cmb_credits_cn52xx cn66xx; + struct cvmx_iob_to_cmb_credits_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t dwb:3; + uint64_t ncb_rd:3; + uint64_t ncb_wr:3; +#else + uint64_t ncb_wr:3; + uint64_t ncb_rd:3; + uint64_t dwb:3; + uint64_t reserved_9_63:55; +#endif + } cn68xx; + struct cvmx_iob_to_cmb_credits_cn68xx cn68xxp1; + struct cvmx_iob_to_cmb_credits_cn52xx cnf71xx; +}; + +union cvmx_iob_to_ncb_did_00_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_00_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_00_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_00_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_111_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_111_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_111_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_111_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_223_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_223_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_223_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_223_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_24_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_24_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_24_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_24_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_32_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_32_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_32_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_32_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_40_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_40_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_40_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_40_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_55_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_55_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_55_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_55_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_64_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_64_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_64_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_64_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_79_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_79_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_79_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_79_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_96_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_96_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_96_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_96_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_98_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_98_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif } s; - struct cvmx_iob_to_cmb_credits_s cn52xx; - struct cvmx_iob_to_cmb_credits_s cn63xx; - struct cvmx_iob_to_cmb_credits_s cn63xxp1; + struct cvmx_iob_to_ncb_did_98_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_98_credits_s cn68xxp1; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h index e0a5bfe88d04..1193f73bb74a 100644 --- a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -32,23 +32,37 @@ #define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull)) #define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull)) #define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull)) +#define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8) +#define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8) #define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull)) #define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull)) +#define CVMX_IPD_CREDITS (CVMX_ADD_IO_SEG(0x00014F0000004410ull)) #define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull)) +#define CVMX_IPD_ECC_CTL (CVMX_ADD_IO_SEG(0x00014F0000004408ull)) +#define CVMX_IPD_FREE_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000780ull)) +#define CVMX_IPD_FREE_PTR_VALUE (CVMX_ADD_IO_SEG(0x00014F0000000788ull)) +#define CVMX_IPD_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000790ull)) #define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull)) #define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull)) +#define CVMX_IPD_NEXT_PKT_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A0ull)) +#define CVMX_IPD_NEXT_WQE_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A8ull)) #define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull)) +#define CVMX_IPD_ON_BP_DROP_PKTX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004100ull)) #define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull)) +#define CVMX_IPD_PKT_ERR (CVMX_ADD_IO_SEG(0x00014F00000003F0ull)) #define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull)) #define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8) #define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36) #define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40) #define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36) #define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40) +#define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44) #define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8) +#define CVMX_IPD_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000798ull)) #define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8) #define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8) #define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8) +#define CVMX_IPD_PORT_SOPX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004400ull)) #define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull)) #define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull)) #define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull)) @@ -63,6 +77,8 @@ #define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7) #define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8) #define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull)) +#define CVMX_IPD_RED_BPID_ENABLEX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004200ull)) +#define CVMX_IPD_RED_DELAY (CVMX_ADD_IO_SEG(0x00014F0000004300ull)) #define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull)) #define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull)) #define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0) @@ -74,6 +90,7 @@ #define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6) #define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7) #define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8) +#define CVMX_IPD_REQ_WGT (CVMX_ADD_IO_SEG(0x00014F0000004418ull)) #define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull)) #define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull)) #define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull)) @@ -83,8 +100,13 @@ union cvmx_ipd_1st_mbuff_skip { uint64_t u64; struct cvmx_ipd_1st_mbuff_skip_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t skip_sz:6; +#else + uint64_t skip_sz:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_ipd_1st_mbuff_skip_s cn30xx; struct cvmx_ipd_1st_mbuff_skip_s cn31xx; @@ -97,15 +119,25 @@ union cvmx_ipd_1st_mbuff_skip { struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1; struct cvmx_ipd_1st_mbuff_skip_s cn58xx; struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1; + struct cvmx_ipd_1st_mbuff_skip_s cn61xx; struct cvmx_ipd_1st_mbuff_skip_s cn63xx; struct cvmx_ipd_1st_mbuff_skip_s cn63xxp1; + struct cvmx_ipd_1st_mbuff_skip_s cn66xx; + struct cvmx_ipd_1st_mbuff_skip_s cn68xx; + struct cvmx_ipd_1st_mbuff_skip_s cn68xxp1; + struct cvmx_ipd_1st_mbuff_skip_s cnf71xx; }; union cvmx_ipd_1st_next_ptr_back { uint64_t u64; struct cvmx_ipd_1st_next_ptr_back_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t back:4; +#else + uint64_t back:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_ipd_1st_next_ptr_back_s cn30xx; struct cvmx_ipd_1st_next_ptr_back_s cn31xx; @@ -118,15 +150,25 @@ union cvmx_ipd_1st_next_ptr_back { struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1; struct cvmx_ipd_1st_next_ptr_back_s cn58xx; struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1; + struct cvmx_ipd_1st_next_ptr_back_s cn61xx; struct cvmx_ipd_1st_next_ptr_back_s cn63xx; struct cvmx_ipd_1st_next_ptr_back_s cn63xxp1; + struct cvmx_ipd_1st_next_ptr_back_s cn66xx; + struct cvmx_ipd_1st_next_ptr_back_s cn68xx; + struct cvmx_ipd_1st_next_ptr_back_s cn68xxp1; + struct cvmx_ipd_1st_next_ptr_back_s cnf71xx; }; union cvmx_ipd_2nd_next_ptr_back { uint64_t u64; struct cvmx_ipd_2nd_next_ptr_back_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t back:4; +#else + uint64_t back:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_ipd_2nd_next_ptr_back_s cn30xx; struct cvmx_ipd_2nd_next_ptr_back_s cn31xx; @@ -139,14 +181,25 @@ union cvmx_ipd_2nd_next_ptr_back { struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1; struct cvmx_ipd_2nd_next_ptr_back_s cn58xx; struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1; + struct cvmx_ipd_2nd_next_ptr_back_s cn61xx; struct cvmx_ipd_2nd_next_ptr_back_s cn63xx; struct cvmx_ipd_2nd_next_ptr_back_s cn63xxp1; + struct cvmx_ipd_2nd_next_ptr_back_s cn66xx; + struct cvmx_ipd_2nd_next_ptr_back_s cn68xx; + struct cvmx_ipd_2nd_next_ptr_back_s cn68xxp1; + struct cvmx_ipd_2nd_next_ptr_back_s cnf71xx; }; union cvmx_ipd_bist_status { uint64_t u64; struct cvmx_ipd_bist_status_s { - uint64_t reserved_18_63:46; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_23_63:41; + uint64_t iiwo1:1; + uint64_t iiwo0:1; + uint64_t iio1:1; + uint64_t iio0:1; + uint64_t pbm4:1; uint64_t csr_mem:1; uint64_t csr_ncmd:1; uint64_t pwq_wqed:1; @@ -165,8 +218,35 @@ union cvmx_ipd_bist_status { uint64_t ipd_old:1; uint64_t ipd_new:1; uint64_t pwp:1; +#else + uint64_t pwp:1; + uint64_t ipd_new:1; + uint64_t ipd_old:1; + uint64_t prc_off:1; + uint64_t pwq0:1; + uint64_t pwq1:1; + uint64_t pbm_word:1; + uint64_t pbm0:1; + uint64_t pbm1:1; + uint64_t pbm2:1; + uint64_t pbm3:1; + uint64_t ipq_pbe0:1; + uint64_t ipq_pbe1:1; + uint64_t pwq_pow:1; + uint64_t pwq_wp1:1; + uint64_t pwq_wqed:1; + uint64_t csr_ncmd:1; + uint64_t csr_mem:1; + uint64_t pbm4:1; + uint64_t iio0:1; + uint64_t iio1:1; + uint64_t iiwo0:1; + uint64_t iiwo1:1; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_ipd_bist_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t pwq_wqed:1; uint64_t pwq_wp1:1; @@ -184,52 +264,180 @@ union cvmx_ipd_bist_status { uint64_t ipd_old:1; uint64_t ipd_new:1; uint64_t pwp:1; +#else + uint64_t pwp:1; + uint64_t ipd_new:1; + uint64_t ipd_old:1; + uint64_t prc_off:1; + uint64_t pwq0:1; + uint64_t pwq1:1; + uint64_t pbm_word:1; + uint64_t pbm0:1; + uint64_t pbm1:1; + uint64_t pbm2:1; + uint64_t pbm3:1; + uint64_t ipq_pbe0:1; + uint64_t ipq_pbe1:1; + uint64_t pwq_pow:1; + uint64_t pwq_wp1:1; + uint64_t pwq_wqed:1; + uint64_t reserved_16_63:48; +#endif } cn30xx; struct cvmx_ipd_bist_status_cn30xx cn31xx; struct cvmx_ipd_bist_status_cn30xx cn38xx; struct cvmx_ipd_bist_status_cn30xx cn38xxp2; struct cvmx_ipd_bist_status_cn30xx cn50xx; - struct cvmx_ipd_bist_status_s cn52xx; - struct cvmx_ipd_bist_status_s cn52xxp1; - struct cvmx_ipd_bist_status_s cn56xx; - struct cvmx_ipd_bist_status_s cn56xxp1; + struct cvmx_ipd_bist_status_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t csr_mem:1; + uint64_t csr_ncmd:1; + uint64_t pwq_wqed:1; + uint64_t pwq_wp1:1; + uint64_t pwq_pow:1; + uint64_t ipq_pbe1:1; + uint64_t ipq_pbe0:1; + uint64_t pbm3:1; + uint64_t pbm2:1; + uint64_t pbm1:1; + uint64_t pbm0:1; + uint64_t pbm_word:1; + uint64_t pwq1:1; + uint64_t pwq0:1; + uint64_t prc_off:1; + uint64_t ipd_old:1; + uint64_t ipd_new:1; + uint64_t pwp:1; +#else + uint64_t pwp:1; + uint64_t ipd_new:1; + uint64_t ipd_old:1; + uint64_t prc_off:1; + uint64_t pwq0:1; + uint64_t pwq1:1; + uint64_t pbm_word:1; + uint64_t pbm0:1; + uint64_t pbm1:1; + uint64_t pbm2:1; + uint64_t pbm3:1; + uint64_t ipq_pbe0:1; + uint64_t ipq_pbe1:1; + uint64_t pwq_pow:1; + uint64_t pwq_wp1:1; + uint64_t pwq_wqed:1; + uint64_t csr_ncmd:1; + uint64_t csr_mem:1; + uint64_t reserved_18_63:46; +#endif + } cn52xx; + struct cvmx_ipd_bist_status_cn52xx cn52xxp1; + struct cvmx_ipd_bist_status_cn52xx cn56xx; + struct cvmx_ipd_bist_status_cn52xx cn56xxp1; struct cvmx_ipd_bist_status_cn30xx cn58xx; struct cvmx_ipd_bist_status_cn30xx cn58xxp1; - struct cvmx_ipd_bist_status_s cn63xx; - struct cvmx_ipd_bist_status_s cn63xxp1; + struct cvmx_ipd_bist_status_cn52xx cn61xx; + struct cvmx_ipd_bist_status_cn52xx cn63xx; + struct cvmx_ipd_bist_status_cn52xx cn63xxp1; + struct cvmx_ipd_bist_status_cn52xx cn66xx; + struct cvmx_ipd_bist_status_s cn68xx; + struct cvmx_ipd_bist_status_s cn68xxp1; + struct cvmx_ipd_bist_status_cn52xx cnf71xx; }; union cvmx_ipd_bp_prt_red_end { uint64_t u64; struct cvmx_ipd_bp_prt_red_end_s { - uint64_t reserved_44_63:20; - uint64_t prt_enb:44; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t prt_enb:48; +#else + uint64_t prt_enb:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_ipd_bp_prt_red_end_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t prt_enb:36; +#else + uint64_t prt_enb:36; + uint64_t reserved_36_63:28; +#endif } cn30xx; struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx; struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx; struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2; struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx; struct cvmx_ipd_bp_prt_red_end_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t prt_enb:40; +#else + uint64_t prt_enb:40; + uint64_t reserved_40_63:24; +#endif } cn52xx; struct cvmx_ipd_bp_prt_red_end_cn52xx cn52xxp1; struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xx; struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1; struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx; struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1; - struct cvmx_ipd_bp_prt_red_end_s cn63xx; - struct cvmx_ipd_bp_prt_red_end_s cn63xxp1; + struct cvmx_ipd_bp_prt_red_end_s cn61xx; + struct cvmx_ipd_bp_prt_red_end_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_44_63:20; + uint64_t prt_enb:44; +#else + uint64_t prt_enb:44; + uint64_t reserved_44_63:20; +#endif + } cn63xx; + struct cvmx_ipd_bp_prt_red_end_cn63xx cn63xxp1; + struct cvmx_ipd_bp_prt_red_end_s cn66xx; + struct cvmx_ipd_bp_prt_red_end_s cnf71xx; +}; + +union cvmx_ipd_bpidx_mbuf_th { + uint64_t u64; + struct cvmx_ipd_bpidx_mbuf_th_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t bp_enb:1; + uint64_t page_cnt:17; +#else + uint64_t page_cnt:17; + uint64_t bp_enb:1; + uint64_t reserved_18_63:46; +#endif + } s; + struct cvmx_ipd_bpidx_mbuf_th_s cn68xx; + struct cvmx_ipd_bpidx_mbuf_th_s cn68xxp1; +}; + +union cvmx_ipd_bpid_bp_counterx { + uint64_t u64; + struct cvmx_ipd_bpid_bp_counterx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t cnt_val:25; +#else + uint64_t cnt_val:25; + uint64_t reserved_25_63:39; +#endif + } s; + struct cvmx_ipd_bpid_bp_counterx_s cn68xx; + struct cvmx_ipd_bpid_bp_counterx_s cn68xxp1; }; union cvmx_ipd_clk_count { uint64_t u64; struct cvmx_ipd_clk_count_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t clk_cnt:64; +#else + uint64_t clk_cnt:64; +#endif } s; struct cvmx_ipd_clk_count_s cn30xx; struct cvmx_ipd_clk_count_s cn31xx; @@ -242,13 +450,36 @@ union cvmx_ipd_clk_count { struct cvmx_ipd_clk_count_s cn56xxp1; struct cvmx_ipd_clk_count_s cn58xx; struct cvmx_ipd_clk_count_s cn58xxp1; + struct cvmx_ipd_clk_count_s cn61xx; struct cvmx_ipd_clk_count_s cn63xx; struct cvmx_ipd_clk_count_s cn63xxp1; + struct cvmx_ipd_clk_count_s cn66xx; + struct cvmx_ipd_clk_count_s cn68xx; + struct cvmx_ipd_clk_count_s cn68xxp1; + struct cvmx_ipd_clk_count_s cnf71xx; +}; + +union cvmx_ipd_credits { + uint64_t u64; + struct cvmx_ipd_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t iob_wrc:8; + uint64_t iob_wr:8; +#else + uint64_t iob_wr:8; + uint64_t iob_wrc:8; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ipd_credits_s cn68xx; + struct cvmx_ipd_credits_s cn68xxp1; }; union cvmx_ipd_ctl_status { uint64_t u64; struct cvmx_ipd_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t use_sop:1; uint64_t rst_done:1; @@ -267,8 +498,29 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t len_m8:1; + uint64_t pkt_off:1; + uint64_t ipd_full:1; + uint64_t pq_nabuf:1; + uint64_t pq_apkt:1; + uint64_t no_wptr:1; + uint64_t clken:1; + uint64_t rst_done:1; + uint64_t use_sop:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_ipd_ctl_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t len_m8:1; uint64_t reset:1; @@ -279,10 +531,23 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t len_m8:1; + uint64_t reserved_10_63:54; +#endif } cn30xx; struct cvmx_ipd_ctl_status_cn30xx cn31xx; struct cvmx_ipd_ctl_status_cn30xx cn38xx; struct cvmx_ipd_ctl_status_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t reset:1; uint64_t addpkt:1; @@ -292,8 +557,20 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t reserved_9_63:55; +#endif } cn38xxp2; struct cvmx_ipd_ctl_status_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t no_wptr:1; uint64_t pq_apkt:1; @@ -309,12 +586,30 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t len_m8:1; + uint64_t pkt_off:1; + uint64_t ipd_full:1; + uint64_t pq_nabuf:1; + uint64_t pq_apkt:1; + uint64_t no_wptr:1; + uint64_t reserved_15_63:49; +#endif } cn50xx; struct cvmx_ipd_ctl_status_cn50xx cn52xx; struct cvmx_ipd_ctl_status_cn50xx cn52xxp1; struct cvmx_ipd_ctl_status_cn50xx cn56xx; struct cvmx_ipd_ctl_status_cn50xx cn56xxp1; struct cvmx_ipd_ctl_status_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t ipd_full:1; uint64_t pkt_off:1; @@ -327,10 +622,26 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t len_m8:1; + uint64_t pkt_off:1; + uint64_t ipd_full:1; + uint64_t reserved_12_63:52; +#endif } cn58xx; struct cvmx_ipd_ctl_status_cn58xx cn58xxp1; + struct cvmx_ipd_ctl_status_s cn61xx; struct cvmx_ipd_ctl_status_s cn63xx; struct cvmx_ipd_ctl_status_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t clken:1; uint64_t no_wptr:1; @@ -347,13 +658,129 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t len_m8:1; + uint64_t pkt_off:1; + uint64_t ipd_full:1; + uint64_t pq_nabuf:1; + uint64_t pq_apkt:1; + uint64_t no_wptr:1; + uint64_t clken:1; + uint64_t reserved_16_63:48; +#endif } cn63xxp1; + struct cvmx_ipd_ctl_status_s cn66xx; + struct cvmx_ipd_ctl_status_s cn68xx; + struct cvmx_ipd_ctl_status_s cn68xxp1; + struct cvmx_ipd_ctl_status_s cnf71xx; +}; + +union cvmx_ipd_ecc_ctl { + uint64_t u64; + struct cvmx_ipd_ecc_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_8_63:56; + uint64_t pm3_syn:2; + uint64_t pm2_syn:2; + uint64_t pm1_syn:2; + uint64_t pm0_syn:2; +#else + uint64_t pm0_syn:2; + uint64_t pm1_syn:2; + uint64_t pm2_syn:2; + uint64_t pm3_syn:2; + uint64_t reserved_8_63:56; +#endif + } s; + struct cvmx_ipd_ecc_ctl_s cn68xx; + struct cvmx_ipd_ecc_ctl_s cn68xxp1; +}; + +union cvmx_ipd_free_ptr_fifo_ctl { + uint64_t u64; + struct cvmx_ipd_free_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t max_cnts:7; + uint64_t wraddr:8; + uint64_t praddr:8; + uint64_t cena:1; + uint64_t raddr:8; +#else + uint64_t raddr:8; + uint64_t cena:1; + uint64_t praddr:8; + uint64_t wraddr:8; + uint64_t max_cnts:7; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ipd_free_ptr_fifo_ctl_s cn68xx; + struct cvmx_ipd_free_ptr_fifo_ctl_s cn68xxp1; +}; + +union cvmx_ipd_free_ptr_value { + uint64_t u64; + struct cvmx_ipd_free_ptr_value_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t ptr:33; +#else + uint64_t ptr:33; + uint64_t reserved_33_63:31; +#endif + } s; + struct cvmx_ipd_free_ptr_value_s cn68xx; + struct cvmx_ipd_free_ptr_value_s cn68xxp1; +}; + +union cvmx_ipd_hold_ptr_fifo_ctl { + uint64_t u64; + struct cvmx_ipd_hold_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_43_63:21; + uint64_t ptr:33; + uint64_t max_pkt:3; + uint64_t praddr:3; + uint64_t cena:1; + uint64_t raddr:3; +#else + uint64_t raddr:3; + uint64_t cena:1; + uint64_t praddr:3; + uint64_t max_pkt:3; + uint64_t ptr:33; + uint64_t reserved_43_63:21; +#endif + } s; + struct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xx; + struct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xxp1; }; union cvmx_ipd_int_enb { uint64_t u64; struct cvmx_ipd_int_enb_s { - uint64_t reserved_12_63:52; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_23_63:41; + uint64_t pw3_dbe:1; + uint64_t pw3_sbe:1; + uint64_t pw2_dbe:1; + uint64_t pw2_sbe:1; + uint64_t pw1_dbe:1; + uint64_t pw1_sbe:1; + uint64_t pw0_dbe:1; + uint64_t pw0_sbe:1; + uint64_t dat:1; + uint64_t eop:1; + uint64_t sop:1; uint64_t pq_sub:1; uint64_t pq_add:1; uint64_t bc_ovr:1; @@ -366,17 +793,53 @@ union cvmx_ipd_int_enb { uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t pq_add:1; + uint64_t pq_sub:1; + uint64_t sop:1; + uint64_t eop:1; + uint64_t dat:1; + uint64_t pw0_sbe:1; + uint64_t pw0_dbe:1; + uint64_t pw1_sbe:1; + uint64_t pw1_dbe:1; + uint64_t pw2_sbe:1; + uint64_t pw2_dbe:1; + uint64_t pw3_sbe:1; + uint64_t pw3_dbe:1; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_ipd_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t bp_sub:1; uint64_t prc_par3:1; uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t reserved_5_63:59; +#endif } cn30xx; struct cvmx_ipd_int_enb_cn30xx cn31xx; struct cvmx_ipd_int_enb_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t bc_ovr:1; uint64_t d_coll:1; @@ -388,23 +851,83 @@ union cvmx_ipd_int_enb { uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t reserved_10_63:54; +#endif } cn38xx; struct cvmx_ipd_int_enb_cn30xx cn38xxp2; struct cvmx_ipd_int_enb_cn38xx cn50xx; - struct cvmx_ipd_int_enb_s cn52xx; - struct cvmx_ipd_int_enb_s cn52xxp1; - struct cvmx_ipd_int_enb_s cn56xx; - struct cvmx_ipd_int_enb_s cn56xxp1; + struct cvmx_ipd_int_enb_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t pq_sub:1; + uint64_t pq_add:1; + uint64_t bc_ovr:1; + uint64_t d_coll:1; + uint64_t c_coll:1; + uint64_t cc_ovr:1; + uint64_t dc_ovr:1; + uint64_t bp_sub:1; + uint64_t prc_par3:1; + uint64_t prc_par2:1; + uint64_t prc_par1:1; + uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t pq_add:1; + uint64_t pq_sub:1; + uint64_t reserved_12_63:52; +#endif + } cn52xx; + struct cvmx_ipd_int_enb_cn52xx cn52xxp1; + struct cvmx_ipd_int_enb_cn52xx cn56xx; + struct cvmx_ipd_int_enb_cn52xx cn56xxp1; struct cvmx_ipd_int_enb_cn38xx cn58xx; struct cvmx_ipd_int_enb_cn38xx cn58xxp1; - struct cvmx_ipd_int_enb_s cn63xx; - struct cvmx_ipd_int_enb_s cn63xxp1; + struct cvmx_ipd_int_enb_cn52xx cn61xx; + struct cvmx_ipd_int_enb_cn52xx cn63xx; + struct cvmx_ipd_int_enb_cn52xx cn63xxp1; + struct cvmx_ipd_int_enb_cn52xx cn66xx; + struct cvmx_ipd_int_enb_s cn68xx; + struct cvmx_ipd_int_enb_s cn68xxp1; + struct cvmx_ipd_int_enb_cn52xx cnf71xx; }; union cvmx_ipd_int_sum { uint64_t u64; struct cvmx_ipd_int_sum_s { - uint64_t reserved_12_63:52; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_23_63:41; + uint64_t pw3_dbe:1; + uint64_t pw3_sbe:1; + uint64_t pw2_dbe:1; + uint64_t pw2_sbe:1; + uint64_t pw1_dbe:1; + uint64_t pw1_sbe:1; + uint64_t pw0_dbe:1; + uint64_t pw0_sbe:1; + uint64_t dat:1; + uint64_t eop:1; + uint64_t sop:1; uint64_t pq_sub:1; uint64_t pq_add:1; uint64_t bc_ovr:1; @@ -417,17 +940,53 @@ union cvmx_ipd_int_sum { uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t pq_add:1; + uint64_t pq_sub:1; + uint64_t sop:1; + uint64_t eop:1; + uint64_t dat:1; + uint64_t pw0_sbe:1; + uint64_t pw0_dbe:1; + uint64_t pw1_sbe:1; + uint64_t pw1_dbe:1; + uint64_t pw2_sbe:1; + uint64_t pw2_dbe:1; + uint64_t pw3_sbe:1; + uint64_t pw3_dbe:1; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_ipd_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t bp_sub:1; uint64_t prc_par3:1; uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t reserved_5_63:59; +#endif } cn30xx; struct cvmx_ipd_int_sum_cn30xx cn31xx; struct cvmx_ipd_int_sum_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t bc_ovr:1; uint64_t d_coll:1; @@ -439,24 +998,107 @@ union cvmx_ipd_int_sum { uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t reserved_10_63:54; +#endif } cn38xx; struct cvmx_ipd_int_sum_cn30xx cn38xxp2; struct cvmx_ipd_int_sum_cn38xx cn50xx; - struct cvmx_ipd_int_sum_s cn52xx; - struct cvmx_ipd_int_sum_s cn52xxp1; - struct cvmx_ipd_int_sum_s cn56xx; - struct cvmx_ipd_int_sum_s cn56xxp1; + struct cvmx_ipd_int_sum_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t pq_sub:1; + uint64_t pq_add:1; + uint64_t bc_ovr:1; + uint64_t d_coll:1; + uint64_t c_coll:1; + uint64_t cc_ovr:1; + uint64_t dc_ovr:1; + uint64_t bp_sub:1; + uint64_t prc_par3:1; + uint64_t prc_par2:1; + uint64_t prc_par1:1; + uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t pq_add:1; + uint64_t pq_sub:1; + uint64_t reserved_12_63:52; +#endif + } cn52xx; + struct cvmx_ipd_int_sum_cn52xx cn52xxp1; + struct cvmx_ipd_int_sum_cn52xx cn56xx; + struct cvmx_ipd_int_sum_cn52xx cn56xxp1; struct cvmx_ipd_int_sum_cn38xx cn58xx; struct cvmx_ipd_int_sum_cn38xx cn58xxp1; - struct cvmx_ipd_int_sum_s cn63xx; - struct cvmx_ipd_int_sum_s cn63xxp1; + struct cvmx_ipd_int_sum_cn52xx cn61xx; + struct cvmx_ipd_int_sum_cn52xx cn63xx; + struct cvmx_ipd_int_sum_cn52xx cn63xxp1; + struct cvmx_ipd_int_sum_cn52xx cn66xx; + struct cvmx_ipd_int_sum_s cn68xx; + struct cvmx_ipd_int_sum_s cn68xxp1; + struct cvmx_ipd_int_sum_cn52xx cnf71xx; +}; + +union cvmx_ipd_next_pkt_ptr { + uint64_t u64; + struct cvmx_ipd_next_pkt_ptr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t ptr:33; +#else + uint64_t ptr:33; + uint64_t reserved_33_63:31; +#endif + } s; + struct cvmx_ipd_next_pkt_ptr_s cn68xx; + struct cvmx_ipd_next_pkt_ptr_s cn68xxp1; +}; + +union cvmx_ipd_next_wqe_ptr { + uint64_t u64; + struct cvmx_ipd_next_wqe_ptr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t ptr:33; +#else + uint64_t ptr:33; + uint64_t reserved_33_63:31; +#endif + } s; + struct cvmx_ipd_next_wqe_ptr_s cn68xx; + struct cvmx_ipd_next_wqe_ptr_s cn68xxp1; }; union cvmx_ipd_not_1st_mbuff_skip { uint64_t u64; struct cvmx_ipd_not_1st_mbuff_skip_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t skip_sz:6; +#else + uint64_t skip_sz:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx; struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx; @@ -469,15 +1111,38 @@ union cvmx_ipd_not_1st_mbuff_skip { struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1; struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx; struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1; + struct cvmx_ipd_not_1st_mbuff_skip_s cn61xx; struct cvmx_ipd_not_1st_mbuff_skip_s cn63xx; struct cvmx_ipd_not_1st_mbuff_skip_s cn63xxp1; + struct cvmx_ipd_not_1st_mbuff_skip_s cn66xx; + struct cvmx_ipd_not_1st_mbuff_skip_s cn68xx; + struct cvmx_ipd_not_1st_mbuff_skip_s cn68xxp1; + struct cvmx_ipd_not_1st_mbuff_skip_s cnf71xx; +}; + +union cvmx_ipd_on_bp_drop_pktx { + uint64_t u64; + struct cvmx_ipd_on_bp_drop_pktx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t prt_enb:64; +#else + uint64_t prt_enb:64; +#endif + } s; + struct cvmx_ipd_on_bp_drop_pktx_s cn68xx; + struct cvmx_ipd_on_bp_drop_pktx_s cn68xxp1; }; union cvmx_ipd_packet_mbuff_size { uint64_t u64; struct cvmx_ipd_packet_mbuff_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t mb_size:12; +#else + uint64_t mb_size:12; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_ipd_packet_mbuff_size_s cn30xx; struct cvmx_ipd_packet_mbuff_size_s cn31xx; @@ -490,15 +1155,40 @@ union cvmx_ipd_packet_mbuff_size { struct cvmx_ipd_packet_mbuff_size_s cn56xxp1; struct cvmx_ipd_packet_mbuff_size_s cn58xx; struct cvmx_ipd_packet_mbuff_size_s cn58xxp1; + struct cvmx_ipd_packet_mbuff_size_s cn61xx; struct cvmx_ipd_packet_mbuff_size_s cn63xx; struct cvmx_ipd_packet_mbuff_size_s cn63xxp1; + struct cvmx_ipd_packet_mbuff_size_s cn66xx; + struct cvmx_ipd_packet_mbuff_size_s cn68xx; + struct cvmx_ipd_packet_mbuff_size_s cn68xxp1; + struct cvmx_ipd_packet_mbuff_size_s cnf71xx; +}; + +union cvmx_ipd_pkt_err { + uint64_t u64; + struct cvmx_ipd_pkt_err_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_63:58; + uint64_t reasm:6; +#else + uint64_t reasm:6; + uint64_t reserved_6_63:58; +#endif + } s; + struct cvmx_ipd_pkt_err_s cn68xx; + struct cvmx_ipd_pkt_err_s cn68xxp1; }; union cvmx_ipd_pkt_ptr_valid { uint64_t u64; struct cvmx_ipd_pkt_ptr_valid_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t ptr:29; +#else + uint64_t ptr:29; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_ipd_pkt_ptr_valid_s cn30xx; struct cvmx_ipd_pkt_ptr_valid_s cn31xx; @@ -510,16 +1200,25 @@ union cvmx_ipd_pkt_ptr_valid { struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1; struct cvmx_ipd_pkt_ptr_valid_s cn58xx; struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1; + struct cvmx_ipd_pkt_ptr_valid_s cn61xx; struct cvmx_ipd_pkt_ptr_valid_s cn63xx; struct cvmx_ipd_pkt_ptr_valid_s cn63xxp1; + struct cvmx_ipd_pkt_ptr_valid_s cn66xx; + struct cvmx_ipd_pkt_ptr_valid_s cnf71xx; }; union cvmx_ipd_portx_bp_page_cnt { uint64_t u64; struct cvmx_ipd_portx_bp_page_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t bp_enb:1; uint64_t page_cnt:17; +#else + uint64_t page_cnt:17; + uint64_t bp_enb:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_ipd_portx_bp_page_cnt_s cn30xx; struct cvmx_ipd_portx_bp_page_cnt_s cn31xx; @@ -532,65 +1231,123 @@ union cvmx_ipd_portx_bp_page_cnt { struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1; struct cvmx_ipd_portx_bp_page_cnt_s cn58xx; struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1; + struct cvmx_ipd_portx_bp_page_cnt_s cn61xx; struct cvmx_ipd_portx_bp_page_cnt_s cn63xx; struct cvmx_ipd_portx_bp_page_cnt_s cn63xxp1; + struct cvmx_ipd_portx_bp_page_cnt_s cn66xx; + struct cvmx_ipd_portx_bp_page_cnt_s cnf71xx; }; union cvmx_ipd_portx_bp_page_cnt2 { uint64_t u64; struct cvmx_ipd_portx_bp_page_cnt2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t bp_enb:1; uint64_t page_cnt:17; +#else + uint64_t page_cnt:17; + uint64_t bp_enb:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx; struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1; struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx; struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1; + struct cvmx_ipd_portx_bp_page_cnt2_s cn61xx; struct cvmx_ipd_portx_bp_page_cnt2_s cn63xx; struct cvmx_ipd_portx_bp_page_cnt2_s cn63xxp1; + struct cvmx_ipd_portx_bp_page_cnt2_s cn66xx; + struct cvmx_ipd_portx_bp_page_cnt2_s cnf71xx; }; union cvmx_ipd_portx_bp_page_cnt3 { uint64_t u64; struct cvmx_ipd_portx_bp_page_cnt3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t bp_enb:1; uint64_t page_cnt:17; +#else + uint64_t page_cnt:17; + uint64_t bp_enb:1; + uint64_t reserved_18_63:46; +#endif } s; + struct cvmx_ipd_portx_bp_page_cnt3_s cn61xx; struct cvmx_ipd_portx_bp_page_cnt3_s cn63xx; struct cvmx_ipd_portx_bp_page_cnt3_s cn63xxp1; + struct cvmx_ipd_portx_bp_page_cnt3_s cn66xx; + struct cvmx_ipd_portx_bp_page_cnt3_s cnf71xx; }; union cvmx_ipd_port_bp_counters2_pairx { uint64_t u64; struct cvmx_ipd_port_bp_counters2_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t cnt_val:25; +#else + uint64_t cnt_val:25; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx; struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1; struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx; struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1; + struct cvmx_ipd_port_bp_counters2_pairx_s cn61xx; struct cvmx_ipd_port_bp_counters2_pairx_s cn63xx; struct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1; + struct cvmx_ipd_port_bp_counters2_pairx_s cn66xx; + struct cvmx_ipd_port_bp_counters2_pairx_s cnf71xx; }; union cvmx_ipd_port_bp_counters3_pairx { uint64_t u64; struct cvmx_ipd_port_bp_counters3_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t cnt_val:25; +#else + uint64_t cnt_val:25; + uint64_t reserved_25_63:39; +#endif } s; + struct cvmx_ipd_port_bp_counters3_pairx_s cn61xx; struct cvmx_ipd_port_bp_counters3_pairx_s cn63xx; struct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1; + struct cvmx_ipd_port_bp_counters3_pairx_s cn66xx; + struct cvmx_ipd_port_bp_counters3_pairx_s cnf71xx; +}; + +union cvmx_ipd_port_bp_counters4_pairx { + uint64_t u64; + struct cvmx_ipd_port_bp_counters4_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t cnt_val:25; +#else + uint64_t cnt_val:25; + uint64_t reserved_25_63:39; +#endif + } s; + struct cvmx_ipd_port_bp_counters4_pairx_s cn61xx; + struct cvmx_ipd_port_bp_counters4_pairx_s cn66xx; + struct cvmx_ipd_port_bp_counters4_pairx_s cnf71xx; }; union cvmx_ipd_port_bp_counters_pairx { uint64_t u64; struct cvmx_ipd_port_bp_counters_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t cnt_val:25; +#else + uint64_t cnt_val:25; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_ipd_port_bp_counters_pairx_s cn30xx; struct cvmx_ipd_port_bp_counters_pairx_s cn31xx; @@ -603,59 +1360,133 @@ union cvmx_ipd_port_bp_counters_pairx { struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1; struct cvmx_ipd_port_bp_counters_pairx_s cn58xx; struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1; + struct cvmx_ipd_port_bp_counters_pairx_s cn61xx; struct cvmx_ipd_port_bp_counters_pairx_s cn63xx; struct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1; + struct cvmx_ipd_port_bp_counters_pairx_s cn66xx; + struct cvmx_ipd_port_bp_counters_pairx_s cnf71xx; +}; + +union cvmx_ipd_port_ptr_fifo_ctl { + uint64_t u64; + struct cvmx_ipd_port_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t ptr:33; + uint64_t max_pkt:7; + uint64_t cena:1; + uint64_t raddr:7; +#else + uint64_t raddr:7; + uint64_t cena:1; + uint64_t max_pkt:7; + uint64_t ptr:33; + uint64_t reserved_48_63:16; +#endif + } s; + struct cvmx_ipd_port_ptr_fifo_ctl_s cn68xx; + struct cvmx_ipd_port_ptr_fifo_ctl_s cn68xxp1; }; union cvmx_ipd_port_qos_x_cnt { uint64_t u64; struct cvmx_ipd_port_qos_x_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wmark:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t wmark:32; +#endif } s; struct cvmx_ipd_port_qos_x_cnt_s cn52xx; struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1; struct cvmx_ipd_port_qos_x_cnt_s cn56xx; struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1; + struct cvmx_ipd_port_qos_x_cnt_s cn61xx; struct cvmx_ipd_port_qos_x_cnt_s cn63xx; struct cvmx_ipd_port_qos_x_cnt_s cn63xxp1; + struct cvmx_ipd_port_qos_x_cnt_s cn66xx; + struct cvmx_ipd_port_qos_x_cnt_s cn68xx; + struct cvmx_ipd_port_qos_x_cnt_s cn68xxp1; + struct cvmx_ipd_port_qos_x_cnt_s cnf71xx; }; union cvmx_ipd_port_qos_intx { uint64_t u64; struct cvmx_ipd_port_qos_intx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t intr:64; +#else uint64_t intr:64; +#endif } s; struct cvmx_ipd_port_qos_intx_s cn52xx; struct cvmx_ipd_port_qos_intx_s cn52xxp1; struct cvmx_ipd_port_qos_intx_s cn56xx; struct cvmx_ipd_port_qos_intx_s cn56xxp1; + struct cvmx_ipd_port_qos_intx_s cn61xx; struct cvmx_ipd_port_qos_intx_s cn63xx; struct cvmx_ipd_port_qos_intx_s cn63xxp1; + struct cvmx_ipd_port_qos_intx_s cn66xx; + struct cvmx_ipd_port_qos_intx_s cn68xx; + struct cvmx_ipd_port_qos_intx_s cn68xxp1; + struct cvmx_ipd_port_qos_intx_s cnf71xx; }; union cvmx_ipd_port_qos_int_enbx { uint64_t u64; struct cvmx_ipd_port_qos_int_enbx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t enb:64; +#else uint64_t enb:64; +#endif } s; struct cvmx_ipd_port_qos_int_enbx_s cn52xx; struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1; struct cvmx_ipd_port_qos_int_enbx_s cn56xx; struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1; + struct cvmx_ipd_port_qos_int_enbx_s cn61xx; struct cvmx_ipd_port_qos_int_enbx_s cn63xx; struct cvmx_ipd_port_qos_int_enbx_s cn63xxp1; + struct cvmx_ipd_port_qos_int_enbx_s cn66xx; + struct cvmx_ipd_port_qos_int_enbx_s cn68xx; + struct cvmx_ipd_port_qos_int_enbx_s cn68xxp1; + struct cvmx_ipd_port_qos_int_enbx_s cnf71xx; +}; + +union cvmx_ipd_port_sopx { + uint64_t u64; + struct cvmx_ipd_port_sopx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t sop:64; +#else + uint64_t sop:64; +#endif + } s; + struct cvmx_ipd_port_sopx_s cn68xx; + struct cvmx_ipd_port_sopx_s cn68xxp1; }; union cvmx_ipd_prc_hold_ptr_fifo_ctl { uint64_t u64; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t max_pkt:3; uint64_t praddr:3; uint64_t ptr:29; uint64_t cena:1; uint64_t raddr:3; +#else + uint64_t raddr:3; + uint64_t cena:1; + uint64_t ptr:29; + uint64_t praddr:3; + uint64_t max_pkt:3; + uint64_t reserved_39_63:25; +#endif } s; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx; @@ -667,18 +1498,29 @@ union cvmx_ipd_prc_hold_ptr_fifo_ctl { struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1; + struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn61xx; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1; + struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn66xx; + struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cnf71xx; }; union cvmx_ipd_prc_port_ptr_fifo_ctl { uint64_t u64; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t max_pkt:7; uint64_t ptr:29; uint64_t cena:1; uint64_t raddr:7; +#else + uint64_t raddr:7; + uint64_t cena:1; + uint64_t ptr:29; + uint64_t max_pkt:7; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx; @@ -690,19 +1532,31 @@ union cvmx_ipd_prc_port_ptr_fifo_ctl { struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1; + struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn61xx; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1; + struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn66xx; + struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cnf71xx; }; union cvmx_ipd_ptr_count { uint64_t u64; struct cvmx_ipd_ptr_count_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t pktv_cnt:1; uint64_t wqev_cnt:1; uint64_t pfif_cnt:3; uint64_t pkt_pcnt:7; uint64_t wqe_pcnt:7; +#else + uint64_t wqe_pcnt:7; + uint64_t pkt_pcnt:7; + uint64_t pfif_cnt:3; + uint64_t wqev_cnt:1; + uint64_t pktv_cnt:1; + uint64_t reserved_19_63:45; +#endif } s; struct cvmx_ipd_ptr_count_s cn30xx; struct cvmx_ipd_ptr_count_s cn31xx; @@ -715,13 +1569,19 @@ union cvmx_ipd_ptr_count { struct cvmx_ipd_ptr_count_s cn56xxp1; struct cvmx_ipd_ptr_count_s cn58xx; struct cvmx_ipd_ptr_count_s cn58xxp1; + struct cvmx_ipd_ptr_count_s cn61xx; struct cvmx_ipd_ptr_count_s cn63xx; struct cvmx_ipd_ptr_count_s cn63xxp1; + struct cvmx_ipd_ptr_count_s cn66xx; + struct cvmx_ipd_ptr_count_s cn68xx; + struct cvmx_ipd_ptr_count_s cn68xxp1; + struct cvmx_ipd_ptr_count_s cnf71xx; }; union cvmx_ipd_pwp_ptr_fifo_ctl { uint64_t u64; struct cvmx_ipd_pwp_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t max_cnts:7; uint64_t wraddr:8; @@ -729,6 +1589,15 @@ union cvmx_ipd_pwp_ptr_fifo_ctl { uint64_t ptr:29; uint64_t cena:1; uint64_t raddr:8; +#else + uint64_t raddr:8; + uint64_t cena:1; + uint64_t ptr:29; + uint64_t praddr:8; + uint64_t wraddr:8; + uint64_t max_cnts:7; + uint64_t reserved_61_63:3; +#endif } s; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn30xx; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn31xx; @@ -740,15 +1609,23 @@ union cvmx_ipd_pwp_ptr_fifo_ctl { struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1; + struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn61xx; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xx; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xxp1; + struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn66xx; + struct cvmx_ipd_pwp_ptr_fifo_ctl_s cnf71xx; }; union cvmx_ipd_qosx_red_marks { uint64_t u64; struct cvmx_ipd_qosx_red_marks_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t drop:32; uint64_t pass:32; +#else + uint64_t pass:32; + uint64_t drop:32; +#endif } s; struct cvmx_ipd_qosx_red_marks_s cn30xx; struct cvmx_ipd_qosx_red_marks_s cn31xx; @@ -761,15 +1638,25 @@ union cvmx_ipd_qosx_red_marks { struct cvmx_ipd_qosx_red_marks_s cn56xxp1; struct cvmx_ipd_qosx_red_marks_s cn58xx; struct cvmx_ipd_qosx_red_marks_s cn58xxp1; + struct cvmx_ipd_qosx_red_marks_s cn61xx; struct cvmx_ipd_qosx_red_marks_s cn63xx; struct cvmx_ipd_qosx_red_marks_s cn63xxp1; + struct cvmx_ipd_qosx_red_marks_s cn66xx; + struct cvmx_ipd_qosx_red_marks_s cn68xx; + struct cvmx_ipd_qosx_red_marks_s cn68xxp1; + struct cvmx_ipd_qosx_red_marks_s cnf71xx; }; union cvmx_ipd_que0_free_page_cnt { uint64_t u64; struct cvmx_ipd_que0_free_page_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t q0_pcnt:32; +#else + uint64_t q0_pcnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ipd_que0_free_page_cnt_s cn30xx; struct cvmx_ipd_que0_free_page_cnt_s cn31xx; @@ -782,16 +1669,57 @@ union cvmx_ipd_que0_free_page_cnt { struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1; struct cvmx_ipd_que0_free_page_cnt_s cn58xx; struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1; + struct cvmx_ipd_que0_free_page_cnt_s cn61xx; struct cvmx_ipd_que0_free_page_cnt_s cn63xx; struct cvmx_ipd_que0_free_page_cnt_s cn63xxp1; + struct cvmx_ipd_que0_free_page_cnt_s cn66xx; + struct cvmx_ipd_que0_free_page_cnt_s cn68xx; + struct cvmx_ipd_que0_free_page_cnt_s cn68xxp1; + struct cvmx_ipd_que0_free_page_cnt_s cnf71xx; +}; + +union cvmx_ipd_red_bpid_enablex { + uint64_t u64; + struct cvmx_ipd_red_bpid_enablex_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t prt_enb:64; +#else + uint64_t prt_enb:64; +#endif + } s; + struct cvmx_ipd_red_bpid_enablex_s cn68xx; + struct cvmx_ipd_red_bpid_enablex_s cn68xxp1; +}; + +union cvmx_ipd_red_delay { + uint64_t u64; + struct cvmx_ipd_red_delay_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_28_63:36; + uint64_t prb_dly:14; + uint64_t avg_dly:14; +#else + uint64_t avg_dly:14; + uint64_t prb_dly:14; + uint64_t reserved_28_63:36; +#endif + } s; + struct cvmx_ipd_red_delay_s cn68xx; + struct cvmx_ipd_red_delay_s cn68xxp1; }; union cvmx_ipd_red_port_enable { uint64_t u64; struct cvmx_ipd_red_port_enable_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t prb_dly:14; uint64_t avg_dly:14; uint64_t prt_enb:36; +#else + uint64_t prt_enb:36; + uint64_t avg_dly:14; + uint64_t prb_dly:14; +#endif } s; struct cvmx_ipd_red_port_enable_s cn30xx; struct cvmx_ipd_red_port_enable_s cn31xx; @@ -804,35 +1732,67 @@ union cvmx_ipd_red_port_enable { struct cvmx_ipd_red_port_enable_s cn56xxp1; struct cvmx_ipd_red_port_enable_s cn58xx; struct cvmx_ipd_red_port_enable_s cn58xxp1; + struct cvmx_ipd_red_port_enable_s cn61xx; struct cvmx_ipd_red_port_enable_s cn63xx; struct cvmx_ipd_red_port_enable_s cn63xxp1; + struct cvmx_ipd_red_port_enable_s cn66xx; + struct cvmx_ipd_red_port_enable_s cnf71xx; }; union cvmx_ipd_red_port_enable2 { uint64_t u64; struct cvmx_ipd_red_port_enable2_s { - uint64_t reserved_8_63:56; - uint64_t prt_enb:8; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t prt_enb:12; +#else + uint64_t prt_enb:12; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_ipd_red_port_enable2_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t prt_enb:4; +#else + uint64_t prt_enb:4; + uint64_t reserved_4_63:60; +#endif } cn52xx; struct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1; struct cvmx_ipd_red_port_enable2_cn52xx cn56xx; struct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1; - struct cvmx_ipd_red_port_enable2_s cn63xx; - struct cvmx_ipd_red_port_enable2_s cn63xxp1; + struct cvmx_ipd_red_port_enable2_s cn61xx; + struct cvmx_ipd_red_port_enable2_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_8_63:56; + uint64_t prt_enb:8; +#else + uint64_t prt_enb:8; + uint64_t reserved_8_63:56; +#endif + } cn63xx; + struct cvmx_ipd_red_port_enable2_cn63xx cn63xxp1; + struct cvmx_ipd_red_port_enable2_s cn66xx; + struct cvmx_ipd_red_port_enable2_s cnf71xx; }; union cvmx_ipd_red_quex_param { uint64_t u64; struct cvmx_ipd_red_quex_param_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t use_pcnt:1; uint64_t new_con:8; uint64_t avg_con:8; uint64_t prb_con:32; +#else + uint64_t prb_con:32; + uint64_t avg_con:8; + uint64_t new_con:8; + uint64_t use_pcnt:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_ipd_red_quex_param_s cn30xx; struct cvmx_ipd_red_quex_param_s cn31xx; @@ -845,16 +1805,53 @@ union cvmx_ipd_red_quex_param { struct cvmx_ipd_red_quex_param_s cn56xxp1; struct cvmx_ipd_red_quex_param_s cn58xx; struct cvmx_ipd_red_quex_param_s cn58xxp1; + struct cvmx_ipd_red_quex_param_s cn61xx; struct cvmx_ipd_red_quex_param_s cn63xx; struct cvmx_ipd_red_quex_param_s cn63xxp1; + struct cvmx_ipd_red_quex_param_s cn66xx; + struct cvmx_ipd_red_quex_param_s cn68xx; + struct cvmx_ipd_red_quex_param_s cn68xxp1; + struct cvmx_ipd_red_quex_param_s cnf71xx; +}; + +union cvmx_ipd_req_wgt { + uint64_t u64; + struct cvmx_ipd_req_wgt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t wgt7:8; + uint64_t wgt6:8; + uint64_t wgt5:8; + uint64_t wgt4:8; + uint64_t wgt3:8; + uint64_t wgt2:8; + uint64_t wgt1:8; + uint64_t wgt0:8; +#else + uint64_t wgt0:8; + uint64_t wgt1:8; + uint64_t wgt2:8; + uint64_t wgt3:8; + uint64_t wgt4:8; + uint64_t wgt5:8; + uint64_t wgt6:8; + uint64_t wgt7:8; +#endif + } s; + struct cvmx_ipd_req_wgt_s cn68xx; }; union cvmx_ipd_sub_port_bp_page_cnt { uint64_t u64; struct cvmx_ipd_sub_port_bp_page_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t port:6; uint64_t page_cnt:25; +#else + uint64_t page_cnt:25; + uint64_t port:6; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx; struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx; @@ -867,26 +1864,48 @@ union cvmx_ipd_sub_port_bp_page_cnt { struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1; struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx; struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1; + struct cvmx_ipd_sub_port_bp_page_cnt_s cn61xx; struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx; struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1; + struct cvmx_ipd_sub_port_bp_page_cnt_s cn66xx; + struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xx; + struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xxp1; + struct cvmx_ipd_sub_port_bp_page_cnt_s cnf71xx; }; union cvmx_ipd_sub_port_fcs { uint64_t u64; struct cvmx_ipd_sub_port_fcs_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t port_bit2:4; uint64_t reserved_32_35:4; uint64_t port_bit:32; +#else + uint64_t port_bit:32; + uint64_t reserved_32_35:4; + uint64_t port_bit2:4; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_ipd_sub_port_fcs_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t port_bit:3; +#else + uint64_t port_bit:3; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_ipd_sub_port_fcs_cn30xx cn31xx; struct cvmx_ipd_sub_port_fcs_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port_bit:32; +#else + uint64_t port_bit:32; + uint64_t reserved_32_63:32; +#endif } cn38xx; struct cvmx_ipd_sub_port_fcs_cn38xx cn38xxp2; struct cvmx_ipd_sub_port_fcs_cn30xx cn50xx; @@ -896,30 +1915,49 @@ union cvmx_ipd_sub_port_fcs { struct cvmx_ipd_sub_port_fcs_s cn56xxp1; struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx; struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1; + struct cvmx_ipd_sub_port_fcs_s cn61xx; struct cvmx_ipd_sub_port_fcs_s cn63xx; struct cvmx_ipd_sub_port_fcs_s cn63xxp1; + struct cvmx_ipd_sub_port_fcs_s cn66xx; + struct cvmx_ipd_sub_port_fcs_s cnf71xx; }; union cvmx_ipd_sub_port_qos_cnt { uint64_t u64; struct cvmx_ipd_sub_port_qos_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_41_63:23; uint64_t port_qos:9; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t port_qos:9; + uint64_t reserved_41_63:23; +#endif } s; struct cvmx_ipd_sub_port_qos_cnt_s cn52xx; struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1; struct cvmx_ipd_sub_port_qos_cnt_s cn56xx; struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1; + struct cvmx_ipd_sub_port_qos_cnt_s cn61xx; struct cvmx_ipd_sub_port_qos_cnt_s cn63xx; struct cvmx_ipd_sub_port_qos_cnt_s cn63xxp1; + struct cvmx_ipd_sub_port_qos_cnt_s cn66xx; + struct cvmx_ipd_sub_port_qos_cnt_s cn68xx; + struct cvmx_ipd_sub_port_qos_cnt_s cn68xxp1; + struct cvmx_ipd_sub_port_qos_cnt_s cnf71xx; }; union cvmx_ipd_wqe_fpa_queue { uint64_t u64; struct cvmx_ipd_wqe_fpa_queue_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t wqe_pool:3; +#else + uint64_t wqe_pool:3; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_ipd_wqe_fpa_queue_s cn30xx; struct cvmx_ipd_wqe_fpa_queue_s cn31xx; @@ -932,15 +1970,25 @@ union cvmx_ipd_wqe_fpa_queue { struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1; struct cvmx_ipd_wqe_fpa_queue_s cn58xx; struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1; + struct cvmx_ipd_wqe_fpa_queue_s cn61xx; struct cvmx_ipd_wqe_fpa_queue_s cn63xx; struct cvmx_ipd_wqe_fpa_queue_s cn63xxp1; + struct cvmx_ipd_wqe_fpa_queue_s cn66xx; + struct cvmx_ipd_wqe_fpa_queue_s cn68xx; + struct cvmx_ipd_wqe_fpa_queue_s cn68xxp1; + struct cvmx_ipd_wqe_fpa_queue_s cnf71xx; }; union cvmx_ipd_wqe_ptr_valid { uint64_t u64; struct cvmx_ipd_wqe_ptr_valid_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t ptr:29; +#else + uint64_t ptr:29; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_ipd_wqe_ptr_valid_s cn30xx; struct cvmx_ipd_wqe_ptr_valid_s cn31xx; @@ -952,8 +2000,11 @@ union cvmx_ipd_wqe_ptr_valid { struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1; struct cvmx_ipd_wqe_ptr_valid_s cn58xx; struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1; + struct cvmx_ipd_wqe_ptr_valid_s cn61xx; struct cvmx_ipd_wqe_ptr_valid_s cn63xx; struct cvmx_ipd_wqe_ptr_valid_s cn63xxp1; + struct cvmx_ipd_wqe_ptr_valid_s cn66xx; + struct cvmx_ipd_wqe_ptr_valid_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h index 7a50a0beb472..10262cb6ff50 100644 --- a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -33,18 +33,18 @@ #define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull)) #define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull)) #define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(0x00011800800007E8ull)) -#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull)) -#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull)) -#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull)) +#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull) + ((block_id) & 3) * 0x40000ull) #define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull)) #define CVMX_L2C_COP0_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8) #define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull)) #define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull)) #define CVMX_L2C_DUT (CVMX_ADD_IO_SEG(0x0001180080000050ull)) -#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 2047) * 8) -#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull)) -#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull)) -#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull)) +#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 8191) * 8) +#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull) + ((block_id) & 3) * 0x40000ull) #define CVMX_L2C_ERR_XMC (CVMX_ADD_IO_SEG(0x00011800808007D8ull)) #define CVMX_L2C_GRPWRR0 (CVMX_ADD_IO_SEG(0x00011800800000C8ull)) #define CVMX_L2C_GRPWRR1 (CVMX_ADD_IO_SEG(0x00011800800000D0ull)) @@ -71,54 +71,119 @@ #define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull)) #define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8) #define CVMX_L2C_PPGRP (CVMX_ADD_IO_SEG(0x00011800800000C0ull)) -#define CVMX_L2C_QOS_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080880200ull)) -#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 7) * 8) +#define CVMX_L2C_QOS_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080880200ull) + ((offset) & 1) * 8) +#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 31) * 8) #define CVMX_L2C_QOS_WGT (CVMX_ADD_IO_SEG(0x0001180080800008ull)) -#define CVMX_L2C_RSCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800410ull)) -#define CVMX_L2C_RSDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800418ull)) +#define CVMX_L2C_RSCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800410ull) + ((offset) & 3) * 64) +#define CVMX_L2C_RSDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800418ull) + ((offset) & 3) * 64) #define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull)) #define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull)) #define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull)) #define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull)) #define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull)) -#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull)) -#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull)) -#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull)) -#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull)) -#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull)) -#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull)) -#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull)) -#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull)) -#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull)) -#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull)) +#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull) + ((block_id) & 3) * 0x40000ull) #define CVMX_L2C_VER_ID (CVMX_ADD_IO_SEG(0x00011800808007E0ull)) #define CVMX_L2C_VER_IOB (CVMX_ADD_IO_SEG(0x00011800808007F0ull)) #define CVMX_L2C_VER_MSC (CVMX_ADD_IO_SEG(0x00011800808007D0ull)) #define CVMX_L2C_VER_PP (CVMX_ADD_IO_SEG(0x00011800808007E8ull)) -#define CVMX_L2C_VIRTID_IOBX(block_id) (CVMX_ADD_IO_SEG(0x00011800808C0200ull)) -#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 7) * 8) +#define CVMX_L2C_VIRTID_IOBX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0200ull) + ((offset) & 1) * 8) +#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 31) * 8) #define CVMX_L2C_VRT_CTL (CVMX_ADD_IO_SEG(0x0001180080800010ull)) #define CVMX_L2C_VRT_MEMX(offset) (CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8) -#define CVMX_L2C_WPAR_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080840200ull)) -#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 7) * 8) -#define CVMX_L2C_XMCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800400ull)) +#define CVMX_L2C_WPAR_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080840200ull) + ((offset) & 1) * 8) +#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 31) * 8) +#define CVMX_L2C_XMCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800400ull) + ((offset) & 3) * 64) #define CVMX_L2C_XMC_CMD (CVMX_ADD_IO_SEG(0x0001180080800028ull)) -#define CVMX_L2C_XMDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800408ull)) +#define CVMX_L2C_XMDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800408ull) + ((offset) & 3) * 64) union cvmx_l2c_big_ctl { uint64_t u64; struct cvmx_l2c_big_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t maxdram:4; uint64_t reserved_1_3:3; uint64_t disable:1; +#else + uint64_t disable:1; + uint64_t reserved_1_3:3; + uint64_t maxdram:4; + uint64_t reserved_8_63:56; +#endif } s; + struct cvmx_l2c_big_ctl_s cn61xx; struct cvmx_l2c_big_ctl_s cn63xx; + struct cvmx_l2c_big_ctl_s cn66xx; + struct cvmx_l2c_big_ctl_s cn68xx; + struct cvmx_l2c_big_ctl_s cn68xxp1; + struct cvmx_l2c_big_ctl_s cnf71xx; }; union cvmx_l2c_bst { uint64_t u64; struct cvmx_l2c_bst_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dutfl:32; + uint64_t rbffl:4; + uint64_t xbffl:4; + uint64_t tdpfl:4; + uint64_t ioccmdfl:4; + uint64_t iocdatfl:4; + uint64_t dutresfl:4; + uint64_t vrtfl:4; + uint64_t tdffl:4; +#else + uint64_t tdffl:4; + uint64_t vrtfl:4; + uint64_t dutresfl:4; + uint64_t iocdatfl:4; + uint64_t ioccmdfl:4; + uint64_t tdpfl:4; + uint64_t xbffl:4; + uint64_t rbffl:4; + uint64_t dutfl:32; +#endif + } s; + struct cvmx_l2c_bst_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_36_63:28; + uint64_t dutfl:4; + uint64_t reserved_17_31:15; + uint64_t ioccmdfl:1; + uint64_t reserved_13_15:3; + uint64_t iocdatfl:1; + uint64_t reserved_9_11:3; + uint64_t dutresfl:1; + uint64_t reserved_5_7:3; + uint64_t vrtfl:1; + uint64_t reserved_1_3:3; + uint64_t tdffl:1; +#else + uint64_t tdffl:1; + uint64_t reserved_1_3:3; + uint64_t vrtfl:1; + uint64_t reserved_5_7:3; + uint64_t dutresfl:1; + uint64_t reserved_9_11:3; + uint64_t iocdatfl:1; + uint64_t reserved_13_15:3; + uint64_t ioccmdfl:1; + uint64_t reserved_17_31:15; + uint64_t dutfl:4; + uint64_t reserved_36_63:28; +#endif + } cn61xx; + struct cvmx_l2c_bst_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t dutfl:6; uint64_t reserved_17_31:15; @@ -131,14 +196,60 @@ union cvmx_l2c_bst { uint64_t vrtfl:1; uint64_t reserved_1_3:3; uint64_t tdffl:1; - } s; - struct cvmx_l2c_bst_s cn63xx; - struct cvmx_l2c_bst_s cn63xxp1; +#else + uint64_t tdffl:1; + uint64_t reserved_1_3:3; + uint64_t vrtfl:1; + uint64_t reserved_5_7:3; + uint64_t dutresfl:1; + uint64_t reserved_9_11:3; + uint64_t iocdatfl:1; + uint64_t reserved_13_15:3; + uint64_t ioccmdfl:1; + uint64_t reserved_17_31:15; + uint64_t dutfl:6; + uint64_t reserved_38_63:26; +#endif + } cn63xx; + struct cvmx_l2c_bst_cn63xx cn63xxp1; + struct cvmx_l2c_bst_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_42_63:22; + uint64_t dutfl:10; + uint64_t reserved_17_31:15; + uint64_t ioccmdfl:1; + uint64_t reserved_13_15:3; + uint64_t iocdatfl:1; + uint64_t reserved_9_11:3; + uint64_t dutresfl:1; + uint64_t reserved_5_7:3; + uint64_t vrtfl:1; + uint64_t reserved_1_3:3; + uint64_t tdffl:1; +#else + uint64_t tdffl:1; + uint64_t reserved_1_3:3; + uint64_t vrtfl:1; + uint64_t reserved_5_7:3; + uint64_t dutresfl:1; + uint64_t reserved_9_11:3; + uint64_t iocdatfl:1; + uint64_t reserved_13_15:3; + uint64_t ioccmdfl:1; + uint64_t reserved_17_31:15; + uint64_t dutfl:10; + uint64_t reserved_42_63:22; +#endif + } cn66xx; + struct cvmx_l2c_bst_s cn68xx; + struct cvmx_l2c_bst_s cn68xxp1; + struct cvmx_l2c_bst_cn61xx cnf71xx; }; union cvmx_l2c_bst0 { uint64_t u64; struct cvmx_l2c_bst0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t dtbnk:1; uint64_t wlb_msk:4; @@ -146,8 +257,18 @@ union cvmx_l2c_bst0 { uint64_t dt:1; uint64_t stin_msk:1; uint64_t wlb_dat:4; +#else + uint64_t wlb_dat:4; + uint64_t stin_msk:1; + uint64_t dt:1; + uint64_t dtcnt:13; + uint64_t wlb_msk:4; + uint64_t dtbnk:1; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_l2c_bst0_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t wlb_msk:4; uint64_t reserved_15_18:4; @@ -155,8 +276,18 @@ union cvmx_l2c_bst0 { uint64_t dt:1; uint64_t reserved_4_4:1; uint64_t wlb_dat:4; +#else + uint64_t wlb_dat:4; + uint64_t reserved_4_4:1; + uint64_t dt:1; + uint64_t dtcnt:9; + uint64_t reserved_15_18:4; + uint64_t wlb_msk:4; + uint64_t reserved_23_63:41; +#endif } cn30xx; struct cvmx_l2c_bst0_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t wlb_msk:4; uint64_t reserved_16_18:3; @@ -164,16 +295,34 @@ union cvmx_l2c_bst0 { uint64_t dt:1; uint64_t stin_msk:1; uint64_t wlb_dat:4; +#else + uint64_t wlb_dat:4; + uint64_t stin_msk:1; + uint64_t dt:1; + uint64_t dtcnt:10; + uint64_t reserved_16_18:3; + uint64_t wlb_msk:4; + uint64_t reserved_23_63:41; +#endif } cn31xx; struct cvmx_l2c_bst0_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t dtcnt:13; uint64_t dt:1; uint64_t stin_msk:1; uint64_t wlb_dat:4; +#else + uint64_t wlb_dat:4; + uint64_t stin_msk:1; + uint64_t dt:1; + uint64_t dtcnt:13; + uint64_t reserved_19_63:45; +#endif } cn38xx; struct cvmx_l2c_bst0_cn38xx cn38xxp2; struct cvmx_l2c_bst0_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t dtbnk:1; uint64_t wlb_msk:4; @@ -182,6 +331,16 @@ union cvmx_l2c_bst0 { uint64_t dt:1; uint64_t stin_msk:1; uint64_t wlb_dat:4; +#else + uint64_t wlb_dat:4; + uint64_t stin_msk:1; + uint64_t dt:1; + uint64_t dtcnt:10; + uint64_t reserved_16_18:3; + uint64_t wlb_msk:4; + uint64_t dtbnk:1; + uint64_t reserved_24_63:40; +#endif } cn50xx; struct cvmx_l2c_bst0_cn50xx cn52xx; struct cvmx_l2c_bst0_cn50xx cn52xxp1; @@ -194,28 +353,51 @@ union cvmx_l2c_bst0 { union cvmx_l2c_bst1 { uint64_t u64; struct cvmx_l2c_bst1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t l2t:9; +#else + uint64_t l2t:9; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_l2c_bst1_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t vwdf:4; uint64_t lrf:2; uint64_t vab_vwcf:1; uint64_t reserved_5_8:4; uint64_t l2t:5; +#else + uint64_t l2t:5; + uint64_t reserved_5_8:4; + uint64_t vab_vwcf:1; + uint64_t lrf:2; + uint64_t vwdf:4; + uint64_t reserved_16_63:48; +#endif } cn30xx; struct cvmx_l2c_bst1_cn30xx cn31xx; struct cvmx_l2c_bst1_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t vwdf:4; uint64_t lrf:2; uint64_t vab_vwcf:1; uint64_t l2t:9; +#else + uint64_t l2t:9; + uint64_t vab_vwcf:1; + uint64_t lrf:2; + uint64_t vwdf:4; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_l2c_bst1_cn38xx cn38xxp2; struct cvmx_l2c_bst1_cn38xx cn50xx; struct cvmx_l2c_bst1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t plc2:1; uint64_t plc1:1; @@ -225,9 +407,21 @@ union cvmx_l2c_bst1 { uint64_t ilc:1; uint64_t vab_vwcf:1; uint64_t l2t:9; +#else + uint64_t l2t:9; + uint64_t vab_vwcf:1; + uint64_t ilc:1; + uint64_t reserved_11_11:1; + uint64_t vwdf:4; + uint64_t plc0:1; + uint64_t plc1:1; + uint64_t plc2:1; + uint64_t reserved_19_63:45; +#endif } cn52xx; struct cvmx_l2c_bst1_cn52xx cn52xxp1; struct cvmx_l2c_bst1_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t plc2:1; uint64_t plc1:1; @@ -239,6 +433,19 @@ union cvmx_l2c_bst1 { uint64_t reserved_10_10:1; uint64_t vab_vwcf0:1; uint64_t l2t:9; +#else + uint64_t l2t:9; + uint64_t vab_vwcf0:1; + uint64_t reserved_10_10:1; + uint64_t vab_vwcf1:1; + uint64_t vwdf0:4; + uint64_t vwdf1:4; + uint64_t ilc:1; + uint64_t plc0:1; + uint64_t plc1:1; + uint64_t plc2:1; + uint64_t reserved_24_63:40; +#endif } cn56xx; struct cvmx_l2c_bst1_cn56xx cn56xxp1; struct cvmx_l2c_bst1_cn38xx cn58xx; @@ -248,6 +455,7 @@ union cvmx_l2c_bst1 { union cvmx_l2c_bst2 { uint64_t u64; struct cvmx_l2c_bst2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mrb:4; uint64_t reserved_4_11:8; @@ -255,8 +463,18 @@ union cvmx_l2c_bst2 { uint64_t picbst:1; uint64_t xrdmsk:1; uint64_t xrddat:1; +#else + uint64_t xrddat:1; + uint64_t xrdmsk:1; + uint64_t picbst:1; + uint64_t ipcbst:1; + uint64_t reserved_4_11:8; + uint64_t mrb:4; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_l2c_bst2_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mrb:4; uint64_t rmdf:4; @@ -265,9 +483,20 @@ union cvmx_l2c_bst2 { uint64_t reserved_2_2:1; uint64_t xrdmsk:1; uint64_t xrddat:1; +#else + uint64_t xrddat:1; + uint64_t xrdmsk:1; + uint64_t reserved_2_2:1; + uint64_t ipcbst:1; + uint64_t reserved_4_7:4; + uint64_t rmdf:4; + uint64_t mrb:4; + uint64_t reserved_16_63:48; +#endif } cn30xx; struct cvmx_l2c_bst2_cn30xx cn31xx; struct cvmx_l2c_bst2_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mrb:4; uint64_t rmdf:4; @@ -276,12 +505,23 @@ union cvmx_l2c_bst2 { uint64_t picbst:1; uint64_t xrdmsk:1; uint64_t xrddat:1; +#else + uint64_t xrddat:1; + uint64_t xrdmsk:1; + uint64_t picbst:1; + uint64_t ipcbst:1; + uint64_t rhdf:4; + uint64_t rmdf:4; + uint64_t mrb:4; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_l2c_bst2_cn38xx cn38xxp2; struct cvmx_l2c_bst2_cn30xx cn50xx; struct cvmx_l2c_bst2_cn30xx cn52xx; struct cvmx_l2c_bst2_cn30xx cn52xxp1; struct cvmx_l2c_bst2_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mrb:4; uint64_t rmdb:4; @@ -290,6 +530,16 @@ union cvmx_l2c_bst2 { uint64_t picbst:1; uint64_t xrdmsk:1; uint64_t xrddat:1; +#else + uint64_t xrddat:1; + uint64_t xrdmsk:1; + uint64_t picbst:1; + uint64_t ipcbst:1; + uint64_t rhdb:4; + uint64_t rmdb:4; + uint64_t mrb:4; + uint64_t reserved_16_63:48; +#endif } cn56xx; struct cvmx_l2c_bst2_cn56xx cn56xxp1; struct cvmx_l2c_bst2_cn56xx cn58xx; @@ -299,48 +549,93 @@ union cvmx_l2c_bst2 { union cvmx_l2c_bst_memx { uint64_t u64; struct cvmx_l2c_bst_memx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t start_bist:1; uint64_t clear_bist:1; uint64_t reserved_5_61:57; uint64_t rdffl:1; uint64_t vbffl:4; +#else + uint64_t vbffl:4; + uint64_t rdffl:1; + uint64_t reserved_5_61:57; + uint64_t clear_bist:1; + uint64_t start_bist:1; +#endif } s; + struct cvmx_l2c_bst_memx_s cn61xx; struct cvmx_l2c_bst_memx_s cn63xx; struct cvmx_l2c_bst_memx_s cn63xxp1; + struct cvmx_l2c_bst_memx_s cn66xx; + struct cvmx_l2c_bst_memx_s cn68xx; + struct cvmx_l2c_bst_memx_s cn68xxp1; + struct cvmx_l2c_bst_memx_s cnf71xx; }; union cvmx_l2c_bst_tdtx { uint64_t u64; struct cvmx_l2c_bst_tdtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t fbfrspfl:8; uint64_t sbffl:8; uint64_t fbffl:8; uint64_t l2dfl:8; +#else + uint64_t l2dfl:8; + uint64_t fbffl:8; + uint64_t sbffl:8; + uint64_t fbfrspfl:8; + uint64_t reserved_32_63:32; +#endif } s; + struct cvmx_l2c_bst_tdtx_s cn61xx; struct cvmx_l2c_bst_tdtx_s cn63xx; struct cvmx_l2c_bst_tdtx_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t sbffl:8; uint64_t fbffl:8; uint64_t l2dfl:8; +#else + uint64_t l2dfl:8; + uint64_t fbffl:8; + uint64_t sbffl:8; + uint64_t reserved_24_63:40; +#endif } cn63xxp1; + struct cvmx_l2c_bst_tdtx_s cn66xx; + struct cvmx_l2c_bst_tdtx_s cn68xx; + struct cvmx_l2c_bst_tdtx_s cn68xxp1; + struct cvmx_l2c_bst_tdtx_s cnf71xx; }; union cvmx_l2c_bst_ttgx { uint64_t u64; struct cvmx_l2c_bst_ttgx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t lrufl:1; uint64_t tagfl:16; +#else + uint64_t tagfl:16; + uint64_t lrufl:1; + uint64_t reserved_17_63:47; +#endif } s; + struct cvmx_l2c_bst_ttgx_s cn61xx; struct cvmx_l2c_bst_ttgx_s cn63xx; struct cvmx_l2c_bst_ttgx_s cn63xxp1; + struct cvmx_l2c_bst_ttgx_s cn66xx; + struct cvmx_l2c_bst_ttgx_s cn68xx; + struct cvmx_l2c_bst_ttgx_s cn68xxp1; + struct cvmx_l2c_bst_ttgx_s cnf71xx; }; union cvmx_l2c_cfg { uint64_t u64; struct cvmx_l2c_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t bstrun:1; uint64_t lbist:1; @@ -356,8 +651,26 @@ union cvmx_l2c_cfg { uint64_t rsp_arb_mode:1; uint64_t rfb_arb_mode:1; uint64_t lrf_arb_mode:1; +#else + uint64_t lrf_arb_mode:1; + uint64_t rfb_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t mwf_crd:4; + uint64_t idxalias:1; + uint64_t fpen:1; + uint64_t fpempty:1; + uint64_t fpexp:4; + uint64_t dfill_dis:1; + uint64_t dpres0:1; + uint64_t dpres1:1; + uint64_t xor_bank:1; + uint64_t lbist:1; + uint64_t bstrun:1; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_l2c_cfg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t fpexp:4; uint64_t fpempty:1; @@ -367,11 +680,23 @@ union cvmx_l2c_cfg { uint64_t rsp_arb_mode:1; uint64_t rfb_arb_mode:1; uint64_t lrf_arb_mode:1; +#else + uint64_t lrf_arb_mode:1; + uint64_t rfb_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t mwf_crd:4; + uint64_t idxalias:1; + uint64_t fpen:1; + uint64_t fpempty:1; + uint64_t fpexp:4; + uint64_t reserved_14_63:50; +#endif } cn30xx; struct cvmx_l2c_cfg_cn30xx cn31xx; struct cvmx_l2c_cfg_cn30xx cn38xx; struct cvmx_l2c_cfg_cn30xx cn38xxp2; struct cvmx_l2c_cfg_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t bstrun:1; uint64_t lbist:1; @@ -384,12 +709,27 @@ union cvmx_l2c_cfg { uint64_t rsp_arb_mode:1; uint64_t rfb_arb_mode:1; uint64_t lrf_arb_mode:1; +#else + uint64_t lrf_arb_mode:1; + uint64_t rfb_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t mwf_crd:4; + uint64_t idxalias:1; + uint64_t fpen:1; + uint64_t fpempty:1; + uint64_t fpexp:4; + uint64_t reserved_14_17:4; + uint64_t lbist:1; + uint64_t bstrun:1; + uint64_t reserved_20_63:44; +#endif } cn50xx; struct cvmx_l2c_cfg_cn50xx cn52xx; struct cvmx_l2c_cfg_cn50xx cn52xxp1; struct cvmx_l2c_cfg_s cn56xx; struct cvmx_l2c_cfg_s cn56xxp1; struct cvmx_l2c_cfg_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t bstrun:1; uint64_t lbist:1; @@ -403,8 +743,24 @@ union cvmx_l2c_cfg { uint64_t rsp_arb_mode:1; uint64_t rfb_arb_mode:1; uint64_t lrf_arb_mode:1; +#else + uint64_t lrf_arb_mode:1; + uint64_t rfb_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t mwf_crd:4; + uint64_t idxalias:1; + uint64_t fpen:1; + uint64_t fpempty:1; + uint64_t fpexp:4; + uint64_t dfill_dis:1; + uint64_t reserved_15_17:3; + uint64_t lbist:1; + uint64_t bstrun:1; + uint64_t reserved_20_63:44; +#endif } cn58xx; struct cvmx_l2c_cfg_cn58xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t dfill_dis:1; uint64_t fpexp:4; @@ -415,22 +771,46 @@ union cvmx_l2c_cfg { uint64_t rsp_arb_mode:1; uint64_t rfb_arb_mode:1; uint64_t lrf_arb_mode:1; +#else + uint64_t lrf_arb_mode:1; + uint64_t rfb_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t mwf_crd:4; + uint64_t idxalias:1; + uint64_t fpen:1; + uint64_t fpempty:1; + uint64_t fpexp:4; + uint64_t dfill_dis:1; + uint64_t reserved_15_63:49; +#endif } cn58xxp1; }; union cvmx_l2c_cop0_mapx { uint64_t u64; struct cvmx_l2c_cop0_mapx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; +#else + uint64_t data:64; +#endif } s; + struct cvmx_l2c_cop0_mapx_s cn61xx; struct cvmx_l2c_cop0_mapx_s cn63xx; struct cvmx_l2c_cop0_mapx_s cn63xxp1; + struct cvmx_l2c_cop0_mapx_s cn66xx; + struct cvmx_l2c_cop0_mapx_s cn68xx; + struct cvmx_l2c_cop0_mapx_s cn68xxp1; + struct cvmx_l2c_cop0_mapx_s cnf71xx; }; union cvmx_l2c_ctl { uint64_t u64; struct cvmx_l2c_ctl_s { - uint64_t reserved_28_63:36; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_30_63:34; + uint64_t sepcmt:1; + uint64_t rdf_fast:1; uint64_t disstgl2i:1; uint64_t l2dfsbe:1; uint64_t l2dfdbe:1; @@ -444,9 +824,95 @@ union cvmx_l2c_ctl { uint64_t vab_thresh:4; uint64_t disecc:1; uint64_t disidxalias:1; +#else + uint64_t disidxalias:1; + uint64_t disecc:1; + uint64_t vab_thresh:4; + uint64_t ef_cnt:7; + uint64_t ef_ena:1; + uint64_t xmc_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t maxlfb:4; + uint64_t maxvab:4; + uint64_t discclk:1; + uint64_t l2dfdbe:1; + uint64_t l2dfsbe:1; + uint64_t disstgl2i:1; + uint64_t rdf_fast:1; + uint64_t sepcmt:1; + uint64_t reserved_30_63:34; +#endif } s; - struct cvmx_l2c_ctl_s cn63xx; + struct cvmx_l2c_ctl_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t rdf_fast:1; + uint64_t disstgl2i:1; + uint64_t l2dfsbe:1; + uint64_t l2dfdbe:1; + uint64_t discclk:1; + uint64_t maxvab:4; + uint64_t maxlfb:4; + uint64_t rsp_arb_mode:1; + uint64_t xmc_arb_mode:1; + uint64_t ef_ena:1; + uint64_t ef_cnt:7; + uint64_t vab_thresh:4; + uint64_t disecc:1; + uint64_t disidxalias:1; +#else + uint64_t disidxalias:1; + uint64_t disecc:1; + uint64_t vab_thresh:4; + uint64_t ef_cnt:7; + uint64_t ef_ena:1; + uint64_t xmc_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t maxlfb:4; + uint64_t maxvab:4; + uint64_t discclk:1; + uint64_t l2dfdbe:1; + uint64_t l2dfsbe:1; + uint64_t disstgl2i:1; + uint64_t rdf_fast:1; + uint64_t reserved_29_63:35; +#endif + } cn61xx; + struct cvmx_l2c_ctl_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_28_63:36; + uint64_t disstgl2i:1; + uint64_t l2dfsbe:1; + uint64_t l2dfdbe:1; + uint64_t discclk:1; + uint64_t maxvab:4; + uint64_t maxlfb:4; + uint64_t rsp_arb_mode:1; + uint64_t xmc_arb_mode:1; + uint64_t ef_ena:1; + uint64_t ef_cnt:7; + uint64_t vab_thresh:4; + uint64_t disecc:1; + uint64_t disidxalias:1; +#else + uint64_t disidxalias:1; + uint64_t disecc:1; + uint64_t vab_thresh:4; + uint64_t ef_cnt:7; + uint64_t ef_ena:1; + uint64_t xmc_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t maxlfb:4; + uint64_t maxvab:4; + uint64_t discclk:1; + uint64_t l2dfdbe:1; + uint64_t l2dfsbe:1; + uint64_t disstgl2i:1; + uint64_t reserved_28_63:36; +#endif + } cn63xx; struct cvmx_l2c_ctl_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t discclk:1; uint64_t maxvab:4; @@ -458,12 +924,30 @@ union cvmx_l2c_ctl { uint64_t vab_thresh:4; uint64_t disecc:1; uint64_t disidxalias:1; +#else + uint64_t disidxalias:1; + uint64_t disecc:1; + uint64_t vab_thresh:4; + uint64_t ef_cnt:7; + uint64_t ef_ena:1; + uint64_t xmc_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t maxlfb:4; + uint64_t maxvab:4; + uint64_t discclk:1; + uint64_t reserved_25_63:39; +#endif } cn63xxp1; + struct cvmx_l2c_ctl_cn61xx cn66xx; + struct cvmx_l2c_ctl_s cn68xx; + struct cvmx_l2c_ctl_cn63xx cn68xxp1; + struct cvmx_l2c_ctl_cn61xx cnf71xx; }; union cvmx_l2c_dbg { uint64_t u64; struct cvmx_l2c_dbg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t lfb_enum:4; uint64_t lfb_dmp:1; @@ -472,8 +956,19 @@ union cvmx_l2c_dbg { uint64_t finv:1; uint64_t l2d:1; uint64_t l2t:1; +#else + uint64_t l2t:1; + uint64_t l2d:1; + uint64_t finv:1; + uint64_t set:3; + uint64_t ppnum:4; + uint64_t lfb_dmp:1; + uint64_t lfb_enum:4; + uint64_t reserved_15_63:49; +#endif } s; struct cvmx_l2c_dbg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t lfb_enum:2; uint64_t lfb_dmp:1; @@ -484,8 +979,21 @@ union cvmx_l2c_dbg { uint64_t finv:1; uint64_t l2d:1; uint64_t l2t:1; +#else + uint64_t l2t:1; + uint64_t l2d:1; + uint64_t finv:1; + uint64_t set:2; + uint64_t reserved_5_5:1; + uint64_t ppnum:1; + uint64_t reserved_7_9:3; + uint64_t lfb_dmp:1; + uint64_t lfb_enum:2; + uint64_t reserved_13_63:51; +#endif } cn30xx; struct cvmx_l2c_dbg_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t lfb_enum:3; uint64_t lfb_dmp:1; @@ -496,10 +1004,23 @@ union cvmx_l2c_dbg { uint64_t finv:1; uint64_t l2d:1; uint64_t l2t:1; +#else + uint64_t l2t:1; + uint64_t l2d:1; + uint64_t finv:1; + uint64_t set:2; + uint64_t reserved_5_5:1; + uint64_t ppnum:1; + uint64_t reserved_7_9:3; + uint64_t lfb_dmp:1; + uint64_t lfb_enum:3; + uint64_t reserved_14_63:50; +#endif } cn31xx; struct cvmx_l2c_dbg_s cn38xx; struct cvmx_l2c_dbg_s cn38xxp2; struct cvmx_l2c_dbg_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t lfb_enum:3; uint64_t lfb_dmp:1; @@ -509,8 +1030,20 @@ union cvmx_l2c_dbg { uint64_t finv:1; uint64_t l2d:1; uint64_t l2t:1; +#else + uint64_t l2t:1; + uint64_t l2d:1; + uint64_t finv:1; + uint64_t set:3; + uint64_t ppnum:1; + uint64_t reserved_7_9:3; + uint64_t lfb_dmp:1; + uint64_t lfb_enum:3; + uint64_t reserved_14_63:50; +#endif } cn50xx; struct cvmx_l2c_dbg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t lfb_enum:3; uint64_t lfb_dmp:1; @@ -520,6 +1053,17 @@ union cvmx_l2c_dbg { uint64_t finv:1; uint64_t l2d:1; uint64_t l2t:1; +#else + uint64_t l2t:1; + uint64_t l2d:1; + uint64_t finv:1; + uint64_t set:3; + uint64_t ppnum:2; + uint64_t reserved_8_9:2; + uint64_t lfb_dmp:1; + uint64_t lfb_enum:3; + uint64_t reserved_14_63:50; +#endif } cn52xx; struct cvmx_l2c_dbg_cn52xx cn52xxp1; struct cvmx_l2c_dbg_s cn56xx; @@ -531,11 +1075,19 @@ union cvmx_l2c_dbg { union cvmx_l2c_dut { uint64_t u64; struct cvmx_l2c_dut_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t dtena:1; uint64_t reserved_30_30:1; uint64_t dt_vld:1; uint64_t dt_tag:29; +#else + uint64_t dt_tag:29; + uint64_t dt_vld:1; + uint64_t reserved_30_30:1; + uint64_t dtena:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_l2c_dut_s cn30xx; struct cvmx_l2c_dut_s cn31xx; @@ -553,18 +1105,77 @@ union cvmx_l2c_dut { union cvmx_l2c_dut_mapx { uint64_t u64; struct cvmx_l2c_dut_mapx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t tag:28; uint64_t reserved_1_9:9; uint64_t valid:1; +#else + uint64_t valid:1; + uint64_t reserved_1_9:9; + uint64_t tag:28; + uint64_t reserved_38_63:26; +#endif } s; + struct cvmx_l2c_dut_mapx_s cn61xx; struct cvmx_l2c_dut_mapx_s cn63xx; struct cvmx_l2c_dut_mapx_s cn63xxp1; + struct cvmx_l2c_dut_mapx_s cn66xx; + struct cvmx_l2c_dut_mapx_s cn68xx; + struct cvmx_l2c_dut_mapx_s cn68xxp1; + struct cvmx_l2c_dut_mapx_s cnf71xx; }; union cvmx_l2c_err_tdtx { uint64_t u64; struct cvmx_l2c_err_tdtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dbe:1; + uint64_t sbe:1; + uint64_t vdbe:1; + uint64_t vsbe:1; + uint64_t syn:10; + uint64_t reserved_22_49:28; + uint64_t wayidx:18; + uint64_t reserved_2_3:2; + uint64_t type:2; +#else + uint64_t type:2; + uint64_t reserved_2_3:2; + uint64_t wayidx:18; + uint64_t reserved_22_49:28; + uint64_t syn:10; + uint64_t vsbe:1; + uint64_t vdbe:1; + uint64_t sbe:1; + uint64_t dbe:1; +#endif + } s; + struct cvmx_l2c_err_tdtx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dbe:1; + uint64_t sbe:1; + uint64_t vdbe:1; + uint64_t vsbe:1; + uint64_t syn:10; + uint64_t reserved_20_49:30; + uint64_t wayidx:16; + uint64_t reserved_2_3:2; + uint64_t type:2; +#else + uint64_t type:2; + uint64_t reserved_2_3:2; + uint64_t wayidx:16; + uint64_t reserved_20_49:30; + uint64_t syn:10; + uint64_t vsbe:1; + uint64_t vdbe:1; + uint64_t sbe:1; + uint64_t dbe:1; +#endif + } cn61xx; + struct cvmx_l2c_err_tdtx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dbe:1; uint64_t sbe:1; uint64_t vdbe:1; @@ -574,14 +1185,75 @@ union cvmx_l2c_err_tdtx { uint64_t wayidx:17; uint64_t reserved_2_3:2; uint64_t type:2; - } s; - struct cvmx_l2c_err_tdtx_s cn63xx; - struct cvmx_l2c_err_tdtx_s cn63xxp1; +#else + uint64_t type:2; + uint64_t reserved_2_3:2; + uint64_t wayidx:17; + uint64_t reserved_21_49:29; + uint64_t syn:10; + uint64_t vsbe:1; + uint64_t vdbe:1; + uint64_t sbe:1; + uint64_t dbe:1; +#endif + } cn63xx; + struct cvmx_l2c_err_tdtx_cn63xx cn63xxp1; + struct cvmx_l2c_err_tdtx_cn63xx cn66xx; + struct cvmx_l2c_err_tdtx_s cn68xx; + struct cvmx_l2c_err_tdtx_s cn68xxp1; + struct cvmx_l2c_err_tdtx_cn61xx cnf71xx; }; union cvmx_l2c_err_ttgx { uint64_t u64; struct cvmx_l2c_err_ttgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dbe:1; + uint64_t sbe:1; + uint64_t noway:1; + uint64_t reserved_56_60:5; + uint64_t syn:6; + uint64_t reserved_22_49:28; + uint64_t wayidx:15; + uint64_t reserved_2_6:5; + uint64_t type:2; +#else + uint64_t type:2; + uint64_t reserved_2_6:5; + uint64_t wayidx:15; + uint64_t reserved_22_49:28; + uint64_t syn:6; + uint64_t reserved_56_60:5; + uint64_t noway:1; + uint64_t sbe:1; + uint64_t dbe:1; +#endif + } s; + struct cvmx_l2c_err_ttgx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dbe:1; + uint64_t sbe:1; + uint64_t noway:1; + uint64_t reserved_56_60:5; + uint64_t syn:6; + uint64_t reserved_20_49:30; + uint64_t wayidx:13; + uint64_t reserved_2_6:5; + uint64_t type:2; +#else + uint64_t type:2; + uint64_t reserved_2_6:5; + uint64_t wayidx:13; + uint64_t reserved_20_49:30; + uint64_t syn:6; + uint64_t reserved_56_60:5; + uint64_t noway:1; + uint64_t sbe:1; + uint64_t dbe:1; +#endif + } cn61xx; + struct cvmx_l2c_err_ttgx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dbe:1; uint64_t sbe:1; uint64_t noway:1; @@ -591,43 +1263,117 @@ union cvmx_l2c_err_ttgx { uint64_t wayidx:14; uint64_t reserved_2_6:5; uint64_t type:2; - } s; - struct cvmx_l2c_err_ttgx_s cn63xx; - struct cvmx_l2c_err_ttgx_s cn63xxp1; +#else + uint64_t type:2; + uint64_t reserved_2_6:5; + uint64_t wayidx:14; + uint64_t reserved_21_49:29; + uint64_t syn:6; + uint64_t reserved_56_60:5; + uint64_t noway:1; + uint64_t sbe:1; + uint64_t dbe:1; +#endif + } cn63xx; + struct cvmx_l2c_err_ttgx_cn63xx cn63xxp1; + struct cvmx_l2c_err_ttgx_cn63xx cn66xx; + struct cvmx_l2c_err_ttgx_s cn68xx; + struct cvmx_l2c_err_ttgx_s cn68xxp1; + struct cvmx_l2c_err_ttgx_cn61xx cnf71xx; }; union cvmx_l2c_err_vbfx { uint64_t u64; struct cvmx_l2c_err_vbfx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t vdbe:1; uint64_t vsbe:1; uint64_t vsyn:10; uint64_t reserved_2_49:48; uint64_t type:2; +#else + uint64_t type:2; + uint64_t reserved_2_49:48; + uint64_t vsyn:10; + uint64_t vsbe:1; + uint64_t vdbe:1; + uint64_t reserved_62_63:2; +#endif } s; + struct cvmx_l2c_err_vbfx_s cn61xx; struct cvmx_l2c_err_vbfx_s cn63xx; struct cvmx_l2c_err_vbfx_s cn63xxp1; + struct cvmx_l2c_err_vbfx_s cn66xx; + struct cvmx_l2c_err_vbfx_s cn68xx; + struct cvmx_l2c_err_vbfx_s cn68xxp1; + struct cvmx_l2c_err_vbfx_s cnf71xx; }; union cvmx_l2c_err_xmc { uint64_t u64; struct cvmx_l2c_err_xmc_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t cmd:6; + uint64_t reserved_54_57:4; + uint64_t sid:6; + uint64_t reserved_38_47:10; + uint64_t addr:38; +#else + uint64_t addr:38; + uint64_t reserved_38_47:10; + uint64_t sid:6; + uint64_t reserved_54_57:4; + uint64_t cmd:6; +#endif + } s; + struct cvmx_l2c_err_xmc_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t cmd:6; uint64_t reserved_52_57:6; uint64_t sid:4; uint64_t reserved_38_47:10; uint64_t addr:38; - } s; - struct cvmx_l2c_err_xmc_s cn63xx; - struct cvmx_l2c_err_xmc_s cn63xxp1; +#else + uint64_t addr:38; + uint64_t reserved_38_47:10; + uint64_t sid:4; + uint64_t reserved_52_57:6; + uint64_t cmd:6; +#endif + } cn61xx; + struct cvmx_l2c_err_xmc_cn61xx cn63xx; + struct cvmx_l2c_err_xmc_cn61xx cn63xxp1; + struct cvmx_l2c_err_xmc_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t cmd:6; + uint64_t reserved_53_57:5; + uint64_t sid:5; + uint64_t reserved_38_47:10; + uint64_t addr:38; +#else + uint64_t addr:38; + uint64_t reserved_38_47:10; + uint64_t sid:5; + uint64_t reserved_53_57:5; + uint64_t cmd:6; +#endif + } cn66xx; + struct cvmx_l2c_err_xmc_s cn68xx; + struct cvmx_l2c_err_xmc_s cn68xxp1; + struct cvmx_l2c_err_xmc_cn61xx cnf71xx; }; union cvmx_l2c_grpwrr0 { uint64_t u64; struct cvmx_l2c_grpwrr0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t plc1rmsk:32; uint64_t plc0rmsk:32; +#else + uint64_t plc0rmsk:32; + uint64_t plc1rmsk:32; +#endif } s; struct cvmx_l2c_grpwrr0_s cn52xx; struct cvmx_l2c_grpwrr0_s cn52xxp1; @@ -638,8 +1384,13 @@ union cvmx_l2c_grpwrr0 { union cvmx_l2c_grpwrr1 { uint64_t u64; struct cvmx_l2c_grpwrr1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t ilcrmsk:32; uint64_t plc2rmsk:32; +#else + uint64_t plc2rmsk:32; + uint64_t ilcrmsk:32; +#endif } s; struct cvmx_l2c_grpwrr1_s cn52xx; struct cvmx_l2c_grpwrr1_s cn52xxp1; @@ -650,6 +1401,7 @@ union cvmx_l2c_grpwrr1 { union cvmx_l2c_int_en { uint64_t u64; struct cvmx_l2c_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t lck2ena:1; uint64_t lckena:1; @@ -660,6 +1412,18 @@ union cvmx_l2c_int_en { uint64_t oob3en:1; uint64_t oob2en:1; uint64_t oob1en:1; +#else + uint64_t oob1en:1; + uint64_t oob2en:1; + uint64_t oob3en:1; + uint64_t l2tsecen:1; + uint64_t l2tdeden:1; + uint64_t l2dsecen:1; + uint64_t l2ddeden:1; + uint64_t lckena:1; + uint64_t lck2ena:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_l2c_int_en_s cn52xx; struct cvmx_l2c_int_en_s cn52xxp1; @@ -670,6 +1434,7 @@ union cvmx_l2c_int_en { union cvmx_l2c_int_ena { uint64_t u64; struct cvmx_l2c_int_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t bigrd:1; uint64_t bigwr:1; @@ -679,9 +1444,22 @@ union cvmx_l2c_int_ena { uint64_t vrtwr:1; uint64_t holewr:1; uint64_t holerd:1; +#else + uint64_t holerd:1; + uint64_t holewr:1; + uint64_t vrtwr:1; + uint64_t vrtidrng:1; + uint64_t vrtadrng:1; + uint64_t vrtpe:1; + uint64_t bigwr:1; + uint64_t bigrd:1; + uint64_t reserved_8_63:56; +#endif } s; + struct cvmx_l2c_int_ena_s cn61xx; struct cvmx_l2c_int_ena_s cn63xx; struct cvmx_l2c_int_ena_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t vrtpe:1; uint64_t vrtadrng:1; @@ -689,13 +1467,30 @@ union cvmx_l2c_int_ena { uint64_t vrtwr:1; uint64_t holewr:1; uint64_t holerd:1; +#else + uint64_t holerd:1; + uint64_t holewr:1; + uint64_t vrtwr:1; + uint64_t vrtidrng:1; + uint64_t vrtadrng:1; + uint64_t vrtpe:1; + uint64_t reserved_6_63:58; +#endif } cn63xxp1; + struct cvmx_l2c_int_ena_s cn66xx; + struct cvmx_l2c_int_ena_s cn68xx; + struct cvmx_l2c_int_ena_s cn68xxp1; + struct cvmx_l2c_int_ena_s cnf71xx; }; union cvmx_l2c_int_reg { uint64_t u64; struct cvmx_l2c_int_reg_s { - uint64_t reserved_17_63:47; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t tad3:1; + uint64_t tad2:1; + uint64_t tad1:1; uint64_t tad0:1; uint64_t reserved_8_15:8; uint64_t bigrd:1; @@ -706,9 +1501,53 @@ union cvmx_l2c_int_reg { uint64_t vrtwr:1; uint64_t holewr:1; uint64_t holerd:1; +#else + uint64_t holerd:1; + uint64_t holewr:1; + uint64_t vrtwr:1; + uint64_t vrtidrng:1; + uint64_t vrtadrng:1; + uint64_t vrtpe:1; + uint64_t bigwr:1; + uint64_t bigrd:1; + uint64_t reserved_8_15:8; + uint64_t tad0:1; + uint64_t tad1:1; + uint64_t tad2:1; + uint64_t tad3:1; + uint64_t reserved_20_63:44; +#endif } s; - struct cvmx_l2c_int_reg_s cn63xx; + struct cvmx_l2c_int_reg_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_17_63:47; + uint64_t tad0:1; + uint64_t reserved_8_15:8; + uint64_t bigrd:1; + uint64_t bigwr:1; + uint64_t vrtpe:1; + uint64_t vrtadrng:1; + uint64_t vrtidrng:1; + uint64_t vrtwr:1; + uint64_t holewr:1; + uint64_t holerd:1; +#else + uint64_t holerd:1; + uint64_t holewr:1; + uint64_t vrtwr:1; + uint64_t vrtidrng:1; + uint64_t vrtadrng:1; + uint64_t vrtpe:1; + uint64_t bigwr:1; + uint64_t bigrd:1; + uint64_t reserved_8_15:8; + uint64_t tad0:1; + uint64_t reserved_17_63:47; +#endif + } cn61xx; + struct cvmx_l2c_int_reg_cn61xx cn63xx; struct cvmx_l2c_int_reg_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t tad0:1; uint64_t reserved_6_15:10; @@ -718,12 +1557,28 @@ union cvmx_l2c_int_reg { uint64_t vrtwr:1; uint64_t holewr:1; uint64_t holerd:1; +#else + uint64_t holerd:1; + uint64_t holewr:1; + uint64_t vrtwr:1; + uint64_t vrtidrng:1; + uint64_t vrtadrng:1; + uint64_t vrtpe:1; + uint64_t reserved_6_15:10; + uint64_t tad0:1; + uint64_t reserved_17_63:47; +#endif } cn63xxp1; + struct cvmx_l2c_int_reg_cn61xx cn66xx; + struct cvmx_l2c_int_reg_s cn68xx; + struct cvmx_l2c_int_reg_s cn68xxp1; + struct cvmx_l2c_int_reg_cn61xx cnf71xx; }; union cvmx_l2c_int_stat { uint64_t u64; struct cvmx_l2c_int_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t lck2:1; uint64_t lck:1; @@ -734,6 +1589,18 @@ union cvmx_l2c_int_stat { uint64_t oob3:1; uint64_t oob2:1; uint64_t oob1:1; +#else + uint64_t oob1:1; + uint64_t oob2:1; + uint64_t oob3:1; + uint64_t l2tsec:1; + uint64_t l2tded:1; + uint64_t l2dsec:1; + uint64_t l2dded:1; + uint64_t lck:1; + uint64_t lck2:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_l2c_int_stat_s cn52xx; struct cvmx_l2c_int_stat_s cn52xxp1; @@ -744,28 +1611,53 @@ union cvmx_l2c_int_stat { union cvmx_l2c_iocx_pfc { uint64_t u64; struct cvmx_l2c_iocx_pfc_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t count:64; +#else uint64_t count:64; +#endif } s; + struct cvmx_l2c_iocx_pfc_s cn61xx; struct cvmx_l2c_iocx_pfc_s cn63xx; struct cvmx_l2c_iocx_pfc_s cn63xxp1; + struct cvmx_l2c_iocx_pfc_s cn66xx; + struct cvmx_l2c_iocx_pfc_s cn68xx; + struct cvmx_l2c_iocx_pfc_s cn68xxp1; + struct cvmx_l2c_iocx_pfc_s cnf71xx; }; union cvmx_l2c_iorx_pfc { uint64_t u64; struct cvmx_l2c_iorx_pfc_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t count:64; +#else uint64_t count:64; +#endif } s; + struct cvmx_l2c_iorx_pfc_s cn61xx; struct cvmx_l2c_iorx_pfc_s cn63xx; struct cvmx_l2c_iorx_pfc_s cn63xxp1; + struct cvmx_l2c_iorx_pfc_s cn66xx; + struct cvmx_l2c_iorx_pfc_s cn68xx; + struct cvmx_l2c_iorx_pfc_s cn68xxp1; + struct cvmx_l2c_iorx_pfc_s cnf71xx; }; union cvmx_l2c_lckbase { uint64_t u64; struct cvmx_l2c_lckbase_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t lck_base:27; uint64_t reserved_1_3:3; uint64_t lck_ena:1; +#else + uint64_t lck_ena:1; + uint64_t reserved_1_3:3; + uint64_t lck_base:27; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_l2c_lckbase_s cn30xx; struct cvmx_l2c_lckbase_s cn31xx; @@ -783,8 +1675,13 @@ union cvmx_l2c_lckbase { union cvmx_l2c_lckoff { uint64_t u64; struct cvmx_l2c_lckoff_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t lck_offset:10; +#else + uint64_t lck_offset:10; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_l2c_lckoff_s cn30xx; struct cvmx_l2c_lckoff_s cn31xx; @@ -802,6 +1699,7 @@ union cvmx_l2c_lckoff { union cvmx_l2c_lfb0 { uint64_t u64; struct cvmx_l2c_lfb0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t stcpnd:1; uint64_t stpnd:1; @@ -816,8 +1714,25 @@ union cvmx_l2c_lfb0 { uint64_t sid:9; uint64_t cmd:4; uint64_t vld:1; +#else + uint64_t vld:1; + uint64_t cmd:4; + uint64_t sid:9; + uint64_t vabnum:4; + uint64_t set:3; + uint64_t ihd:1; + uint64_t itl:1; + uint64_t inxt:4; + uint64_t vam:1; + uint64_t stcfl:1; + uint64_t stinv:1; + uint64_t stpnd:1; + uint64_t stcpnd:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_l2c_lfb0_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t stcpnd:1; uint64_t stpnd:1; @@ -835,8 +1750,28 @@ union cvmx_l2c_lfb0 { uint64_t sid:9; uint64_t cmd:4; uint64_t vld:1; +#else + uint64_t vld:1; + uint64_t cmd:4; + uint64_t sid:9; + uint64_t vabnum:2; + uint64_t reserved_16_17:2; + uint64_t set:2; + uint64_t reserved_20_20:1; + uint64_t ihd:1; + uint64_t itl:1; + uint64_t inxt:2; + uint64_t reserved_25_26:2; + uint64_t vam:1; + uint64_t stcfl:1; + uint64_t stinv:1; + uint64_t stpnd:1; + uint64_t stcpnd:1; + uint64_t reserved_32_63:32; +#endif } cn30xx; struct cvmx_l2c_lfb0_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t stcpnd:1; uint64_t stpnd:1; @@ -854,10 +1789,30 @@ union cvmx_l2c_lfb0 { uint64_t sid:9; uint64_t cmd:4; uint64_t vld:1; +#else + uint64_t vld:1; + uint64_t cmd:4; + uint64_t sid:9; + uint64_t vabnum:3; + uint64_t reserved_17_17:1; + uint64_t set:2; + uint64_t reserved_20_20:1; + uint64_t ihd:1; + uint64_t itl:1; + uint64_t inxt:3; + uint64_t reserved_26_26:1; + uint64_t vam:1; + uint64_t stcfl:1; + uint64_t stinv:1; + uint64_t stpnd:1; + uint64_t stcpnd:1; + uint64_t reserved_32_63:32; +#endif } cn31xx; struct cvmx_l2c_lfb0_s cn38xx; struct cvmx_l2c_lfb0_s cn38xxp2; struct cvmx_l2c_lfb0_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t stcpnd:1; uint64_t stpnd:1; @@ -874,6 +1829,24 @@ union cvmx_l2c_lfb0 { uint64_t sid:9; uint64_t cmd:4; uint64_t vld:1; +#else + uint64_t vld:1; + uint64_t cmd:4; + uint64_t sid:9; + uint64_t vabnum:3; + uint64_t reserved_17_17:1; + uint64_t set:3; + uint64_t ihd:1; + uint64_t itl:1; + uint64_t inxt:3; + uint64_t reserved_26_26:1; + uint64_t vam:1; + uint64_t stcfl:1; + uint64_t stinv:1; + uint64_t stpnd:1; + uint64_t stcpnd:1; + uint64_t reserved_32_63:32; +#endif } cn50xx; struct cvmx_l2c_lfb0_cn50xx cn52xx; struct cvmx_l2c_lfb0_cn50xx cn52xxp1; @@ -886,6 +1859,7 @@ union cvmx_l2c_lfb0 { union cvmx_l2c_lfb1 { uint64_t u64; struct cvmx_l2c_lfb1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t dsgoing:1; uint64_t bid:2; @@ -905,6 +1879,27 @@ union cvmx_l2c_lfb1 { uint64_t prbrty:1; uint64_t wtprb:1; uint64_t vld:1; +#else + uint64_t vld:1; + uint64_t wtprb:1; + uint64_t prbrty:1; + uint64_t wtmfl:1; + uint64_t wtvtm:1; + uint64_t wtstrsc:1; + uint64_t wtstrsp:1; + uint64_t wtstdt:1; + uint64_t wtrda:1; + uint64_t wtstm:1; + uint64_t wtwrm:1; + uint64_t wtwhf:1; + uint64_t wtwhp:1; + uint64_t wtdq:1; + uint64_t wtdw:1; + uint64_t wtrsp:1; + uint64_t bid:2; + uint64_t dsgoing:1; + uint64_t reserved_19_63:45; +#endif } s; struct cvmx_l2c_lfb1_s cn30xx; struct cvmx_l2c_lfb1_s cn31xx; @@ -922,35 +1917,69 @@ union cvmx_l2c_lfb1 { union cvmx_l2c_lfb2 { uint64_t u64; struct cvmx_l2c_lfb2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_l2c_lfb2_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t lfb_tag:19; uint64_t lfb_idx:8; +#else + uint64_t lfb_idx:8; + uint64_t lfb_tag:19; + uint64_t reserved_27_63:37; +#endif } cn30xx; struct cvmx_l2c_lfb2_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t lfb_tag:17; uint64_t lfb_idx:10; +#else + uint64_t lfb_idx:10; + uint64_t lfb_tag:17; + uint64_t reserved_27_63:37; +#endif } cn31xx; struct cvmx_l2c_lfb2_cn31xx cn38xx; struct cvmx_l2c_lfb2_cn31xx cn38xxp2; struct cvmx_l2c_lfb2_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t lfb_tag:20; uint64_t lfb_idx:7; +#else + uint64_t lfb_idx:7; + uint64_t lfb_tag:20; + uint64_t reserved_27_63:37; +#endif } cn50xx; struct cvmx_l2c_lfb2_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t lfb_tag:18; uint64_t lfb_idx:9; +#else + uint64_t lfb_idx:9; + uint64_t lfb_tag:18; + uint64_t reserved_27_63:37; +#endif } cn52xx; struct cvmx_l2c_lfb2_cn52xx cn52xxp1; struct cvmx_l2c_lfb2_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t lfb_tag:16; uint64_t lfb_idx:11; +#else + uint64_t lfb_idx:11; + uint64_t lfb_tag:16; + uint64_t reserved_27_63:37; +#endif } cn56xx; struct cvmx_l2c_lfb2_cn56xx cn56xxp1; struct cvmx_l2c_lfb2_cn56xx cn58xx; @@ -960,21 +1989,41 @@ union cvmx_l2c_lfb2 { union cvmx_l2c_lfb3 { uint64_t u64; struct cvmx_l2c_lfb3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t stpartdis:1; uint64_t lfb_hwm:4; +#else + uint64_t lfb_hwm:4; + uint64_t stpartdis:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_l2c_lfb3_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t stpartdis:1; uint64_t reserved_2_3:2; uint64_t lfb_hwm:2; +#else + uint64_t lfb_hwm:2; + uint64_t reserved_2_3:2; + uint64_t stpartdis:1; + uint64_t reserved_5_63:59; +#endif } cn30xx; struct cvmx_l2c_lfb3_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t stpartdis:1; uint64_t reserved_3_3:1; uint64_t lfb_hwm:3; +#else + uint64_t lfb_hwm:3; + uint64_t reserved_3_3:1; + uint64_t stpartdis:1; + uint64_t reserved_5_63:59; +#endif } cn31xx; struct cvmx_l2c_lfb3_s cn38xx; struct cvmx_l2c_lfb3_s cn38xxp2; @@ -990,9 +2039,15 @@ union cvmx_l2c_lfb3 { union cvmx_l2c_oob { uint64_t u64; struct cvmx_l2c_oob_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dwbena:1; uint64_t stena:1; +#else + uint64_t stena:1; + uint64_t dwbena:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_l2c_oob_s cn52xx; struct cvmx_l2c_oob_s cn52xxp1; @@ -1003,12 +2058,21 @@ union cvmx_l2c_oob { union cvmx_l2c_oob1 { uint64_t u64; struct cvmx_l2c_oob1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t fadr:27; uint64_t fsrc:1; uint64_t reserved_34_35:2; uint64_t sadr:14; uint64_t reserved_14_19:6; uint64_t size:14; +#else + uint64_t size:14; + uint64_t reserved_14_19:6; + uint64_t sadr:14; + uint64_t reserved_34_35:2; + uint64_t fsrc:1; + uint64_t fadr:27; +#endif } s; struct cvmx_l2c_oob1_s cn52xx; struct cvmx_l2c_oob1_s cn52xxp1; @@ -1019,12 +2083,21 @@ union cvmx_l2c_oob1 { union cvmx_l2c_oob2 { uint64_t u64; struct cvmx_l2c_oob2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t fadr:27; uint64_t fsrc:1; uint64_t reserved_34_35:2; uint64_t sadr:14; uint64_t reserved_14_19:6; uint64_t size:14; +#else + uint64_t size:14; + uint64_t reserved_14_19:6; + uint64_t sadr:14; + uint64_t reserved_34_35:2; + uint64_t fsrc:1; + uint64_t fadr:27; +#endif } s; struct cvmx_l2c_oob2_s cn52xx; struct cvmx_l2c_oob2_s cn52xxp1; @@ -1035,12 +2108,21 @@ union cvmx_l2c_oob2 { union cvmx_l2c_oob3 { uint64_t u64; struct cvmx_l2c_oob3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t fadr:27; uint64_t fsrc:1; uint64_t reserved_34_35:2; uint64_t sadr:14; uint64_t reserved_14_19:6; uint64_t size:14; +#else + uint64_t size:14; + uint64_t reserved_14_19:6; + uint64_t sadr:14; + uint64_t reserved_34_35:2; + uint64_t fsrc:1; + uint64_t fadr:27; +#endif } s; struct cvmx_l2c_oob3_s cn52xx; struct cvmx_l2c_oob3_s cn52xxp1; @@ -1051,8 +2133,13 @@ union cvmx_l2c_oob3 { union cvmx_l2c_pfcx { uint64_t u64; struct cvmx_l2c_pfcx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t pfcnt0:36; +#else + uint64_t pfcnt0:36; + uint64_t reserved_36_63:28; +#endif } s; struct cvmx_l2c_pfcx_s cn30xx; struct cvmx_l2c_pfcx_s cn31xx; @@ -1070,6 +2157,7 @@ union cvmx_l2c_pfcx { union cvmx_l2c_pfctl { uint64_t u64; struct cvmx_l2c_pfctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t cnt3rdclr:1; uint64_t cnt2rdclr:1; @@ -1087,6 +2175,25 @@ union cvmx_l2c_pfctl { uint64_t cnt0ena:1; uint64_t cnt0clr:1; uint64_t cnt0sel:6; +#else + uint64_t cnt0sel:6; + uint64_t cnt0clr:1; + uint64_t cnt0ena:1; + uint64_t cnt1sel:6; + uint64_t cnt1clr:1; + uint64_t cnt1ena:1; + uint64_t cnt2sel:6; + uint64_t cnt2clr:1; + uint64_t cnt2ena:1; + uint64_t cnt3sel:6; + uint64_t cnt3clr:1; + uint64_t cnt3ena:1; + uint64_t cnt0rdclr:1; + uint64_t cnt1rdclr:1; + uint64_t cnt2rdclr:1; + uint64_t cnt3rdclr:1; + uint64_t reserved_36_63:28; +#endif } s; struct cvmx_l2c_pfctl_s cn30xx; struct cvmx_l2c_pfctl_s cn31xx; @@ -1104,6 +2211,7 @@ union cvmx_l2c_pfctl { union cvmx_l2c_ppgrp { uint64_t u64; struct cvmx_l2c_ppgrp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t pp11grp:2; uint64_t pp10grp:2; @@ -1117,13 +2225,36 @@ union cvmx_l2c_ppgrp { uint64_t pp2grp:2; uint64_t pp1grp:2; uint64_t pp0grp:2; +#else + uint64_t pp0grp:2; + uint64_t pp1grp:2; + uint64_t pp2grp:2; + uint64_t pp3grp:2; + uint64_t pp4grp:2; + uint64_t pp5grp:2; + uint64_t pp6grp:2; + uint64_t pp7grp:2; + uint64_t pp8grp:2; + uint64_t pp9grp:2; + uint64_t pp10grp:2; + uint64_t pp11grp:2; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_l2c_ppgrp_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t pp3grp:2; uint64_t pp2grp:2; uint64_t pp1grp:2; uint64_t pp0grp:2; +#else + uint64_t pp0grp:2; + uint64_t pp1grp:2; + uint64_t pp2grp:2; + uint64_t pp3grp:2; + uint64_t reserved_8_63:56; +#endif } cn52xx; struct cvmx_l2c_ppgrp_cn52xx cn52xxp1; struct cvmx_l2c_ppgrp_s cn56xx; @@ -1133,81 +2264,200 @@ union cvmx_l2c_ppgrp { union cvmx_l2c_qos_iobx { uint64_t u64; struct cvmx_l2c_qos_iobx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t dwblvl:3; + uint64_t reserved_3_3:1; + uint64_t lvl:3; +#else + uint64_t lvl:3; + uint64_t reserved_3_3:1; + uint64_t dwblvl:3; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_l2c_qos_iobx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t dwblvl:2; uint64_t reserved_2_3:2; uint64_t lvl:2; - } s; - struct cvmx_l2c_qos_iobx_s cn63xx; - struct cvmx_l2c_qos_iobx_s cn63xxp1; +#else + uint64_t lvl:2; + uint64_t reserved_2_3:2; + uint64_t dwblvl:2; + uint64_t reserved_6_63:58; +#endif + } cn61xx; + struct cvmx_l2c_qos_iobx_cn61xx cn63xx; + struct cvmx_l2c_qos_iobx_cn61xx cn63xxp1; + struct cvmx_l2c_qos_iobx_cn61xx cn66xx; + struct cvmx_l2c_qos_iobx_s cn68xx; + struct cvmx_l2c_qos_iobx_s cn68xxp1; + struct cvmx_l2c_qos_iobx_cn61xx cnf71xx; }; union cvmx_l2c_qos_ppx { uint64_t u64; struct cvmx_l2c_qos_ppx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t lvl:3; +#else + uint64_t lvl:3; + uint64_t reserved_3_63:61; +#endif + } s; + struct cvmx_l2c_qos_ppx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t lvl:2; - } s; - struct cvmx_l2c_qos_ppx_s cn63xx; - struct cvmx_l2c_qos_ppx_s cn63xxp1; +#else + uint64_t lvl:2; + uint64_t reserved_2_63:62; +#endif + } cn61xx; + struct cvmx_l2c_qos_ppx_cn61xx cn63xx; + struct cvmx_l2c_qos_ppx_cn61xx cn63xxp1; + struct cvmx_l2c_qos_ppx_cn61xx cn66xx; + struct cvmx_l2c_qos_ppx_s cn68xx; + struct cvmx_l2c_qos_ppx_s cn68xxp1; + struct cvmx_l2c_qos_ppx_cn61xx cnf71xx; }; union cvmx_l2c_qos_wgt { uint64_t u64; struct cvmx_l2c_qos_wgt_s { - uint64_t reserved_32_63:32; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t wgt7:8; + uint64_t wgt6:8; + uint64_t wgt5:8; + uint64_t wgt4:8; uint64_t wgt3:8; uint64_t wgt2:8; uint64_t wgt1:8; uint64_t wgt0:8; +#else + uint64_t wgt0:8; + uint64_t wgt1:8; + uint64_t wgt2:8; + uint64_t wgt3:8; + uint64_t wgt4:8; + uint64_t wgt5:8; + uint64_t wgt6:8; + uint64_t wgt7:8; +#endif } s; - struct cvmx_l2c_qos_wgt_s cn63xx; - struct cvmx_l2c_qos_wgt_s cn63xxp1; + struct cvmx_l2c_qos_wgt_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wgt3:8; + uint64_t wgt2:8; + uint64_t wgt1:8; + uint64_t wgt0:8; +#else + uint64_t wgt0:8; + uint64_t wgt1:8; + uint64_t wgt2:8; + uint64_t wgt3:8; + uint64_t reserved_32_63:32; +#endif + } cn61xx; + struct cvmx_l2c_qos_wgt_cn61xx cn63xx; + struct cvmx_l2c_qos_wgt_cn61xx cn63xxp1; + struct cvmx_l2c_qos_wgt_cn61xx cn66xx; + struct cvmx_l2c_qos_wgt_s cn68xx; + struct cvmx_l2c_qos_wgt_s cn68xxp1; + struct cvmx_l2c_qos_wgt_cn61xx cnf71xx; }; union cvmx_l2c_rscx_pfc { uint64_t u64; struct cvmx_l2c_rscx_pfc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; +#else + uint64_t count:64; +#endif } s; + struct cvmx_l2c_rscx_pfc_s cn61xx; struct cvmx_l2c_rscx_pfc_s cn63xx; struct cvmx_l2c_rscx_pfc_s cn63xxp1; + struct cvmx_l2c_rscx_pfc_s cn66xx; + struct cvmx_l2c_rscx_pfc_s cn68xx; + struct cvmx_l2c_rscx_pfc_s cn68xxp1; + struct cvmx_l2c_rscx_pfc_s cnf71xx; }; union cvmx_l2c_rsdx_pfc { uint64_t u64; struct cvmx_l2c_rsdx_pfc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; +#else + uint64_t count:64; +#endif } s; + struct cvmx_l2c_rsdx_pfc_s cn61xx; struct cvmx_l2c_rsdx_pfc_s cn63xx; struct cvmx_l2c_rsdx_pfc_s cn63xxp1; + struct cvmx_l2c_rsdx_pfc_s cn66xx; + struct cvmx_l2c_rsdx_pfc_s cn68xx; + struct cvmx_l2c_rsdx_pfc_s cn68xxp1; + struct cvmx_l2c_rsdx_pfc_s cnf71xx; }; union cvmx_l2c_spar0 { uint64_t u64; struct cvmx_l2c_spar0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t umsk3:8; uint64_t umsk2:8; uint64_t umsk1:8; uint64_t umsk0:8; +#else + uint64_t umsk0:8; + uint64_t umsk1:8; + uint64_t umsk2:8; + uint64_t umsk3:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_l2c_spar0_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t umsk0:4; +#else + uint64_t umsk0:4; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_l2c_spar0_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t umsk1:4; uint64_t reserved_4_7:4; uint64_t umsk0:4; +#else + uint64_t umsk0:4; + uint64_t reserved_4_7:4; + uint64_t umsk1:4; + uint64_t reserved_12_63:52; +#endif } cn31xx; struct cvmx_l2c_spar0_s cn38xx; struct cvmx_l2c_spar0_s cn38xxp2; struct cvmx_l2c_spar0_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t umsk1:8; uint64_t umsk0:8; +#else + uint64_t umsk0:8; + uint64_t umsk1:8; + uint64_t reserved_16_63:48; +#endif } cn50xx; struct cvmx_l2c_spar0_s cn52xx; struct cvmx_l2c_spar0_s cn52xxp1; @@ -1220,11 +2470,19 @@ union cvmx_l2c_spar0 { union cvmx_l2c_spar1 { uint64_t u64; struct cvmx_l2c_spar1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t umsk7:8; uint64_t umsk6:8; uint64_t umsk5:8; uint64_t umsk4:8; +#else + uint64_t umsk4:8; + uint64_t umsk5:8; + uint64_t umsk6:8; + uint64_t umsk7:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_l2c_spar1_s cn38xx; struct cvmx_l2c_spar1_s cn38xxp2; @@ -1237,11 +2495,19 @@ union cvmx_l2c_spar1 { union cvmx_l2c_spar2 { uint64_t u64; struct cvmx_l2c_spar2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t umsk11:8; uint64_t umsk10:8; uint64_t umsk9:8; uint64_t umsk8:8; +#else + uint64_t umsk8:8; + uint64_t umsk9:8; + uint64_t umsk10:8; + uint64_t umsk11:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_l2c_spar2_s cn38xx; struct cvmx_l2c_spar2_s cn38xxp2; @@ -1254,11 +2520,19 @@ union cvmx_l2c_spar2 { union cvmx_l2c_spar3 { uint64_t u64; struct cvmx_l2c_spar3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t umsk15:8; uint64_t umsk14:8; uint64_t umsk13:8; uint64_t umsk12:8; +#else + uint64_t umsk12:8; + uint64_t umsk13:8; + uint64_t umsk14:8; + uint64_t umsk15:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_l2c_spar3_s cn38xx; struct cvmx_l2c_spar3_s cn38xxp2; @@ -1269,12 +2543,22 @@ union cvmx_l2c_spar3 { union cvmx_l2c_spar4 { uint64_t u64; struct cvmx_l2c_spar4_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t umskiob:8; +#else + uint64_t umskiob:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_l2c_spar4_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t umskiob:4; +#else + uint64_t umskiob:4; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_l2c_spar4_cn30xx cn31xx; struct cvmx_l2c_spar4_s cn38xx; @@ -1291,6 +2575,7 @@ union cvmx_l2c_spar4 { union cvmx_l2c_tadx_ecc0 { uint64_t u64; struct cvmx_l2c_tadx_ecc0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t ow3ecc:10; uint64_t reserved_42_47:6; @@ -1299,14 +2584,30 @@ union cvmx_l2c_tadx_ecc0 { uint64_t ow1ecc:10; uint64_t reserved_10_15:6; uint64_t ow0ecc:10; +#else + uint64_t ow0ecc:10; + uint64_t reserved_10_15:6; + uint64_t ow1ecc:10; + uint64_t reserved_26_31:6; + uint64_t ow2ecc:10; + uint64_t reserved_42_47:6; + uint64_t ow3ecc:10; + uint64_t reserved_58_63:6; +#endif } s; + struct cvmx_l2c_tadx_ecc0_s cn61xx; struct cvmx_l2c_tadx_ecc0_s cn63xx; struct cvmx_l2c_tadx_ecc0_s cn63xxp1; + struct cvmx_l2c_tadx_ecc0_s cn66xx; + struct cvmx_l2c_tadx_ecc0_s cn68xx; + struct cvmx_l2c_tadx_ecc0_s cn68xxp1; + struct cvmx_l2c_tadx_ecc0_s cnf71xx; }; union cvmx_l2c_tadx_ecc1 { uint64_t u64; struct cvmx_l2c_tadx_ecc1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t ow7ecc:10; uint64_t reserved_42_47:6; @@ -1315,14 +2616,30 @@ union cvmx_l2c_tadx_ecc1 { uint64_t ow5ecc:10; uint64_t reserved_10_15:6; uint64_t ow4ecc:10; +#else + uint64_t ow4ecc:10; + uint64_t reserved_10_15:6; + uint64_t ow5ecc:10; + uint64_t reserved_26_31:6; + uint64_t ow6ecc:10; + uint64_t reserved_42_47:6; + uint64_t ow7ecc:10; + uint64_t reserved_58_63:6; +#endif } s; + struct cvmx_l2c_tadx_ecc1_s cn61xx; struct cvmx_l2c_tadx_ecc1_s cn63xx; struct cvmx_l2c_tadx_ecc1_s cn63xxp1; + struct cvmx_l2c_tadx_ecc1_s cn66xx; + struct cvmx_l2c_tadx_ecc1_s cn68xx; + struct cvmx_l2c_tadx_ecc1_s cn68xxp1; + struct cvmx_l2c_tadx_ecc1_s cnf71xx; }; union cvmx_l2c_tadx_ien { uint64_t u64; struct cvmx_l2c_tadx_ien_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t wrdislmc:1; uint64_t rddislmc:1; @@ -1333,9 +2650,23 @@ union cvmx_l2c_tadx_ien { uint64_t tagsbe:1; uint64_t l2ddbe:1; uint64_t l2dsbe:1; +#else + uint64_t l2dsbe:1; + uint64_t l2ddbe:1; + uint64_t tagsbe:1; + uint64_t tagdbe:1; + uint64_t vbfsbe:1; + uint64_t vbfdbe:1; + uint64_t noway:1; + uint64_t rddislmc:1; + uint64_t wrdislmc:1; + uint64_t reserved_9_63:55; +#endif } s; + struct cvmx_l2c_tadx_ien_s cn61xx; struct cvmx_l2c_tadx_ien_s cn63xx; struct cvmx_l2c_tadx_ien_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t noway:1; uint64_t vbfdbe:1; @@ -1344,12 +2675,27 @@ union cvmx_l2c_tadx_ien { uint64_t tagsbe:1; uint64_t l2ddbe:1; uint64_t l2dsbe:1; +#else + uint64_t l2dsbe:1; + uint64_t l2ddbe:1; + uint64_t tagsbe:1; + uint64_t tagdbe:1; + uint64_t vbfsbe:1; + uint64_t vbfdbe:1; + uint64_t noway:1; + uint64_t reserved_7_63:57; +#endif } cn63xxp1; + struct cvmx_l2c_tadx_ien_s cn66xx; + struct cvmx_l2c_tadx_ien_s cn68xx; + struct cvmx_l2c_tadx_ien_s cn68xxp1; + struct cvmx_l2c_tadx_ien_s cnf71xx; }; union cvmx_l2c_tadx_int { uint64_t u64; struct cvmx_l2c_tadx_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t wrdislmc:1; uint64_t rddislmc:1; @@ -1360,62 +2706,129 @@ union cvmx_l2c_tadx_int { uint64_t tagsbe:1; uint64_t l2ddbe:1; uint64_t l2dsbe:1; +#else + uint64_t l2dsbe:1; + uint64_t l2ddbe:1; + uint64_t tagsbe:1; + uint64_t tagdbe:1; + uint64_t vbfsbe:1; + uint64_t vbfdbe:1; + uint64_t noway:1; + uint64_t rddislmc:1; + uint64_t wrdislmc:1; + uint64_t reserved_9_63:55; +#endif } s; + struct cvmx_l2c_tadx_int_s cn61xx; struct cvmx_l2c_tadx_int_s cn63xx; + struct cvmx_l2c_tadx_int_s cn66xx; + struct cvmx_l2c_tadx_int_s cn68xx; + struct cvmx_l2c_tadx_int_s cn68xxp1; + struct cvmx_l2c_tadx_int_s cnf71xx; }; union cvmx_l2c_tadx_pfc0 { uint64_t u64; struct cvmx_l2c_tadx_pfc0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; +#else + uint64_t count:64; +#endif } s; + struct cvmx_l2c_tadx_pfc0_s cn61xx; struct cvmx_l2c_tadx_pfc0_s cn63xx; struct cvmx_l2c_tadx_pfc0_s cn63xxp1; + struct cvmx_l2c_tadx_pfc0_s cn66xx; + struct cvmx_l2c_tadx_pfc0_s cn68xx; + struct cvmx_l2c_tadx_pfc0_s cn68xxp1; + struct cvmx_l2c_tadx_pfc0_s cnf71xx; }; union cvmx_l2c_tadx_pfc1 { uint64_t u64; struct cvmx_l2c_tadx_pfc1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; +#else + uint64_t count:64; +#endif } s; + struct cvmx_l2c_tadx_pfc1_s cn61xx; struct cvmx_l2c_tadx_pfc1_s cn63xx; struct cvmx_l2c_tadx_pfc1_s cn63xxp1; + struct cvmx_l2c_tadx_pfc1_s cn66xx; + struct cvmx_l2c_tadx_pfc1_s cn68xx; + struct cvmx_l2c_tadx_pfc1_s cn68xxp1; + struct cvmx_l2c_tadx_pfc1_s cnf71xx; }; union cvmx_l2c_tadx_pfc2 { uint64_t u64; struct cvmx_l2c_tadx_pfc2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; +#else + uint64_t count:64; +#endif } s; + struct cvmx_l2c_tadx_pfc2_s cn61xx; struct cvmx_l2c_tadx_pfc2_s cn63xx; struct cvmx_l2c_tadx_pfc2_s cn63xxp1; + struct cvmx_l2c_tadx_pfc2_s cn66xx; + struct cvmx_l2c_tadx_pfc2_s cn68xx; + struct cvmx_l2c_tadx_pfc2_s cn68xxp1; + struct cvmx_l2c_tadx_pfc2_s cnf71xx; }; union cvmx_l2c_tadx_pfc3 { uint64_t u64; struct cvmx_l2c_tadx_pfc3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; +#else + uint64_t count:64; +#endif } s; + struct cvmx_l2c_tadx_pfc3_s cn61xx; struct cvmx_l2c_tadx_pfc3_s cn63xx; struct cvmx_l2c_tadx_pfc3_s cn63xxp1; + struct cvmx_l2c_tadx_pfc3_s cn66xx; + struct cvmx_l2c_tadx_pfc3_s cn68xx; + struct cvmx_l2c_tadx_pfc3_s cn68xxp1; + struct cvmx_l2c_tadx_pfc3_s cnf71xx; }; union cvmx_l2c_tadx_prf { uint64_t u64; struct cvmx_l2c_tadx_prf_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt3sel:8; uint64_t cnt2sel:8; uint64_t cnt1sel:8; uint64_t cnt0sel:8; +#else + uint64_t cnt0sel:8; + uint64_t cnt1sel:8; + uint64_t cnt2sel:8; + uint64_t cnt3sel:8; + uint64_t reserved_32_63:32; +#endif } s; + struct cvmx_l2c_tadx_prf_s cn61xx; struct cvmx_l2c_tadx_prf_s cn63xx; struct cvmx_l2c_tadx_prf_s cn63xxp1; + struct cvmx_l2c_tadx_prf_s cn66xx; + struct cvmx_l2c_tadx_prf_s cn68xx; + struct cvmx_l2c_tadx_prf_s cn68xxp1; + struct cvmx_l2c_tadx_prf_s cnf71xx; }; union cvmx_l2c_tadx_tag { uint64_t u64; struct cvmx_l2c_tadx_tag_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_46_63:18; uint64_t ecc:6; uint64_t reserved_36_39:4; @@ -1425,145 +2838,330 @@ union cvmx_l2c_tadx_tag { uint64_t valid:1; uint64_t dirty:1; uint64_t lock:1; +#else + uint64_t lock:1; + uint64_t dirty:1; + uint64_t valid:1; + uint64_t use:1; + uint64_t reserved_4_16:13; + uint64_t tag:19; + uint64_t reserved_36_39:4; + uint64_t ecc:6; + uint64_t reserved_46_63:18; +#endif } s; + struct cvmx_l2c_tadx_tag_s cn61xx; struct cvmx_l2c_tadx_tag_s cn63xx; struct cvmx_l2c_tadx_tag_s cn63xxp1; + struct cvmx_l2c_tadx_tag_s cn66xx; + struct cvmx_l2c_tadx_tag_s cn68xx; + struct cvmx_l2c_tadx_tag_s cn68xxp1; + struct cvmx_l2c_tadx_tag_s cnf71xx; }; union cvmx_l2c_ver_id { uint64_t u64; struct cvmx_l2c_ver_id_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mask:64; +#else + uint64_t mask:64; +#endif } s; + struct cvmx_l2c_ver_id_s cn61xx; struct cvmx_l2c_ver_id_s cn63xx; struct cvmx_l2c_ver_id_s cn63xxp1; + struct cvmx_l2c_ver_id_s cn66xx; + struct cvmx_l2c_ver_id_s cn68xx; + struct cvmx_l2c_ver_id_s cn68xxp1; + struct cvmx_l2c_ver_id_s cnf71xx; }; union cvmx_l2c_ver_iob { uint64_t u64; struct cvmx_l2c_ver_iob_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_2_63:62; + uint64_t mask:2; +#else + uint64_t mask:2; + uint64_t reserved_2_63:62; +#endif + } s; + struct cvmx_l2c_ver_iob_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t mask:1; - } s; - struct cvmx_l2c_ver_iob_s cn63xx; - struct cvmx_l2c_ver_iob_s cn63xxp1; +#else + uint64_t mask:1; + uint64_t reserved_1_63:63; +#endif + } cn61xx; + struct cvmx_l2c_ver_iob_cn61xx cn63xx; + struct cvmx_l2c_ver_iob_cn61xx cn63xxp1; + struct cvmx_l2c_ver_iob_cn61xx cn66xx; + struct cvmx_l2c_ver_iob_s cn68xx; + struct cvmx_l2c_ver_iob_s cn68xxp1; + struct cvmx_l2c_ver_iob_cn61xx cnf71xx; }; union cvmx_l2c_ver_msc { uint64_t u64; struct cvmx_l2c_ver_msc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t invl2:1; uint64_t dwb:1; +#else + uint64_t dwb:1; + uint64_t invl2:1; + uint64_t reserved_2_63:62; +#endif } s; + struct cvmx_l2c_ver_msc_s cn61xx; struct cvmx_l2c_ver_msc_s cn63xx; + struct cvmx_l2c_ver_msc_s cn66xx; + struct cvmx_l2c_ver_msc_s cn68xx; + struct cvmx_l2c_ver_msc_s cn68xxp1; + struct cvmx_l2c_ver_msc_s cnf71xx; }; union cvmx_l2c_ver_pp { uint64_t u64; struct cvmx_l2c_ver_pp_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t mask:32; +#else + uint64_t mask:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_l2c_ver_pp_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mask:4; +#else + uint64_t mask:4; + uint64_t reserved_4_63:60; +#endif + } cn61xx; + struct cvmx_l2c_ver_pp_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mask:6; - } s; - struct cvmx_l2c_ver_pp_s cn63xx; - struct cvmx_l2c_ver_pp_s cn63xxp1; +#else + uint64_t mask:6; + uint64_t reserved_6_63:58; +#endif + } cn63xx; + struct cvmx_l2c_ver_pp_cn63xx cn63xxp1; + struct cvmx_l2c_ver_pp_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t mask:10; +#else + uint64_t mask:10; + uint64_t reserved_10_63:54; +#endif + } cn66xx; + struct cvmx_l2c_ver_pp_s cn68xx; + struct cvmx_l2c_ver_pp_s cn68xxp1; + struct cvmx_l2c_ver_pp_cn61xx cnf71xx; }; union cvmx_l2c_virtid_iobx { uint64_t u64; struct cvmx_l2c_virtid_iobx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t dwbid:6; uint64_t reserved_6_7:2; uint64_t id:6; +#else + uint64_t id:6; + uint64_t reserved_6_7:2; + uint64_t dwbid:6; + uint64_t reserved_14_63:50; +#endif } s; + struct cvmx_l2c_virtid_iobx_s cn61xx; struct cvmx_l2c_virtid_iobx_s cn63xx; struct cvmx_l2c_virtid_iobx_s cn63xxp1; + struct cvmx_l2c_virtid_iobx_s cn66xx; + struct cvmx_l2c_virtid_iobx_s cn68xx; + struct cvmx_l2c_virtid_iobx_s cn68xxp1; + struct cvmx_l2c_virtid_iobx_s cnf71xx; }; union cvmx_l2c_virtid_ppx { uint64_t u64; struct cvmx_l2c_virtid_ppx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t id:6; +#else + uint64_t id:6; + uint64_t reserved_6_63:58; +#endif } s; + struct cvmx_l2c_virtid_ppx_s cn61xx; struct cvmx_l2c_virtid_ppx_s cn63xx; struct cvmx_l2c_virtid_ppx_s cn63xxp1; + struct cvmx_l2c_virtid_ppx_s cn66xx; + struct cvmx_l2c_virtid_ppx_s cn68xx; + struct cvmx_l2c_virtid_ppx_s cn68xxp1; + struct cvmx_l2c_virtid_ppx_s cnf71xx; }; union cvmx_l2c_vrt_ctl { uint64_t u64; struct cvmx_l2c_vrt_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t ooberr:1; uint64_t reserved_7_7:1; uint64_t memsz:3; uint64_t numid:3; uint64_t enable:1; +#else + uint64_t enable:1; + uint64_t numid:3; + uint64_t memsz:3; + uint64_t reserved_7_7:1; + uint64_t ooberr:1; + uint64_t reserved_9_63:55; +#endif } s; + struct cvmx_l2c_vrt_ctl_s cn61xx; struct cvmx_l2c_vrt_ctl_s cn63xx; struct cvmx_l2c_vrt_ctl_s cn63xxp1; + struct cvmx_l2c_vrt_ctl_s cn66xx; + struct cvmx_l2c_vrt_ctl_s cn68xx; + struct cvmx_l2c_vrt_ctl_s cn68xxp1; + struct cvmx_l2c_vrt_ctl_s cnf71xx; }; union cvmx_l2c_vrt_memx { uint64_t u64; struct cvmx_l2c_vrt_memx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t parity:4; uint64_t data:32; +#else + uint64_t data:32; + uint64_t parity:4; + uint64_t reserved_36_63:28; +#endif } s; + struct cvmx_l2c_vrt_memx_s cn61xx; struct cvmx_l2c_vrt_memx_s cn63xx; struct cvmx_l2c_vrt_memx_s cn63xxp1; + struct cvmx_l2c_vrt_memx_s cn66xx; + struct cvmx_l2c_vrt_memx_s cn68xx; + struct cvmx_l2c_vrt_memx_s cn68xxp1; + struct cvmx_l2c_vrt_memx_s cnf71xx; }; union cvmx_l2c_wpar_iobx { uint64_t u64; struct cvmx_l2c_wpar_iobx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mask:16; +#else + uint64_t mask:16; + uint64_t reserved_16_63:48; +#endif } s; + struct cvmx_l2c_wpar_iobx_s cn61xx; struct cvmx_l2c_wpar_iobx_s cn63xx; struct cvmx_l2c_wpar_iobx_s cn63xxp1; + struct cvmx_l2c_wpar_iobx_s cn66xx; + struct cvmx_l2c_wpar_iobx_s cn68xx; + struct cvmx_l2c_wpar_iobx_s cn68xxp1; + struct cvmx_l2c_wpar_iobx_s cnf71xx; }; union cvmx_l2c_wpar_ppx { uint64_t u64; struct cvmx_l2c_wpar_ppx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mask:16; +#else + uint64_t mask:16; + uint64_t reserved_16_63:48; +#endif } s; + struct cvmx_l2c_wpar_ppx_s cn61xx; struct cvmx_l2c_wpar_ppx_s cn63xx; struct cvmx_l2c_wpar_ppx_s cn63xxp1; + struct cvmx_l2c_wpar_ppx_s cn66xx; + struct cvmx_l2c_wpar_ppx_s cn68xx; + struct cvmx_l2c_wpar_ppx_s cn68xxp1; + struct cvmx_l2c_wpar_ppx_s cnf71xx; }; union cvmx_l2c_xmcx_pfc { uint64_t u64; struct cvmx_l2c_xmcx_pfc_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t count:64; +#else uint64_t count:64; +#endif } s; + struct cvmx_l2c_xmcx_pfc_s cn61xx; struct cvmx_l2c_xmcx_pfc_s cn63xx; struct cvmx_l2c_xmcx_pfc_s cn63xxp1; + struct cvmx_l2c_xmcx_pfc_s cn66xx; + struct cvmx_l2c_xmcx_pfc_s cn68xx; + struct cvmx_l2c_xmcx_pfc_s cn68xxp1; + struct cvmx_l2c_xmcx_pfc_s cnf71xx; }; union cvmx_l2c_xmc_cmd { uint64_t u64; struct cvmx_l2c_xmc_cmd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t inuse:1; uint64_t cmd:6; uint64_t reserved_38_56:19; uint64_t addr:38; +#else + uint64_t addr:38; + uint64_t reserved_38_56:19; + uint64_t cmd:6; + uint64_t inuse:1; +#endif } s; + struct cvmx_l2c_xmc_cmd_s cn61xx; struct cvmx_l2c_xmc_cmd_s cn63xx; struct cvmx_l2c_xmc_cmd_s cn63xxp1; + struct cvmx_l2c_xmc_cmd_s cn66xx; + struct cvmx_l2c_xmc_cmd_s cn68xx; + struct cvmx_l2c_xmc_cmd_s cn68xxp1; + struct cvmx_l2c_xmc_cmd_s cnf71xx; }; union cvmx_l2c_xmdx_pfc { uint64_t u64; struct cvmx_l2c_xmdx_pfc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; +#else + uint64_t count:64; +#endif } s; + struct cvmx_l2c_xmdx_pfc_s cn61xx; struct cvmx_l2c_xmdx_pfc_s cn63xx; struct cvmx_l2c_xmdx_pfc_s cn63xxp1; + struct cvmx_l2c_xmdx_pfc_s cn66xx; + struct cvmx_l2c_xmdx_pfc_s cn68xx; + struct cvmx_l2c_xmdx_pfc_s cn68xxp1; + struct cvmx_l2c_xmdx_pfc_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h index 60543e0e77fc..11a456215638 100644 --- a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -44,9 +44,15 @@ union cvmx_l2d_bst0 { uint64_t u64; struct cvmx_l2d_bst0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t ftl:1; uint64_t q0stat:34; +#else + uint64_t q0stat:34; + uint64_t ftl:1; + uint64_t reserved_35_63:29; +#endif } s; struct cvmx_l2d_bst0_s cn30xx; struct cvmx_l2d_bst0_s cn31xx; @@ -64,8 +70,13 @@ union cvmx_l2d_bst0 { union cvmx_l2d_bst1 { uint64_t u64; struct cvmx_l2d_bst1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q1stat:34; +#else + uint64_t q1stat:34; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_l2d_bst1_s cn30xx; struct cvmx_l2d_bst1_s cn31xx; @@ -83,8 +94,13 @@ union cvmx_l2d_bst1 { union cvmx_l2d_bst2 { uint64_t u64; struct cvmx_l2d_bst2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q2stat:34; +#else + uint64_t q2stat:34; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_l2d_bst2_s cn30xx; struct cvmx_l2d_bst2_s cn31xx; @@ -102,8 +118,13 @@ union cvmx_l2d_bst2 { union cvmx_l2d_bst3 { uint64_t u64; struct cvmx_l2d_bst3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q3stat:34; +#else + uint64_t q3stat:34; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_l2d_bst3_s cn30xx; struct cvmx_l2d_bst3_s cn31xx; @@ -121,6 +142,7 @@ union cvmx_l2d_bst3 { union cvmx_l2d_err { uint64_t u64; struct cvmx_l2d_err_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t bmhclsel:1; uint64_t ded_err:1; @@ -128,6 +150,15 @@ union cvmx_l2d_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t bmhclsel:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_l2d_err_s cn30xx; struct cvmx_l2d_err_s cn31xx; @@ -145,48 +176,97 @@ union cvmx_l2d_err { union cvmx_l2d_fadr { uint64_t u64; struct cvmx_l2d_fadr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t fadru:1; uint64_t fowmsk:4; uint64_t fset:3; uint64_t fadr:11; +#else + uint64_t fadr:11; + uint64_t fset:3; + uint64_t fowmsk:4; + uint64_t fadru:1; + uint64_t reserved_19_63:45; +#endif } s; struct cvmx_l2d_fadr_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t fowmsk:4; uint64_t reserved_13_13:1; uint64_t fset:2; uint64_t reserved_9_10:2; uint64_t fadr:9; +#else + uint64_t fadr:9; + uint64_t reserved_9_10:2; + uint64_t fset:2; + uint64_t reserved_13_13:1; + uint64_t fowmsk:4; + uint64_t reserved_18_63:46; +#endif } cn30xx; struct cvmx_l2d_fadr_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t fowmsk:4; uint64_t reserved_13_13:1; uint64_t fset:2; uint64_t reserved_10_10:1; uint64_t fadr:10; +#else + uint64_t fadr:10; + uint64_t reserved_10_10:1; + uint64_t fset:2; + uint64_t reserved_13_13:1; + uint64_t fowmsk:4; + uint64_t reserved_18_63:46; +#endif } cn31xx; struct cvmx_l2d_fadr_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t fowmsk:4; uint64_t fset:3; uint64_t fadr:11; +#else + uint64_t fadr:11; + uint64_t fset:3; + uint64_t fowmsk:4; + uint64_t reserved_18_63:46; +#endif } cn38xx; struct cvmx_l2d_fadr_cn38xx cn38xxp2; struct cvmx_l2d_fadr_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t fowmsk:4; uint64_t fset:3; uint64_t reserved_8_10:3; uint64_t fadr:8; +#else + uint64_t fadr:8; + uint64_t reserved_8_10:3; + uint64_t fset:3; + uint64_t fowmsk:4; + uint64_t reserved_18_63:46; +#endif } cn50xx; struct cvmx_l2d_fadr_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t fowmsk:4; uint64_t fset:3; uint64_t reserved_10_10:1; uint64_t fadr:10; +#else + uint64_t fadr:10; + uint64_t reserved_10_10:1; + uint64_t fset:3; + uint64_t fowmsk:4; + uint64_t reserved_18_63:46; +#endif } cn52xx; struct cvmx_l2d_fadr_cn52xx cn52xxp1; struct cvmx_l2d_fadr_s cn56xx; @@ -198,9 +278,15 @@ union cvmx_l2d_fadr { union cvmx_l2d_fsyn0 { uint64_t u64; struct cvmx_l2d_fsyn0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t fsyn_ow1:10; uint64_t fsyn_ow0:10; +#else + uint64_t fsyn_ow0:10; + uint64_t fsyn_ow1:10; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_l2d_fsyn0_s cn30xx; struct cvmx_l2d_fsyn0_s cn31xx; @@ -218,9 +304,15 @@ union cvmx_l2d_fsyn0 { union cvmx_l2d_fsyn1 { uint64_t u64; struct cvmx_l2d_fsyn1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t fsyn_ow3:10; uint64_t fsyn_ow2:10; +#else + uint64_t fsyn_ow2:10; + uint64_t fsyn_ow3:10; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_l2d_fsyn1_s cn30xx; struct cvmx_l2d_fsyn1_s cn31xx; @@ -238,8 +330,13 @@ union cvmx_l2d_fsyn1 { union cvmx_l2d_fus0 { uint64_t u64; struct cvmx_l2d_fus0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q0fus:34; +#else + uint64_t q0fus:34; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_l2d_fus0_s cn30xx; struct cvmx_l2d_fus0_s cn31xx; @@ -257,8 +354,13 @@ union cvmx_l2d_fus0 { union cvmx_l2d_fus1 { uint64_t u64; struct cvmx_l2d_fus1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q1fus:34; +#else + uint64_t q1fus:34; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_l2d_fus1_s cn30xx; struct cvmx_l2d_fus1_s cn31xx; @@ -276,8 +378,13 @@ union cvmx_l2d_fus1 { union cvmx_l2d_fus2 { uint64_t u64; struct cvmx_l2d_fus2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q2fus:34; +#else + uint64_t q2fus:34; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_l2d_fus2_s cn30xx; struct cvmx_l2d_fus2_s cn31xx; @@ -295,61 +402,123 @@ union cvmx_l2d_fus2 { union cvmx_l2d_fus3 { uint64_t u64; struct cvmx_l2d_fus3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ema_ctl:3; uint64_t reserved_34_36:3; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t reserved_34_36:3; + uint64_t ema_ctl:3; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_l2d_fus3_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t crip_64k:1; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t crip_64k:1; + uint64_t reserved_35_63:29; +#endif } cn30xx; struct cvmx_l2d_fus3_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t crip_128k:1; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t crip_128k:1; + uint64_t reserved_35_63:29; +#endif } cn31xx; struct cvmx_l2d_fus3_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t crip_256k:1; uint64_t crip_512k:1; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t crip_512k:1; + uint64_t crip_256k:1; + uint64_t reserved_36_63:28; +#endif } cn38xx; struct cvmx_l2d_fus3_cn38xx cn38xxp2; struct cvmx_l2d_fus3_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ema_ctl:3; uint64_t reserved_36_36:1; uint64_t crip_32k:1; uint64_t crip_64k:1; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t crip_64k:1; + uint64_t crip_32k:1; + uint64_t reserved_36_36:1; + uint64_t ema_ctl:3; + uint64_t reserved_40_63:24; +#endif } cn50xx; struct cvmx_l2d_fus3_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ema_ctl:3; uint64_t reserved_36_36:1; uint64_t crip_128k:1; uint64_t crip_256k:1; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t crip_256k:1; + uint64_t crip_128k:1; + uint64_t reserved_36_36:1; + uint64_t ema_ctl:3; + uint64_t reserved_40_63:24; +#endif } cn52xx; struct cvmx_l2d_fus3_cn52xx cn52xxp1; struct cvmx_l2d_fus3_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ema_ctl:3; uint64_t reserved_36_36:1; uint64_t crip_512k:1; uint64_t crip_1024k:1; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t crip_1024k:1; + uint64_t crip_512k:1; + uint64_t reserved_36_36:1; + uint64_t ema_ctl:3; + uint64_t reserved_40_63:24; +#endif } cn56xx; struct cvmx_l2d_fus3_cn56xx cn56xxp1; struct cvmx_l2d_fus3_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t ema_ctl:2; uint64_t reserved_36_36:1; uint64_t crip_512k:1; uint64_t crip_1024k:1; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t crip_1024k:1; + uint64_t crip_512k:1; + uint64_t reserved_36_36:1; + uint64_t ema_ctl:2; + uint64_t reserved_39_63:25; +#endif } cn58xx; struct cvmx_l2d_fus3_cn58xx cn58xxp1; }; diff --git a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h index 873968f55eeb..83ce22c080e6 100644 --- a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -33,6 +33,7 @@ union cvmx_l2t_err { uint64_t u64; struct cvmx_l2t_err_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t fadru:1; uint64_t lck_intena2:1; @@ -47,8 +48,25 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:10; + uint64_t fset:3; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t fadru:1; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_l2t_err_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -64,8 +82,26 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:8; + uint64_t reserved_19_20:2; + uint64_t fset:2; + uint64_t reserved_23_23:1; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t reserved_28_63:36; +#endif } cn30xx; struct cvmx_l2t_err_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -81,8 +117,26 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:9; + uint64_t reserved_20_20:1; + uint64_t fset:2; + uint64_t reserved_23_23:1; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t reserved_28_63:36; +#endif } cn31xx; struct cvmx_l2t_err_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -96,9 +150,25 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:10; + uint64_t fset:3; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t reserved_28_63:36; +#endif } cn38xx; struct cvmx_l2t_err_cn38xx cn38xxp2; struct cvmx_l2t_err_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -113,8 +183,25 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:7; + uint64_t reserved_18_20:3; + uint64_t fset:3; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t reserved_28_63:36; +#endif } cn50xx; struct cvmx_l2t_err_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -129,6 +216,22 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:9; + uint64_t reserved_20_20:1; + uint64_t fset:3; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t reserved_28_63:36; +#endif } cn52xx; struct cvmx_l2t_err_cn52xx cn52xxp1; struct cvmx_l2t_err_s cn56xx; diff --git a/arch/mips/include/asm/octeon/cvmx-led-defs.h b/arch/mips/include/asm/octeon/cvmx-led-defs.h index e25173bb8bb7..d36d42b8307b 100644 --- a/arch/mips/include/asm/octeon/cvmx-led-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-led-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -45,8 +45,13 @@ union cvmx_led_blink { uint64_t u64; struct cvmx_led_blink_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rate:8; +#else + uint64_t rate:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_led_blink_s cn38xx; struct cvmx_led_blink_s cn38xxp2; @@ -59,8 +64,13 @@ union cvmx_led_blink { union cvmx_led_clk_phase { uint64_t u64; struct cvmx_led_clk_phase_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t phase:7; +#else + uint64_t phase:7; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_led_clk_phase_s cn38xx; struct cvmx_led_clk_phase_s cn38xxp2; @@ -73,8 +83,13 @@ union cvmx_led_clk_phase { union cvmx_led_cylon { uint64_t u64; struct cvmx_led_cylon_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t rate:16; +#else + uint64_t rate:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_led_cylon_s cn38xx; struct cvmx_led_cylon_s cn38xxp2; @@ -87,8 +102,13 @@ union cvmx_led_cylon { union cvmx_led_dbg { uint64_t u64; struct cvmx_led_dbg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t dbg_en:1; +#else + uint64_t dbg_en:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_led_dbg_s cn38xx; struct cvmx_led_dbg_s cn38xxp2; @@ -101,8 +121,13 @@ union cvmx_led_dbg { union cvmx_led_en { uint64_t u64; struct cvmx_led_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t en:1; +#else + uint64_t en:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_led_en_s cn38xx; struct cvmx_led_en_s cn38xxp2; @@ -115,8 +140,13 @@ union cvmx_led_en { union cvmx_led_polarity { uint64_t u64; struct cvmx_led_polarity_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t polarity:1; +#else + uint64_t polarity:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_led_polarity_s cn38xx; struct cvmx_led_polarity_s cn38xxp2; @@ -129,8 +159,13 @@ union cvmx_led_polarity { union cvmx_led_prt { uint64_t u64; struct cvmx_led_prt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t prt_en:8; +#else + uint64_t prt_en:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_led_prt_s cn38xx; struct cvmx_led_prt_s cn38xxp2; @@ -143,8 +178,13 @@ union cvmx_led_prt { union cvmx_led_prt_fmt { uint64_t u64; struct cvmx_led_prt_fmt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t format:4; +#else + uint64_t format:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_led_prt_fmt_s cn38xx; struct cvmx_led_prt_fmt_s cn38xxp2; @@ -157,8 +197,13 @@ union cvmx_led_prt_fmt { union cvmx_led_prt_statusx { uint64_t u64; struct cvmx_led_prt_statusx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t status:6; +#else + uint64_t status:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_led_prt_statusx_s cn38xx; struct cvmx_led_prt_statusx_s cn38xxp2; @@ -171,8 +216,13 @@ union cvmx_led_prt_statusx { union cvmx_led_udd_cntx { uint64_t u64; struct cvmx_led_udd_cntx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t cnt:6; +#else + uint64_t cnt:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_led_udd_cntx_s cn38xx; struct cvmx_led_udd_cntx_s cn38xxp2; @@ -185,8 +235,13 @@ union cvmx_led_udd_cntx { union cvmx_led_udd_datx { uint64_t u64; struct cvmx_led_udd_datx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t dat:32; +#else + uint64_t dat:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_led_udd_datx_s cn38xx; struct cvmx_led_udd_datx_s cn38xxp2; @@ -199,8 +254,13 @@ union cvmx_led_udd_datx { union cvmx_led_udd_dat_clrx { uint64_t u64; struct cvmx_led_udd_dat_clrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t clr:32; +#else + uint64_t clr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_led_udd_dat_clrx_s cn38xx; struct cvmx_led_udd_dat_clrx_s cn38xxp2; @@ -213,8 +273,13 @@ union cvmx_led_udd_dat_clrx { union cvmx_led_udd_dat_setx { uint64_t u64; struct cvmx_led_udd_dat_setx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t set:32; +#else + uint64_t set:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_led_udd_dat_setx_s cn38xx; struct cvmx_led_udd_dat_setx_s cn38xxp2; diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h index b1774126736d..bb0ae338a460 100644 --- a/arch/mips/include/asm/octeon/cvmx-mio-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -94,6 +94,7 @@ #define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull)) #define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull)) #define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull)) +#define CVMX_MIO_PTP_PHY_1PPS_IN (CVMX_ADD_IO_SEG(0x0001070000000F70ull)) #define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull)) #define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull)) #define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull)) @@ -166,24 +167,44 @@ union cvmx_mio_boot_bist_stat { uint64_t u64; struct cvmx_mio_boot_bist_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_mio_boot_bist_stat_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t ncbo_1:1; uint64_t ncbo_0:1; uint64_t loc:1; uint64_t ncbi:1; +#else + uint64_t ncbi:1; + uint64_t loc:1; + uint64_t ncbo_0:1; + uint64_t ncbo_1:1; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_mio_boot_bist_stat_cn30xx cn31xx; struct cvmx_mio_boot_bist_stat_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t ncbo_0:1; uint64_t loc:1; uint64_t ncbi:1; +#else + uint64_t ncbi:1; + uint64_t loc:1; + uint64_t ncbo_0:1; + uint64_t reserved_3_63:61; +#endif } cn38xx; struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2; struct cvmx_mio_boot_bist_stat_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t pcm_1:1; uint64_t pcm_0:1; @@ -191,72 +212,132 @@ union cvmx_mio_boot_bist_stat { uint64_t ncbo_0:1; uint64_t loc:1; uint64_t ncbi:1; +#else + uint64_t ncbi:1; + uint64_t loc:1; + uint64_t ncbo_0:1; + uint64_t ncbo_1:1; + uint64_t pcm_0:1; + uint64_t pcm_1:1; + uint64_t reserved_6_63:58; +#endif } cn50xx; struct cvmx_mio_boot_bist_stat_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t ndf:2; uint64_t ncbo_0:1; uint64_t dma:1; uint64_t loc:1; uint64_t ncbi:1; +#else + uint64_t ncbi:1; + uint64_t loc:1; + uint64_t dma:1; + uint64_t ncbo_0:1; + uint64_t ndf:2; + uint64_t reserved_6_63:58; +#endif } cn52xx; struct cvmx_mio_boot_bist_stat_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t ncbo_0:1; uint64_t dma:1; uint64_t loc:1; uint64_t ncbi:1; +#else + uint64_t ncbi:1; + uint64_t loc:1; + uint64_t dma:1; + uint64_t ncbo_0:1; + uint64_t reserved_4_63:60; +#endif } cn52xxp1; struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx; struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1; struct cvmx_mio_boot_bist_stat_cn38xx cn58xx; struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1; struct cvmx_mio_boot_bist_stat_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t stat:12; +#else + uint64_t stat:12; + uint64_t reserved_12_63:52; +#endif } cn61xx; struct cvmx_mio_boot_bist_stat_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t stat:9; +#else + uint64_t stat:9; + uint64_t reserved_9_63:55; +#endif } cn63xx; struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1; struct cvmx_mio_boot_bist_stat_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t stat:10; +#else + uint64_t stat:10; + uint64_t reserved_10_63:54; +#endif } cn66xx; struct cvmx_mio_boot_bist_stat_cn66xx cn68xx; struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1; + struct cvmx_mio_boot_bist_stat_cn61xx cnf71xx; }; union cvmx_mio_boot_comp { uint64_t u64; struct cvmx_mio_boot_comp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_mio_boot_comp_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pctl:5; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t pctl:5; + uint64_t reserved_10_63:54; +#endif } cn50xx; struct cvmx_mio_boot_comp_cn50xx cn52xx; struct cvmx_mio_boot_comp_cn50xx cn52xxp1; struct cvmx_mio_boot_comp_cn50xx cn56xx; struct cvmx_mio_boot_comp_cn50xx cn56xxp1; struct cvmx_mio_boot_comp_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t pctl:6; uint64_t nctl:6; +#else + uint64_t nctl:6; + uint64_t pctl:6; + uint64_t reserved_12_63:52; +#endif } cn61xx; struct cvmx_mio_boot_comp_cn61xx cn63xx; struct cvmx_mio_boot_comp_cn61xx cn63xxp1; struct cvmx_mio_boot_comp_cn61xx cn66xx; struct cvmx_mio_boot_comp_cn61xx cn68xx; struct cvmx_mio_boot_comp_cn61xx cn68xxp1; + struct cvmx_mio_boot_comp_cn61xx cnf71xx; }; union cvmx_mio_boot_dma_cfgx { uint64_t u64; struct cvmx_mio_boot_dma_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t en:1; uint64_t rw:1; uint64_t clr:1; @@ -267,6 +348,18 @@ union cvmx_mio_boot_dma_cfgx { uint64_t endian:1; uint64_t size:20; uint64_t adr:36; +#else + uint64_t adr:36; + uint64_t size:20; + uint64_t endian:1; + uint64_t swap8:1; + uint64_t swap16:1; + uint64_t swap32:1; + uint64_t reserved_60_60:1; + uint64_t clr:1; + uint64_t rw:1; + uint64_t en:1; +#endif } s; struct cvmx_mio_boot_dma_cfgx_s cn52xx; struct cvmx_mio_boot_dma_cfgx_s cn52xxp1; @@ -278,14 +371,21 @@ union cvmx_mio_boot_dma_cfgx { struct cvmx_mio_boot_dma_cfgx_s cn66xx; struct cvmx_mio_boot_dma_cfgx_s cn68xx; struct cvmx_mio_boot_dma_cfgx_s cn68xxp1; + struct cvmx_mio_boot_dma_cfgx_s cnf71xx; }; union cvmx_mio_boot_dma_intx { uint64_t u64; struct cvmx_mio_boot_dma_intx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dmarq:1; uint64_t done:1; +#else + uint64_t done:1; + uint64_t dmarq:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_boot_dma_intx_s cn52xx; struct cvmx_mio_boot_dma_intx_s cn52xxp1; @@ -297,14 +397,21 @@ union cvmx_mio_boot_dma_intx { struct cvmx_mio_boot_dma_intx_s cn66xx; struct cvmx_mio_boot_dma_intx_s cn68xx; struct cvmx_mio_boot_dma_intx_s cn68xxp1; + struct cvmx_mio_boot_dma_intx_s cnf71xx; }; union cvmx_mio_boot_dma_int_enx { uint64_t u64; struct cvmx_mio_boot_dma_int_enx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dmarq:1; uint64_t done:1; +#else + uint64_t done:1; + uint64_t dmarq:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_boot_dma_int_enx_s cn52xx; struct cvmx_mio_boot_dma_int_enx_s cn52xxp1; @@ -316,11 +423,13 @@ union cvmx_mio_boot_dma_int_enx { struct cvmx_mio_boot_dma_int_enx_s cn66xx; struct cvmx_mio_boot_dma_int_enx_s cn68xx; struct cvmx_mio_boot_dma_int_enx_s cn68xxp1; + struct cvmx_mio_boot_dma_int_enx_s cnf71xx; }; union cvmx_mio_boot_dma_timx { uint64_t u64; struct cvmx_mio_boot_dma_timx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dmack_pi:1; uint64_t dmarq_pi:1; uint64_t tim_mult:2; @@ -336,6 +445,23 @@ union cvmx_mio_boot_dma_timx { uint64_t oe_a:6; uint64_t dmack_s:6; uint64_t dmarq:6; +#else + uint64_t dmarq:6; + uint64_t dmack_s:6; + uint64_t oe_a:6; + uint64_t oe_n:6; + uint64_t we_a:6; + uint64_t we_n:6; + uint64_t dmack_h:6; + uint64_t pause:6; + uint64_t reserved_48_54:7; + uint64_t width:1; + uint64_t ddr:1; + uint64_t rd_dly:3; + uint64_t tim_mult:2; + uint64_t dmarq_pi:1; + uint64_t dmack_pi:1; +#endif } s; struct cvmx_mio_boot_dma_timx_s cn52xx; struct cvmx_mio_boot_dma_timx_s cn52xxp1; @@ -347,14 +473,21 @@ union cvmx_mio_boot_dma_timx { struct cvmx_mio_boot_dma_timx_s cn66xx; struct cvmx_mio_boot_dma_timx_s cn68xx; struct cvmx_mio_boot_dma_timx_s cn68xxp1; + struct cvmx_mio_boot_dma_timx_s cnf71xx; }; union cvmx_mio_boot_err { uint64_t u64; struct cvmx_mio_boot_err_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t wait_err:1; uint64_t adr_err:1; +#else + uint64_t adr_err:1; + uint64_t wait_err:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_boot_err_s cn30xx; struct cvmx_mio_boot_err_s cn31xx; @@ -373,14 +506,21 @@ union cvmx_mio_boot_err { struct cvmx_mio_boot_err_s cn66xx; struct cvmx_mio_boot_err_s cn68xx; struct cvmx_mio_boot_err_s cn68xxp1; + struct cvmx_mio_boot_err_s cnf71xx; }; union cvmx_mio_boot_int { uint64_t u64; struct cvmx_mio_boot_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t wait_int:1; uint64_t adr_int:1; +#else + uint64_t adr_int:1; + uint64_t wait_int:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_boot_int_s cn30xx; struct cvmx_mio_boot_int_s cn31xx; @@ -399,14 +539,21 @@ union cvmx_mio_boot_int { struct cvmx_mio_boot_int_s cn66xx; struct cvmx_mio_boot_int_s cn68xx; struct cvmx_mio_boot_int_s cn68xxp1; + struct cvmx_mio_boot_int_s cnf71xx; }; union cvmx_mio_boot_loc_adr { uint64_t u64; struct cvmx_mio_boot_loc_adr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t adr:5; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t adr:5; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_boot_loc_adr_s cn30xx; struct cvmx_mio_boot_loc_adr_s cn31xx; @@ -425,16 +572,25 @@ union cvmx_mio_boot_loc_adr { struct cvmx_mio_boot_loc_adr_s cn66xx; struct cvmx_mio_boot_loc_adr_s cn68xx; struct cvmx_mio_boot_loc_adr_s cn68xxp1; + struct cvmx_mio_boot_loc_adr_s cnf71xx; }; union cvmx_mio_boot_loc_cfgx { uint64_t u64; struct cvmx_mio_boot_loc_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t en:1; uint64_t reserved_28_30:3; uint64_t base:25; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t base:25; + uint64_t reserved_28_30:3; + uint64_t en:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_boot_loc_cfgx_s cn30xx; struct cvmx_mio_boot_loc_cfgx_s cn31xx; @@ -453,12 +609,17 @@ union cvmx_mio_boot_loc_cfgx { struct cvmx_mio_boot_loc_cfgx_s cn66xx; struct cvmx_mio_boot_loc_cfgx_s cn68xx; struct cvmx_mio_boot_loc_cfgx_s cn68xxp1; + struct cvmx_mio_boot_loc_cfgx_s cnf71xx; }; union cvmx_mio_boot_loc_dat { uint64_t u64; struct cvmx_mio_boot_loc_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; +#else + uint64_t data:64; +#endif } s; struct cvmx_mio_boot_loc_dat_s cn30xx; struct cvmx_mio_boot_loc_dat_s cn31xx; @@ -477,11 +638,13 @@ union cvmx_mio_boot_loc_dat { struct cvmx_mio_boot_loc_dat_s cn66xx; struct cvmx_mio_boot_loc_dat_s cn68xx; struct cvmx_mio_boot_loc_dat_s cn68xxp1; + struct cvmx_mio_boot_loc_dat_s cnf71xx; }; union cvmx_mio_boot_pin_defs { uint64_t u64; struct cvmx_mio_boot_pin_defs_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t user1:16; uint64_t ale:1; @@ -492,8 +655,21 @@ union cvmx_mio_boot_pin_defs { uint64_t term:2; uint64_t nand:1; uint64_t user0:8; +#else + uint64_t user0:8; + uint64_t nand:1; + uint64_t term:2; + uint64_t dmack_p0:1; + uint64_t dmack_p1:1; + uint64_t dmack_p2:1; + uint64_t width:1; + uint64_t ale:1; + uint64_t user1:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_boot_pin_defs_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ale:1; uint64_t width:1; @@ -503,8 +679,20 @@ union cvmx_mio_boot_pin_defs { uint64_t term:2; uint64_t nand:1; uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t nand:1; + uint64_t term:2; + uint64_t dmack_p0:1; + uint64_t dmack_p1:1; + uint64_t reserved_13_13:1; + uint64_t width:1; + uint64_t ale:1; + uint64_t reserved_16_63:48; +#endif } cn52xx; struct cvmx_mio_boot_pin_defs_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ale:1; uint64_t width:1; @@ -513,8 +701,19 @@ union cvmx_mio_boot_pin_defs { uint64_t dmack_p0:1; uint64_t term:2; uint64_t reserved_0_8:9; +#else + uint64_t reserved_0_8:9; + uint64_t term:2; + uint64_t dmack_p0:1; + uint64_t dmack_p1:1; + uint64_t dmack_p2:1; + uint64_t width:1; + uint64_t ale:1; + uint64_t reserved_16_63:48; +#endif } cn56xx; struct cvmx_mio_boot_pin_defs_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t user1:16; uint64_t ale:1; @@ -525,17 +724,31 @@ union cvmx_mio_boot_pin_defs { uint64_t term:2; uint64_t nand:1; uint64_t user0:8; +#else + uint64_t user0:8; + uint64_t nand:1; + uint64_t term:2; + uint64_t dmack_p0:1; + uint64_t dmack_p1:1; + uint64_t reserved_13_13:1; + uint64_t width:1; + uint64_t ale:1; + uint64_t user1:16; + uint64_t reserved_32_63:32; +#endif } cn61xx; struct cvmx_mio_boot_pin_defs_cn52xx cn63xx; struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1; struct cvmx_mio_boot_pin_defs_cn52xx cn66xx; struct cvmx_mio_boot_pin_defs_cn52xx cn68xx; struct cvmx_mio_boot_pin_defs_cn52xx cn68xxp1; + struct cvmx_mio_boot_pin_defs_cn61xx cnf71xx; }; union cvmx_mio_boot_reg_cfgx { uint64_t u64; struct cvmx_mio_boot_reg_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t dmack:2; uint64_t tim_mult:2; @@ -549,8 +762,24 @@ union cvmx_mio_boot_reg_cfgx { uint64_t width:1; uint64_t size:12; uint64_t base:16; +#else + uint64_t base:16; + uint64_t size:12; + uint64_t width:1; + uint64_t ale:1; + uint64_t orbit:1; + uint64_t en:1; + uint64_t oe_ext:2; + uint64_t we_ext:2; + uint64_t sam:1; + uint64_t rd_dly:3; + uint64_t tim_mult:2; + uint64_t dmack:2; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_mio_boot_reg_cfgx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t sam:1; uint64_t we_ext:2; @@ -561,18 +790,40 @@ union cvmx_mio_boot_reg_cfgx { uint64_t width:1; uint64_t size:12; uint64_t base:16; +#else + uint64_t base:16; + uint64_t size:12; + uint64_t width:1; + uint64_t ale:1; + uint64_t orbit:1; + uint64_t en:1; + uint64_t oe_ext:2; + uint64_t we_ext:2; + uint64_t sam:1; + uint64_t reserved_37_63:27; +#endif } cn30xx; struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx; struct cvmx_mio_boot_reg_cfgx_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t en:1; uint64_t orbit:1; uint64_t reserved_28_29:2; uint64_t size:12; uint64_t base:16; +#else + uint64_t base:16; + uint64_t size:12; + uint64_t reserved_28_29:2; + uint64_t orbit:1; + uint64_t en:1; + uint64_t reserved_32_63:32; +#endif } cn38xx; struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2; struct cvmx_mio_boot_reg_cfgx_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t tim_mult:2; uint64_t rd_dly:3; @@ -585,6 +836,20 @@ union cvmx_mio_boot_reg_cfgx { uint64_t width:1; uint64_t size:12; uint64_t base:16; +#else + uint64_t base:16; + uint64_t size:12; + uint64_t width:1; + uint64_t ale:1; + uint64_t orbit:1; + uint64_t en:1; + uint64_t oe_ext:2; + uint64_t we_ext:2; + uint64_t sam:1; + uint64_t rd_dly:3; + uint64_t tim_mult:2; + uint64_t reserved_42_63:22; +#endif } cn50xx; struct cvmx_mio_boot_reg_cfgx_s cn52xx; struct cvmx_mio_boot_reg_cfgx_s cn52xxp1; @@ -598,11 +863,13 @@ union cvmx_mio_boot_reg_cfgx { struct cvmx_mio_boot_reg_cfgx_s cn66xx; struct cvmx_mio_boot_reg_cfgx_s cn68xx; struct cvmx_mio_boot_reg_cfgx_s cn68xxp1; + struct cvmx_mio_boot_reg_cfgx_s cnf71xx; }; union cvmx_mio_boot_reg_timx { uint64_t u64; struct cvmx_mio_boot_reg_timx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t pagem:1; uint64_t waitm:1; uint64_t pages:2; @@ -616,10 +883,26 @@ union cvmx_mio_boot_reg_timx { uint64_t oe:6; uint64_t ce:6; uint64_t adr:6; +#else + uint64_t adr:6; + uint64_t ce:6; + uint64_t oe:6; + uint64_t we:6; + uint64_t rd_hld:6; + uint64_t wr_hld:6; + uint64_t pause:6; + uint64_t wait:6; + uint64_t page:6; + uint64_t ale:6; + uint64_t pages:2; + uint64_t waitm:1; + uint64_t pagem:1; +#endif } s; struct cvmx_mio_boot_reg_timx_s cn30xx; struct cvmx_mio_boot_reg_timx_s cn31xx; struct cvmx_mio_boot_reg_timx_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t pagem:1; uint64_t waitm:1; uint64_t pages:2; @@ -633,6 +916,21 @@ union cvmx_mio_boot_reg_timx { uint64_t oe:6; uint64_t ce:6; uint64_t adr:6; +#else + uint64_t adr:6; + uint64_t ce:6; + uint64_t oe:6; + uint64_t we:6; + uint64_t rd_hld:6; + uint64_t wr_hld:6; + uint64_t pause:6; + uint64_t wait:6; + uint64_t page:6; + uint64_t reserved_54_59:6; + uint64_t pages:2; + uint64_t waitm:1; + uint64_t pagem:1; +#endif } cn38xx; struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2; struct cvmx_mio_boot_reg_timx_s cn50xx; @@ -648,23 +946,40 @@ union cvmx_mio_boot_reg_timx { struct cvmx_mio_boot_reg_timx_s cn66xx; struct cvmx_mio_boot_reg_timx_s cn68xx; struct cvmx_mio_boot_reg_timx_s cn68xxp1; + struct cvmx_mio_boot_reg_timx_s cnf71xx; }; union cvmx_mio_boot_thr { uint64_t u64; struct cvmx_mio_boot_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t dma_thr:6; uint64_t reserved_14_15:2; uint64_t fif_cnt:6; uint64_t reserved_6_7:2; uint64_t fif_thr:6; +#else + uint64_t fif_thr:6; + uint64_t reserved_6_7:2; + uint64_t fif_cnt:6; + uint64_t reserved_14_15:2; + uint64_t dma_thr:6; + uint64_t reserved_22_63:42; +#endif } s; struct cvmx_mio_boot_thr_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t fif_cnt:6; uint64_t reserved_6_7:2; uint64_t fif_thr:6; +#else + uint64_t fif_thr:6; + uint64_t reserved_6_7:2; + uint64_t fif_cnt:6; + uint64_t reserved_14_63:50; +#endif } cn30xx; struct cvmx_mio_boot_thr_cn30xx cn31xx; struct cvmx_mio_boot_thr_cn30xx cn38xx; @@ -682,42 +997,66 @@ union cvmx_mio_boot_thr { struct cvmx_mio_boot_thr_s cn66xx; struct cvmx_mio_boot_thr_s cn68xx; struct cvmx_mio_boot_thr_s cn68xxp1; + struct cvmx_mio_boot_thr_s cnf71xx; }; union cvmx_mio_emm_buf_dat { uint64_t u64; struct cvmx_mio_emm_buf_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dat:64; +#else + uint64_t dat:64; +#endif } s; struct cvmx_mio_emm_buf_dat_s cn61xx; + struct cvmx_mio_emm_buf_dat_s cnf71xx; }; union cvmx_mio_emm_buf_idx { uint64_t u64; struct cvmx_mio_emm_buf_idx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t inc:1; uint64_t reserved_7_15:9; uint64_t buf_num:1; uint64_t offset:6; +#else + uint64_t offset:6; + uint64_t buf_num:1; + uint64_t reserved_7_15:9; + uint64_t inc:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_mio_emm_buf_idx_s cn61xx; + struct cvmx_mio_emm_buf_idx_s cnf71xx; }; union cvmx_mio_emm_cfg { uint64_t u64; struct cvmx_mio_emm_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t boot_fail:1; uint64_t reserved_4_15:12; uint64_t bus_ena:4; +#else + uint64_t bus_ena:4; + uint64_t reserved_4_15:12; + uint64_t boot_fail:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_mio_emm_cfg_s cn61xx; + struct cvmx_mio_emm_cfg_s cnf71xx; }; union cvmx_mio_emm_cmd { uint64_t u64; struct cvmx_mio_emm_cmd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t bus_id:2; uint64_t cmd_val:1; @@ -729,13 +1068,28 @@ union cvmx_mio_emm_cmd { uint64_t rtype_xor:3; uint64_t cmd_idx:6; uint64_t arg:32; +#else + uint64_t arg:32; + uint64_t cmd_idx:6; + uint64_t rtype_xor:3; + uint64_t ctype_xor:2; + uint64_t reserved_43_48:6; + uint64_t offset:6; + uint64_t dbuf:1; + uint64_t reserved_56_58:3; + uint64_t cmd_val:1; + uint64_t bus_id:2; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_mio_emm_cmd_s cn61xx; + struct cvmx_mio_emm_cmd_s cnf71xx; }; union cvmx_mio_emm_dma { uint64_t u64; struct cvmx_mio_emm_dma_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t bus_id:2; uint64_t dma_val:1; @@ -747,13 +1101,28 @@ union cvmx_mio_emm_dma { uint64_t multi:1; uint64_t block_cnt:16; uint64_t card_addr:32; +#else + uint64_t card_addr:32; + uint64_t block_cnt:16; + uint64_t multi:1; + uint64_t rw:1; + uint64_t rel_wr:1; + uint64_t thres:6; + uint64_t dat_null:1; + uint64_t sector:1; + uint64_t dma_val:1; + uint64_t bus_id:2; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_mio_emm_dma_s cn61xx; + struct cvmx_mio_emm_dma_s cnf71xx; }; union cvmx_mio_emm_int { uint64_t u64; struct cvmx_mio_emm_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t switch_err:1; uint64_t switch_done:1; @@ -762,13 +1131,25 @@ union cvmx_mio_emm_int { uint64_t dma_done:1; uint64_t cmd_done:1; uint64_t buf_done:1; +#else + uint64_t buf_done:1; + uint64_t cmd_done:1; + uint64_t dma_done:1; + uint64_t cmd_err:1; + uint64_t dma_err:1; + uint64_t switch_done:1; + uint64_t switch_err:1; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_mio_emm_int_s cn61xx; + struct cvmx_mio_emm_int_s cnf71xx; }; union cvmx_mio_emm_int_en { uint64_t u64; struct cvmx_mio_emm_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t switch_err:1; uint64_t switch_done:1; @@ -777,13 +1158,25 @@ union cvmx_mio_emm_int_en { uint64_t dma_done:1; uint64_t cmd_done:1; uint64_t buf_done:1; +#else + uint64_t buf_done:1; + uint64_t cmd_done:1; + uint64_t dma_done:1; + uint64_t cmd_err:1; + uint64_t dma_err:1; + uint64_t switch_done:1; + uint64_t switch_err:1; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_mio_emm_int_en_s cn61xx; + struct cvmx_mio_emm_int_en_s cnf71xx; }; union cvmx_mio_emm_modex { uint64_t u64; struct cvmx_mio_emm_modex_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t hs_timing:1; uint64_t reserved_43_47:5; @@ -792,38 +1185,66 @@ union cvmx_mio_emm_modex { uint64_t power_class:4; uint64_t clk_hi:16; uint64_t clk_lo:16; +#else + uint64_t clk_lo:16; + uint64_t clk_hi:16; + uint64_t power_class:4; + uint64_t reserved_36_39:4; + uint64_t bus_width:3; + uint64_t reserved_43_47:5; + uint64_t hs_timing:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_mio_emm_modex_s cn61xx; + struct cvmx_mio_emm_modex_s cnf71xx; }; union cvmx_mio_emm_rca { uint64_t u64; struct cvmx_mio_emm_rca_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t card_rca:16; +#else + uint64_t card_rca:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_mio_emm_rca_s cn61xx; + struct cvmx_mio_emm_rca_s cnf71xx; }; union cvmx_mio_emm_rsp_hi { uint64_t u64; struct cvmx_mio_emm_rsp_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dat:64; +#else uint64_t dat:64; +#endif } s; struct cvmx_mio_emm_rsp_hi_s cn61xx; + struct cvmx_mio_emm_rsp_hi_s cnf71xx; }; union cvmx_mio_emm_rsp_lo { uint64_t u64; struct cvmx_mio_emm_rsp_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dat:64; +#else + uint64_t dat:64; +#endif } s; struct cvmx_mio_emm_rsp_lo_s cn61xx; + struct cvmx_mio_emm_rsp_lo_s cnf71xx; }; union cvmx_mio_emm_rsp_sts { uint64_t u64; struct cvmx_mio_emm_rsp_sts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t bus_id:2; uint64_t cmd_val:1; @@ -849,33 +1270,76 @@ union cvmx_mio_emm_rsp_sts { uint64_t cmd_type:2; uint64_t cmd_idx:6; uint64_t cmd_done:1; +#else + uint64_t cmd_done:1; + uint64_t cmd_idx:6; + uint64_t cmd_type:2; + uint64_t rsp_type:3; + uint64_t rsp_val:1; + uint64_t rsp_bad_sts:1; + uint64_t rsp_crc_err:1; + uint64_t rsp_timeout:1; + uint64_t stp_val:1; + uint64_t stp_bad_sts:1; + uint64_t stp_crc_err:1; + uint64_t stp_timeout:1; + uint64_t rsp_busybit:1; + uint64_t blk_crc_err:1; + uint64_t blk_timeout:1; + uint64_t dbuf:1; + uint64_t reserved_24_27:4; + uint64_t dbuf_err:1; + uint64_t reserved_29_55:27; + uint64_t dma_pend:1; + uint64_t dma_val:1; + uint64_t switch_val:1; + uint64_t cmd_val:1; + uint64_t bus_id:2; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_mio_emm_rsp_sts_s cn61xx; + struct cvmx_mio_emm_rsp_sts_s cnf71xx; }; union cvmx_mio_emm_sample { uint64_t u64; struct cvmx_mio_emm_sample_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t cmd_cnt:10; uint64_t reserved_10_15:6; uint64_t dat_cnt:10; +#else + uint64_t dat_cnt:10; + uint64_t reserved_10_15:6; + uint64_t cmd_cnt:10; + uint64_t reserved_26_63:38; +#endif } s; struct cvmx_mio_emm_sample_s cn61xx; + struct cvmx_mio_emm_sample_s cnf71xx; }; union cvmx_mio_emm_sts_mask { uint64_t u64; struct cvmx_mio_emm_sts_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t sts_msk:32; +#else + uint64_t sts_msk:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_emm_sts_mask_s cn61xx; + struct cvmx_mio_emm_sts_mask_s cnf71xx; }; union cvmx_mio_emm_switch { uint64_t u64; struct cvmx_mio_emm_switch_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t bus_id:2; uint64_t switch_exe:1; @@ -890,23 +1354,50 @@ union cvmx_mio_emm_switch { uint64_t power_class:4; uint64_t clk_hi:16; uint64_t clk_lo:16; +#else + uint64_t clk_lo:16; + uint64_t clk_hi:16; + uint64_t power_class:4; + uint64_t reserved_36_39:4; + uint64_t bus_width:3; + uint64_t reserved_43_47:5; + uint64_t hs_timing:1; + uint64_t reserved_49_55:7; + uint64_t switch_err2:1; + uint64_t switch_err1:1; + uint64_t switch_err0:1; + uint64_t switch_exe:1; + uint64_t bus_id:2; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_mio_emm_switch_s cn61xx; + struct cvmx_mio_emm_switch_s cnf71xx; }; union cvmx_mio_emm_wdog { uint64_t u64; struct cvmx_mio_emm_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t clk_cnt:26; +#else + uint64_t clk_cnt:26; + uint64_t reserved_26_63:38; +#endif } s; struct cvmx_mio_emm_wdog_s cn61xx; + struct cvmx_mio_emm_wdog_s cnf71xx; }; union cvmx_mio_fus_bnk_datx { uint64_t u64; struct cvmx_mio_fus_bnk_datx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dat:64; +#else uint64_t dat:64; +#endif } s; struct cvmx_mio_fus_bnk_datx_s cn50xx; struct cvmx_mio_fus_bnk_datx_s cn52xx; @@ -921,13 +1412,19 @@ union cvmx_mio_fus_bnk_datx { struct cvmx_mio_fus_bnk_datx_s cn66xx; struct cvmx_mio_fus_bnk_datx_s cn68xx; struct cvmx_mio_fus_bnk_datx_s cn68xxp1; + struct cvmx_mio_fus_bnk_datx_s cnf71xx; }; union cvmx_mio_fus_dat0 { uint64_t u64; struct cvmx_mio_fus_dat0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t man_info:32; +#else + uint64_t man_info:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_fus_dat0_s cn30xx; struct cvmx_mio_fus_dat0_s cn31xx; @@ -946,13 +1443,19 @@ union cvmx_mio_fus_dat0 { struct cvmx_mio_fus_dat0_s cn66xx; struct cvmx_mio_fus_dat0_s cn68xx; struct cvmx_mio_fus_dat0_s cn68xxp1; + struct cvmx_mio_fus_dat0_s cnf71xx; }; union cvmx_mio_fus_dat1 { uint64_t u64; struct cvmx_mio_fus_dat1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t man_info:32; +#else + uint64_t man_info:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_fus_dat1_s cn30xx; struct cvmx_mio_fus_dat1_s cn31xx; @@ -971,11 +1474,13 @@ union cvmx_mio_fus_dat1 { struct cvmx_mio_fus_dat1_s cn66xx; struct cvmx_mio_fus_dat1_s cn68xx; struct cvmx_mio_fus_dat1_s cn68xxp1; + struct cvmx_mio_fus_dat1_s cnf71xx; }; union cvmx_mio_fus_dat2 { uint64_t u64; struct cvmx_mio_fus_dat2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t fus118:1; uint64_t rom_info:10; @@ -992,8 +1497,27 @@ union cvmx_mio_fus_dat2 { uint64_t bist_dis:1; uint64_t chip_id:8; uint64_t reserved_0_15:16; +#else + uint64_t reserved_0_15:16; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t nokasu:1; + uint64_t reserved_30_31:2; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t dorm_crypto:1; + uint64_t power_limit:2; + uint64_t rom_info:10; + uint64_t fus118:1; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_mio_fus_dat2_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t nodfa_cp2:1; uint64_t nomul:1; @@ -1004,8 +1528,21 @@ union cvmx_mio_fus_dat2 { uint64_t pll_off:4; uint64_t reserved_1_11:11; uint64_t pp_dis:1; +#else + uint64_t pp_dis:1; + uint64_t reserved_1_11:11; + uint64_t pll_off:4; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t reserved_29_63:35; +#endif } cn30xx; struct cvmx_mio_fus_dat2_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t nodfa_cp2:1; uint64_t nomul:1; @@ -1016,8 +1553,21 @@ union cvmx_mio_fus_dat2 { uint64_t pll_off:4; uint64_t reserved_2_11:10; uint64_t pp_dis:2; +#else + uint64_t pp_dis:2; + uint64_t reserved_2_11:10; + uint64_t pll_off:4; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t reserved_29_63:35; +#endif } cn31xx; struct cvmx_mio_fus_dat2_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t nodfa_cp2:1; uint64_t nomul:1; @@ -1026,9 +1576,20 @@ union cvmx_mio_fus_dat2 { uint64_t bist_dis:1; uint64_t chip_id:8; uint64_t pp_dis:16; +#else + uint64_t pp_dis:16; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t reserved_29_63:35; +#endif } cn38xx; struct cvmx_mio_fus_dat2_cn38xx cn38xxp2; struct cvmx_mio_fus_dat2_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t fus318:1; uint64_t raid_en:1; @@ -1042,8 +1603,24 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_2_15:14; uint64_t pp_dis:2; +#else + uint64_t pp_dis:2; + uint64_t reserved_2_15:14; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t nokasu:1; + uint64_t reserved_30_31:2; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t reserved_34_63:30; +#endif } cn50xx; struct cvmx_mio_fus_dat2_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t fus318:1; uint64_t raid_en:1; @@ -1057,9 +1634,25 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_4_15:12; uint64_t pp_dis:4; +#else + uint64_t pp_dis:4; + uint64_t reserved_4_15:12; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t nokasu:1; + uint64_t reserved_30_31:2; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t reserved_34_63:30; +#endif } cn52xx; struct cvmx_mio_fus_dat2_cn52xx cn52xxp1; struct cvmx_mio_fus_dat2_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t fus318:1; uint64_t raid_en:1; @@ -1073,9 +1666,25 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_12_15:4; uint64_t pp_dis:12; +#else + uint64_t pp_dis:12; + uint64_t reserved_12_15:4; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t nokasu:1; + uint64_t reserved_30_31:2; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t reserved_34_63:30; +#endif } cn56xx; struct cvmx_mio_fus_dat2_cn56xx cn56xxp1; struct cvmx_mio_fus_dat2_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_30_63:34; uint64_t nokasu:1; uint64_t nodfa_cp2:1; @@ -1085,9 +1694,21 @@ union cvmx_mio_fus_dat2 { uint64_t bist_dis:1; uint64_t chip_id:8; uint64_t pp_dis:16; +#else + uint64_t pp_dis:16; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t nokasu:1; + uint64_t reserved_30_63:34; +#endif } cn58xx; struct cvmx_mio_fus_dat2_cn58xx cn58xxp1; struct cvmx_mio_fus_dat2_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t fus118:1; uint64_t rom_info:10; @@ -1103,8 +1724,26 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_4_15:12; uint64_t pp_dis:4; +#else + uint64_t pp_dis:4; + uint64_t reserved_4_15:12; + uint64_t chip_id:8; + uint64_t reserved_24_25:2; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t reserved_29_31:3; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t dorm_crypto:1; + uint64_t power_limit:2; + uint64_t rom_info:10; + uint64_t fus118:1; + uint64_t reserved_48_63:16; +#endif } cn61xx; struct cvmx_mio_fus_dat2_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t dorm_crypto:1; uint64_t fus318:1; @@ -1117,9 +1756,24 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_6_15:10; uint64_t pp_dis:6; +#else + uint64_t pp_dis:6; + uint64_t reserved_6_15:10; + uint64_t chip_id:8; + uint64_t reserved_24_25:2; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t reserved_29_31:3; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t dorm_crypto:1; + uint64_t reserved_35_63:29; +#endif } cn63xx; struct cvmx_mio_fus_dat2_cn63xx cn63xxp1; struct cvmx_mio_fus_dat2_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t fus118:1; uint64_t rom_info:10; @@ -1135,8 +1789,26 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_10_15:6; uint64_t pp_dis:10; +#else + uint64_t pp_dis:10; + uint64_t reserved_10_15:6; + uint64_t chip_id:8; + uint64_t reserved_24_25:2; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t reserved_29_31:3; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t dorm_crypto:1; + uint64_t power_limit:2; + uint64_t rom_info:10; + uint64_t fus118:1; + uint64_t reserved_48_63:16; +#endif } cn66xx; struct cvmx_mio_fus_dat2_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t power_limit:2; uint64_t dorm_crypto:1; @@ -1149,13 +1821,29 @@ union cvmx_mio_fus_dat2 { uint64_t reserved_24_25:2; uint64_t chip_id:8; uint64_t reserved_0_15:16; +#else + uint64_t reserved_0_15:16; + uint64_t chip_id:8; + uint64_t reserved_24_25:2; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t reserved_29_31:3; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t dorm_crypto:1; + uint64_t power_limit:2; + uint64_t reserved_37_63:27; +#endif } cn68xx; struct cvmx_mio_fus_dat2_cn68xx cn68xxp1; + struct cvmx_mio_fus_dat2_cn61xx cnf71xx; }; union cvmx_mio_fus_dat3 { uint64_t u64; struct cvmx_mio_fus_dat3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t pll_ctl:10; uint64_t dfa_info_dte:3; @@ -1174,8 +1862,29 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t icache:24; +#else + uint64_t icache:24; + uint64_t nodfa_dte:1; + uint64_t nozip:1; + uint64_t efus_ign:1; + uint64_t efus_lck:1; + uint64_t bar2_en:1; + uint64_t reserved_29_30:2; + uint64_t pll_div4:1; + uint64_t l2c_crip:3; + uint64_t pll_half_dis:1; + uint64_t efus_lck_man:1; + uint64_t efus_lck_rsv:1; + uint64_t ema:2; + uint64_t reserved_40_40:1; + uint64_t dfa_info_clm:4; + uint64_t dfa_info_dte:3; + uint64_t pll_ctl:10; + uint64_t reserved_58_63:6; +#endif } s; struct cvmx_mio_fus_dat3_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pll_div4:1; uint64_t reserved_29_30:2; @@ -1185,8 +1894,20 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t icache:24; +#else + uint64_t icache:24; + uint64_t nodfa_dte:1; + uint64_t nozip:1; + uint64_t efus_ign:1; + uint64_t efus_lck:1; + uint64_t bar2_en:1; + uint64_t reserved_29_30:2; + uint64_t pll_div4:1; + uint64_t reserved_32_63:32; +#endif } cn30xx; struct cvmx_mio_fus_dat3_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pll_div4:1; uint64_t zip_crip:2; @@ -1196,8 +1917,20 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t icache:24; +#else + uint64_t icache:24; + uint64_t nodfa_dte:1; + uint64_t nozip:1; + uint64_t efus_ign:1; + uint64_t efus_lck:1; + uint64_t bar2_en:1; + uint64_t zip_crip:2; + uint64_t pll_div4:1; + uint64_t reserved_32_63:32; +#endif } cn31xx; struct cvmx_mio_fus_dat3_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t zip_crip:2; uint64_t bar2_en:1; @@ -1206,8 +1939,19 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t icache:24; +#else + uint64_t icache:24; + uint64_t nodfa_dte:1; + uint64_t nozip:1; + uint64_t efus_ign:1; + uint64_t efus_lck:1; + uint64_t bar2_en:1; + uint64_t zip_crip:2; + uint64_t reserved_31_63:33; +#endif } cn38xx; struct cvmx_mio_fus_dat3_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t bar2_en:1; uint64_t efus_lck:1; @@ -1215,6 +1959,15 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t icache:24; +#else + uint64_t icache:24; + uint64_t nodfa_dte:1; + uint64_t nozip:1; + uint64_t efus_ign:1; + uint64_t efus_lck:1; + uint64_t bar2_en:1; + uint64_t reserved_29_63:35; +#endif } cn38xxp2; struct cvmx_mio_fus_dat3_cn38xx cn50xx; struct cvmx_mio_fus_dat3_cn38xx cn52xx; @@ -1224,6 +1977,7 @@ union cvmx_mio_fus_dat3 { struct cvmx_mio_fus_dat3_cn38xx cn58xx; struct cvmx_mio_fus_dat3_cn38xx cn58xxp1; struct cvmx_mio_fus_dat3_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t pll_ctl:10; uint64_t dfa_info_dte:3; @@ -1242,21 +1996,49 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t reserved_0_23:24; +#else + uint64_t reserved_0_23:24; + uint64_t nodfa_dte:1; + uint64_t nozip:1; + uint64_t efus_ign:1; + uint64_t efus_lck:1; + uint64_t bar2_en:1; + uint64_t zip_info:2; + uint64_t reserved_31_31:1; + uint64_t l2c_crip:3; + uint64_t pll_half_dis:1; + uint64_t efus_lck_man:1; + uint64_t efus_lck_rsv:1; + uint64_t ema:2; + uint64_t reserved_40_40:1; + uint64_t dfa_info_clm:4; + uint64_t dfa_info_dte:3; + uint64_t pll_ctl:10; + uint64_t reserved_58_63:6; +#endif } cn61xx; struct cvmx_mio_fus_dat3_cn61xx cn63xx; struct cvmx_mio_fus_dat3_cn61xx cn63xxp1; struct cvmx_mio_fus_dat3_cn61xx cn66xx; struct cvmx_mio_fus_dat3_cn61xx cn68xx; struct cvmx_mio_fus_dat3_cn61xx cn68xxp1; + struct cvmx_mio_fus_dat3_cn61xx cnf71xx; }; union cvmx_mio_fus_ema { uint64_t u64; struct cvmx_mio_fus_ema_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t eff_ema:3; uint64_t reserved_3_3:1; uint64_t ema:3; +#else + uint64_t ema:3; + uint64_t reserved_3_3:1; + uint64_t eff_ema:3; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_mio_fus_ema_s cn50xx; struct cvmx_mio_fus_ema_s cn52xx; @@ -1264,8 +2046,13 @@ union cvmx_mio_fus_ema { struct cvmx_mio_fus_ema_s cn56xx; struct cvmx_mio_fus_ema_s cn56xxp1; struct cvmx_mio_fus_ema_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t ema:2; +#else + uint64_t ema:2; + uint64_t reserved_2_63:62; +#endif } cn58xx; struct cvmx_mio_fus_ema_cn58xx cn58xxp1; struct cvmx_mio_fus_ema_s cn61xx; @@ -1274,12 +2061,17 @@ union cvmx_mio_fus_ema { struct cvmx_mio_fus_ema_s cn66xx; struct cvmx_mio_fus_ema_s cn68xx; struct cvmx_mio_fus_ema_s cn68xxp1; + struct cvmx_mio_fus_ema_s cnf71xx; }; union cvmx_mio_fus_pdf { uint64_t u64; struct cvmx_mio_fus_pdf_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t pdf:64; +#else uint64_t pdf:64; +#endif } s; struct cvmx_mio_fus_pdf_s cn50xx; struct cvmx_mio_fus_pdf_s cn52xx; @@ -1293,11 +2085,13 @@ union cvmx_mio_fus_pdf { struct cvmx_mio_fus_pdf_s cn66xx; struct cvmx_mio_fus_pdf_s cn68xx; struct cvmx_mio_fus_pdf_s cn68xxp1; + struct cvmx_mio_fus_pdf_s cnf71xx; }; union cvmx_mio_fus_pll { uint64_t u64; struct cvmx_mio_fus_pll_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t rclk_align_r:8; uint64_t rclk_align_l:8; @@ -1308,11 +2102,29 @@ union cvmx_mio_fus_pll { uint64_t pnr_cout_sel:2; uint64_t rfslip:1; uint64_t fbslip:1; +#else + uint64_t fbslip:1; + uint64_t rfslip:1; + uint64_t pnr_cout_sel:2; + uint64_t pnr_cout_rst:1; + uint64_t c_cout_sel:2; + uint64_t c_cout_rst:1; + uint64_t reserved_8_31:24; + uint64_t rclk_align_l:8; + uint64_t rclk_align_r:8; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_mio_fus_pll_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t rfslip:1; uint64_t fbslip:1; +#else + uint64_t fbslip:1; + uint64_t rfslip:1; + uint64_t reserved_2_63:62; +#endif } cn50xx; struct cvmx_mio_fus_pll_cn50xx cn52xx; struct cvmx_mio_fus_pll_cn50xx cn52xxp1; @@ -1321,6 +2133,7 @@ union cvmx_mio_fus_pll { struct cvmx_mio_fus_pll_cn50xx cn58xx; struct cvmx_mio_fus_pll_cn50xx cn58xxp1; struct cvmx_mio_fus_pll_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t c_cout_rst:1; uint64_t c_cout_sel:2; @@ -1328,24 +2141,45 @@ union cvmx_mio_fus_pll { uint64_t pnr_cout_sel:2; uint64_t rfslip:1; uint64_t fbslip:1; +#else + uint64_t fbslip:1; + uint64_t rfslip:1; + uint64_t pnr_cout_sel:2; + uint64_t pnr_cout_rst:1; + uint64_t c_cout_sel:2; + uint64_t c_cout_rst:1; + uint64_t reserved_8_63:56; +#endif } cn61xx; struct cvmx_mio_fus_pll_cn61xx cn63xx; struct cvmx_mio_fus_pll_cn61xx cn63xxp1; struct cvmx_mio_fus_pll_cn61xx cn66xx; struct cvmx_mio_fus_pll_s cn68xx; struct cvmx_mio_fus_pll_s cn68xxp1; + struct cvmx_mio_fus_pll_cn61xx cnf71xx; }; union cvmx_mio_fus_prog { uint64_t u64; struct cvmx_mio_fus_prog_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t soft:1; uint64_t prog:1; +#else + uint64_t prog:1; + uint64_t soft:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_fus_prog_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t prog:1; +#else + uint64_t prog:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_mio_fus_prog_cn30xx cn31xx; struct cvmx_mio_fus_prog_cn30xx cn38xx; @@ -1363,25 +2197,44 @@ union cvmx_mio_fus_prog { struct cvmx_mio_fus_prog_s cn66xx; struct cvmx_mio_fus_prog_s cn68xx; struct cvmx_mio_fus_prog_s cn68xxp1; + struct cvmx_mio_fus_prog_s cnf71xx; }; union cvmx_mio_fus_prog_times { uint64_t u64; struct cvmx_mio_fus_prog_times_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t vgate_pin:1; uint64_t fsrc_pin:1; uint64_t prog_pin:1; uint64_t reserved_6_31:26; uint64_t setup:6; +#else + uint64_t setup:6; + uint64_t reserved_6_31:26; + uint64_t prog_pin:1; + uint64_t fsrc_pin:1; + uint64_t vgate_pin:1; + uint64_t reserved_35_63:29; +#endif } s; struct cvmx_mio_fus_prog_times_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_33_63:31; uint64_t prog_pin:1; uint64_t out:8; uint64_t sclk_lo:4; uint64_t sclk_hi:12; uint64_t setup:8; +#else + uint64_t setup:8; + uint64_t sclk_hi:12; + uint64_t sclk_lo:4; + uint64_t out:8; + uint64_t prog_pin:1; + uint64_t reserved_33_63:31; +#endif } cn50xx; struct cvmx_mio_fus_prog_times_cn50xx cn52xx; struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1; @@ -1390,6 +2243,7 @@ union cvmx_mio_fus_prog_times { struct cvmx_mio_fus_prog_times_cn50xx cn58xx; struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1; struct cvmx_mio_fus_prog_times_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t vgate_pin:1; uint64_t fsrc_pin:1; @@ -1398,17 +2252,29 @@ union cvmx_mio_fus_prog_times { uint64_t sclk_lo:4; uint64_t sclk_hi:15; uint64_t setup:6; +#else + uint64_t setup:6; + uint64_t sclk_hi:15; + uint64_t sclk_lo:4; + uint64_t out:7; + uint64_t prog_pin:1; + uint64_t fsrc_pin:1; + uint64_t vgate_pin:1; + uint64_t reserved_35_63:29; +#endif } cn61xx; struct cvmx_mio_fus_prog_times_cn61xx cn63xx; struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1; struct cvmx_mio_fus_prog_times_cn61xx cn66xx; struct cvmx_mio_fus_prog_times_cn61xx cn68xx; struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1; + struct cvmx_mio_fus_prog_times_cn61xx cnf71xx; }; union cvmx_mio_fus_rcmd { uint64_t u64; struct cvmx_mio_fus_rcmd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t dat:8; uint64_t reserved_13_15:3; @@ -1416,8 +2282,18 @@ union cvmx_mio_fus_rcmd { uint64_t reserved_9_11:3; uint64_t efuse:1; uint64_t addr:8; +#else + uint64_t addr:8; + uint64_t efuse:1; + uint64_t reserved_9_11:3; + uint64_t pend:1; + uint64_t reserved_13_15:3; + uint64_t dat:8; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_mio_fus_rcmd_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t dat:8; uint64_t reserved_13_15:3; @@ -1426,6 +2302,16 @@ union cvmx_mio_fus_rcmd { uint64_t efuse:1; uint64_t reserved_7_7:1; uint64_t addr:7; +#else + uint64_t addr:7; + uint64_t reserved_7_7:1; + uint64_t efuse:1; + uint64_t reserved_9_11:3; + uint64_t pend:1; + uint64_t reserved_13_15:3; + uint64_t dat:8; + uint64_t reserved_24_63:40; +#endif } cn30xx; struct cvmx_mio_fus_rcmd_cn30xx cn31xx; struct cvmx_mio_fus_rcmd_cn30xx cn38xx; @@ -1443,17 +2329,27 @@ union cvmx_mio_fus_rcmd { struct cvmx_mio_fus_rcmd_s cn66xx; struct cvmx_mio_fus_rcmd_s cn68xx; struct cvmx_mio_fus_rcmd_s cn68xxp1; + struct cvmx_mio_fus_rcmd_s cnf71xx; }; union cvmx_mio_fus_read_times { uint64_t u64; struct cvmx_mio_fus_read_times_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t sch:4; uint64_t fsh:4; uint64_t prh:4; uint64_t sdh:4; uint64_t setup:10; +#else + uint64_t setup:10; + uint64_t sdh:4; + uint64_t prh:4; + uint64_t fsh:4; + uint64_t sch:4; + uint64_t reserved_26_63:38; +#endif } s; struct cvmx_mio_fus_read_times_s cn61xx; struct cvmx_mio_fus_read_times_s cn63xx; @@ -1461,16 +2357,25 @@ union cvmx_mio_fus_read_times { struct cvmx_mio_fus_read_times_s cn66xx; struct cvmx_mio_fus_read_times_s cn68xx; struct cvmx_mio_fus_read_times_s cn68xxp1; + struct cvmx_mio_fus_read_times_s cnf71xx; }; union cvmx_mio_fus_repair_res0 { uint64_t u64; struct cvmx_mio_fus_repair_res0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_55_63:9; uint64_t too_many:1; uint64_t repair2:18; uint64_t repair1:18; uint64_t repair0:18; +#else + uint64_t repair0:18; + uint64_t repair1:18; + uint64_t repair2:18; + uint64_t too_many:1; + uint64_t reserved_55_63:9; +#endif } s; struct cvmx_mio_fus_repair_res0_s cn61xx; struct cvmx_mio_fus_repair_res0_s cn63xx; @@ -1478,15 +2383,23 @@ union cvmx_mio_fus_repair_res0 { struct cvmx_mio_fus_repair_res0_s cn66xx; struct cvmx_mio_fus_repair_res0_s cn68xx; struct cvmx_mio_fus_repair_res0_s cn68xxp1; + struct cvmx_mio_fus_repair_res0_s cnf71xx; }; union cvmx_mio_fus_repair_res1 { uint64_t u64; struct cvmx_mio_fus_repair_res1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t repair5:18; uint64_t repair4:18; uint64_t repair3:18; +#else + uint64_t repair3:18; + uint64_t repair4:18; + uint64_t repair5:18; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_mio_fus_repair_res1_s cn61xx; struct cvmx_mio_fus_repair_res1_s cn63xx; @@ -1494,13 +2407,19 @@ union cvmx_mio_fus_repair_res1 { struct cvmx_mio_fus_repair_res1_s cn66xx; struct cvmx_mio_fus_repair_res1_s cn68xx; struct cvmx_mio_fus_repair_res1_s cn68xxp1; + struct cvmx_mio_fus_repair_res1_s cnf71xx; }; union cvmx_mio_fus_repair_res2 { uint64_t u64; struct cvmx_mio_fus_repair_res2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t repair6:18; +#else + uint64_t repair6:18; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_mio_fus_repair_res2_s cn61xx; struct cvmx_mio_fus_repair_res2_s cn63xx; @@ -1508,15 +2427,23 @@ union cvmx_mio_fus_repair_res2 { struct cvmx_mio_fus_repair_res2_s cn66xx; struct cvmx_mio_fus_repair_res2_s cn68xx; struct cvmx_mio_fus_repair_res2_s cn68xxp1; + struct cvmx_mio_fus_repair_res2_s cnf71xx; }; union cvmx_mio_fus_spr_repair_res { uint64_t u64; struct cvmx_mio_fus_spr_repair_res_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t repair2:14; uint64_t repair1:14; uint64_t repair0:14; +#else + uint64_t repair0:14; + uint64_t repair1:14; + uint64_t repair2:14; + uint64_t reserved_42_63:22; +#endif } s; struct cvmx_mio_fus_spr_repair_res_s cn30xx; struct cvmx_mio_fus_spr_repair_res_s cn31xx; @@ -1534,13 +2461,19 @@ union cvmx_mio_fus_spr_repair_res { struct cvmx_mio_fus_spr_repair_res_s cn66xx; struct cvmx_mio_fus_spr_repair_res_s cn68xx; struct cvmx_mio_fus_spr_repair_res_s cn68xxp1; + struct cvmx_mio_fus_spr_repair_res_s cnf71xx; }; union cvmx_mio_fus_spr_repair_sum { uint64_t u64; struct cvmx_mio_fus_spr_repair_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t too_many:1; +#else + uint64_t too_many:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_fus_spr_repair_sum_s cn30xx; struct cvmx_mio_fus_spr_repair_sum_s cn31xx; @@ -1558,23 +2491,35 @@ union cvmx_mio_fus_spr_repair_sum { struct cvmx_mio_fus_spr_repair_sum_s cn66xx; struct cvmx_mio_fus_spr_repair_sum_s cn68xx; struct cvmx_mio_fus_spr_repair_sum_s cn68xxp1; + struct cvmx_mio_fus_spr_repair_sum_s cnf71xx; }; union cvmx_mio_fus_tgg { uint64_t u64; struct cvmx_mio_fus_tgg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t val:1; uint64_t dat:63; +#else + uint64_t dat:63; + uint64_t val:1; +#endif } s; struct cvmx_mio_fus_tgg_s cn61xx; struct cvmx_mio_fus_tgg_s cn66xx; + struct cvmx_mio_fus_tgg_s cnf71xx; }; union cvmx_mio_fus_unlock { uint64_t u64; struct cvmx_mio_fus_unlock_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t key:24; +#else + uint64_t key:24; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_mio_fus_unlock_s cn30xx; struct cvmx_mio_fus_unlock_s cn31xx; @@ -1583,20 +2528,35 @@ union cvmx_mio_fus_unlock { union cvmx_mio_fus_wadr { uint64_t u64; struct cvmx_mio_fus_wadr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t addr:10; +#else + uint64_t addr:10; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_mio_fus_wadr_s cn30xx; struct cvmx_mio_fus_wadr_s cn31xx; struct cvmx_mio_fus_wadr_s cn38xx; struct cvmx_mio_fus_wadr_s cn38xxp2; struct cvmx_mio_fus_wadr_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t addr:2; +#else + uint64_t addr:2; + uint64_t reserved_2_63:62; +#endif } cn50xx; struct cvmx_mio_fus_wadr_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t addr:3; +#else + uint64_t addr:3; + uint64_t reserved_3_63:61; +#endif } cn52xx; struct cvmx_mio_fus_wadr_cn52xx cn52xxp1; struct cvmx_mio_fus_wadr_cn52xx cn56xx; @@ -1604,22 +2564,34 @@ union cvmx_mio_fus_wadr { struct cvmx_mio_fus_wadr_cn50xx cn58xx; struct cvmx_mio_fus_wadr_cn50xx cn58xxp1; struct cvmx_mio_fus_wadr_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t addr:4; +#else + uint64_t addr:4; + uint64_t reserved_4_63:60; +#endif } cn61xx; struct cvmx_mio_fus_wadr_cn61xx cn63xx; struct cvmx_mio_fus_wadr_cn61xx cn63xxp1; struct cvmx_mio_fus_wadr_cn61xx cn66xx; struct cvmx_mio_fus_wadr_cn61xx cn68xx; struct cvmx_mio_fus_wadr_cn61xx cn68xxp1; + struct cvmx_mio_fus_wadr_cn61xx cnf71xx; }; union cvmx_mio_gpio_comp { uint64_t u64; struct cvmx_mio_gpio_comp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t pctl:6; uint64_t nctl:6; +#else + uint64_t nctl:6; + uint64_t pctl:6; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_mio_gpio_comp_s cn61xx; struct cvmx_mio_gpio_comp_s cn63xx; @@ -1627,11 +2599,13 @@ union cvmx_mio_gpio_comp { struct cvmx_mio_gpio_comp_s cn66xx; struct cvmx_mio_gpio_comp_s cn68xx; struct cvmx_mio_gpio_comp_s cn68xxp1; + struct cvmx_mio_gpio_comp_s cnf71xx; }; union cvmx_mio_ndf_dma_cfg { uint64_t u64; struct cvmx_mio_ndf_dma_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t en:1; uint64_t rw:1; uint64_t clr:1; @@ -1642,6 +2616,18 @@ union cvmx_mio_ndf_dma_cfg { uint64_t endian:1; uint64_t size:20; uint64_t adr:36; +#else + uint64_t adr:36; + uint64_t size:20; + uint64_t endian:1; + uint64_t swap8:1; + uint64_t swap16:1; + uint64_t swap32:1; + uint64_t reserved_60_60:1; + uint64_t clr:1; + uint64_t rw:1; + uint64_t en:1; +#endif } s; struct cvmx_mio_ndf_dma_cfg_s cn52xx; struct cvmx_mio_ndf_dma_cfg_s cn61xx; @@ -1650,13 +2636,19 @@ union cvmx_mio_ndf_dma_cfg { struct cvmx_mio_ndf_dma_cfg_s cn66xx; struct cvmx_mio_ndf_dma_cfg_s cn68xx; struct cvmx_mio_ndf_dma_cfg_s cn68xxp1; + struct cvmx_mio_ndf_dma_cfg_s cnf71xx; }; union cvmx_mio_ndf_dma_int { uint64_t u64; struct cvmx_mio_ndf_dma_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t done:1; +#else + uint64_t done:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_ndf_dma_int_s cn52xx; struct cvmx_mio_ndf_dma_int_s cn61xx; @@ -1665,13 +2657,19 @@ union cvmx_mio_ndf_dma_int { struct cvmx_mio_ndf_dma_int_s cn66xx; struct cvmx_mio_ndf_dma_int_s cn68xx; struct cvmx_mio_ndf_dma_int_s cn68xxp1; + struct cvmx_mio_ndf_dma_int_s cnf71xx; }; union cvmx_mio_ndf_dma_int_en { uint64_t u64; struct cvmx_mio_ndf_dma_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t done:1; +#else + uint64_t done:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_ndf_dma_int_en_s cn52xx; struct cvmx_mio_ndf_dma_int_en_s cn61xx; @@ -1680,13 +2678,19 @@ union cvmx_mio_ndf_dma_int_en { struct cvmx_mio_ndf_dma_int_en_s cn66xx; struct cvmx_mio_ndf_dma_int_en_s cn68xx; struct cvmx_mio_ndf_dma_int_en_s cn68xxp1; + struct cvmx_mio_ndf_dma_int_en_s cnf71xx; }; union cvmx_mio_pll_ctl { uint64_t u64; struct cvmx_mio_pll_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t bw_ctl:5; +#else + uint64_t bw_ctl:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_mio_pll_ctl_s cn30xx; struct cvmx_mio_pll_ctl_s cn31xx; @@ -1695,8 +2699,13 @@ union cvmx_mio_pll_ctl { union cvmx_mio_pll_setting { uint64_t u64; struct cvmx_mio_pll_setting_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t setting:17; +#else + uint64_t setting:17; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_mio_pll_setting_s cn30xx; struct cvmx_mio_pll_setting_s cn31xx; @@ -1705,49 +2714,73 @@ union cvmx_mio_pll_setting { union cvmx_mio_ptp_ckout_hi_incr { uint64_t u64; struct cvmx_mio_ptp_ckout_hi_incr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t nanosec:32; +#endif } s; struct cvmx_mio_ptp_ckout_hi_incr_s cn61xx; struct cvmx_mio_ptp_ckout_hi_incr_s cn66xx; struct cvmx_mio_ptp_ckout_hi_incr_s cn68xx; + struct cvmx_mio_ptp_ckout_hi_incr_s cnf71xx; }; union cvmx_mio_ptp_ckout_lo_incr { uint64_t u64; struct cvmx_mio_ptp_ckout_lo_incr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t nanosec:32; +#endif } s; struct cvmx_mio_ptp_ckout_lo_incr_s cn61xx; struct cvmx_mio_ptp_ckout_lo_incr_s cn66xx; struct cvmx_mio_ptp_ckout_lo_incr_s cn68xx; + struct cvmx_mio_ptp_ckout_lo_incr_s cnf71xx; }; union cvmx_mio_ptp_ckout_thresh_hi { uint64_t u64; struct cvmx_mio_ptp_ckout_thresh_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t nanosec:64; +#else uint64_t nanosec:64; +#endif } s; struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx; struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx; struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx; + struct cvmx_mio_ptp_ckout_thresh_hi_s cnf71xx; }; union cvmx_mio_ptp_ckout_thresh_lo { uint64_t u64; struct cvmx_mio_ptp_ckout_thresh_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx; struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx; struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx; + struct cvmx_mio_ptp_ckout_thresh_lo_s cnf71xx; }; union cvmx_mio_ptp_clock_cfg { uint64_t u64; struct cvmx_mio_ptp_clock_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t pps:1; uint64_t ckout:1; @@ -1768,9 +2801,32 @@ union cvmx_mio_ptp_clock_cfg { uint64_t ext_clk_in:6; uint64_t ext_clk_en:1; uint64_t ptp_en:1; +#else + uint64_t ptp_en:1; + uint64_t ext_clk_en:1; + uint64_t ext_clk_in:6; + uint64_t tstmp_en:1; + uint64_t tstmp_edge:1; + uint64_t tstmp_in:6; + uint64_t evcnt_en:1; + uint64_t evcnt_edge:1; + uint64_t evcnt_in:6; + uint64_t ckout_en:1; + uint64_t ckout_inv:1; + uint64_t ckout_out:4; + uint64_t pps_en:1; + uint64_t pps_inv:1; + uint64_t pps_out:5; + uint64_t ckout_out4:1; + uint64_t ext_clk_edge:2; + uint64_t ckout:1; + uint64_t pps:1; + uint64_t reserved_42_63:22; +#endif } s; struct cvmx_mio_ptp_clock_cfg_s cn61xx; struct cvmx_mio_ptp_clock_cfg_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t evcnt_in:6; uint64_t evcnt_edge:1; @@ -1781,9 +2837,22 @@ union cvmx_mio_ptp_clock_cfg { uint64_t ext_clk_in:6; uint64_t ext_clk_en:1; uint64_t ptp_en:1; +#else + uint64_t ptp_en:1; + uint64_t ext_clk_en:1; + uint64_t ext_clk_in:6; + uint64_t tstmp_en:1; + uint64_t tstmp_edge:1; + uint64_t tstmp_in:6; + uint64_t evcnt_en:1; + uint64_t evcnt_edge:1; + uint64_t evcnt_in:6; + uint64_t reserved_24_63:40; +#endif } cn63xx; struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1; struct cvmx_mio_ptp_clock_cfg_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ext_clk_edge:2; uint64_t ckout_out4:1; @@ -1802,16 +2871,42 @@ union cvmx_mio_ptp_clock_cfg { uint64_t ext_clk_in:6; uint64_t ext_clk_en:1; uint64_t ptp_en:1; +#else + uint64_t ptp_en:1; + uint64_t ext_clk_en:1; + uint64_t ext_clk_in:6; + uint64_t tstmp_en:1; + uint64_t tstmp_edge:1; + uint64_t tstmp_in:6; + uint64_t evcnt_en:1; + uint64_t evcnt_edge:1; + uint64_t evcnt_in:6; + uint64_t ckout_en:1; + uint64_t ckout_inv:1; + uint64_t ckout_out:4; + uint64_t pps_en:1; + uint64_t pps_inv:1; + uint64_t pps_out:5; + uint64_t ckout_out4:1; + uint64_t ext_clk_edge:2; + uint64_t reserved_40_63:24; +#endif } cn66xx; struct cvmx_mio_ptp_clock_cfg_s cn68xx; struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1; + struct cvmx_mio_ptp_clock_cfg_s cnf71xx; }; union cvmx_mio_ptp_clock_comp { uint64_t u64; struct cvmx_mio_ptp_clock_comp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t nanosec:32; +#endif } s; struct cvmx_mio_ptp_clock_comp_s cn61xx; struct cvmx_mio_ptp_clock_comp_s cn63xx; @@ -1819,12 +2914,17 @@ union cvmx_mio_ptp_clock_comp { struct cvmx_mio_ptp_clock_comp_s cn66xx; struct cvmx_mio_ptp_clock_comp_s cn68xx; struct cvmx_mio_ptp_clock_comp_s cn68xxp1; + struct cvmx_mio_ptp_clock_comp_s cnf71xx; }; union cvmx_mio_ptp_clock_hi { uint64_t u64; struct cvmx_mio_ptp_clock_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t nanosec:64; +#else uint64_t nanosec:64; +#endif } s; struct cvmx_mio_ptp_clock_hi_s cn61xx; struct cvmx_mio_ptp_clock_hi_s cn63xx; @@ -1832,13 +2932,19 @@ union cvmx_mio_ptp_clock_hi { struct cvmx_mio_ptp_clock_hi_s cn66xx; struct cvmx_mio_ptp_clock_hi_s cn68xx; struct cvmx_mio_ptp_clock_hi_s cn68xxp1; + struct cvmx_mio_ptp_clock_hi_s cnf71xx; }; union cvmx_mio_ptp_clock_lo { uint64_t u64; struct cvmx_mio_ptp_clock_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_ptp_clock_lo_s cn61xx; struct cvmx_mio_ptp_clock_lo_s cn63xx; @@ -1846,12 +2952,17 @@ union cvmx_mio_ptp_clock_lo { struct cvmx_mio_ptp_clock_lo_s cn66xx; struct cvmx_mio_ptp_clock_lo_s cn68xx; struct cvmx_mio_ptp_clock_lo_s cn68xxp1; + struct cvmx_mio_ptp_clock_lo_s cnf71xx; }; union cvmx_mio_ptp_evt_cnt { uint64_t u64; struct cvmx_mio_ptp_evt_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t cntr:64; +#else uint64_t cntr:64; +#endif } s; struct cvmx_mio_ptp_evt_cnt_s cn61xx; struct cvmx_mio_ptp_evt_cnt_s cn63xx; @@ -1859,55 +2970,97 @@ union cvmx_mio_ptp_evt_cnt { struct cvmx_mio_ptp_evt_cnt_s cn66xx; struct cvmx_mio_ptp_evt_cnt_s cn68xx; struct cvmx_mio_ptp_evt_cnt_s cn68xxp1; + struct cvmx_mio_ptp_evt_cnt_s cnf71xx; +}; + +union cvmx_mio_ptp_phy_1pps_in { + uint64_t u64; + struct cvmx_mio_ptp_phy_1pps_in_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_5_63:59; + uint64_t sel:5; +#else + uint64_t sel:5; + uint64_t reserved_5_63:59; +#endif + } s; + struct cvmx_mio_ptp_phy_1pps_in_s cnf71xx; }; union cvmx_mio_ptp_pps_hi_incr { uint64_t u64; struct cvmx_mio_ptp_pps_hi_incr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t nanosec:32; +#endif } s; struct cvmx_mio_ptp_pps_hi_incr_s cn61xx; struct cvmx_mio_ptp_pps_hi_incr_s cn66xx; struct cvmx_mio_ptp_pps_hi_incr_s cn68xx; + struct cvmx_mio_ptp_pps_hi_incr_s cnf71xx; }; union cvmx_mio_ptp_pps_lo_incr { uint64_t u64; struct cvmx_mio_ptp_pps_lo_incr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t nanosec:32; +#endif } s; struct cvmx_mio_ptp_pps_lo_incr_s cn61xx; struct cvmx_mio_ptp_pps_lo_incr_s cn66xx; struct cvmx_mio_ptp_pps_lo_incr_s cn68xx; + struct cvmx_mio_ptp_pps_lo_incr_s cnf71xx; }; union cvmx_mio_ptp_pps_thresh_hi { uint64_t u64; struct cvmx_mio_ptp_pps_thresh_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t nanosec:64; +#else uint64_t nanosec:64; +#endif } s; struct cvmx_mio_ptp_pps_thresh_hi_s cn61xx; struct cvmx_mio_ptp_pps_thresh_hi_s cn66xx; struct cvmx_mio_ptp_pps_thresh_hi_s cn68xx; + struct cvmx_mio_ptp_pps_thresh_hi_s cnf71xx; }; union cvmx_mio_ptp_pps_thresh_lo { uint64_t u64; struct cvmx_mio_ptp_pps_thresh_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_ptp_pps_thresh_lo_s cn61xx; struct cvmx_mio_ptp_pps_thresh_lo_s cn66xx; struct cvmx_mio_ptp_pps_thresh_lo_s cn68xx; + struct cvmx_mio_ptp_pps_thresh_lo_s cnf71xx; }; union cvmx_mio_ptp_timestamp { uint64_t u64; struct cvmx_mio_ptp_timestamp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:64; +#else + uint64_t nanosec:64; +#endif } s; struct cvmx_mio_ptp_timestamp_s cn61xx; struct cvmx_mio_ptp_timestamp_s cn63xx; @@ -1915,35 +3068,79 @@ union cvmx_mio_ptp_timestamp { struct cvmx_mio_ptp_timestamp_s cn66xx; struct cvmx_mio_ptp_timestamp_s cn68xx; struct cvmx_mio_ptp_timestamp_s cn68xxp1; + struct cvmx_mio_ptp_timestamp_s cnf71xx; }; union cvmx_mio_qlmx_cfg { uint64_t u64; struct cvmx_mio_qlmx_cfg_s { - uint64_t reserved_12_63:52; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t prtmode:1; + uint64_t reserved_12_13:2; uint64_t qlm_spd:4; uint64_t reserved_4_7:4; uint64_t qlm_cfg:4; +#else + uint64_t qlm_cfg:4; + uint64_t reserved_4_7:4; + uint64_t qlm_spd:4; + uint64_t reserved_12_13:2; + uint64_t prtmode:1; + uint64_t reserved_15_63:49; +#endif } s; struct cvmx_mio_qlmx_cfg_cn61xx { - uint64_t reserved_12_63:52; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t prtmode:1; + uint64_t reserved_12_13:2; uint64_t qlm_spd:4; uint64_t reserved_2_7:6; uint64_t qlm_cfg:2; +#else + uint64_t qlm_cfg:2; + uint64_t reserved_2_7:6; + uint64_t qlm_spd:4; + uint64_t reserved_12_13:2; + uint64_t prtmode:1; + uint64_t reserved_15_63:49; +#endif } cn61xx; - struct cvmx_mio_qlmx_cfg_s cn66xx; + struct cvmx_mio_qlmx_cfg_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t qlm_spd:4; + uint64_t reserved_4_7:4; + uint64_t qlm_cfg:4; +#else + uint64_t qlm_cfg:4; + uint64_t reserved_4_7:4; + uint64_t qlm_spd:4; + uint64_t reserved_12_63:52; +#endif + } cn66xx; struct cvmx_mio_qlmx_cfg_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t qlm_spd:4; uint64_t reserved_3_7:5; uint64_t qlm_cfg:3; +#else + uint64_t qlm_cfg:3; + uint64_t reserved_3_7:5; + uint64_t qlm_spd:4; + uint64_t reserved_12_63:52; +#endif } cn68xx; struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1; + struct cvmx_mio_qlmx_cfg_cn61xx cnf71xx; }; union cvmx_mio_rst_boot { uint64_t u64; struct cvmx_mio_rst_boot_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t chipkill:1; uint64_t jtcsrdis:1; uint64_t ejtagdis:1; @@ -1963,8 +3160,30 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; +#else + uint64_t rboot_pin:1; + uint64_t rboot:1; + uint64_t lboot:10; + uint64_t qlm0_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm2_spd:4; + uint64_t pnr_mul:6; + uint64_t c_mul:6; + uint64_t qlm3_spd:4; + uint64_t qlm4_spd:4; + uint64_t reserved_44_47:4; + uint64_t lboot_ext:2; + uint64_t reserved_50_57:8; + uint64_t jt_tstmode:1; + uint64_t ckill_ppdis:1; + uint64_t romen:1; + uint64_t ejtagdis:1; + uint64_t jtcsrdis:1; + uint64_t chipkill:1; +#endif } s; struct cvmx_mio_rst_boot_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t chipkill:1; uint64_t jtcsrdis:1; uint64_t ejtagdis:1; @@ -1982,8 +3201,28 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; +#else + uint64_t rboot_pin:1; + uint64_t rboot:1; + uint64_t lboot:10; + uint64_t qlm0_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm2_spd:4; + uint64_t pnr_mul:6; + uint64_t c_mul:6; + uint64_t reserved_36_47:12; + uint64_t lboot_ext:2; + uint64_t reserved_50_57:8; + uint64_t jt_tstmode:1; + uint64_t ckill_ppdis:1; + uint64_t romen:1; + uint64_t ejtagdis:1; + uint64_t jtcsrdis:1; + uint64_t chipkill:1; +#endif } cn61xx; struct cvmx_mio_rst_boot_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t c_mul:6; uint64_t pnr_mul:6; @@ -1993,9 +3232,21 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; +#else + uint64_t rboot_pin:1; + uint64_t rboot:1; + uint64_t lboot:10; + uint64_t qlm0_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm2_spd:4; + uint64_t pnr_mul:6; + uint64_t c_mul:6; + uint64_t reserved_36_63:28; +#endif } cn63xx; struct cvmx_mio_rst_boot_cn63xx cn63xxp1; struct cvmx_mio_rst_boot_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t chipkill:1; uint64_t jtcsrdis:1; uint64_t ejtagdis:1; @@ -2012,8 +3263,27 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; +#else + uint64_t rboot_pin:1; + uint64_t rboot:1; + uint64_t lboot:10; + uint64_t qlm0_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm2_spd:4; + uint64_t pnr_mul:6; + uint64_t c_mul:6; + uint64_t reserved_36_47:12; + uint64_t lboot_ext:2; + uint64_t reserved_50_58:9; + uint64_t ckill_ppdis:1; + uint64_t romen:1; + uint64_t ejtagdis:1; + uint64_t jtcsrdis:1; + uint64_t chipkill:1; +#endif } cn66xx; struct cvmx_mio_rst_boot_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t jt_tstmode:1; uint64_t reserved_44_57:14; @@ -2027,8 +3297,24 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; +#else + uint64_t rboot_pin:1; + uint64_t rboot:1; + uint64_t lboot:10; + uint64_t qlm0_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm2_spd:4; + uint64_t pnr_mul:6; + uint64_t c_mul:6; + uint64_t qlm3_spd:4; + uint64_t qlm4_spd:4; + uint64_t reserved_44_57:14; + uint64_t jt_tstmode:1; + uint64_t reserved_59_63:5; +#endif } cn68xx; struct cvmx_mio_rst_boot_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t qlm4_spd:4; uint64_t qlm3_spd:4; @@ -2040,55 +3326,107 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; +#else + uint64_t rboot_pin:1; + uint64_t rboot:1; + uint64_t lboot:10; + uint64_t qlm0_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm2_spd:4; + uint64_t pnr_mul:6; + uint64_t c_mul:6; + uint64_t qlm3_spd:4; + uint64_t qlm4_spd:4; + uint64_t reserved_44_63:20; +#endif } cn68xxp1; + struct cvmx_mio_rst_boot_cn61xx cnf71xx; }; union cvmx_mio_rst_cfg { uint64_t u64; struct cvmx_mio_rst_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t cntl_clr_bist:1; uint64_t warm_clr_bist:1; uint64_t soft_clr_bist:1; +#else + uint64_t soft_clr_bist:1; + uint64_t warm_clr_bist:1; + uint64_t cntl_clr_bist:1; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_mio_rst_cfg_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bist_delay:58; uint64_t reserved_3_5:3; uint64_t cntl_clr_bist:1; uint64_t warm_clr_bist:1; uint64_t soft_clr_bist:1; +#else + uint64_t soft_clr_bist:1; + uint64_t warm_clr_bist:1; + uint64_t cntl_clr_bist:1; + uint64_t reserved_3_5:3; + uint64_t bist_delay:58; +#endif } cn61xx; struct cvmx_mio_rst_cfg_cn61xx cn63xx; struct cvmx_mio_rst_cfg_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bist_delay:58; uint64_t reserved_2_5:4; uint64_t warm_clr_bist:1; uint64_t soft_clr_bist:1; +#else + uint64_t soft_clr_bist:1; + uint64_t warm_clr_bist:1; + uint64_t reserved_2_5:4; + uint64_t bist_delay:58; +#endif } cn63xxp1; struct cvmx_mio_rst_cfg_cn61xx cn66xx; struct cvmx_mio_rst_cfg_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bist_delay:56; uint64_t reserved_3_7:5; uint64_t cntl_clr_bist:1; uint64_t warm_clr_bist:1; uint64_t soft_clr_bist:1; +#else + uint64_t soft_clr_bist:1; + uint64_t warm_clr_bist:1; + uint64_t cntl_clr_bist:1; + uint64_t reserved_3_7:5; + uint64_t bist_delay:56; +#endif } cn68xx; struct cvmx_mio_rst_cfg_cn68xx cn68xxp1; + struct cvmx_mio_rst_cfg_cn61xx cnf71xx; }; union cvmx_mio_rst_ckill { uint64_t u64; struct cvmx_mio_rst_ckill_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_47_63:17; uint64_t timer:47; +#else + uint64_t timer:47; + uint64_t reserved_47_63:17; +#endif } s; struct cvmx_mio_rst_ckill_s cn61xx; struct cvmx_mio_rst_ckill_s cn66xx; + struct cvmx_mio_rst_ckill_s cnf71xx; }; union cvmx_mio_rst_cntlx { uint64_t u64; struct cvmx_mio_rst_cntlx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t in_rev_ln:1; uint64_t rev_lanes:1; @@ -2102,9 +3440,25 @@ union cvmx_mio_rst_cntlx { uint64_t rst_rcv:1; uint64_t rst_chip:1; uint64_t rst_val:1; +#else + uint64_t rst_val:1; + uint64_t rst_chip:1; + uint64_t rst_rcv:1; + uint64_t rst_drv:1; + uint64_t prtmode:2; + uint64_t host_mode:1; + uint64_t rst_link:1; + uint64_t rst_done:1; + uint64_t prst_link:1; + uint64_t gen1_only:1; + uint64_t rev_lanes:1; + uint64_t in_rev_ln:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_mio_rst_cntlx_s cn61xx; struct cvmx_mio_rst_cntlx_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t prst_link:1; uint64_t rst_done:1; @@ -2115,13 +3469,27 @@ union cvmx_mio_rst_cntlx { uint64_t rst_rcv:1; uint64_t rst_chip:1; uint64_t rst_val:1; +#else + uint64_t rst_val:1; + uint64_t rst_chip:1; + uint64_t rst_rcv:1; + uint64_t rst_drv:1; + uint64_t prtmode:2; + uint64_t host_mode:1; + uint64_t rst_link:1; + uint64_t rst_done:1; + uint64_t prst_link:1; + uint64_t reserved_10_63:54; +#endif } cn66xx; struct cvmx_mio_rst_cntlx_cn66xx cn68xx; + struct cvmx_mio_rst_cntlx_s cnf71xx; }; union cvmx_mio_rst_ctlx { uint64_t u64; struct cvmx_mio_rst_ctlx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t in_rev_ln:1; uint64_t rev_lanes:1; @@ -2135,9 +3503,25 @@ union cvmx_mio_rst_ctlx { uint64_t rst_rcv:1; uint64_t rst_chip:1; uint64_t rst_val:1; +#else + uint64_t rst_val:1; + uint64_t rst_chip:1; + uint64_t rst_rcv:1; + uint64_t rst_drv:1; + uint64_t prtmode:2; + uint64_t host_mode:1; + uint64_t rst_link:1; + uint64_t rst_done:1; + uint64_t prst_link:1; + uint64_t gen1_only:1; + uint64_t rev_lanes:1; + uint64_t in_rev_ln:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_mio_rst_ctlx_s cn61xx; struct cvmx_mio_rst_ctlx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t prst_link:1; uint64_t rst_done:1; @@ -2148,8 +3532,21 @@ union cvmx_mio_rst_ctlx { uint64_t rst_rcv:1; uint64_t rst_chip:1; uint64_t rst_val:1; +#else + uint64_t rst_val:1; + uint64_t rst_chip:1; + uint64_t rst_rcv:1; + uint64_t rst_drv:1; + uint64_t prtmode:2; + uint64_t host_mode:1; + uint64_t rst_link:1; + uint64_t rst_done:1; + uint64_t prst_link:1; + uint64_t reserved_10_63:54; +#endif } cn63xx; struct cvmx_mio_rst_ctlx_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t rst_done:1; uint64_t rst_link:1; @@ -2159,18 +3556,36 @@ union cvmx_mio_rst_ctlx { uint64_t rst_rcv:1; uint64_t rst_chip:1; uint64_t rst_val:1; +#else + uint64_t rst_val:1; + uint64_t rst_chip:1; + uint64_t rst_rcv:1; + uint64_t rst_drv:1; + uint64_t prtmode:2; + uint64_t host_mode:1; + uint64_t rst_link:1; + uint64_t rst_done:1; + uint64_t reserved_9_63:55; +#endif } cn63xxp1; struct cvmx_mio_rst_ctlx_cn63xx cn66xx; struct cvmx_mio_rst_ctlx_cn63xx cn68xx; struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1; + struct cvmx_mio_rst_ctlx_s cnf71xx; }; union cvmx_mio_rst_delay { uint64_t u64; struct cvmx_mio_rst_delay_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t warm_rst_dly:16; uint64_t soft_rst_dly:16; +#else + uint64_t soft_rst_dly:16; + uint64_t warm_rst_dly:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_rst_delay_s cn61xx; struct cvmx_mio_rst_delay_s cn63xx; @@ -2178,11 +3593,13 @@ union cvmx_mio_rst_delay { struct cvmx_mio_rst_delay_s cn66xx; struct cvmx_mio_rst_delay_s cn68xx; struct cvmx_mio_rst_delay_s cn68xxp1; + struct cvmx_mio_rst_delay_s cnf71xx; }; union cvmx_mio_rst_int { uint64_t u64; struct cvmx_mio_rst_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t perst1:1; uint64_t perst0:1; @@ -2191,25 +3608,46 @@ union cvmx_mio_rst_int { uint64_t rst_link2:1; uint64_t rst_link1:1; uint64_t rst_link0:1; +#else + uint64_t rst_link0:1; + uint64_t rst_link1:1; + uint64_t rst_link2:1; + uint64_t rst_link3:1; + uint64_t reserved_4_7:4; + uint64_t perst0:1; + uint64_t perst1:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_mio_rst_int_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t perst1:1; uint64_t perst0:1; uint64_t reserved_2_7:6; uint64_t rst_link1:1; uint64_t rst_link0:1; +#else + uint64_t rst_link0:1; + uint64_t rst_link1:1; + uint64_t reserved_2_7:6; + uint64_t perst0:1; + uint64_t perst1:1; + uint64_t reserved_10_63:54; +#endif } cn61xx; struct cvmx_mio_rst_int_cn61xx cn63xx; struct cvmx_mio_rst_int_cn61xx cn63xxp1; struct cvmx_mio_rst_int_s cn66xx; struct cvmx_mio_rst_int_cn61xx cn68xx; struct cvmx_mio_rst_int_cn61xx cn68xxp1; + struct cvmx_mio_rst_int_cn61xx cnf71xx; }; union cvmx_mio_rst_int_en { uint64_t u64; struct cvmx_mio_rst_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t perst1:1; uint64_t perst0:1; @@ -2218,25 +3656,46 @@ union cvmx_mio_rst_int_en { uint64_t rst_link2:1; uint64_t rst_link1:1; uint64_t rst_link0:1; +#else + uint64_t rst_link0:1; + uint64_t rst_link1:1; + uint64_t rst_link2:1; + uint64_t rst_link3:1; + uint64_t reserved_4_7:4; + uint64_t perst0:1; + uint64_t perst1:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_mio_rst_int_en_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t perst1:1; uint64_t perst0:1; uint64_t reserved_2_7:6; uint64_t rst_link1:1; uint64_t rst_link0:1; +#else + uint64_t rst_link0:1; + uint64_t rst_link1:1; + uint64_t reserved_2_7:6; + uint64_t perst0:1; + uint64_t perst1:1; + uint64_t reserved_10_63:54; +#endif } cn61xx; struct cvmx_mio_rst_int_en_cn61xx cn63xx; struct cvmx_mio_rst_int_en_cn61xx cn63xxp1; struct cvmx_mio_rst_int_en_s cn66xx; struct cvmx_mio_rst_int_en_cn61xx cn68xx; struct cvmx_mio_rst_int_en_cn61xx cn68xxp1; + struct cvmx_mio_rst_int_en_cn61xx cnf71xx; }; union cvmx_mio_twsx_int { uint64_t u64; struct cvmx_mio_twsx_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t scl:1; uint64_t sda:1; @@ -2250,11 +3709,27 @@ union cvmx_mio_twsx_int { uint64_t core_int:1; uint64_t ts_int:1; uint64_t st_int:1; +#else + uint64_t st_int:1; + uint64_t ts_int:1; + uint64_t core_int:1; + uint64_t reserved_3_3:1; + uint64_t st_en:1; + uint64_t ts_en:1; + uint64_t core_en:1; + uint64_t reserved_7_7:1; + uint64_t sda_ovr:1; + uint64_t scl_ovr:1; + uint64_t sda:1; + uint64_t scl:1; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_mio_twsx_int_s cn30xx; struct cvmx_mio_twsx_int_s cn31xx; struct cvmx_mio_twsx_int_s cn38xx; struct cvmx_mio_twsx_int_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t core_en:1; uint64_t ts_en:1; @@ -2263,6 +3738,16 @@ union cvmx_mio_twsx_int { uint64_t core_int:1; uint64_t ts_int:1; uint64_t st_int:1; +#else + uint64_t st_int:1; + uint64_t ts_int:1; + uint64_t core_int:1; + uint64_t reserved_3_3:1; + uint64_t st_en:1; + uint64_t ts_en:1; + uint64_t core_en:1; + uint64_t reserved_7_63:57; +#endif } cn38xxp2; struct cvmx_mio_twsx_int_s cn50xx; struct cvmx_mio_twsx_int_s cn52xx; @@ -2277,11 +3762,13 @@ union cvmx_mio_twsx_int { struct cvmx_mio_twsx_int_s cn66xx; struct cvmx_mio_twsx_int_s cn68xx; struct cvmx_mio_twsx_int_s cn68xxp1; + struct cvmx_mio_twsx_int_s cnf71xx; }; union cvmx_mio_twsx_sw_twsi { uint64_t u64; struct cvmx_mio_twsx_sw_twsi_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t v:1; uint64_t slonly:1; uint64_t eia:1; @@ -2294,6 +3781,20 @@ union cvmx_mio_twsx_sw_twsi { uint64_t ia:5; uint64_t eop_ia:3; uint64_t d:32; +#else + uint64_t d:32; + uint64_t eop_ia:3; + uint64_t ia:5; + uint64_t a:10; + uint64_t scr:2; + uint64_t size:3; + uint64_t sovr:1; + uint64_t r:1; + uint64_t op:4; + uint64_t eia:1; + uint64_t slonly:1; + uint64_t v:1; +#endif } s; struct cvmx_mio_twsx_sw_twsi_s cn30xx; struct cvmx_mio_twsx_sw_twsi_s cn31xx; @@ -2312,14 +3813,21 @@ union cvmx_mio_twsx_sw_twsi { struct cvmx_mio_twsx_sw_twsi_s cn66xx; struct cvmx_mio_twsx_sw_twsi_s cn68xx; struct cvmx_mio_twsx_sw_twsi_s cn68xxp1; + struct cvmx_mio_twsx_sw_twsi_s cnf71xx; }; union cvmx_mio_twsx_sw_twsi_ext { uint64_t u64; struct cvmx_mio_twsx_sw_twsi_ext_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ia:8; uint64_t d:32; +#else + uint64_t d:32; + uint64_t ia:8; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx; struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx; @@ -2338,14 +3846,21 @@ union cvmx_mio_twsx_sw_twsi_ext { struct cvmx_mio_twsx_sw_twsi_ext_s cn66xx; struct cvmx_mio_twsx_sw_twsi_ext_s cn68xx; struct cvmx_mio_twsx_sw_twsi_ext_s cn68xxp1; + struct cvmx_mio_twsx_sw_twsi_ext_s cnf71xx; }; union cvmx_mio_twsx_twsi_sw { uint64_t u64; struct cvmx_mio_twsx_twsi_sw_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t v:2; uint64_t reserved_32_61:30; uint64_t d:32; +#else + uint64_t d:32; + uint64_t reserved_32_61:30; + uint64_t v:2; +#endif } s; struct cvmx_mio_twsx_twsi_sw_s cn30xx; struct cvmx_mio_twsx_twsi_sw_s cn31xx; @@ -2364,13 +3879,19 @@ union cvmx_mio_twsx_twsi_sw { struct cvmx_mio_twsx_twsi_sw_s cn66xx; struct cvmx_mio_twsx_twsi_sw_s cn68xx; struct cvmx_mio_twsx_twsi_sw_s cn68xxp1; + struct cvmx_mio_twsx_twsi_sw_s cnf71xx; }; union cvmx_mio_uartx_dlh { uint64_t u64; struct cvmx_mio_uartx_dlh_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dlh:8; +#else + uint64_t dlh:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_dlh_s cn30xx; struct cvmx_mio_uartx_dlh_s cn31xx; @@ -2389,13 +3910,19 @@ union cvmx_mio_uartx_dlh { struct cvmx_mio_uartx_dlh_s cn66xx; struct cvmx_mio_uartx_dlh_s cn68xx; struct cvmx_mio_uartx_dlh_s cn68xxp1; + struct cvmx_mio_uartx_dlh_s cnf71xx; }; union cvmx_mio_uartx_dll { uint64_t u64; struct cvmx_mio_uartx_dll_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dll:8; +#else + uint64_t dll:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_dll_s cn30xx; struct cvmx_mio_uartx_dll_s cn31xx; @@ -2414,13 +3941,19 @@ union cvmx_mio_uartx_dll { struct cvmx_mio_uartx_dll_s cn66xx; struct cvmx_mio_uartx_dll_s cn68xx; struct cvmx_mio_uartx_dll_s cn68xxp1; + struct cvmx_mio_uartx_dll_s cnf71xx; }; union cvmx_mio_uartx_far { uint64_t u64; struct cvmx_mio_uartx_far_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t far:1; +#else + uint64_t far:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uartx_far_s cn30xx; struct cvmx_mio_uartx_far_s cn31xx; @@ -2439,11 +3972,13 @@ union cvmx_mio_uartx_far { struct cvmx_mio_uartx_far_s cn66xx; struct cvmx_mio_uartx_far_s cn68xx; struct cvmx_mio_uartx_far_s cn68xxp1; + struct cvmx_mio_uartx_far_s cnf71xx; }; union cvmx_mio_uartx_fcr { uint64_t u64; struct cvmx_mio_uartx_fcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rxtrig:2; uint64_t txtrig:2; @@ -2451,6 +3986,15 @@ union cvmx_mio_uartx_fcr { uint64_t txfr:1; uint64_t rxfr:1; uint64_t en:1; +#else + uint64_t en:1; + uint64_t rxfr:1; + uint64_t txfr:1; + uint64_t reserved_3_3:1; + uint64_t txtrig:2; + uint64_t rxtrig:2; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_fcr_s cn30xx; struct cvmx_mio_uartx_fcr_s cn31xx; @@ -2469,13 +4013,19 @@ union cvmx_mio_uartx_fcr { struct cvmx_mio_uartx_fcr_s cn66xx; struct cvmx_mio_uartx_fcr_s cn68xx; struct cvmx_mio_uartx_fcr_s cn68xxp1; + struct cvmx_mio_uartx_fcr_s cnf71xx; }; union cvmx_mio_uartx_htx { uint64_t u64; struct cvmx_mio_uartx_htx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t htx:1; +#else + uint64_t htx:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uartx_htx_s cn30xx; struct cvmx_mio_uartx_htx_s cn31xx; @@ -2494,11 +4044,13 @@ union cvmx_mio_uartx_htx { struct cvmx_mio_uartx_htx_s cn66xx; struct cvmx_mio_uartx_htx_s cn68xx; struct cvmx_mio_uartx_htx_s cn68xxp1; + struct cvmx_mio_uartx_htx_s cnf71xx; }; union cvmx_mio_uartx_ier { uint64_t u64; struct cvmx_mio_uartx_ier_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ptime:1; uint64_t reserved_4_6:3; @@ -2506,6 +4058,15 @@ union cvmx_mio_uartx_ier { uint64_t elsi:1; uint64_t etbei:1; uint64_t erbfi:1; +#else + uint64_t erbfi:1; + uint64_t etbei:1; + uint64_t elsi:1; + uint64_t edssi:1; + uint64_t reserved_4_6:3; + uint64_t ptime:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_ier_s cn30xx; struct cvmx_mio_uartx_ier_s cn31xx; @@ -2524,15 +4085,23 @@ union cvmx_mio_uartx_ier { struct cvmx_mio_uartx_ier_s cn66xx; struct cvmx_mio_uartx_ier_s cn68xx; struct cvmx_mio_uartx_ier_s cn68xxp1; + struct cvmx_mio_uartx_ier_s cnf71xx; }; union cvmx_mio_uartx_iir { uint64_t u64; struct cvmx_mio_uartx_iir_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t fen:2; uint64_t reserved_4_5:2; uint64_t iid:4; +#else + uint64_t iid:4; + uint64_t reserved_4_5:2; + uint64_t fen:2; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_iir_s cn30xx; struct cvmx_mio_uartx_iir_s cn31xx; @@ -2551,11 +4120,13 @@ union cvmx_mio_uartx_iir { struct cvmx_mio_uartx_iir_s cn66xx; struct cvmx_mio_uartx_iir_s cn68xx; struct cvmx_mio_uartx_iir_s cn68xxp1; + struct cvmx_mio_uartx_iir_s cnf71xx; }; union cvmx_mio_uartx_lcr { uint64_t u64; struct cvmx_mio_uartx_lcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dlab:1; uint64_t brk:1; @@ -2564,6 +4135,16 @@ union cvmx_mio_uartx_lcr { uint64_t pen:1; uint64_t stop:1; uint64_t cls:2; +#else + uint64_t cls:2; + uint64_t stop:1; + uint64_t pen:1; + uint64_t eps:1; + uint64_t reserved_5_5:1; + uint64_t brk:1; + uint64_t dlab:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_lcr_s cn30xx; struct cvmx_mio_uartx_lcr_s cn31xx; @@ -2582,11 +4163,13 @@ union cvmx_mio_uartx_lcr { struct cvmx_mio_uartx_lcr_s cn66xx; struct cvmx_mio_uartx_lcr_s cn68xx; struct cvmx_mio_uartx_lcr_s cn68xxp1; + struct cvmx_mio_uartx_lcr_s cnf71xx; }; union cvmx_mio_uartx_lsr { uint64_t u64; struct cvmx_mio_uartx_lsr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ferr:1; uint64_t temt:1; @@ -2596,6 +4179,17 @@ union cvmx_mio_uartx_lsr { uint64_t pe:1; uint64_t oe:1; uint64_t dr:1; +#else + uint64_t dr:1; + uint64_t oe:1; + uint64_t pe:1; + uint64_t fe:1; + uint64_t bi:1; + uint64_t thre:1; + uint64_t temt:1; + uint64_t ferr:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_lsr_s cn30xx; struct cvmx_mio_uartx_lsr_s cn31xx; @@ -2614,11 +4208,13 @@ union cvmx_mio_uartx_lsr { struct cvmx_mio_uartx_lsr_s cn66xx; struct cvmx_mio_uartx_lsr_s cn68xx; struct cvmx_mio_uartx_lsr_s cn68xxp1; + struct cvmx_mio_uartx_lsr_s cnf71xx; }; union cvmx_mio_uartx_mcr { uint64_t u64; struct cvmx_mio_uartx_mcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t afce:1; uint64_t loop:1; @@ -2626,6 +4222,15 @@ union cvmx_mio_uartx_mcr { uint64_t out1:1; uint64_t rts:1; uint64_t dtr:1; +#else + uint64_t dtr:1; + uint64_t rts:1; + uint64_t out1:1; + uint64_t out2:1; + uint64_t loop:1; + uint64_t afce:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_mio_uartx_mcr_s cn30xx; struct cvmx_mio_uartx_mcr_s cn31xx; @@ -2644,11 +4249,13 @@ union cvmx_mio_uartx_mcr { struct cvmx_mio_uartx_mcr_s cn66xx; struct cvmx_mio_uartx_mcr_s cn68xx; struct cvmx_mio_uartx_mcr_s cn68xxp1; + struct cvmx_mio_uartx_mcr_s cnf71xx; }; union cvmx_mio_uartx_msr { uint64_t u64; struct cvmx_mio_uartx_msr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dcd:1; uint64_t ri:1; @@ -2658,6 +4265,17 @@ union cvmx_mio_uartx_msr { uint64_t teri:1; uint64_t ddsr:1; uint64_t dcts:1; +#else + uint64_t dcts:1; + uint64_t ddsr:1; + uint64_t teri:1; + uint64_t ddcd:1; + uint64_t cts:1; + uint64_t dsr:1; + uint64_t ri:1; + uint64_t dcd:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_msr_s cn30xx; struct cvmx_mio_uartx_msr_s cn31xx; @@ -2676,13 +4294,19 @@ union cvmx_mio_uartx_msr { struct cvmx_mio_uartx_msr_s cn66xx; struct cvmx_mio_uartx_msr_s cn68xx; struct cvmx_mio_uartx_msr_s cn68xxp1; + struct cvmx_mio_uartx_msr_s cnf71xx; }; union cvmx_mio_uartx_rbr { uint64_t u64; struct cvmx_mio_uartx_rbr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rbr:8; +#else + uint64_t rbr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_rbr_s cn30xx; struct cvmx_mio_uartx_rbr_s cn31xx; @@ -2701,13 +4325,19 @@ union cvmx_mio_uartx_rbr { struct cvmx_mio_uartx_rbr_s cn66xx; struct cvmx_mio_uartx_rbr_s cn68xx; struct cvmx_mio_uartx_rbr_s cn68xxp1; + struct cvmx_mio_uartx_rbr_s cnf71xx; }; union cvmx_mio_uartx_rfl { uint64_t u64; struct cvmx_mio_uartx_rfl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t rfl:7; +#else + uint64_t rfl:7; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_mio_uartx_rfl_s cn30xx; struct cvmx_mio_uartx_rfl_s cn31xx; @@ -2726,15 +4356,23 @@ union cvmx_mio_uartx_rfl { struct cvmx_mio_uartx_rfl_s cn66xx; struct cvmx_mio_uartx_rfl_s cn68xx; struct cvmx_mio_uartx_rfl_s cn68xxp1; + struct cvmx_mio_uartx_rfl_s cnf71xx; }; union cvmx_mio_uartx_rfw { uint64_t u64; struct cvmx_mio_uartx_rfw_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t rffe:1; uint64_t rfpe:1; uint64_t rfwd:8; +#else + uint64_t rfwd:8; + uint64_t rfpe:1; + uint64_t rffe:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_mio_uartx_rfw_s cn30xx; struct cvmx_mio_uartx_rfw_s cn31xx; @@ -2753,13 +4391,19 @@ union cvmx_mio_uartx_rfw { struct cvmx_mio_uartx_rfw_s cn66xx; struct cvmx_mio_uartx_rfw_s cn68xx; struct cvmx_mio_uartx_rfw_s cn68xxp1; + struct cvmx_mio_uartx_rfw_s cnf71xx; }; union cvmx_mio_uartx_sbcr { uint64_t u64; struct cvmx_mio_uartx_sbcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t sbcr:1; +#else + uint64_t sbcr:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uartx_sbcr_s cn30xx; struct cvmx_mio_uartx_sbcr_s cn31xx; @@ -2778,13 +4422,19 @@ union cvmx_mio_uartx_sbcr { struct cvmx_mio_uartx_sbcr_s cn66xx; struct cvmx_mio_uartx_sbcr_s cn68xx; struct cvmx_mio_uartx_sbcr_s cn68xxp1; + struct cvmx_mio_uartx_sbcr_s cnf71xx; }; union cvmx_mio_uartx_scr { uint64_t u64; struct cvmx_mio_uartx_scr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t scr:8; +#else + uint64_t scr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_scr_s cn30xx; struct cvmx_mio_uartx_scr_s cn31xx; @@ -2803,13 +4453,19 @@ union cvmx_mio_uartx_scr { struct cvmx_mio_uartx_scr_s cn66xx; struct cvmx_mio_uartx_scr_s cn68xx; struct cvmx_mio_uartx_scr_s cn68xxp1; + struct cvmx_mio_uartx_scr_s cnf71xx; }; union cvmx_mio_uartx_sfe { uint64_t u64; struct cvmx_mio_uartx_sfe_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t sfe:1; +#else + uint64_t sfe:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uartx_sfe_s cn30xx; struct cvmx_mio_uartx_sfe_s cn31xx; @@ -2828,15 +4484,23 @@ union cvmx_mio_uartx_sfe { struct cvmx_mio_uartx_sfe_s cn66xx; struct cvmx_mio_uartx_sfe_s cn68xx; struct cvmx_mio_uartx_sfe_s cn68xxp1; + struct cvmx_mio_uartx_sfe_s cnf71xx; }; union cvmx_mio_uartx_srr { uint64_t u64; struct cvmx_mio_uartx_srr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t stfr:1; uint64_t srfr:1; uint64_t usr:1; +#else + uint64_t usr:1; + uint64_t srfr:1; + uint64_t stfr:1; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_mio_uartx_srr_s cn30xx; struct cvmx_mio_uartx_srr_s cn31xx; @@ -2855,13 +4519,19 @@ union cvmx_mio_uartx_srr { struct cvmx_mio_uartx_srr_s cn66xx; struct cvmx_mio_uartx_srr_s cn68xx; struct cvmx_mio_uartx_srr_s cn68xxp1; + struct cvmx_mio_uartx_srr_s cnf71xx; }; union cvmx_mio_uartx_srt { uint64_t u64; struct cvmx_mio_uartx_srt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t srt:2; +#else + uint64_t srt:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_uartx_srt_s cn30xx; struct cvmx_mio_uartx_srt_s cn31xx; @@ -2880,13 +4550,19 @@ union cvmx_mio_uartx_srt { struct cvmx_mio_uartx_srt_s cn66xx; struct cvmx_mio_uartx_srt_s cn68xx; struct cvmx_mio_uartx_srt_s cn68xxp1; + struct cvmx_mio_uartx_srt_s cnf71xx; }; union cvmx_mio_uartx_srts { uint64_t u64; struct cvmx_mio_uartx_srts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t srts:1; +#else + uint64_t srts:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uartx_srts_s cn30xx; struct cvmx_mio_uartx_srts_s cn31xx; @@ -2905,13 +4581,19 @@ union cvmx_mio_uartx_srts { struct cvmx_mio_uartx_srts_s cn66xx; struct cvmx_mio_uartx_srts_s cn68xx; struct cvmx_mio_uartx_srts_s cn68xxp1; + struct cvmx_mio_uartx_srts_s cnf71xx; }; union cvmx_mio_uartx_stt { uint64_t u64; struct cvmx_mio_uartx_stt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t stt:2; +#else + uint64_t stt:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_uartx_stt_s cn30xx; struct cvmx_mio_uartx_stt_s cn31xx; @@ -2930,13 +4612,19 @@ union cvmx_mio_uartx_stt { struct cvmx_mio_uartx_stt_s cn66xx; struct cvmx_mio_uartx_stt_s cn68xx; struct cvmx_mio_uartx_stt_s cn68xxp1; + struct cvmx_mio_uartx_stt_s cnf71xx; }; union cvmx_mio_uartx_tfl { uint64_t u64; struct cvmx_mio_uartx_tfl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t tfl:7; +#else + uint64_t tfl:7; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_mio_uartx_tfl_s cn30xx; struct cvmx_mio_uartx_tfl_s cn31xx; @@ -2955,13 +4643,19 @@ union cvmx_mio_uartx_tfl { struct cvmx_mio_uartx_tfl_s cn66xx; struct cvmx_mio_uartx_tfl_s cn68xx; struct cvmx_mio_uartx_tfl_s cn68xxp1; + struct cvmx_mio_uartx_tfl_s cnf71xx; }; union cvmx_mio_uartx_tfr { uint64_t u64; struct cvmx_mio_uartx_tfr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t tfr:8; +#else + uint64_t tfr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_tfr_s cn30xx; struct cvmx_mio_uartx_tfr_s cn31xx; @@ -2980,13 +4674,19 @@ union cvmx_mio_uartx_tfr { struct cvmx_mio_uartx_tfr_s cn66xx; struct cvmx_mio_uartx_tfr_s cn68xx; struct cvmx_mio_uartx_tfr_s cn68xxp1; + struct cvmx_mio_uartx_tfr_s cnf71xx; }; union cvmx_mio_uartx_thr { uint64_t u64; struct cvmx_mio_uartx_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t thr:8; +#else + uint64_t thr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_thr_s cn30xx; struct cvmx_mio_uartx_thr_s cn31xx; @@ -3005,17 +4705,27 @@ union cvmx_mio_uartx_thr { struct cvmx_mio_uartx_thr_s cn66xx; struct cvmx_mio_uartx_thr_s cn68xx; struct cvmx_mio_uartx_thr_s cn68xxp1; + struct cvmx_mio_uartx_thr_s cnf71xx; }; union cvmx_mio_uartx_usr { uint64_t u64; struct cvmx_mio_uartx_usr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t rff:1; uint64_t rfne:1; uint64_t tfe:1; uint64_t tfnf:1; uint64_t busy:1; +#else + uint64_t busy:1; + uint64_t tfnf:1; + uint64_t tfe:1; + uint64_t rfne:1; + uint64_t rff:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_mio_uartx_usr_s cn30xx; struct cvmx_mio_uartx_usr_s cn31xx; @@ -3034,13 +4744,19 @@ union cvmx_mio_uartx_usr { struct cvmx_mio_uartx_usr_s cn66xx; struct cvmx_mio_uartx_usr_s cn68xx; struct cvmx_mio_uartx_usr_s cn68xxp1; + struct cvmx_mio_uartx_usr_s cnf71xx; }; union cvmx_mio_uart2_dlh { uint64_t u64; struct cvmx_mio_uart2_dlh_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dlh:8; +#else + uint64_t dlh:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_dlh_s cn52xx; struct cvmx_mio_uart2_dlh_s cn52xxp1; @@ -3049,8 +4765,13 @@ union cvmx_mio_uart2_dlh { union cvmx_mio_uart2_dll { uint64_t u64; struct cvmx_mio_uart2_dll_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dll:8; +#else + uint64_t dll:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_dll_s cn52xx; struct cvmx_mio_uart2_dll_s cn52xxp1; @@ -3059,8 +4780,13 @@ union cvmx_mio_uart2_dll { union cvmx_mio_uart2_far { uint64_t u64; struct cvmx_mio_uart2_far_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t far:1; +#else + uint64_t far:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uart2_far_s cn52xx; struct cvmx_mio_uart2_far_s cn52xxp1; @@ -3069,6 +4795,7 @@ union cvmx_mio_uart2_far { union cvmx_mio_uart2_fcr { uint64_t u64; struct cvmx_mio_uart2_fcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rxtrig:2; uint64_t txtrig:2; @@ -3076,6 +4803,15 @@ union cvmx_mio_uart2_fcr { uint64_t txfr:1; uint64_t rxfr:1; uint64_t en:1; +#else + uint64_t en:1; + uint64_t rxfr:1; + uint64_t txfr:1; + uint64_t reserved_3_3:1; + uint64_t txtrig:2; + uint64_t rxtrig:2; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_fcr_s cn52xx; struct cvmx_mio_uart2_fcr_s cn52xxp1; @@ -3084,8 +4820,13 @@ union cvmx_mio_uart2_fcr { union cvmx_mio_uart2_htx { uint64_t u64; struct cvmx_mio_uart2_htx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t htx:1; +#else + uint64_t htx:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uart2_htx_s cn52xx; struct cvmx_mio_uart2_htx_s cn52xxp1; @@ -3094,6 +4835,7 @@ union cvmx_mio_uart2_htx { union cvmx_mio_uart2_ier { uint64_t u64; struct cvmx_mio_uart2_ier_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ptime:1; uint64_t reserved_4_6:3; @@ -3101,6 +4843,15 @@ union cvmx_mio_uart2_ier { uint64_t elsi:1; uint64_t etbei:1; uint64_t erbfi:1; +#else + uint64_t erbfi:1; + uint64_t etbei:1; + uint64_t elsi:1; + uint64_t edssi:1; + uint64_t reserved_4_6:3; + uint64_t ptime:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_ier_s cn52xx; struct cvmx_mio_uart2_ier_s cn52xxp1; @@ -3109,10 +4860,17 @@ union cvmx_mio_uart2_ier { union cvmx_mio_uart2_iir { uint64_t u64; struct cvmx_mio_uart2_iir_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t fen:2; uint64_t reserved_4_5:2; uint64_t iid:4; +#else + uint64_t iid:4; + uint64_t reserved_4_5:2; + uint64_t fen:2; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_iir_s cn52xx; struct cvmx_mio_uart2_iir_s cn52xxp1; @@ -3121,6 +4879,7 @@ union cvmx_mio_uart2_iir { union cvmx_mio_uart2_lcr { uint64_t u64; struct cvmx_mio_uart2_lcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dlab:1; uint64_t brk:1; @@ -3129,6 +4888,16 @@ union cvmx_mio_uart2_lcr { uint64_t pen:1; uint64_t stop:1; uint64_t cls:2; +#else + uint64_t cls:2; + uint64_t stop:1; + uint64_t pen:1; + uint64_t eps:1; + uint64_t reserved_5_5:1; + uint64_t brk:1; + uint64_t dlab:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_lcr_s cn52xx; struct cvmx_mio_uart2_lcr_s cn52xxp1; @@ -3137,6 +4906,7 @@ union cvmx_mio_uart2_lcr { union cvmx_mio_uart2_lsr { uint64_t u64; struct cvmx_mio_uart2_lsr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ferr:1; uint64_t temt:1; @@ -3146,6 +4916,17 @@ union cvmx_mio_uart2_lsr { uint64_t pe:1; uint64_t oe:1; uint64_t dr:1; +#else + uint64_t dr:1; + uint64_t oe:1; + uint64_t pe:1; + uint64_t fe:1; + uint64_t bi:1; + uint64_t thre:1; + uint64_t temt:1; + uint64_t ferr:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_lsr_s cn52xx; struct cvmx_mio_uart2_lsr_s cn52xxp1; @@ -3154,6 +4935,7 @@ union cvmx_mio_uart2_lsr { union cvmx_mio_uart2_mcr { uint64_t u64; struct cvmx_mio_uart2_mcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t afce:1; uint64_t loop:1; @@ -3161,6 +4943,15 @@ union cvmx_mio_uart2_mcr { uint64_t out1:1; uint64_t rts:1; uint64_t dtr:1; +#else + uint64_t dtr:1; + uint64_t rts:1; + uint64_t out1:1; + uint64_t out2:1; + uint64_t loop:1; + uint64_t afce:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_mio_uart2_mcr_s cn52xx; struct cvmx_mio_uart2_mcr_s cn52xxp1; @@ -3169,6 +4960,7 @@ union cvmx_mio_uart2_mcr { union cvmx_mio_uart2_msr { uint64_t u64; struct cvmx_mio_uart2_msr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dcd:1; uint64_t ri:1; @@ -3178,6 +4970,17 @@ union cvmx_mio_uart2_msr { uint64_t teri:1; uint64_t ddsr:1; uint64_t dcts:1; +#else + uint64_t dcts:1; + uint64_t ddsr:1; + uint64_t teri:1; + uint64_t ddcd:1; + uint64_t cts:1; + uint64_t dsr:1; + uint64_t ri:1; + uint64_t dcd:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_msr_s cn52xx; struct cvmx_mio_uart2_msr_s cn52xxp1; @@ -3186,8 +4989,13 @@ union cvmx_mio_uart2_msr { union cvmx_mio_uart2_rbr { uint64_t u64; struct cvmx_mio_uart2_rbr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rbr:8; +#else + uint64_t rbr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_rbr_s cn52xx; struct cvmx_mio_uart2_rbr_s cn52xxp1; @@ -3196,8 +5004,13 @@ union cvmx_mio_uart2_rbr { union cvmx_mio_uart2_rfl { uint64_t u64; struct cvmx_mio_uart2_rfl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t rfl:7; +#else + uint64_t rfl:7; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_mio_uart2_rfl_s cn52xx; struct cvmx_mio_uart2_rfl_s cn52xxp1; @@ -3206,10 +5019,17 @@ union cvmx_mio_uart2_rfl { union cvmx_mio_uart2_rfw { uint64_t u64; struct cvmx_mio_uart2_rfw_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t rffe:1; uint64_t rfpe:1; uint64_t rfwd:8; +#else + uint64_t rfwd:8; + uint64_t rfpe:1; + uint64_t rffe:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_mio_uart2_rfw_s cn52xx; struct cvmx_mio_uart2_rfw_s cn52xxp1; @@ -3218,8 +5038,13 @@ union cvmx_mio_uart2_rfw { union cvmx_mio_uart2_sbcr { uint64_t u64; struct cvmx_mio_uart2_sbcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t sbcr:1; +#else + uint64_t sbcr:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uart2_sbcr_s cn52xx; struct cvmx_mio_uart2_sbcr_s cn52xxp1; @@ -3228,8 +5053,13 @@ union cvmx_mio_uart2_sbcr { union cvmx_mio_uart2_scr { uint64_t u64; struct cvmx_mio_uart2_scr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t scr:8; +#else + uint64_t scr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_scr_s cn52xx; struct cvmx_mio_uart2_scr_s cn52xxp1; @@ -3238,8 +5068,13 @@ union cvmx_mio_uart2_scr { union cvmx_mio_uart2_sfe { uint64_t u64; struct cvmx_mio_uart2_sfe_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t sfe:1; +#else + uint64_t sfe:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uart2_sfe_s cn52xx; struct cvmx_mio_uart2_sfe_s cn52xxp1; @@ -3248,10 +5083,17 @@ union cvmx_mio_uart2_sfe { union cvmx_mio_uart2_srr { uint64_t u64; struct cvmx_mio_uart2_srr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t stfr:1; uint64_t srfr:1; uint64_t usr:1; +#else + uint64_t usr:1; + uint64_t srfr:1; + uint64_t stfr:1; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_mio_uart2_srr_s cn52xx; struct cvmx_mio_uart2_srr_s cn52xxp1; @@ -3260,8 +5102,13 @@ union cvmx_mio_uart2_srr { union cvmx_mio_uart2_srt { uint64_t u64; struct cvmx_mio_uart2_srt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t srt:2; +#else + uint64_t srt:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_uart2_srt_s cn52xx; struct cvmx_mio_uart2_srt_s cn52xxp1; @@ -3270,8 +5117,13 @@ union cvmx_mio_uart2_srt { union cvmx_mio_uart2_srts { uint64_t u64; struct cvmx_mio_uart2_srts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t srts:1; +#else + uint64_t srts:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uart2_srts_s cn52xx; struct cvmx_mio_uart2_srts_s cn52xxp1; @@ -3280,8 +5132,13 @@ union cvmx_mio_uart2_srts { union cvmx_mio_uart2_stt { uint64_t u64; struct cvmx_mio_uart2_stt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t stt:2; +#else + uint64_t stt:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_uart2_stt_s cn52xx; struct cvmx_mio_uart2_stt_s cn52xxp1; @@ -3290,8 +5147,13 @@ union cvmx_mio_uart2_stt { union cvmx_mio_uart2_tfl { uint64_t u64; struct cvmx_mio_uart2_tfl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t tfl:7; +#else + uint64_t tfl:7; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_mio_uart2_tfl_s cn52xx; struct cvmx_mio_uart2_tfl_s cn52xxp1; @@ -3300,8 +5162,13 @@ union cvmx_mio_uart2_tfl { union cvmx_mio_uart2_tfr { uint64_t u64; struct cvmx_mio_uart2_tfr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t tfr:8; +#else + uint64_t tfr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_tfr_s cn52xx; struct cvmx_mio_uart2_tfr_s cn52xxp1; @@ -3310,8 +5177,13 @@ union cvmx_mio_uart2_tfr { union cvmx_mio_uart2_thr { uint64_t u64; struct cvmx_mio_uart2_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t thr:8; +#else + uint64_t thr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_thr_s cn52xx; struct cvmx_mio_uart2_thr_s cn52xxp1; @@ -3320,12 +5192,21 @@ union cvmx_mio_uart2_thr { union cvmx_mio_uart2_usr { uint64_t u64; struct cvmx_mio_uart2_usr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t rff:1; uint64_t rfne:1; uint64_t tfe:1; uint64_t tfnf:1; uint64_t busy:1; +#else + uint64_t busy:1; + uint64_t tfnf:1; + uint64_t tfe:1; + uint64_t rfne:1; + uint64_t rff:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_mio_uart2_usr_s cn52xx; struct cvmx_mio_uart2_usr_s cn52xxp1; diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h index 7057c447e69e..3155e6019dc8 100644 --- a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -47,6 +47,7 @@ union cvmx_mixx_bist { uint64_t u64; struct cvmx_mixx_bist_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t opfdat:1; uint64_t mrgdat:1; @@ -54,24 +55,46 @@ union cvmx_mixx_bist { uint64_t ipfdat:1; uint64_t irfdat:1; uint64_t orfdat:1; +#else + uint64_t orfdat:1; + uint64_t irfdat:1; + uint64_t ipfdat:1; + uint64_t mrqdat:1; + uint64_t mrgdat:1; + uint64_t opfdat:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_mixx_bist_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t mrqdat:1; uint64_t ipfdat:1; uint64_t irfdat:1; uint64_t orfdat:1; +#else + uint64_t orfdat:1; + uint64_t irfdat:1; + uint64_t ipfdat:1; + uint64_t mrqdat:1; + uint64_t reserved_4_63:60; +#endif } cn52xx; struct cvmx_mixx_bist_cn52xx cn52xxp1; struct cvmx_mixx_bist_cn52xx cn56xx; struct cvmx_mixx_bist_cn52xx cn56xxp1; + struct cvmx_mixx_bist_s cn61xx; struct cvmx_mixx_bist_s cn63xx; struct cvmx_mixx_bist_s cn63xxp1; + struct cvmx_mixx_bist_s cn66xx; + struct cvmx_mixx_bist_s cn68xx; + struct cvmx_mixx_bist_s cn68xxp1; }; union cvmx_mixx_ctl { uint64_t u64; struct cvmx_mixx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t ts_thresh:4; uint64_t crc_strip:1; @@ -81,8 +104,20 @@ union cvmx_mixx_ctl { uint64_t lendian:1; uint64_t nbtarb:1; uint64_t mrq_hwm:2; +#else + uint64_t mrq_hwm:2; + uint64_t nbtarb:1; + uint64_t lendian:1; + uint64_t reset:1; + uint64_t en:1; + uint64_t busy:1; + uint64_t crc_strip:1; + uint64_t ts_thresh:4; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_mixx_ctl_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t crc_strip:1; uint64_t busy:1; @@ -91,17 +126,32 @@ union cvmx_mixx_ctl { uint64_t lendian:1; uint64_t nbtarb:1; uint64_t mrq_hwm:2; +#else + uint64_t mrq_hwm:2; + uint64_t nbtarb:1; + uint64_t lendian:1; + uint64_t reset:1; + uint64_t en:1; + uint64_t busy:1; + uint64_t crc_strip:1; + uint64_t reserved_8_63:56; +#endif } cn52xx; struct cvmx_mixx_ctl_cn52xx cn52xxp1; struct cvmx_mixx_ctl_cn52xx cn56xx; struct cvmx_mixx_ctl_cn52xx cn56xxp1; + struct cvmx_mixx_ctl_s cn61xx; struct cvmx_mixx_ctl_s cn63xx; struct cvmx_mixx_ctl_s cn63xxp1; + struct cvmx_mixx_ctl_s cn66xx; + struct cvmx_mixx_ctl_s cn68xx; + struct cvmx_mixx_ctl_s cn68xxp1; }; union cvmx_mixx_intena { uint64_t u64; struct cvmx_mixx_intena_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t tsena:1; uint64_t orunena:1; @@ -111,8 +161,20 @@ union cvmx_mixx_intena { uint64_t othena:1; uint64_t ivfena:1; uint64_t ovfena:1; +#else + uint64_t ovfena:1; + uint64_t ivfena:1; + uint64_t othena:1; + uint64_t ithena:1; + uint64_t data_drpena:1; + uint64_t irunena:1; + uint64_t orunena:1; + uint64_t tsena:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mixx_intena_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t orunena:1; uint64_t irunena:1; @@ -121,84 +183,148 @@ union cvmx_mixx_intena { uint64_t othena:1; uint64_t ivfena:1; uint64_t ovfena:1; +#else + uint64_t ovfena:1; + uint64_t ivfena:1; + uint64_t othena:1; + uint64_t ithena:1; + uint64_t data_drpena:1; + uint64_t irunena:1; + uint64_t orunena:1; + uint64_t reserved_7_63:57; +#endif } cn52xx; struct cvmx_mixx_intena_cn52xx cn52xxp1; struct cvmx_mixx_intena_cn52xx cn56xx; struct cvmx_mixx_intena_cn52xx cn56xxp1; + struct cvmx_mixx_intena_s cn61xx; struct cvmx_mixx_intena_s cn63xx; struct cvmx_mixx_intena_s cn63xxp1; + struct cvmx_mixx_intena_s cn66xx; + struct cvmx_mixx_intena_s cn68xx; + struct cvmx_mixx_intena_s cn68xxp1; }; union cvmx_mixx_ircnt { uint64_t u64; struct cvmx_mixx_ircnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t ircnt:20; +#else + uint64_t ircnt:20; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_mixx_ircnt_s cn52xx; struct cvmx_mixx_ircnt_s cn52xxp1; struct cvmx_mixx_ircnt_s cn56xx; struct cvmx_mixx_ircnt_s cn56xxp1; + struct cvmx_mixx_ircnt_s cn61xx; struct cvmx_mixx_ircnt_s cn63xx; struct cvmx_mixx_ircnt_s cn63xxp1; + struct cvmx_mixx_ircnt_s cn66xx; + struct cvmx_mixx_ircnt_s cn68xx; + struct cvmx_mixx_ircnt_s cn68xxp1; }; union cvmx_mixx_irhwm { uint64_t u64; struct cvmx_mixx_irhwm_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ibplwm:20; uint64_t irhwm:20; +#else + uint64_t irhwm:20; + uint64_t ibplwm:20; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_mixx_irhwm_s cn52xx; struct cvmx_mixx_irhwm_s cn52xxp1; struct cvmx_mixx_irhwm_s cn56xx; struct cvmx_mixx_irhwm_s cn56xxp1; + struct cvmx_mixx_irhwm_s cn61xx; struct cvmx_mixx_irhwm_s cn63xx; struct cvmx_mixx_irhwm_s cn63xxp1; + struct cvmx_mixx_irhwm_s cn66xx; + struct cvmx_mixx_irhwm_s cn68xx; + struct cvmx_mixx_irhwm_s cn68xxp1; }; union cvmx_mixx_iring1 { uint64_t u64; struct cvmx_mixx_iring1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t isize:20; uint64_t ibase:37; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t ibase:37; + uint64_t isize:20; + uint64_t reserved_60_63:4; +#endif } s; struct cvmx_mixx_iring1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t isize:20; uint64_t reserved_36_39:4; uint64_t ibase:33; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t ibase:33; + uint64_t reserved_36_39:4; + uint64_t isize:20; + uint64_t reserved_60_63:4; +#endif } cn52xx; struct cvmx_mixx_iring1_cn52xx cn52xxp1; struct cvmx_mixx_iring1_cn52xx cn56xx; struct cvmx_mixx_iring1_cn52xx cn56xxp1; + struct cvmx_mixx_iring1_s cn61xx; struct cvmx_mixx_iring1_s cn63xx; struct cvmx_mixx_iring1_s cn63xxp1; + struct cvmx_mixx_iring1_s cn66xx; + struct cvmx_mixx_iring1_s cn68xx; + struct cvmx_mixx_iring1_s cn68xxp1; }; union cvmx_mixx_iring2 { uint64_t u64; struct cvmx_mixx_iring2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_52_63:12; uint64_t itlptr:20; uint64_t reserved_20_31:12; uint64_t idbell:20; +#else + uint64_t idbell:20; + uint64_t reserved_20_31:12; + uint64_t itlptr:20; + uint64_t reserved_52_63:12; +#endif } s; struct cvmx_mixx_iring2_s cn52xx; struct cvmx_mixx_iring2_s cn52xxp1; struct cvmx_mixx_iring2_s cn56xx; struct cvmx_mixx_iring2_s cn56xxp1; + struct cvmx_mixx_iring2_s cn61xx; struct cvmx_mixx_iring2_s cn63xx; struct cvmx_mixx_iring2_s cn63xxp1; + struct cvmx_mixx_iring2_s cn66xx; + struct cvmx_mixx_iring2_s cn68xx; + struct cvmx_mixx_iring2_s cn68xxp1; }; union cvmx_mixx_isr { uint64_t u64; struct cvmx_mixx_isr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ts:1; uint64_t orun:1; @@ -208,8 +334,20 @@ union cvmx_mixx_isr { uint64_t orthresh:1; uint64_t idblovf:1; uint64_t odblovf:1; +#else + uint64_t odblovf:1; + uint64_t idblovf:1; + uint64_t orthresh:1; + uint64_t irthresh:1; + uint64_t data_drp:1; + uint64_t irun:1; + uint64_t orun:1; + uint64_t ts:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mixx_isr_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t orun:1; uint64_t irun:1; @@ -218,117 +356,211 @@ union cvmx_mixx_isr { uint64_t orthresh:1; uint64_t idblovf:1; uint64_t odblovf:1; +#else + uint64_t odblovf:1; + uint64_t idblovf:1; + uint64_t orthresh:1; + uint64_t irthresh:1; + uint64_t data_drp:1; + uint64_t irun:1; + uint64_t orun:1; + uint64_t reserved_7_63:57; +#endif } cn52xx; struct cvmx_mixx_isr_cn52xx cn52xxp1; struct cvmx_mixx_isr_cn52xx cn56xx; struct cvmx_mixx_isr_cn52xx cn56xxp1; + struct cvmx_mixx_isr_s cn61xx; struct cvmx_mixx_isr_s cn63xx; struct cvmx_mixx_isr_s cn63xxp1; + struct cvmx_mixx_isr_s cn66xx; + struct cvmx_mixx_isr_s cn68xx; + struct cvmx_mixx_isr_s cn68xxp1; }; union cvmx_mixx_orcnt { uint64_t u64; struct cvmx_mixx_orcnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t orcnt:20; +#else + uint64_t orcnt:20; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_mixx_orcnt_s cn52xx; struct cvmx_mixx_orcnt_s cn52xxp1; struct cvmx_mixx_orcnt_s cn56xx; struct cvmx_mixx_orcnt_s cn56xxp1; + struct cvmx_mixx_orcnt_s cn61xx; struct cvmx_mixx_orcnt_s cn63xx; struct cvmx_mixx_orcnt_s cn63xxp1; + struct cvmx_mixx_orcnt_s cn66xx; + struct cvmx_mixx_orcnt_s cn68xx; + struct cvmx_mixx_orcnt_s cn68xxp1; }; union cvmx_mixx_orhwm { uint64_t u64; struct cvmx_mixx_orhwm_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t orhwm:20; +#else + uint64_t orhwm:20; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_mixx_orhwm_s cn52xx; struct cvmx_mixx_orhwm_s cn52xxp1; struct cvmx_mixx_orhwm_s cn56xx; struct cvmx_mixx_orhwm_s cn56xxp1; + struct cvmx_mixx_orhwm_s cn61xx; struct cvmx_mixx_orhwm_s cn63xx; struct cvmx_mixx_orhwm_s cn63xxp1; + struct cvmx_mixx_orhwm_s cn66xx; + struct cvmx_mixx_orhwm_s cn68xx; + struct cvmx_mixx_orhwm_s cn68xxp1; }; union cvmx_mixx_oring1 { uint64_t u64; struct cvmx_mixx_oring1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t osize:20; uint64_t obase:37; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t obase:37; + uint64_t osize:20; + uint64_t reserved_60_63:4; +#endif } s; struct cvmx_mixx_oring1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t osize:20; uint64_t reserved_36_39:4; uint64_t obase:33; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t obase:33; + uint64_t reserved_36_39:4; + uint64_t osize:20; + uint64_t reserved_60_63:4; +#endif } cn52xx; struct cvmx_mixx_oring1_cn52xx cn52xxp1; struct cvmx_mixx_oring1_cn52xx cn56xx; struct cvmx_mixx_oring1_cn52xx cn56xxp1; + struct cvmx_mixx_oring1_s cn61xx; struct cvmx_mixx_oring1_s cn63xx; struct cvmx_mixx_oring1_s cn63xxp1; + struct cvmx_mixx_oring1_s cn66xx; + struct cvmx_mixx_oring1_s cn68xx; + struct cvmx_mixx_oring1_s cn68xxp1; }; union cvmx_mixx_oring2 { uint64_t u64; struct cvmx_mixx_oring2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_52_63:12; uint64_t otlptr:20; uint64_t reserved_20_31:12; uint64_t odbell:20; +#else + uint64_t odbell:20; + uint64_t reserved_20_31:12; + uint64_t otlptr:20; + uint64_t reserved_52_63:12; +#endif } s; struct cvmx_mixx_oring2_s cn52xx; struct cvmx_mixx_oring2_s cn52xxp1; struct cvmx_mixx_oring2_s cn56xx; struct cvmx_mixx_oring2_s cn56xxp1; + struct cvmx_mixx_oring2_s cn61xx; struct cvmx_mixx_oring2_s cn63xx; struct cvmx_mixx_oring2_s cn63xxp1; + struct cvmx_mixx_oring2_s cn66xx; + struct cvmx_mixx_oring2_s cn68xx; + struct cvmx_mixx_oring2_s cn68xxp1; }; union cvmx_mixx_remcnt { uint64_t u64; struct cvmx_mixx_remcnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_52_63:12; uint64_t iremcnt:20; uint64_t reserved_20_31:12; uint64_t oremcnt:20; +#else + uint64_t oremcnt:20; + uint64_t reserved_20_31:12; + uint64_t iremcnt:20; + uint64_t reserved_52_63:12; +#endif } s; struct cvmx_mixx_remcnt_s cn52xx; struct cvmx_mixx_remcnt_s cn52xxp1; struct cvmx_mixx_remcnt_s cn56xx; struct cvmx_mixx_remcnt_s cn56xxp1; + struct cvmx_mixx_remcnt_s cn61xx; struct cvmx_mixx_remcnt_s cn63xx; struct cvmx_mixx_remcnt_s cn63xxp1; + struct cvmx_mixx_remcnt_s cn66xx; + struct cvmx_mixx_remcnt_s cn68xx; + struct cvmx_mixx_remcnt_s cn68xxp1; }; union cvmx_mixx_tsctl { uint64_t u64; struct cvmx_mixx_tsctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t tsavl:5; uint64_t reserved_13_15:3; uint64_t tstot:5; uint64_t reserved_5_7:3; uint64_t tscnt:5; +#else + uint64_t tscnt:5; + uint64_t reserved_5_7:3; + uint64_t tstot:5; + uint64_t reserved_13_15:3; + uint64_t tsavl:5; + uint64_t reserved_21_63:43; +#endif } s; + struct cvmx_mixx_tsctl_s cn61xx; struct cvmx_mixx_tsctl_s cn63xx; struct cvmx_mixx_tsctl_s cn63xxp1; + struct cvmx_mixx_tsctl_s cn66xx; + struct cvmx_mixx_tsctl_s cn68xx; + struct cvmx_mixx_tsctl_s cn68xxp1; }; union cvmx_mixx_tstamp { uint64_t u64; struct cvmx_mixx_tstamp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t tstamp:64; +#else + uint64_t tstamp:64; +#endif } s; + struct cvmx_mixx_tstamp_s cn61xx; struct cvmx_mixx_tstamp_s cn63xx; struct cvmx_mixx_tstamp_s cn63xxp1; + struct cvmx_mixx_tstamp_s cn66xx; + struct cvmx_mixx_tstamp_s cn68xx; + struct cvmx_mixx_tstamp_s cn68xxp1; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-mpi-defs.h b/arch/mips/include/asm/octeon/cvmx-mpi-defs.h new file mode 100644 index 000000000000..4615b102625b --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-mpi-defs.h @@ -0,0 +1,328 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_MPI_DEFS_H__ +#define __CVMX_MPI_DEFS_H__ + +#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull)) +#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8) +#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull)) +#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull)) + +union cvmx_mpi_cfg { + uint64_t u64; + struct cvmx_mpi_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t clkdiv:13; + uint64_t csena3:1; + uint64_t csena2:1; + uint64_t csena1:1; + uint64_t csena0:1; + uint64_t cslate:1; + uint64_t tritx:1; + uint64_t idleclks:2; + uint64_t cshi:1; + uint64_t csena:1; + uint64_t int_ena:1; + uint64_t lsbfirst:1; + uint64_t wireor:1; + uint64_t clk_cont:1; + uint64_t idlelo:1; + uint64_t enable:1; +#else + uint64_t enable:1; + uint64_t idlelo:1; + uint64_t clk_cont:1; + uint64_t wireor:1; + uint64_t lsbfirst:1; + uint64_t int_ena:1; + uint64_t csena:1; + uint64_t cshi:1; + uint64_t idleclks:2; + uint64_t tritx:1; + uint64_t cslate:1; + uint64_t csena0:1; + uint64_t csena1:1; + uint64_t csena2:1; + uint64_t csena3:1; + uint64_t clkdiv:13; + uint64_t reserved_29_63:35; +#endif + } s; + struct cvmx_mpi_cfg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t clkdiv:13; + uint64_t reserved_12_15:4; + uint64_t cslate:1; + uint64_t tritx:1; + uint64_t idleclks:2; + uint64_t cshi:1; + uint64_t csena:1; + uint64_t int_ena:1; + uint64_t lsbfirst:1; + uint64_t wireor:1; + uint64_t clk_cont:1; + uint64_t idlelo:1; + uint64_t enable:1; +#else + uint64_t enable:1; + uint64_t idlelo:1; + uint64_t clk_cont:1; + uint64_t wireor:1; + uint64_t lsbfirst:1; + uint64_t int_ena:1; + uint64_t csena:1; + uint64_t cshi:1; + uint64_t idleclks:2; + uint64_t tritx:1; + uint64_t cslate:1; + uint64_t reserved_12_15:4; + uint64_t clkdiv:13; + uint64_t reserved_29_63:35; +#endif + } cn30xx; + struct cvmx_mpi_cfg_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t clkdiv:13; + uint64_t reserved_11_15:5; + uint64_t tritx:1; + uint64_t idleclks:2; + uint64_t cshi:1; + uint64_t csena:1; + uint64_t int_ena:1; + uint64_t lsbfirst:1; + uint64_t wireor:1; + uint64_t clk_cont:1; + uint64_t idlelo:1; + uint64_t enable:1; +#else + uint64_t enable:1; + uint64_t idlelo:1; + uint64_t clk_cont:1; + uint64_t wireor:1; + uint64_t lsbfirst:1; + uint64_t int_ena:1; + uint64_t csena:1; + uint64_t cshi:1; + uint64_t idleclks:2; + uint64_t tritx:1; + uint64_t reserved_11_15:5; + uint64_t clkdiv:13; + uint64_t reserved_29_63:35; +#endif + } cn31xx; + struct cvmx_mpi_cfg_cn30xx cn50xx; + struct cvmx_mpi_cfg_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t clkdiv:13; + uint64_t reserved_14_15:2; + uint64_t csena1:1; + uint64_t csena0:1; + uint64_t cslate:1; + uint64_t tritx:1; + uint64_t idleclks:2; + uint64_t cshi:1; + uint64_t reserved_6_6:1; + uint64_t int_ena:1; + uint64_t lsbfirst:1; + uint64_t wireor:1; + uint64_t clk_cont:1; + uint64_t idlelo:1; + uint64_t enable:1; +#else + uint64_t enable:1; + uint64_t idlelo:1; + uint64_t clk_cont:1; + uint64_t wireor:1; + uint64_t lsbfirst:1; + uint64_t int_ena:1; + uint64_t reserved_6_6:1; + uint64_t cshi:1; + uint64_t idleclks:2; + uint64_t tritx:1; + uint64_t cslate:1; + uint64_t csena0:1; + uint64_t csena1:1; + uint64_t reserved_14_15:2; + uint64_t clkdiv:13; + uint64_t reserved_29_63:35; +#endif + } cn61xx; + struct cvmx_mpi_cfg_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t clkdiv:13; + uint64_t csena3:1; + uint64_t csena2:1; + uint64_t reserved_12_13:2; + uint64_t cslate:1; + uint64_t tritx:1; + uint64_t idleclks:2; + uint64_t cshi:1; + uint64_t reserved_6_6:1; + uint64_t int_ena:1; + uint64_t lsbfirst:1; + uint64_t wireor:1; + uint64_t clk_cont:1; + uint64_t idlelo:1; + uint64_t enable:1; +#else + uint64_t enable:1; + uint64_t idlelo:1; + uint64_t clk_cont:1; + uint64_t wireor:1; + uint64_t lsbfirst:1; + uint64_t int_ena:1; + uint64_t reserved_6_6:1; + uint64_t cshi:1; + uint64_t idleclks:2; + uint64_t tritx:1; + uint64_t cslate:1; + uint64_t reserved_12_13:2; + uint64_t csena2:1; + uint64_t csena3:1; + uint64_t clkdiv:13; + uint64_t reserved_29_63:35; +#endif + } cn66xx; + struct cvmx_mpi_cfg_cn61xx cnf71xx; +}; + +union cvmx_mpi_datx { + uint64_t u64; + struct cvmx_mpi_datx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_8_63:56; + uint64_t data:8; +#else + uint64_t data:8; + uint64_t reserved_8_63:56; +#endif + } s; + struct cvmx_mpi_datx_s cn30xx; + struct cvmx_mpi_datx_s cn31xx; + struct cvmx_mpi_datx_s cn50xx; + struct cvmx_mpi_datx_s cn61xx; + struct cvmx_mpi_datx_s cn66xx; + struct cvmx_mpi_datx_s cnf71xx; +}; + +union cvmx_mpi_sts { + uint64_t u64; + struct cvmx_mpi_sts_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_13_63:51; + uint64_t rxnum:5; + uint64_t reserved_1_7:7; + uint64_t busy:1; +#else + uint64_t busy:1; + uint64_t reserved_1_7:7; + uint64_t rxnum:5; + uint64_t reserved_13_63:51; +#endif + } s; + struct cvmx_mpi_sts_s cn30xx; + struct cvmx_mpi_sts_s cn31xx; + struct cvmx_mpi_sts_s cn50xx; + struct cvmx_mpi_sts_s cn61xx; + struct cvmx_mpi_sts_s cn66xx; + struct cvmx_mpi_sts_s cnf71xx; +}; + +union cvmx_mpi_tx { + uint64_t u64; + struct cvmx_mpi_tx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_22_63:42; + uint64_t csid:2; + uint64_t reserved_17_19:3; + uint64_t leavecs:1; + uint64_t reserved_13_15:3; + uint64_t txnum:5; + uint64_t reserved_5_7:3; + uint64_t totnum:5; +#else + uint64_t totnum:5; + uint64_t reserved_5_7:3; + uint64_t txnum:5; + uint64_t reserved_13_15:3; + uint64_t leavecs:1; + uint64_t reserved_17_19:3; + uint64_t csid:2; + uint64_t reserved_22_63:42; +#endif + } s; + struct cvmx_mpi_tx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_17_63:47; + uint64_t leavecs:1; + uint64_t reserved_13_15:3; + uint64_t txnum:5; + uint64_t reserved_5_7:3; + uint64_t totnum:5; +#else + uint64_t totnum:5; + uint64_t reserved_5_7:3; + uint64_t txnum:5; + uint64_t reserved_13_15:3; + uint64_t leavecs:1; + uint64_t reserved_17_63:47; +#endif + } cn30xx; + struct cvmx_mpi_tx_cn30xx cn31xx; + struct cvmx_mpi_tx_cn30xx cn50xx; + struct cvmx_mpi_tx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_21_63:43; + uint64_t csid:1; + uint64_t reserved_17_19:3; + uint64_t leavecs:1; + uint64_t reserved_13_15:3; + uint64_t txnum:5; + uint64_t reserved_5_7:3; + uint64_t totnum:5; +#else + uint64_t totnum:5; + uint64_t reserved_5_7:3; + uint64_t txnum:5; + uint64_t reserved_13_15:3; + uint64_t leavecs:1; + uint64_t reserved_17_19:3; + uint64_t csid:1; + uint64_t reserved_21_63:43; +#endif + } cn61xx; + struct cvmx_mpi_tx_s cn66xx; + struct cvmx_mpi_tx_cn61xx cnf71xx; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h index a3075f733ca5..58114d414356 100644 --- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2011 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -140,11 +140,19 @@ union cvmx_npei_bar1_indexx { uint32_t u32; struct cvmx_npei_bar1_indexx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_18_31:14; uint32_t addr_idx:14; uint32_t ca:1; uint32_t end_swp:2; uint32_t addr_v:1; +#else + uint32_t addr_v:1; + uint32_t end_swp:2; + uint32_t ca:1; + uint32_t addr_idx:14; + uint32_t reserved_18_31:14; +#endif } s; struct cvmx_npei_bar1_indexx_s cn52xx; struct cvmx_npei_bar1_indexx_s cn52xxp1; @@ -155,6 +163,7 @@ union cvmx_npei_bar1_indexx { union cvmx_npei_bist_status { uint64_t u64; struct cvmx_npei_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t pkt_rdf:1; uint64_t reserved_60_62:3; uint64_t pcr_gim:1; @@ -204,8 +213,60 @@ union cvmx_npei_bist_status { uint64_t reserved_2_2:1; uint64_t msi:1; uint64_t ncb_cmd:1; +#else + uint64_t ncb_cmd:1; + uint64_t msi:1; + uint64_t reserved_2_2:1; + uint64_t dif3:1; + uint64_t dif2:1; + uint64_t dif1:1; + uint64_t dif0:1; + uint64_t csm1:1; + uint64_t csm0:1; + uint64_t p2n1_p1:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_n:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_c0:1; + uint64_t p2n0_p1:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_n:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_c0:1; + uint64_t p2n0_co:1; + uint64_t p2n0_no:1; + uint64_t p2n0_po:1; + uint64_t p2n1_co:1; + uint64_t p2n1_no:1; + uint64_t p2n1_po:1; + uint64_t cpl_p1:1; + uint64_t cpl_p0:1; + uint64_t n2p1_o:1; + uint64_t n2p1_c:1; + uint64_t n2p0_o:1; + uint64_t n2p0_c:1; + uint64_t reserved_31_31:1; + uint64_t d3_pst:1; + uint64_t d2_pst:1; + uint64_t d1_pst:1; + uint64_t d0_pst:1; + uint64_t reserved_36_47:12; + uint64_t pkt_slm:1; + uint64_t pkt_ind:1; + uint64_t reserved_50_52:3; + uint64_t pcsr_sl:1; + uint64_t pcsr_id:1; + uint64_t pcsr_cnt:1; + uint64_t pcsr_im:1; + uint64_t pcsr_int:1; + uint64_t pkt_pif:1; + uint64_t pcr_gim:1; + uint64_t reserved_60_62:3; + uint64_t pkt_rdf:1; +#endif } s; struct cvmx_npei_bist_status_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t pkt_rdf:1; uint64_t reserved_60_62:3; uint64_t pcr_gim:1; @@ -264,8 +325,69 @@ union cvmx_npei_bist_status { uint64_t dif4:1; uint64_t msi:1; uint64_t ncb_cmd:1; +#else + uint64_t ncb_cmd:1; + uint64_t msi:1; + uint64_t dif4:1; + uint64_t dif3:1; + uint64_t dif2:1; + uint64_t dif1:1; + uint64_t dif0:1; + uint64_t csm1:1; + uint64_t csm0:1; + uint64_t p2n1_p1:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_n:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_c0:1; + uint64_t p2n0_p1:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_n:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_c0:1; + uint64_t p2n0_co:1; + uint64_t p2n0_no:1; + uint64_t p2n0_po:1; + uint64_t p2n1_co:1; + uint64_t p2n1_no:1; + uint64_t p2n1_po:1; + uint64_t cpl_p1:1; + uint64_t cpl_p0:1; + uint64_t n2p1_o:1; + uint64_t n2p1_c:1; + uint64_t n2p0_o:1; + uint64_t n2p0_c:1; + uint64_t d4_pst:1; + uint64_t d3_pst:1; + uint64_t d2_pst:1; + uint64_t d1_pst:1; + uint64_t d0_pst:1; + uint64_t reserved_36_39:4; + uint64_t ds_mem:1; + uint64_t d4_mem:1; + uint64_t d3_mem:1; + uint64_t d2_mem:1; + uint64_t d1_mem:1; + uint64_t d0_mem:1; + uint64_t pkt_pop1:1; + uint64_t pkt_pop0:1; + uint64_t reserved_48_49:2; + uint64_t pkt_pof:1; + uint64_t pkt_pfm:1; + uint64_t pkt_imem:1; + uint64_t pcsr_sl:1; + uint64_t pcsr_id:1; + uint64_t pcsr_cnt:1; + uint64_t pcsr_im:1; + uint64_t pcsr_int:1; + uint64_t pkt_pif:1; + uint64_t pcr_gim:1; + uint64_t reserved_60_62:3; + uint64_t pkt_rdf:1; +#endif } cn52xx; struct cvmx_npei_bist_status_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_46_63:18; uint64_t d0_mem0:1; uint64_t d1_mem1:1; @@ -313,9 +435,59 @@ union cvmx_npei_bist_status { uint64_t dr3_mem:1; uint64_t msi:1; uint64_t ncb_cmd:1; +#else + uint64_t ncb_cmd:1; + uint64_t msi:1; + uint64_t dr3_mem:1; + uint64_t dif3:1; + uint64_t dif2:1; + uint64_t dif1:1; + uint64_t dif0:1; + uint64_t csm1:1; + uint64_t csm0:1; + uint64_t p2n1_p1:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_n:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_c0:1; + uint64_t p2n0_p1:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_n:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_c0:1; + uint64_t p2n0_co:1; + uint64_t p2n0_no:1; + uint64_t p2n0_po:1; + uint64_t p2n1_co:1; + uint64_t p2n1_no:1; + uint64_t p2n1_po:1; + uint64_t cpl_p1:1; + uint64_t cpl_p0:1; + uint64_t n2p1_o:1; + uint64_t n2p1_c:1; + uint64_t n2p0_o:1; + uint64_t n2p0_c:1; + uint64_t dr2_mem:1; + uint64_t d3_pst:1; + uint64_t d2_pst:1; + uint64_t d1_pst:1; + uint64_t d0_pst:1; + uint64_t dr1_mem:1; + uint64_t d3_mem:1; + uint64_t d2_mem:1; + uint64_t d1_mem:1; + uint64_t d0_mem:1; + uint64_t dr0_mem:1; + uint64_t d3_mem3:1; + uint64_t d2_mem2:1; + uint64_t d1_mem1:1; + uint64_t d0_mem0:1; + uint64_t reserved_46_63:18; +#endif } cn52xxp1; struct cvmx_npei_bist_status_cn52xx cn56xx; struct cvmx_npei_bist_status_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t pcsr_int:1; uint64_t pcsr_im:1; @@ -375,12 +547,74 @@ union cvmx_npei_bist_status { uint64_t dif4:1; uint64_t msi:1; uint64_t ncb_cmd:1; +#else + uint64_t ncb_cmd:1; + uint64_t msi:1; + uint64_t dif4:1; + uint64_t dif3:1; + uint64_t dif2:1; + uint64_t dif1:1; + uint64_t dif0:1; + uint64_t csm1:1; + uint64_t csm0:1; + uint64_t p2n1_p1:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_n:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_c0:1; + uint64_t p2n0_p1:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_n:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_c0:1; + uint64_t p2n0_co:1; + uint64_t p2n0_no:1; + uint64_t p2n0_po:1; + uint64_t p2n1_co:1; + uint64_t p2n1_no:1; + uint64_t p2n1_po:1; + uint64_t cpl_p1:1; + uint64_t cpl_p0:1; + uint64_t n2p1_o:1; + uint64_t n2p1_c:1; + uint64_t n2p0_o:1; + uint64_t n2p0_c:1; + uint64_t d4_pst:1; + uint64_t d3_pst:1; + uint64_t d2_pst:1; + uint64_t d1_pst:1; + uint64_t d0_pst:1; + uint64_t d4_mem:1; + uint64_t d3_mem:1; + uint64_t d2_mem:1; + uint64_t d1_mem:1; + uint64_t d0_mem:1; + uint64_t pkt_s1:1; + uint64_t pkt_s0:1; + uint64_t pkt_i1:1; + uint64_t pkt_i0:1; + uint64_t pkt_out:1; + uint64_t pkt_oif:1; + uint64_t pkt_odf:1; + uint64_t pkt_slm:1; + uint64_t pkt_ind:1; + uint64_t pkt_cntm:1; + uint64_t pkt_imem:1; + uint64_t pkt_pout:1; + uint64_t pcsr_sl:1; + uint64_t pcsr_id:1; + uint64_t pcsr_cnt:1; + uint64_t pcsr_im:1; + uint64_t pcsr_int:1; + uint64_t reserved_58_63:6; +#endif } cn56xxp1; }; union cvmx_npei_bist_status2 { uint64_t u64; struct cvmx_npei_bist_status2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t prd_tag:1; uint64_t prd_st0:1; @@ -396,6 +630,23 @@ union cvmx_npei_bist_status2 { uint64_t pkt_gd:1; uint64_t pkt_gl:1; uint64_t pkt_blk:1; +#else + uint64_t pkt_blk:1; + uint64_t pkt_gl:1; + uint64_t pkt_gd:1; + uint64_t psc_p1:1; + uint64_t psc_p0:1; + uint64_t pkt_rd:1; + uint64_t nwe_wr1:1; + uint64_t nwe_wr0:1; + uint64_t nwe_st:1; + uint64_t nrd_st:1; + uint64_t prd_err:1; + uint64_t prd_st1:1; + uint64_t prd_st0:1; + uint64_t prd_tag:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_npei_bist_status2_s cn52xx; struct cvmx_npei_bist_status2_s cn56xx; @@ -404,6 +655,7 @@ union cvmx_npei_bist_status2 { union cvmx_npei_ctl_port0 { uint64_t u64; struct cvmx_npei_ctl_port0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t waitl_com:1; uint64_t intd:1; @@ -421,6 +673,25 @@ union cvmx_npei_ctl_port0 { uint64_t bar2_esx:2; uint64_t bar2_cax:1; uint64_t wait_com:1; +#else + uint64_t wait_com:1; + uint64_t bar2_cax:1; + uint64_t bar2_esx:2; + uint64_t bar2_enb:1; + uint64_t ptlp_ro:1; + uint64_t reserved_6_6:1; + uint64_t ctlp_ro:1; + uint64_t inta_map:2; + uint64_t intb_map:2; + uint64_t intc_map:2; + uint64_t intd_map:2; + uint64_t inta:1; + uint64_t intb:1; + uint64_t intc:1; + uint64_t intd:1; + uint64_t waitl_com:1; + uint64_t reserved_21_63:43; +#endif } s; struct cvmx_npei_ctl_port0_s cn52xx; struct cvmx_npei_ctl_port0_s cn52xxp1; @@ -431,6 +702,7 @@ union cvmx_npei_ctl_port0 { union cvmx_npei_ctl_port1 { uint64_t u64; struct cvmx_npei_ctl_port1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t waitl_com:1; uint64_t intd:1; @@ -448,6 +720,25 @@ union cvmx_npei_ctl_port1 { uint64_t bar2_esx:2; uint64_t bar2_cax:1; uint64_t wait_com:1; +#else + uint64_t wait_com:1; + uint64_t bar2_cax:1; + uint64_t bar2_esx:2; + uint64_t bar2_enb:1; + uint64_t ptlp_ro:1; + uint64_t reserved_6_6:1; + uint64_t ctlp_ro:1; + uint64_t inta_map:2; + uint64_t intb_map:2; + uint64_t intc_map:2; + uint64_t intd_map:2; + uint64_t inta:1; + uint64_t intb:1; + uint64_t intc:1; + uint64_t intd:1; + uint64_t waitl_com:1; + uint64_t reserved_21_63:43; +#endif } s; struct cvmx_npei_ctl_port1_s cn52xx; struct cvmx_npei_ctl_port1_s cn52xxp1; @@ -458,6 +749,7 @@ union cvmx_npei_ctl_port1 { union cvmx_npei_ctl_status { uint64_t u64; struct cvmx_npei_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t p1_ntags:6; uint64_t p0_ntags:6; @@ -468,9 +760,22 @@ union cvmx_npei_ctl_status { uint64_t pkt_bp:4; uint64_t host_mode:1; uint64_t chip_rev:8; +#else + uint64_t chip_rev:8; + uint64_t host_mode:1; + uint64_t pkt_bp:4; + uint64_t arb:1; + uint64_t lnk_rst:1; + uint64_t ring_en:1; + uint64_t cfg_rtry:16; + uint64_t p0_ntags:6; + uint64_t p1_ntags:6; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_npei_ctl_status_s cn52xx; struct cvmx_npei_ctl_status_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t p1_ntags:6; uint64_t p0_ntags:6; @@ -481,21 +786,43 @@ union cvmx_npei_ctl_status { uint64_t reserved_9_12:4; uint64_t host_mode:1; uint64_t chip_rev:8; +#else + uint64_t chip_rev:8; + uint64_t host_mode:1; + uint64_t reserved_9_12:4; + uint64_t arb:1; + uint64_t lnk_rst:1; + uint64_t reserved_15_15:1; + uint64_t cfg_rtry:16; + uint64_t p0_ntags:6; + uint64_t p1_ntags:6; + uint64_t reserved_44_63:20; +#endif } cn52xxp1; struct cvmx_npei_ctl_status_s cn56xx; struct cvmx_npei_ctl_status_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t lnk_rst:1; uint64_t arb:1; uint64_t pkt_bp:4; uint64_t host_mode:1; uint64_t chip_rev:8; +#else + uint64_t chip_rev:8; + uint64_t host_mode:1; + uint64_t pkt_bp:4; + uint64_t arb:1; + uint64_t lnk_rst:1; + uint64_t reserved_15_63:49; +#endif } cn56xxp1; }; union cvmx_npei_ctl_status2 { uint64_t u64; struct cvmx_npei_ctl_status2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mps:1; uint64_t mrrs:3; @@ -507,6 +834,19 @@ union cvmx_npei_ctl_status2 { uint64_t c1_b0_d:1; uint64_t c0_wi_d:1; uint64_t c0_b0_d:1; +#else + uint64_t c0_b0_d:1; + uint64_t c0_wi_d:1; + uint64_t c1_b0_d:1; + uint64_t c1_wi_d:1; + uint64_t c0_b1_s:3; + uint64_t c1_b1_s:3; + uint64_t c0_w_flt:1; + uint64_t c1_w_flt:1; + uint64_t mrrs:3; + uint64_t mps:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npei_ctl_status2_s cn52xx; struct cvmx_npei_ctl_status2_s cn52xxp1; @@ -517,11 +857,19 @@ union cvmx_npei_ctl_status2 { union cvmx_npei_data_out_cnt { uint64_t u64; struct cvmx_npei_data_out_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t p1_ucnt:16; uint64_t p1_fcnt:6; uint64_t p0_ucnt:16; uint64_t p0_fcnt:6; +#else + uint64_t p0_fcnt:6; + uint64_t p0_ucnt:16; + uint64_t p1_fcnt:6; + uint64_t p1_ucnt:16; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_npei_data_out_cnt_s cn52xx; struct cvmx_npei_data_out_cnt_s cn52xxp1; @@ -532,6 +880,7 @@ union cvmx_npei_data_out_cnt { union cvmx_npei_dbg_data { uint64_t u64; struct cvmx_npei_dbg_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t qlm0_rev_lanes:1; uint64_t reserved_25_26:2; @@ -539,8 +888,18 @@ union cvmx_npei_dbg_data { uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t c_mul:5; + uint64_t qlm1_spd:2; + uint64_t reserved_25_26:2; + uint64_t qlm0_rev_lanes:1; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_npei_dbg_data_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t qlm0_link_width:1; uint64_t qlm0_rev_lanes:1; @@ -549,9 +908,20 @@ union cvmx_npei_dbg_data { uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t c_mul:5; + uint64_t qlm1_spd:2; + uint64_t qlm1_mode:2; + uint64_t qlm0_rev_lanes:1; + uint64_t qlm0_link_width:1; + uint64_t reserved_29_63:35; +#endif } cn52xx; struct cvmx_npei_dbg_data_cn52xx cn52xxp1; struct cvmx_npei_dbg_data_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t qlm2_rev_lanes:1; uint64_t qlm0_rev_lanes:1; @@ -560,6 +930,16 @@ union cvmx_npei_dbg_data { uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t c_mul:5; + uint64_t qlm1_spd:2; + uint64_t qlm3_spd:2; + uint64_t qlm0_rev_lanes:1; + uint64_t qlm2_rev_lanes:1; + uint64_t reserved_29_63:35; +#endif } cn56xx; struct cvmx_npei_dbg_data_cn56xx cn56xxp1; }; @@ -567,8 +947,13 @@ union cvmx_npei_dbg_data { union cvmx_npei_dbg_select { uint64_t u64; struct cvmx_npei_dbg_select_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dbg_sel:16; +#else + uint64_t dbg_sel:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npei_dbg_select_s cn52xx; struct cvmx_npei_dbg_select_s cn52xxp1; @@ -579,9 +964,15 @@ union cvmx_npei_dbg_select { union cvmx_npei_dmax_counts { uint64_t u64; struct cvmx_npei_dmax_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t fcnt:7; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t fcnt:7; + uint64_t reserved_39_63:25; +#endif } s; struct cvmx_npei_dmax_counts_s cn52xx; struct cvmx_npei_dmax_counts_s cn52xxp1; @@ -592,8 +983,13 @@ union cvmx_npei_dmax_counts { union cvmx_npei_dmax_dbell { uint32_t u32; struct cvmx_npei_dmax_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_16_31:16; uint32_t dbell:16; +#else + uint32_t dbell:16; + uint32_t reserved_16_31:16; +#endif } s; struct cvmx_npei_dmax_dbell_s cn52xx; struct cvmx_npei_dmax_dbell_s cn52xxp1; @@ -604,16 +1000,29 @@ union cvmx_npei_dmax_dbell { union cvmx_npei_dmax_ibuff_saddr { uint64_t u64; struct cvmx_npei_dmax_ibuff_saddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t idle:1; uint64_t saddr:29; uint64_t reserved_0_6:7; +#else + uint64_t reserved_0_6:7; + uint64_t saddr:29; + uint64_t idle:1; + uint64_t reserved_37_63:27; +#endif } s; struct cvmx_npei_dmax_ibuff_saddr_s cn52xx; struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t saddr:29; uint64_t reserved_0_6:7; +#else + uint64_t reserved_0_6:7; + uint64_t saddr:29; + uint64_t reserved_36_63:28; +#endif } cn52xxp1; struct cvmx_npei_dmax_ibuff_saddr_s cn56xx; struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1; @@ -622,8 +1031,13 @@ union cvmx_npei_dmax_ibuff_saddr { union cvmx_npei_dmax_naddr { uint64_t u64; struct cvmx_npei_dmax_naddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t addr:36; +#else + uint64_t addr:36; + uint64_t reserved_36_63:28; +#endif } s; struct cvmx_npei_dmax_naddr_s cn52xx; struct cvmx_npei_dmax_naddr_s cn52xxp1; @@ -634,8 +1048,13 @@ union cvmx_npei_dmax_naddr { union cvmx_npei_dma0_int_level { uint64_t u64; struct cvmx_npei_dma0_int_level_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t time:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t time:32; +#endif } s; struct cvmx_npei_dma0_int_level_s cn52xx; struct cvmx_npei_dma0_int_level_s cn52xxp1; @@ -646,8 +1065,13 @@ union cvmx_npei_dma0_int_level { union cvmx_npei_dma1_int_level { uint64_t u64; struct cvmx_npei_dma1_int_level_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t time:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t time:32; +#endif } s; struct cvmx_npei_dma1_int_level_s cn52xx; struct cvmx_npei_dma1_int_level_s cn52xxp1; @@ -658,8 +1082,13 @@ union cvmx_npei_dma1_int_level { union cvmx_npei_dma_cnts { uint64_t u64; struct cvmx_npei_dma_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dma1:32; uint64_t dma0:32; +#else + uint64_t dma0:32; + uint64_t dma1:32; +#endif } s; struct cvmx_npei_dma_cnts_s cn52xx; struct cvmx_npei_dma_cnts_s cn52xxp1; @@ -670,6 +1099,7 @@ union cvmx_npei_dma_cnts { union cvmx_npei_dma_control { uint64_t u64; struct cvmx_npei_dma_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t p_32b_m:1; uint64_t dma4_enb:1; @@ -687,9 +1117,29 @@ union cvmx_npei_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t csize:14; +#else + uint64_t csize:14; + uint64_t o_mode:1; + uint64_t o_es:2; + uint64_t o_ns:1; + uint64_t o_ro:1; + uint64_t o_add1:1; + uint64_t fpa_que:3; + uint64_t dwb_ichk:9; + uint64_t dwb_denb:1; + uint64_t b0_lend:1; + uint64_t dma0_enb:1; + uint64_t dma1_enb:1; + uint64_t dma2_enb:1; + uint64_t dma3_enb:1; + uint64_t dma4_enb:1; + uint64_t p_32b_m:1; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_npei_dma_control_s cn52xx; struct cvmx_npei_dma_control_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t dma3_enb:1; uint64_t dma2_enb:1; @@ -705,9 +1155,27 @@ union cvmx_npei_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t csize:14; +#else + uint64_t csize:14; + uint64_t o_mode:1; + uint64_t o_es:2; + uint64_t o_ns:1; + uint64_t o_ro:1; + uint64_t o_add1:1; + uint64_t fpa_que:3; + uint64_t dwb_ichk:9; + uint64_t dwb_denb:1; + uint64_t b0_lend:1; + uint64_t dma0_enb:1; + uint64_t dma1_enb:1; + uint64_t dma2_enb:1; + uint64_t dma3_enb:1; + uint64_t reserved_38_63:26; +#endif } cn52xxp1; struct cvmx_npei_dma_control_s cn56xx; struct cvmx_npei_dma_control_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t dma4_enb:1; uint64_t dma3_enb:1; @@ -724,12 +1192,31 @@ union cvmx_npei_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t csize:14; +#else + uint64_t csize:14; + uint64_t o_mode:1; + uint64_t o_es:2; + uint64_t o_ns:1; + uint64_t o_ro:1; + uint64_t o_add1:1; + uint64_t fpa_que:3; + uint64_t dwb_ichk:9; + uint64_t dwb_denb:1; + uint64_t b0_lend:1; + uint64_t dma0_enb:1; + uint64_t dma1_enb:1; + uint64_t dma2_enb:1; + uint64_t dma3_enb:1; + uint64_t dma4_enb:1; + uint64_t reserved_39_63:25; +#endif } cn56xxp1; }; union cvmx_npei_dma_pcie_req_num { uint64_t u64; struct cvmx_npei_dma_pcie_req_num_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dma_arb:1; uint64_t reserved_53_62:10; uint64_t pkt_cnt:5; @@ -745,6 +1232,23 @@ union cvmx_npei_dma_pcie_req_num { uint64_t dma0_cnt:5; uint64_t reserved_5_7:3; uint64_t dma_cnt:5; +#else + uint64_t dma_cnt:5; + uint64_t reserved_5_7:3; + uint64_t dma0_cnt:5; + uint64_t reserved_13_15:3; + uint64_t dma1_cnt:5; + uint64_t reserved_21_23:3; + uint64_t dma2_cnt:5; + uint64_t reserved_29_31:3; + uint64_t dma3_cnt:5; + uint64_t reserved_37_39:3; + uint64_t dma4_cnt:5; + uint64_t reserved_45_47:3; + uint64_t pkt_cnt:5; + uint64_t reserved_53_62:10; + uint64_t dma_arb:1; +#endif } s; struct cvmx_npei_dma_pcie_req_num_s cn52xx; struct cvmx_npei_dma_pcie_req_num_s cn56xx; @@ -753,12 +1257,21 @@ union cvmx_npei_dma_pcie_req_num { union cvmx_npei_dma_state1 { uint64_t u64; struct cvmx_npei_dma_state1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t d4_dwe:8; uint64_t d3_dwe:8; uint64_t d2_dwe:8; uint64_t d1_dwe:8; uint64_t d0_dwe:8; +#else + uint64_t d0_dwe:8; + uint64_t d1_dwe:8; + uint64_t d2_dwe:8; + uint64_t d3_dwe:8; + uint64_t d4_dwe:8; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_npei_dma_state1_s cn52xx; }; @@ -766,6 +1279,7 @@ union cvmx_npei_dma_state1 { union cvmx_npei_dma_state1_p1 { uint64_t u64; struct cvmx_npei_dma_state1_p1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t d0_difst:7; uint64_t d1_difst:7; @@ -777,8 +1291,22 @@ union cvmx_npei_dma_state1_p1 { uint64_t d2_reqst:5; uint64_t d3_reqst:5; uint64_t d4_reqst:5; +#else + uint64_t d4_reqst:5; + uint64_t d3_reqst:5; + uint64_t d2_reqst:5; + uint64_t d1_reqst:5; + uint64_t d0_reqst:5; + uint64_t d4_difst:7; + uint64_t d3_difst:7; + uint64_t d2_difst:7; + uint64_t d1_difst:7; + uint64_t d0_difst:7; + uint64_t reserved_60_63:4; +#endif } s; struct cvmx_npei_dma_state1_p1_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t d0_difst:7; uint64_t d1_difst:7; @@ -790,6 +1318,19 @@ union cvmx_npei_dma_state1_p1 { uint64_t d2_reqst:5; uint64_t d3_reqst:5; uint64_t reserved_0_4:5; +#else + uint64_t reserved_0_4:5; + uint64_t d3_reqst:5; + uint64_t d2_reqst:5; + uint64_t d1_reqst:5; + uint64_t d0_reqst:5; + uint64_t reserved_25_31:7; + uint64_t d3_difst:7; + uint64_t d2_difst:7; + uint64_t d1_difst:7; + uint64_t d0_difst:7; + uint64_t reserved_60_63:4; +#endif } cn52xxp1; struct cvmx_npei_dma_state1_p1_s cn56xxp1; }; @@ -797,12 +1338,21 @@ union cvmx_npei_dma_state1_p1 { union cvmx_npei_dma_state2 { uint64_t u64; struct cvmx_npei_dma_state2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t ndwe:4; uint64_t reserved_21_23:3; uint64_t ndre:5; uint64_t reserved_10_15:6; uint64_t prd:10; +#else + uint64_t prd:10; + uint64_t reserved_10_15:6; + uint64_t ndre:5; + uint64_t reserved_21_23:3; + uint64_t ndwe:4; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_npei_dma_state2_s cn52xx; }; @@ -810,20 +1360,38 @@ union cvmx_npei_dma_state2 { union cvmx_npei_dma_state2_p1 { uint64_t u64; struct cvmx_npei_dma_state2_p1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t d0_dffst:9; uint64_t d1_dffst:9; uint64_t d2_dffst:9; uint64_t d3_dffst:9; uint64_t d4_dffst:9; +#else + uint64_t d4_dffst:9; + uint64_t d3_dffst:9; + uint64_t d2_dffst:9; + uint64_t d1_dffst:9; + uint64_t d0_dffst:9; + uint64_t reserved_45_63:19; +#endif } s; struct cvmx_npei_dma_state2_p1_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t d0_dffst:9; uint64_t d1_dffst:9; uint64_t d2_dffst:9; uint64_t d3_dffst:9; uint64_t reserved_0_8:9; +#else + uint64_t reserved_0_8:9; + uint64_t d3_dffst:9; + uint64_t d2_dffst:9; + uint64_t d1_dffst:9; + uint64_t d0_dffst:9; + uint64_t reserved_45_63:19; +#endif } cn52xxp1; struct cvmx_npei_dma_state2_p1_s cn56xxp1; }; @@ -831,11 +1399,19 @@ union cvmx_npei_dma_state2_p1 { union cvmx_npei_dma_state3_p1 { uint64_t u64; struct cvmx_npei_dma_state3_p1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t d0_drest:15; uint64_t d1_drest:15; uint64_t d2_drest:15; uint64_t d3_drest:15; +#else + uint64_t d3_drest:15; + uint64_t d2_drest:15; + uint64_t d1_drest:15; + uint64_t d0_drest:15; + uint64_t reserved_60_63:4; +#endif } s; struct cvmx_npei_dma_state3_p1_s cn52xxp1; struct cvmx_npei_dma_state3_p1_s cn56xxp1; @@ -844,11 +1420,19 @@ union cvmx_npei_dma_state3_p1 { union cvmx_npei_dma_state4_p1 { uint64_t u64; struct cvmx_npei_dma_state4_p1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_52_63:12; uint64_t d0_dwest:13; uint64_t d1_dwest:13; uint64_t d2_dwest:13; uint64_t d3_dwest:13; +#else + uint64_t d3_dwest:13; + uint64_t d2_dwest:13; + uint64_t d1_dwest:13; + uint64_t d0_dwest:13; + uint64_t reserved_52_63:12; +#endif } s; struct cvmx_npei_dma_state4_p1_s cn52xxp1; struct cvmx_npei_dma_state4_p1_s cn56xxp1; @@ -857,9 +1441,15 @@ union cvmx_npei_dma_state4_p1 { union cvmx_npei_dma_state5_p1 { uint64_t u64; struct cvmx_npei_dma_state5_p1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t d4_drest:15; uint64_t d4_dwest:13; +#else + uint64_t d4_dwest:13; + uint64_t d4_drest:15; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_npei_dma_state5_p1_s cn56xxp1; }; @@ -867,6 +1457,7 @@ union cvmx_npei_dma_state5_p1 { union cvmx_npei_int_a_enb { uint64_t u64; struct cvmx_npei_int_a_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pout_err:1; uint64_t pin_bp:1; @@ -878,12 +1469,31 @@ union cvmx_npei_int_a_enb { uint64_t pins_err:1; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; +#else + uint64_t dma0_cpl:1; + uint64_t dma1_cpl:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t p0_rdlk:1; + uint64_t p1_rdlk:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_npei_int_a_enb_s cn52xx; struct cvmx_npei_int_a_enb_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; +#else + uint64_t dma0_cpl:1; + uint64_t dma1_cpl:1; + uint64_t reserved_2_63:62; +#endif } cn52xxp1; struct cvmx_npei_int_a_enb_s cn56xx; }; @@ -891,6 +1501,7 @@ union cvmx_npei_int_a_enb { union cvmx_npei_int_a_enb2 { uint64_t u64; struct cvmx_npei_int_a_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pout_err:1; uint64_t pin_bp:1; @@ -902,12 +1513,31 @@ union cvmx_npei_int_a_enb2 { uint64_t pins_err:1; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; +#else + uint64_t dma0_cpl:1; + uint64_t dma1_cpl:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t p0_rdlk:1; + uint64_t p1_rdlk:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_npei_int_a_enb2_s cn52xx; struct cvmx_npei_int_a_enb2_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; +#else + uint64_t dma0_cpl:1; + uint64_t dma1_cpl:1; + uint64_t reserved_2_63:62; +#endif } cn52xxp1; struct cvmx_npei_int_a_enb2_s cn56xx; }; @@ -915,6 +1545,7 @@ union cvmx_npei_int_a_enb2 { union cvmx_npei_int_a_sum { uint64_t u64; struct cvmx_npei_int_a_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pout_err:1; uint64_t pin_bp:1; @@ -926,12 +1557,31 @@ union cvmx_npei_int_a_sum { uint64_t pins_err:1; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; +#else + uint64_t dma0_cpl:1; + uint64_t dma1_cpl:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t p0_rdlk:1; + uint64_t p1_rdlk:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_npei_int_a_sum_s cn52xx; struct cvmx_npei_int_a_sum_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; +#else + uint64_t dma0_cpl:1; + uint64_t dma1_cpl:1; + uint64_t reserved_2_63:62; +#endif } cn52xxp1; struct cvmx_npei_int_a_sum_s cn56xx; }; @@ -939,6 +1589,7 @@ union cvmx_npei_int_a_sum { union cvmx_npei_int_enb { uint64_t u64; struct cvmx_npei_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_62_62:1; uint64_t int_a:1; @@ -1003,9 +1654,76 @@ union cvmx_npei_int_enb { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t dma4dbo:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t c0_aeri:1; + uint64_t crs0_er:1; + uint64_t c0_se:1; + uint64_t crs0_dr:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t crs1_er:1; + uint64_t c1_se:1; + uint64_t crs1_dr:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t int_a:1; + uint64_t reserved_62_62:1; + uint64_t mio_inta:1; +#endif } s; struct cvmx_npei_int_enb_s cn52xx; struct cvmx_npei_int_enb_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_62_62:1; uint64_t int_a:1; @@ -1070,9 +1788,76 @@ union cvmx_npei_int_enb { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t reserved_8_8:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t c0_aeri:1; + uint64_t crs0_er:1; + uint64_t c0_se:1; + uint64_t crs0_dr:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t crs1_er:1; + uint64_t c1_se:1; + uint64_t crs1_dr:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t int_a:1; + uint64_t reserved_62_62:1; + uint64_t mio_inta:1; +#endif } cn52xxp1; struct cvmx_npei_int_enb_s cn56xx; struct cvmx_npei_int_enb_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_61_62:2; uint64_t c1_ldwn:1; @@ -1136,12 +1921,78 @@ union cvmx_npei_int_enb { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t dma4dbo:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t c0_aeri:1; + uint64_t reserved_20_20:1; + uint64_t c0_se:1; + uint64_t reserved_22_22:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t reserved_27_27:1; + uint64_t c1_se:1; + uint64_t reserved_29_29:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t reserved_61_62:2; + uint64_t mio_inta:1; +#endif } cn56xxp1; }; union cvmx_npei_int_enb2 { uint64_t u64; struct cvmx_npei_int_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t int_a:1; uint64_t c1_ldwn:1; @@ -1205,9 +2056,75 @@ union cvmx_npei_int_enb2 { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t dma4dbo:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t c0_aeri:1; + uint64_t crs0_er:1; + uint64_t c0_se:1; + uint64_t crs0_dr:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t crs1_er:1; + uint64_t c1_se:1; + uint64_t crs1_dr:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t int_a:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_npei_int_enb2_s cn52xx; struct cvmx_npei_int_enb2_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t int_a:1; uint64_t c1_ldwn:1; @@ -1271,9 +2188,75 @@ union cvmx_npei_int_enb2 { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t reserved_8_8:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t c0_aeri:1; + uint64_t crs0_er:1; + uint64_t c0_se:1; + uint64_t crs0_dr:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t crs1_er:1; + uint64_t c1_se:1; + uint64_t crs1_dr:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t int_a:1; + uint64_t reserved_62_63:2; +#endif } cn52xxp1; struct cvmx_npei_int_enb2_s cn56xx; struct cvmx_npei_int_enb2_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t c1_ldwn:1; uint64_t c0_ldwn:1; @@ -1336,15 +2319,85 @@ union cvmx_npei_int_enb2 { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t dma4dbo:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t c0_aeri:1; + uint64_t reserved_20_20:1; + uint64_t c0_se:1; + uint64_t reserved_22_22:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t reserved_27_27:1; + uint64_t c1_se:1; + uint64_t reserved_29_29:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t reserved_61_63:3; +#endif } cn56xxp1; }; union cvmx_npei_int_info { uint64_t u64; struct cvmx_npei_int_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t pidbof:6; uint64_t psldbof:6; +#else + uint64_t psldbof:6; + uint64_t pidbof:6; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_npei_int_info_s cn52xx; struct cvmx_npei_int_info_s cn56xx; @@ -1354,6 +2407,7 @@ union cvmx_npei_int_info { union cvmx_npei_int_sum { uint64_t u64; struct cvmx_npei_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_62_62:1; uint64_t int_a:1; @@ -1418,9 +2472,76 @@ union cvmx_npei_int_sum { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t dma4dbo:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t c0_aeri:1; + uint64_t crs0_er:1; + uint64_t c0_se:1; + uint64_t crs0_dr:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t crs1_er:1; + uint64_t c1_se:1; + uint64_t crs1_dr:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t int_a:1; + uint64_t reserved_62_62:1; + uint64_t mio_inta:1; +#endif } s; struct cvmx_npei_int_sum_s cn52xx; struct cvmx_npei_int_sum_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_62_62:1; uint64_t int_a:1; @@ -1482,9 +2603,73 @@ union cvmx_npei_int_sum { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t reserved_8_8:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t reserved_15_18:4; + uint64_t c0_aeri:1; + uint64_t crs0_er:1; + uint64_t c0_se:1; + uint64_t crs0_dr:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t crs1_er:1; + uint64_t c1_se:1; + uint64_t crs1_dr:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t int_a:1; + uint64_t reserved_62_62:1; + uint64_t mio_inta:1; +#endif } cn52xxp1; struct cvmx_npei_int_sum_s cn56xx; struct cvmx_npei_int_sum_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_61_62:2; uint64_t c1_ldwn:1; @@ -1545,12 +2730,75 @@ union cvmx_npei_int_sum { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t dma4dbo:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t reserved_15_18:4; + uint64_t c0_aeri:1; + uint64_t reserved_20_20:1; + uint64_t c0_se:1; + uint64_t reserved_22_22:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t reserved_27_27:1; + uint64_t c1_se:1; + uint64_t reserved_29_29:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t reserved_61_62:2; + uint64_t mio_inta:1; +#endif } cn56xxp1; }; union cvmx_npei_int_sum2 { uint64_t u64; struct cvmx_npei_int_sum2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_62_62:1; uint64_t int_a:1; @@ -1612,6 +2860,69 @@ union cvmx_npei_int_sum2 { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t reserved_8_8:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t reserved_15_18:4; + uint64_t c0_aeri:1; + uint64_t crs0_er:1; + uint64_t c0_se:1; + uint64_t crs0_dr:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t crs1_er:1; + uint64_t c1_se:1; + uint64_t crs1_dr:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t int_a:1; + uint64_t reserved_62_62:1; + uint64_t mio_inta:1; +#endif } s; struct cvmx_npei_int_sum2_s cn52xx; struct cvmx_npei_int_sum2_s cn52xxp1; @@ -1621,7 +2932,11 @@ union cvmx_npei_int_sum2 { union cvmx_npei_last_win_rdata0 { uint64_t u64; struct cvmx_npei_last_win_rdata0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; +#else + uint64_t data:64; +#endif } s; struct cvmx_npei_last_win_rdata0_s cn52xx; struct cvmx_npei_last_win_rdata0_s cn52xxp1; @@ -1632,7 +2947,11 @@ union cvmx_npei_last_win_rdata0 { union cvmx_npei_last_win_rdata1 { uint64_t u64; struct cvmx_npei_last_win_rdata1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_npei_last_win_rdata1_s cn52xx; struct cvmx_npei_last_win_rdata1_s cn52xxp1; @@ -1643,9 +2962,15 @@ union cvmx_npei_last_win_rdata1 { union cvmx_npei_mem_access_ctl { uint64_t u64; struct cvmx_npei_mem_access_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t max_word:4; uint64_t timer:10; +#else + uint64_t timer:10; + uint64_t max_word:4; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_npei_mem_access_ctl_s cn52xx; struct cvmx_npei_mem_access_ctl_s cn52xxp1; @@ -1656,6 +2981,7 @@ union cvmx_npei_mem_access_ctl { union cvmx_npei_mem_access_subidx { uint64_t u64; struct cvmx_npei_mem_access_subidx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t zero:1; uint64_t port:2; @@ -1667,6 +2993,19 @@ union cvmx_npei_mem_access_subidx { uint64_t ror:1; uint64_t row:1; uint64_t ba:30; +#else + uint64_t ba:30; + uint64_t row:1; + uint64_t ror:1; + uint64_t nsw:1; + uint64_t nsr:1; + uint64_t esw:2; + uint64_t esr:2; + uint64_t nmerge:1; + uint64_t port:2; + uint64_t zero:1; + uint64_t reserved_42_63:22; +#endif } s; struct cvmx_npei_mem_access_subidx_s cn52xx; struct cvmx_npei_mem_access_subidx_s cn52xxp1; @@ -1677,7 +3016,11 @@ union cvmx_npei_mem_access_subidx { union cvmx_npei_msi_enb0 { uint64_t u64; struct cvmx_npei_msi_enb0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t enb:64; +#else + uint64_t enb:64; +#endif } s; struct cvmx_npei_msi_enb0_s cn52xx; struct cvmx_npei_msi_enb0_s cn52xxp1; @@ -1688,7 +3031,11 @@ union cvmx_npei_msi_enb0 { union cvmx_npei_msi_enb1 { uint64_t u64; struct cvmx_npei_msi_enb1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t enb:64; +#else uint64_t enb:64; +#endif } s; struct cvmx_npei_msi_enb1_s cn52xx; struct cvmx_npei_msi_enb1_s cn52xxp1; @@ -1699,7 +3046,11 @@ union cvmx_npei_msi_enb1 { union cvmx_npei_msi_enb2 { uint64_t u64; struct cvmx_npei_msi_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t enb:64; +#else uint64_t enb:64; +#endif } s; struct cvmx_npei_msi_enb2_s cn52xx; struct cvmx_npei_msi_enb2_s cn52xxp1; @@ -1710,7 +3061,11 @@ union cvmx_npei_msi_enb2 { union cvmx_npei_msi_enb3 { uint64_t u64; struct cvmx_npei_msi_enb3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t enb:64; +#else + uint64_t enb:64; +#endif } s; struct cvmx_npei_msi_enb3_s cn52xx; struct cvmx_npei_msi_enb3_s cn52xxp1; @@ -1721,7 +3076,11 @@ union cvmx_npei_msi_enb3 { union cvmx_npei_msi_rcv0 { uint64_t u64; struct cvmx_npei_msi_rcv0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t intr:64; +#else + uint64_t intr:64; +#endif } s; struct cvmx_npei_msi_rcv0_s cn52xx; struct cvmx_npei_msi_rcv0_s cn52xxp1; @@ -1732,7 +3091,11 @@ union cvmx_npei_msi_rcv0 { union cvmx_npei_msi_rcv1 { uint64_t u64; struct cvmx_npei_msi_rcv1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t intr:64; +#else uint64_t intr:64; +#endif } s; struct cvmx_npei_msi_rcv1_s cn52xx; struct cvmx_npei_msi_rcv1_s cn52xxp1; @@ -1743,7 +3106,11 @@ union cvmx_npei_msi_rcv1 { union cvmx_npei_msi_rcv2 { uint64_t u64; struct cvmx_npei_msi_rcv2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t intr:64; +#else uint64_t intr:64; +#endif } s; struct cvmx_npei_msi_rcv2_s cn52xx; struct cvmx_npei_msi_rcv2_s cn52xxp1; @@ -1754,7 +3121,11 @@ union cvmx_npei_msi_rcv2 { union cvmx_npei_msi_rcv3 { uint64_t u64; struct cvmx_npei_msi_rcv3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t intr:64; +#else + uint64_t intr:64; +#endif } s; struct cvmx_npei_msi_rcv3_s cn52xx; struct cvmx_npei_msi_rcv3_s cn52xxp1; @@ -1765,9 +3136,15 @@ union cvmx_npei_msi_rcv3 { union cvmx_npei_msi_rd_map { uint64_t u64; struct cvmx_npei_msi_rd_map_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t rd_int:8; uint64_t msi_int:8; +#else + uint64_t msi_int:8; + uint64_t rd_int:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npei_msi_rd_map_s cn52xx; struct cvmx_npei_msi_rd_map_s cn52xxp1; @@ -1778,7 +3155,11 @@ union cvmx_npei_msi_rd_map { union cvmx_npei_msi_w1c_enb0 { uint64_t u64; struct cvmx_npei_msi_w1c_enb0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t clr:64; +#else + uint64_t clr:64; +#endif } s; struct cvmx_npei_msi_w1c_enb0_s cn52xx; struct cvmx_npei_msi_w1c_enb0_s cn56xx; @@ -1787,7 +3168,11 @@ union cvmx_npei_msi_w1c_enb0 { union cvmx_npei_msi_w1c_enb1 { uint64_t u64; struct cvmx_npei_msi_w1c_enb1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t clr:64; +#else uint64_t clr:64; +#endif } s; struct cvmx_npei_msi_w1c_enb1_s cn52xx; struct cvmx_npei_msi_w1c_enb1_s cn56xx; @@ -1796,7 +3181,11 @@ union cvmx_npei_msi_w1c_enb1 { union cvmx_npei_msi_w1c_enb2 { uint64_t u64; struct cvmx_npei_msi_w1c_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t clr:64; +#else uint64_t clr:64; +#endif } s; struct cvmx_npei_msi_w1c_enb2_s cn52xx; struct cvmx_npei_msi_w1c_enb2_s cn56xx; @@ -1805,7 +3194,11 @@ union cvmx_npei_msi_w1c_enb2 { union cvmx_npei_msi_w1c_enb3 { uint64_t u64; struct cvmx_npei_msi_w1c_enb3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t clr:64; +#else + uint64_t clr:64; +#endif } s; struct cvmx_npei_msi_w1c_enb3_s cn52xx; struct cvmx_npei_msi_w1c_enb3_s cn56xx; @@ -1814,7 +3207,11 @@ union cvmx_npei_msi_w1c_enb3 { union cvmx_npei_msi_w1s_enb0 { uint64_t u64; struct cvmx_npei_msi_w1s_enb0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t set:64; +#else uint64_t set:64; +#endif } s; struct cvmx_npei_msi_w1s_enb0_s cn52xx; struct cvmx_npei_msi_w1s_enb0_s cn56xx; @@ -1823,7 +3220,11 @@ union cvmx_npei_msi_w1s_enb0 { union cvmx_npei_msi_w1s_enb1 { uint64_t u64; struct cvmx_npei_msi_w1s_enb1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t set:64; +#else uint64_t set:64; +#endif } s; struct cvmx_npei_msi_w1s_enb1_s cn52xx; struct cvmx_npei_msi_w1s_enb1_s cn56xx; @@ -1832,7 +3233,11 @@ union cvmx_npei_msi_w1s_enb1 { union cvmx_npei_msi_w1s_enb2 { uint64_t u64; struct cvmx_npei_msi_w1s_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t set:64; +#else uint64_t set:64; +#endif } s; struct cvmx_npei_msi_w1s_enb2_s cn52xx; struct cvmx_npei_msi_w1s_enb2_s cn56xx; @@ -1841,7 +3246,11 @@ union cvmx_npei_msi_w1s_enb2 { union cvmx_npei_msi_w1s_enb3 { uint64_t u64; struct cvmx_npei_msi_w1s_enb3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t set:64; +#else + uint64_t set:64; +#endif } s; struct cvmx_npei_msi_w1s_enb3_s cn52xx; struct cvmx_npei_msi_w1s_enb3_s cn56xx; @@ -1850,9 +3259,15 @@ union cvmx_npei_msi_w1s_enb3 { union cvmx_npei_msi_wr_map { uint64_t u64; struct cvmx_npei_msi_wr_map_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ciu_int:8; uint64_t msi_int:8; +#else + uint64_t msi_int:8; + uint64_t ciu_int:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npei_msi_wr_map_s cn52xx; struct cvmx_npei_msi_wr_map_s cn52xxp1; @@ -1863,6 +3278,7 @@ union cvmx_npei_msi_wr_map { union cvmx_npei_pcie_credit_cnt { uint64_t u64; struct cvmx_npei_pcie_credit_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t p1_ccnt:8; uint64_t p1_ncnt:8; @@ -1870,6 +3286,15 @@ union cvmx_npei_pcie_credit_cnt { uint64_t p0_ccnt:8; uint64_t p0_ncnt:8; uint64_t p0_pcnt:8; +#else + uint64_t p0_pcnt:8; + uint64_t p0_ncnt:8; + uint64_t p0_ccnt:8; + uint64_t p1_pcnt:8; + uint64_t p1_ncnt:8; + uint64_t p1_ccnt:8; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_npei_pcie_credit_cnt_s cn52xx; struct cvmx_npei_pcie_credit_cnt_s cn56xx; @@ -1878,8 +3303,13 @@ union cvmx_npei_pcie_credit_cnt { union cvmx_npei_pcie_msi_rcv { uint64_t u64; struct cvmx_npei_pcie_msi_rcv_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t intr:8; +#else + uint64_t intr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_npei_pcie_msi_rcv_s cn52xx; struct cvmx_npei_pcie_msi_rcv_s cn52xxp1; @@ -1890,9 +3320,15 @@ union cvmx_npei_pcie_msi_rcv { union cvmx_npei_pcie_msi_rcv_b1 { uint64_t u64; struct cvmx_npei_pcie_msi_rcv_b1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t intr:8; uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t intr:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx; struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1; @@ -1903,9 +3339,15 @@ union cvmx_npei_pcie_msi_rcv_b1 { union cvmx_npei_pcie_msi_rcv_b2 { uint64_t u64; struct cvmx_npei_pcie_msi_rcv_b2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t intr:8; uint64_t reserved_0_15:16; +#else + uint64_t reserved_0_15:16; + uint64_t intr:8; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx; struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1; @@ -1916,9 +3358,15 @@ union cvmx_npei_pcie_msi_rcv_b2 { union cvmx_npei_pcie_msi_rcv_b3 { uint64_t u64; struct cvmx_npei_pcie_msi_rcv_b3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t intr:8; uint64_t reserved_0_23:24; +#else + uint64_t reserved_0_23:24; + uint64_t intr:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx; struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1; @@ -1929,9 +3377,15 @@ union cvmx_npei_pcie_msi_rcv_b3 { union cvmx_npei_pktx_cnts { uint64_t u64; struct cvmx_npei_pktx_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t timer:22; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t timer:22; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_npei_pktx_cnts_s cn52xx; struct cvmx_npei_pktx_cnts_s cn56xx; @@ -1940,8 +3394,13 @@ union cvmx_npei_pktx_cnts { union cvmx_npei_pktx_in_bp { uint64_t u64; struct cvmx_npei_pktx_in_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wmark:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t wmark:32; +#endif } s; struct cvmx_npei_pktx_in_bp_s cn52xx; struct cvmx_npei_pktx_in_bp_s cn56xx; @@ -1950,8 +3409,13 @@ union cvmx_npei_pktx_in_bp { union cvmx_npei_pktx_instr_baddr { uint64_t u64; struct cvmx_npei_pktx_instr_baddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:61; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t addr:61; +#endif } s; struct cvmx_npei_pktx_instr_baddr_s cn52xx; struct cvmx_npei_pktx_instr_baddr_s cn56xx; @@ -1960,8 +3424,13 @@ union cvmx_npei_pktx_instr_baddr { union cvmx_npei_pktx_instr_baoff_dbell { uint64_t u64; struct cvmx_npei_pktx_instr_baoff_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t aoff:32; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t aoff:32; +#endif } s; struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx; struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx; @@ -1970,11 +3439,19 @@ union cvmx_npei_pktx_instr_baoff_dbell { union cvmx_npei_pktx_instr_fifo_rsize { uint64_t u64; struct cvmx_npei_pktx_instr_fifo_rsize_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t max:9; uint64_t rrp:9; uint64_t wrp:9; uint64_t fcnt:5; uint64_t rsize:32; +#else + uint64_t rsize:32; + uint64_t fcnt:5; + uint64_t wrp:9; + uint64_t rrp:9; + uint64_t max:9; +#endif } s; struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx; struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx; @@ -1983,6 +3460,7 @@ union cvmx_npei_pktx_instr_fifo_rsize { union cvmx_npei_pktx_instr_header { uint64_t u64; struct cvmx_npei_pktx_instr_header_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t reserved_38_42:5; @@ -1996,6 +3474,21 @@ union cvmx_npei_pktx_instr_header { uint64_t reserved_13_13:1; uint64_t skp_len:7; uint64_t reserved_0_5:6; +#else + uint64_t reserved_0_5:6; + uint64_t skp_len:7; + uint64_t reserved_13_13:1; + uint64_t par_mode:2; + uint64_t reserved_16_20:5; + uint64_t use_ihdr:1; + uint64_t reserved_22_27:6; + uint64_t rskp_len:7; + uint64_t reserved_35_35:1; + uint64_t rparmode:2; + uint64_t reserved_38_42:5; + uint64_t pbp:1; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_npei_pktx_instr_header_s cn52xx; struct cvmx_npei_pktx_instr_header_s cn56xx; @@ -2004,8 +3497,13 @@ union cvmx_npei_pktx_instr_header { union cvmx_npei_pktx_slist_baddr { uint64_t u64; struct cvmx_npei_pktx_slist_baddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:60; uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t addr:60; +#endif } s; struct cvmx_npei_pktx_slist_baddr_s cn52xx; struct cvmx_npei_pktx_slist_baddr_s cn56xx; @@ -2014,8 +3512,13 @@ union cvmx_npei_pktx_slist_baddr { union cvmx_npei_pktx_slist_baoff_dbell { uint64_t u64; struct cvmx_npei_pktx_slist_baoff_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t aoff:32; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t aoff:32; +#endif } s; struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx; struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx; @@ -2024,8 +3527,13 @@ union cvmx_npei_pktx_slist_baoff_dbell { union cvmx_npei_pktx_slist_fifo_rsize { uint64_t u64; struct cvmx_npei_pktx_slist_fifo_rsize_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rsize:32; +#else + uint64_t rsize:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx; struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx; @@ -2034,8 +3542,13 @@ union cvmx_npei_pktx_slist_fifo_rsize { union cvmx_npei_pkt_cnt_int { uint64_t u64; struct cvmx_npei_pkt_cnt_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_cnt_int_s cn52xx; struct cvmx_npei_pkt_cnt_int_s cn56xx; @@ -2044,8 +3557,13 @@ union cvmx_npei_pkt_cnt_int { union cvmx_npei_pkt_cnt_int_enb { uint64_t u64; struct cvmx_npei_pkt_cnt_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_cnt_int_enb_s cn52xx; struct cvmx_npei_pkt_cnt_int_enb_s cn56xx; @@ -2054,7 +3572,11 @@ union cvmx_npei_pkt_cnt_int_enb { union cvmx_npei_pkt_data_out_es { uint64_t u64; struct cvmx_npei_pkt_data_out_es_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t es:64; +#else uint64_t es:64; +#endif } s; struct cvmx_npei_pkt_data_out_es_s cn52xx; struct cvmx_npei_pkt_data_out_es_s cn56xx; @@ -2063,8 +3585,13 @@ union cvmx_npei_pkt_data_out_es { union cvmx_npei_pkt_data_out_ns { uint64_t u64; struct cvmx_npei_pkt_data_out_ns_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t nsr:32; +#else + uint64_t nsr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_data_out_ns_s cn52xx; struct cvmx_npei_pkt_data_out_ns_s cn56xx; @@ -2073,8 +3600,13 @@ union cvmx_npei_pkt_data_out_ns { union cvmx_npei_pkt_data_out_ror { uint64_t u64; struct cvmx_npei_pkt_data_out_ror_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ror:32; +#else + uint64_t ror:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_data_out_ror_s cn52xx; struct cvmx_npei_pkt_data_out_ror_s cn56xx; @@ -2083,8 +3615,13 @@ union cvmx_npei_pkt_data_out_ror { union cvmx_npei_pkt_dpaddr { uint64_t u64; struct cvmx_npei_pkt_dpaddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t dptr:32; +#else + uint64_t dptr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_dpaddr_s cn52xx; struct cvmx_npei_pkt_dpaddr_s cn56xx; @@ -2093,8 +3630,13 @@ union cvmx_npei_pkt_dpaddr { union cvmx_npei_pkt_in_bp { uint64_t u64; struct cvmx_npei_pkt_in_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bp:32; +#else + uint64_t bp:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_in_bp_s cn52xx; struct cvmx_npei_pkt_in_bp_s cn56xx; @@ -2103,8 +3645,13 @@ union cvmx_npei_pkt_in_bp { union cvmx_npei_pkt_in_donex_cnts { uint64_t u64; struct cvmx_npei_pkt_in_donex_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_in_donex_cnts_s cn52xx; struct cvmx_npei_pkt_in_donex_cnts_s cn56xx; @@ -2113,8 +3660,13 @@ union cvmx_npei_pkt_in_donex_cnts { union cvmx_npei_pkt_in_instr_counts { uint64_t u64; struct cvmx_npei_pkt_in_instr_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_cnt:32; uint64_t rd_cnt:32; +#else + uint64_t rd_cnt:32; + uint64_t wr_cnt:32; +#endif } s; struct cvmx_npei_pkt_in_instr_counts_s cn52xx; struct cvmx_npei_pkt_in_instr_counts_s cn56xx; @@ -2123,7 +3675,11 @@ union cvmx_npei_pkt_in_instr_counts { union cvmx_npei_pkt_in_pcie_port { uint64_t u64; struct cvmx_npei_pkt_in_pcie_port_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t pp:64; +#else uint64_t pp:64; +#endif } s; struct cvmx_npei_pkt_in_pcie_port_s cn52xx; struct cvmx_npei_pkt_in_pcie_port_s cn56xx; @@ -2132,6 +3688,7 @@ union cvmx_npei_pkt_in_pcie_port { union cvmx_npei_pkt_input_control { uint64_t u64; struct cvmx_npei_pkt_input_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t pkt_rr:1; uint64_t pbp_dhi:13; @@ -2142,6 +3699,18 @@ union cvmx_npei_pkt_input_control { uint64_t nsr:1; uint64_t esr:2; uint64_t ror:1; +#else + uint64_t ror:1; + uint64_t esr:2; + uint64_t nsr:1; + uint64_t use_csr:1; + uint64_t d_ror:1; + uint64_t d_esr:2; + uint64_t d_nsr:1; + uint64_t pbp_dhi:13; + uint64_t pkt_rr:1; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_npei_pkt_input_control_s cn52xx; struct cvmx_npei_pkt_input_control_s cn56xx; @@ -2150,8 +3719,13 @@ union cvmx_npei_pkt_input_control { union cvmx_npei_pkt_instr_enb { uint64_t u64; struct cvmx_npei_pkt_instr_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enb:32; +#else + uint64_t enb:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_instr_enb_s cn52xx; struct cvmx_npei_pkt_instr_enb_s cn56xx; @@ -2160,7 +3734,11 @@ union cvmx_npei_pkt_instr_enb { union cvmx_npei_pkt_instr_rd_size { uint64_t u64; struct cvmx_npei_pkt_instr_rd_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rdsize:64; +#else + uint64_t rdsize:64; +#endif } s; struct cvmx_npei_pkt_instr_rd_size_s cn52xx; struct cvmx_npei_pkt_instr_rd_size_s cn56xx; @@ -2169,8 +3747,13 @@ union cvmx_npei_pkt_instr_rd_size { union cvmx_npei_pkt_instr_size { uint64_t u64; struct cvmx_npei_pkt_instr_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t is_64b:32; +#else + uint64_t is_64b:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_instr_size_s cn52xx; struct cvmx_npei_pkt_instr_size_s cn56xx; @@ -2179,9 +3762,15 @@ union cvmx_npei_pkt_instr_size { union cvmx_npei_pkt_int_levels { uint64_t u64; struct cvmx_npei_pkt_int_levels_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t time:22; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t time:22; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_npei_pkt_int_levels_s cn52xx; struct cvmx_npei_pkt_int_levels_s cn56xx; @@ -2190,8 +3779,13 @@ union cvmx_npei_pkt_int_levels { union cvmx_npei_pkt_iptr { uint64_t u64; struct cvmx_npei_pkt_iptr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iptr:32; +#else + uint64_t iptr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_iptr_s cn52xx; struct cvmx_npei_pkt_iptr_s cn56xx; @@ -2200,8 +3794,13 @@ union cvmx_npei_pkt_iptr { union cvmx_npei_pkt_out_bmode { uint64_t u64; struct cvmx_npei_pkt_out_bmode_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bmode:32; +#else + uint64_t bmode:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_out_bmode_s cn52xx; struct cvmx_npei_pkt_out_bmode_s cn56xx; @@ -2210,8 +3809,13 @@ union cvmx_npei_pkt_out_bmode { union cvmx_npei_pkt_out_enb { uint64_t u64; struct cvmx_npei_pkt_out_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enb:32; +#else + uint64_t enb:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_out_enb_s cn52xx; struct cvmx_npei_pkt_out_enb_s cn56xx; @@ -2220,8 +3824,13 @@ union cvmx_npei_pkt_out_enb { union cvmx_npei_pkt_output_wmark { uint64_t u64; struct cvmx_npei_pkt_output_wmark_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t wmark:32; +#else + uint64_t wmark:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_output_wmark_s cn52xx; struct cvmx_npei_pkt_output_wmark_s cn56xx; @@ -2230,7 +3839,11 @@ union cvmx_npei_pkt_output_wmark { union cvmx_npei_pkt_pcie_port { uint64_t u64; struct cvmx_npei_pkt_pcie_port_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t pp:64; +#else + uint64_t pp:64; +#endif } s; struct cvmx_npei_pkt_pcie_port_s cn52xx; struct cvmx_npei_pkt_pcie_port_s cn56xx; @@ -2239,8 +3852,13 @@ union cvmx_npei_pkt_pcie_port { union cvmx_npei_pkt_port_in_rst { uint64_t u64; struct cvmx_npei_pkt_port_in_rst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t in_rst:32; uint64_t out_rst:32; +#else + uint64_t out_rst:32; + uint64_t in_rst:32; +#endif } s; struct cvmx_npei_pkt_port_in_rst_s cn52xx; struct cvmx_npei_pkt_port_in_rst_s cn56xx; @@ -2249,7 +3867,11 @@ union cvmx_npei_pkt_port_in_rst { union cvmx_npei_pkt_slist_es { uint64_t u64; struct cvmx_npei_pkt_slist_es_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t es:64; +#else + uint64_t es:64; +#endif } s; struct cvmx_npei_pkt_slist_es_s cn52xx; struct cvmx_npei_pkt_slist_es_s cn56xx; @@ -2258,9 +3880,15 @@ union cvmx_npei_pkt_slist_es { union cvmx_npei_pkt_slist_id_size { uint64_t u64; struct cvmx_npei_pkt_slist_id_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t isize:7; uint64_t bsize:16; +#else + uint64_t bsize:16; + uint64_t isize:7; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_npei_pkt_slist_id_size_s cn52xx; struct cvmx_npei_pkt_slist_id_size_s cn56xx; @@ -2269,8 +3897,13 @@ union cvmx_npei_pkt_slist_id_size { union cvmx_npei_pkt_slist_ns { uint64_t u64; struct cvmx_npei_pkt_slist_ns_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t nsr:32; +#else + uint64_t nsr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_slist_ns_s cn52xx; struct cvmx_npei_pkt_slist_ns_s cn56xx; @@ -2279,8 +3912,13 @@ union cvmx_npei_pkt_slist_ns { union cvmx_npei_pkt_slist_ror { uint64_t u64; struct cvmx_npei_pkt_slist_ror_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ror:32; +#else + uint64_t ror:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_slist_ror_s cn52xx; struct cvmx_npei_pkt_slist_ror_s cn56xx; @@ -2289,8 +3927,13 @@ union cvmx_npei_pkt_slist_ror { union cvmx_npei_pkt_time_int { uint64_t u64; struct cvmx_npei_pkt_time_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_time_int_s cn52xx; struct cvmx_npei_pkt_time_int_s cn56xx; @@ -2299,8 +3942,13 @@ union cvmx_npei_pkt_time_int { union cvmx_npei_pkt_time_int_enb { uint64_t u64; struct cvmx_npei_pkt_time_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_time_int_enb_s cn52xx; struct cvmx_npei_pkt_time_int_enb_s cn56xx; @@ -2309,6 +3957,7 @@ union cvmx_npei_pkt_time_int_enb { union cvmx_npei_rsl_int_blocks { uint64_t u64; struct cvmx_npei_rsl_int_blocks_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t iob:1; uint64_t lmc1:1; @@ -2338,6 +3987,37 @@ union cvmx_npei_rsl_int_blocks { uint64_t gmx1:1; uint64_t gmx0:1; uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t npei:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t reserved_8_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rad:1; + uint64_t usb1:1; + uint64_t l2c:1; + uint64_t lmc0:1; + uint64_t spx0:1; + uint64_t spx1:1; + uint64_t pip:1; + uint64_t reserved_21_21:1; + uint64_t asxpcs0:1; + uint64_t asxpcs1:1; + uint64_t reserved_24_27:4; + uint64_t agl:1; + uint64_t lmc1:1; + uint64_t iob:1; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_npei_rsl_int_blocks_s cn52xx; struct cvmx_npei_rsl_int_blocks_s cn52xxp1; @@ -2348,7 +4028,11 @@ union cvmx_npei_rsl_int_blocks { union cvmx_npei_scratch_1 { uint64_t u64; struct cvmx_npei_scratch_1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_npei_scratch_1_s cn52xx; struct cvmx_npei_scratch_1_s cn52xxp1; @@ -2359,10 +4043,17 @@ union cvmx_npei_scratch_1 { union cvmx_npei_state1 { uint64_t u64; struct cvmx_npei_state1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t cpl1:12; uint64_t cpl0:12; uint64_t arb:1; uint64_t csr:39; +#else + uint64_t csr:39; + uint64_t arb:1; + uint64_t cpl0:12; + uint64_t cpl1:12; +#endif } s; struct cvmx_npei_state1_s cn52xx; struct cvmx_npei_state1_s cn52xxp1; @@ -2373,6 +4064,7 @@ union cvmx_npei_state1 { union cvmx_npei_state2 { uint64_t u64; struct cvmx_npei_state2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t npei:1; uint64_t rac:1; @@ -2380,6 +4072,15 @@ union cvmx_npei_state2 { uint64_t csm0:15; uint64_t nnp0:8; uint64_t nnd:8; +#else + uint64_t nnd:8; + uint64_t nnp0:8; + uint64_t csm0:15; + uint64_t csm1:15; + uint64_t rac:1; + uint64_t npei:1; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_npei_state2_s cn52xx; struct cvmx_npei_state2_s cn52xxp1; @@ -2390,11 +4091,19 @@ union cvmx_npei_state2 { union cvmx_npei_state3 { uint64_t u64; struct cvmx_npei_state3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t psm1:15; uint64_t psm0:15; uint64_t nsm1:13; uint64_t nsm0:13; +#else + uint64_t nsm0:13; + uint64_t nsm1:13; + uint64_t psm0:15; + uint64_t psm1:15; + uint64_t reserved_56_63:8; +#endif } s; struct cvmx_npei_state3_s cn52xx; struct cvmx_npei_state3_s cn52xxp1; @@ -2405,10 +4114,17 @@ union cvmx_npei_state3 { union cvmx_npei_win_rd_addr { uint64_t u64; struct cvmx_npei_win_rd_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_51_63:13; uint64_t ld_cmd:2; uint64_t iobit:1; uint64_t rd_addr:48; +#else + uint64_t rd_addr:48; + uint64_t iobit:1; + uint64_t ld_cmd:2; + uint64_t reserved_51_63:13; +#endif } s; struct cvmx_npei_win_rd_addr_s cn52xx; struct cvmx_npei_win_rd_addr_s cn52xxp1; @@ -2419,7 +4135,11 @@ union cvmx_npei_win_rd_addr { union cvmx_npei_win_rd_data { uint64_t u64; struct cvmx_npei_win_rd_data_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rd_data:64; +#else uint64_t rd_data:64; +#endif } s; struct cvmx_npei_win_rd_data_s cn52xx; struct cvmx_npei_win_rd_data_s cn52xxp1; @@ -2430,10 +4150,17 @@ union cvmx_npei_win_rd_data { union cvmx_npei_win_wr_addr { uint64_t u64; struct cvmx_npei_win_wr_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t wr_addr:46; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t wr_addr:46; + uint64_t iobit:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_npei_win_wr_addr_s cn52xx; struct cvmx_npei_win_wr_addr_s cn52xxp1; @@ -2444,7 +4171,11 @@ union cvmx_npei_win_wr_addr { union cvmx_npei_win_wr_data { uint64_t u64; struct cvmx_npei_win_wr_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_data:64; +#else + uint64_t wr_data:64; +#endif } s; struct cvmx_npei_win_wr_data_s cn52xx; struct cvmx_npei_win_wr_data_s cn52xxp1; @@ -2455,8 +4186,13 @@ union cvmx_npei_win_wr_data { union cvmx_npei_win_wr_mask { uint64_t u64; struct cvmx_npei_win_wr_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t wr_mask:8; +#else + uint64_t wr_mask:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_npei_win_wr_mask_s cn52xx; struct cvmx_npei_win_wr_mask_s cn52xxp1; @@ -2467,8 +4203,13 @@ union cvmx_npei_win_wr_mask { union cvmx_npei_window_ctl { uint64_t u64; struct cvmx_npei_window_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t time:32; +#else + uint64_t time:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_window_ctl_s cn52xx; struct cvmx_npei_window_ctl_s cn52xxp1; diff --git a/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/arch/mips/include/asm/octeon/cvmx-npi-defs.h index f089c780060f..129bb250e534 100644 --- a/arch/mips/include/asm/octeon/cvmx-npi-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -152,8 +152,13 @@ union cvmx_npi_base_addr_inputx { uint64_t u64; struct cvmx_npi_base_addr_inputx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t baddr:61; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t baddr:61; +#endif } s; struct cvmx_npi_base_addr_inputx_s cn30xx; struct cvmx_npi_base_addr_inputx_s cn31xx; @@ -167,8 +172,13 @@ union cvmx_npi_base_addr_inputx { union cvmx_npi_base_addr_outputx { uint64_t u64; struct cvmx_npi_base_addr_outputx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t baddr:61; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t baddr:61; +#endif } s; struct cvmx_npi_base_addr_outputx_s cn30xx; struct cvmx_npi_base_addr_outputx_s cn31xx; @@ -182,6 +192,7 @@ union cvmx_npi_base_addr_outputx { union cvmx_npi_bist_status { uint64_t u64; struct cvmx_npi_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t csr_bs:1; uint64_t dif_bs:1; @@ -203,8 +214,32 @@ union cvmx_npi_bist_status { uint64_t dob_bs:1; uint64_t pdf_bs:1; uint64_t dpi_bs:1; +#else + uint64_t dpi_bs:1; + uint64_t pdf_bs:1; + uint64_t dob_bs:1; + uint64_t nus_bs:1; + uint64_t pos_bs:1; + uint64_t pof3_bs:1; + uint64_t pof2_bs:1; + uint64_t pof1_bs:1; + uint64_t pof0_bs:1; + uint64_t pig_bs:1; + uint64_t pgf_bs:1; + uint64_t rdnl_bs:1; + uint64_t pcad_bs:1; + uint64_t pcac_bs:1; + uint64_t rdn_bs:1; + uint64_t pcn_bs:1; + uint64_t pcnc_bs:1; + uint64_t rdp_bs:1; + uint64_t dif_bs:1; + uint64_t csr_bs:1; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_npi_bist_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t csr_bs:1; uint64_t dif_bs:1; @@ -224,11 +259,33 @@ union cvmx_npi_bist_status { uint64_t dob_bs:1; uint64_t pdf_bs:1; uint64_t dpi_bs:1; +#else + uint64_t dpi_bs:1; + uint64_t pdf_bs:1; + uint64_t dob_bs:1; + uint64_t nus_bs:1; + uint64_t pos_bs:1; + uint64_t reserved_5_7:3; + uint64_t pof0_bs:1; + uint64_t pig_bs:1; + uint64_t pgf_bs:1; + uint64_t rdnl_bs:1; + uint64_t pcad_bs:1; + uint64_t pcac_bs:1; + uint64_t rdn_bs:1; + uint64_t pcn_bs:1; + uint64_t pcnc_bs:1; + uint64_t rdp_bs:1; + uint64_t dif_bs:1; + uint64_t csr_bs:1; + uint64_t reserved_20_63:44; +#endif } cn30xx; struct cvmx_npi_bist_status_s cn31xx; struct cvmx_npi_bist_status_s cn38xx; struct cvmx_npi_bist_status_s cn38xxp2; struct cvmx_npi_bist_status_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t csr_bs:1; uint64_t dif_bs:1; @@ -249,6 +306,28 @@ union cvmx_npi_bist_status { uint64_t dob_bs:1; uint64_t pdf_bs:1; uint64_t dpi_bs:1; +#else + uint64_t dpi_bs:1; + uint64_t pdf_bs:1; + uint64_t dob_bs:1; + uint64_t nus_bs:1; + uint64_t pos_bs:1; + uint64_t reserved_5_6:2; + uint64_t pof1_bs:1; + uint64_t pof0_bs:1; + uint64_t pig_bs:1; + uint64_t pgf_bs:1; + uint64_t rdnl_bs:1; + uint64_t pcad_bs:1; + uint64_t pcac_bs:1; + uint64_t rdn_bs:1; + uint64_t pcn_bs:1; + uint64_t pcnc_bs:1; + uint64_t rdp_bs:1; + uint64_t dif_bs:1; + uint64_t csr_bs:1; + uint64_t reserved_20_63:44; +#endif } cn50xx; struct cvmx_npi_bist_status_s cn58xx; struct cvmx_npi_bist_status_s cn58xxp1; @@ -257,9 +336,15 @@ union cvmx_npi_bist_status { union cvmx_npi_buff_size_outputx { uint64_t u64; struct cvmx_npi_buff_size_outputx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t isize:7; uint64_t bsize:16; +#else + uint64_t bsize:16; + uint64_t isize:7; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_npi_buff_size_outputx_s cn30xx; struct cvmx_npi_buff_size_outputx_s cn31xx; @@ -273,9 +358,15 @@ union cvmx_npi_buff_size_outputx { union cvmx_npi_comp_ctl { uint64_t u64; struct cvmx_npi_comp_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pctl:5; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t pctl:5; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_npi_comp_ctl_s cn50xx; struct cvmx_npi_comp_ctl_s cn58xx; @@ -285,6 +376,7 @@ union cvmx_npi_comp_ctl { union cvmx_npi_ctl_status { uint64_t u64; struct cvmx_npi_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_63_63:1; uint64_t chip_rev:8; uint64_t dis_pniw:1; @@ -306,8 +398,32 @@ union cvmx_npi_ctl_status { uint64_t max_word:5; uint64_t reserved_10_31:22; uint64_t timer:10; +#else + uint64_t timer:10; + uint64_t reserved_10_31:22; + uint64_t max_word:5; + uint64_t reserved_37_39:3; + uint64_t wait_com:1; + uint64_t pci_wdis:1; + uint64_t ins0_64b:1; + uint64_t ins1_64b:1; + uint64_t ins2_64b:1; + uint64_t ins3_64b:1; + uint64_t ins0_enb:1; + uint64_t ins1_enb:1; + uint64_t ins2_enb:1; + uint64_t ins3_enb:1; + uint64_t out0_enb:1; + uint64_t out1_enb:1; + uint64_t out2_enb:1; + uint64_t out3_enb:1; + uint64_t dis_pniw:1; + uint64_t chip_rev:8; + uint64_t reserved_63_63:1; +#endif } s; struct cvmx_npi_ctl_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_63_63:1; uint64_t chip_rev:8; uint64_t dis_pniw:1; @@ -323,8 +439,26 @@ union cvmx_npi_ctl_status { uint64_t max_word:5; uint64_t reserved_10_31:22; uint64_t timer:10; +#else + uint64_t timer:10; + uint64_t reserved_10_31:22; + uint64_t max_word:5; + uint64_t reserved_37_39:3; + uint64_t wait_com:1; + uint64_t pci_wdis:1; + uint64_t ins0_64b:1; + uint64_t reserved_43_45:3; + uint64_t ins0_enb:1; + uint64_t reserved_47_49:3; + uint64_t out0_enb:1; + uint64_t reserved_51_53:3; + uint64_t dis_pniw:1; + uint64_t chip_rev:8; + uint64_t reserved_63_63:1; +#endif } cn30xx; struct cvmx_npi_ctl_status_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_63_63:1; uint64_t chip_rev:8; uint64_t dis_pniw:1; @@ -343,6 +477,26 @@ union cvmx_npi_ctl_status { uint64_t max_word:5; uint64_t reserved_10_31:22; uint64_t timer:10; +#else + uint64_t timer:10; + uint64_t reserved_10_31:22; + uint64_t max_word:5; + uint64_t reserved_37_39:3; + uint64_t wait_com:1; + uint64_t pci_wdis:1; + uint64_t ins0_64b:1; + uint64_t ins1_64b:1; + uint64_t reserved_44_45:2; + uint64_t ins0_enb:1; + uint64_t ins1_enb:1; + uint64_t reserved_48_49:2; + uint64_t out0_enb:1; + uint64_t out1_enb:1; + uint64_t reserved_52_53:2; + uint64_t dis_pniw:1; + uint64_t chip_rev:8; + uint64_t reserved_63_63:1; +#endif } cn31xx; struct cvmx_npi_ctl_status_s cn38xx; struct cvmx_npi_ctl_status_s cn38xxp2; @@ -354,8 +508,13 @@ union cvmx_npi_ctl_status { union cvmx_npi_dbg_select { uint64_t u64; struct cvmx_npi_dbg_select_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dbg_sel:16; +#else + uint64_t dbg_sel:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npi_dbg_select_s cn30xx; struct cvmx_npi_dbg_select_s cn31xx; @@ -369,6 +528,7 @@ union cvmx_npi_dbg_select { union cvmx_npi_dma_control { uint64_t u64; struct cvmx_npi_dma_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t b0_lend:1; uint64_t dwb_denb:1; @@ -382,6 +542,21 @@ union cvmx_npi_dma_control { uint64_t hp_enb:1; uint64_t lp_enb:1; uint64_t csize:14; +#else + uint64_t csize:14; + uint64_t lp_enb:1; + uint64_t hp_enb:1; + uint64_t o_mode:1; + uint64_t o_es:2; + uint64_t o_ns:1; + uint64_t o_ro:1; + uint64_t o_add1:1; + uint64_t fpa_que:3; + uint64_t dwb_ichk:9; + uint64_t dwb_denb:1; + uint64_t b0_lend:1; + uint64_t reserved_36_63:28; +#endif } s; struct cvmx_npi_dma_control_s cn30xx; struct cvmx_npi_dma_control_s cn31xx; @@ -395,9 +570,15 @@ union cvmx_npi_dma_control { union cvmx_npi_dma_highp_counts { uint64_t u64; struct cvmx_npi_dma_highp_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t fcnt:7; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t fcnt:7; + uint64_t reserved_39_63:25; +#endif } s; struct cvmx_npi_dma_highp_counts_s cn30xx; struct cvmx_npi_dma_highp_counts_s cn31xx; @@ -411,9 +592,15 @@ union cvmx_npi_dma_highp_counts { union cvmx_npi_dma_highp_naddr { uint64_t u64; struct cvmx_npi_dma_highp_naddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t state:4; uint64_t addr:36; +#else + uint64_t addr:36; + uint64_t state:4; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_npi_dma_highp_naddr_s cn30xx; struct cvmx_npi_dma_highp_naddr_s cn31xx; @@ -427,9 +614,15 @@ union cvmx_npi_dma_highp_naddr { union cvmx_npi_dma_lowp_counts { uint64_t u64; struct cvmx_npi_dma_lowp_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t fcnt:7; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t fcnt:7; + uint64_t reserved_39_63:25; +#endif } s; struct cvmx_npi_dma_lowp_counts_s cn30xx; struct cvmx_npi_dma_lowp_counts_s cn31xx; @@ -443,9 +636,15 @@ union cvmx_npi_dma_lowp_counts { union cvmx_npi_dma_lowp_naddr { uint64_t u64; struct cvmx_npi_dma_lowp_naddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t state:4; uint64_t addr:36; +#else + uint64_t addr:36; + uint64_t state:4; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_npi_dma_lowp_naddr_s cn30xx; struct cvmx_npi_dma_lowp_naddr_s cn31xx; @@ -459,8 +658,13 @@ union cvmx_npi_dma_lowp_naddr { union cvmx_npi_highp_dbell { uint64_t u64; struct cvmx_npi_highp_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dbell:16; +#else + uint64_t dbell:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npi_highp_dbell_s cn30xx; struct cvmx_npi_highp_dbell_s cn31xx; @@ -474,8 +678,13 @@ union cvmx_npi_highp_dbell { union cvmx_npi_highp_ibuff_saddr { uint64_t u64; struct cvmx_npi_highp_ibuff_saddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t saddr:36; +#else + uint64_t saddr:36; + uint64_t reserved_36_63:28; +#endif } s; struct cvmx_npi_highp_ibuff_saddr_s cn30xx; struct cvmx_npi_highp_ibuff_saddr_s cn31xx; @@ -489,6 +698,7 @@ union cvmx_npi_highp_ibuff_saddr { union cvmx_npi_input_control { uint64_t u64; struct cvmx_npi_input_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t pkt_rr:1; uint64_t pbp_dhi:13; @@ -499,8 +709,21 @@ union cvmx_npi_input_control { uint64_t nsr:1; uint64_t esr:2; uint64_t ror:1; +#else + uint64_t ror:1; + uint64_t esr:2; + uint64_t nsr:1; + uint64_t use_csr:1; + uint64_t d_ror:1; + uint64_t d_esr:2; + uint64_t d_nsr:1; + uint64_t pbp_dhi:13; + uint64_t pkt_rr:1; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_npi_input_control_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t pbp_dhi:13; uint64_t d_nsr:1; @@ -510,6 +733,17 @@ union cvmx_npi_input_control { uint64_t nsr:1; uint64_t esr:2; uint64_t ror:1; +#else + uint64_t ror:1; + uint64_t esr:2; + uint64_t nsr:1; + uint64_t use_csr:1; + uint64_t d_ror:1; + uint64_t d_esr:2; + uint64_t d_nsr:1; + uint64_t pbp_dhi:13; + uint64_t reserved_22_63:42; +#endif } cn30xx; struct cvmx_npi_input_control_cn30xx cn31xx; struct cvmx_npi_input_control_s cn38xx; @@ -522,6 +756,7 @@ union cvmx_npi_input_control { union cvmx_npi_int_enb { uint64_t u64; struct cvmx_npi_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -585,8 +820,74 @@ union cvmx_npi_int_enb { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t po1_2sml:1; + uint64_t po2_2sml:1; + uint64_t po3_2sml:1; + uint64_t i0_rtout:1; + uint64_t i1_rtout:1; + uint64_t i2_rtout:1; + uint64_t i3_rtout:1; + uint64_t i0_overf:1; + uint64_t i1_overf:1; + uint64_t i2_overf:1; + uint64_t i3_overf:1; + uint64_t p0_rtout:1; + uint64_t p1_rtout:1; + uint64_t p2_rtout:1; + uint64_t p3_rtout:1; + uint64_t p0_perr:1; + uint64_t p1_perr:1; + uint64_t p2_perr:1; + uint64_t p3_perr:1; + uint64_t g0_rtout:1; + uint64_t g1_rtout:1; + uint64_t g2_rtout:1; + uint64_t g3_rtout:1; + uint64_t p0_pperr:1; + uint64_t p1_pperr:1; + uint64_t p2_pperr:1; + uint64_t p3_pperr:1; + uint64_t p0_ptout:1; + uint64_t p1_ptout:1; + uint64_t p2_ptout:1; + uint64_t p3_ptout:1; + uint64_t i0_pperr:1; + uint64_t i1_pperr:1; + uint64_t i2_pperr:1; + uint64_t i3_pperr:1; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t fcr_s_e:1; + uint64_t fcr_a_f:1; + uint64_t pcr_s_e:1; + uint64_t pcr_a_f:1; + uint64_t q2_s_e:1; + uint64_t q2_a_f:1; + uint64_t q3_s_e:1; + uint64_t q3_a_f:1; + uint64_t com_s_e:1; + uint64_t com_a_f:1; + uint64_t pnc_s_e:1; + uint64_t pnc_a_f:1; + uint64_t rwx_s_e:1; + uint64_t rdx_s_e:1; + uint64_t pcf_p_e:1; + uint64_t pcf_p_f:1; + uint64_t pdf_p_e:1; + uint64_t pdf_p_f:1; + uint64_t q1_s_e:1; + uint64_t q1_a_f:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_npi_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -632,8 +933,56 @@ union cvmx_npi_int_enb { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t reserved_4_6:3; + uint64_t i0_rtout:1; + uint64_t reserved_8_10:3; + uint64_t i0_overf:1; + uint64_t reserved_12_14:3; + uint64_t p0_rtout:1; + uint64_t reserved_16_18:3; + uint64_t p0_perr:1; + uint64_t reserved_20_22:3; + uint64_t g0_rtout:1; + uint64_t reserved_24_26:3; + uint64_t p0_pperr:1; + uint64_t reserved_28_30:3; + uint64_t p0_ptout:1; + uint64_t reserved_32_34:3; + uint64_t i0_pperr:1; + uint64_t reserved_36_38:3; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t fcr_s_e:1; + uint64_t fcr_a_f:1; + uint64_t pcr_s_e:1; + uint64_t pcr_a_f:1; + uint64_t q2_s_e:1; + uint64_t q2_a_f:1; + uint64_t q3_s_e:1; + uint64_t q3_a_f:1; + uint64_t com_s_e:1; + uint64_t com_a_f:1; + uint64_t pnc_s_e:1; + uint64_t pnc_a_f:1; + uint64_t rwx_s_e:1; + uint64_t rdx_s_e:1; + uint64_t pcf_p_e:1; + uint64_t pcf_p_f:1; + uint64_t pdf_p_e:1; + uint64_t pdf_p_f:1; + uint64_t q1_s_e:1; + uint64_t q1_a_f:1; + uint64_t reserved_62_63:2; +#endif } cn30xx; struct cvmx_npi_int_enb_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -688,9 +1037,66 @@ union cvmx_npi_int_enb { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t po1_2sml:1; + uint64_t reserved_5_6:2; + uint64_t i0_rtout:1; + uint64_t i1_rtout:1; + uint64_t reserved_9_10:2; + uint64_t i0_overf:1; + uint64_t i1_overf:1; + uint64_t reserved_13_14:2; + uint64_t p0_rtout:1; + uint64_t p1_rtout:1; + uint64_t reserved_17_18:2; + uint64_t p0_perr:1; + uint64_t p1_perr:1; + uint64_t reserved_21_22:2; + uint64_t g0_rtout:1; + uint64_t g1_rtout:1; + uint64_t reserved_25_26:2; + uint64_t p0_pperr:1; + uint64_t p1_pperr:1; + uint64_t reserved_29_30:2; + uint64_t p0_ptout:1; + uint64_t p1_ptout:1; + uint64_t reserved_33_34:2; + uint64_t i0_pperr:1; + uint64_t i1_pperr:1; + uint64_t reserved_37_38:2; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t fcr_s_e:1; + uint64_t fcr_a_f:1; + uint64_t pcr_s_e:1; + uint64_t pcr_a_f:1; + uint64_t q2_s_e:1; + uint64_t q2_a_f:1; + uint64_t q3_s_e:1; + uint64_t q3_a_f:1; + uint64_t com_s_e:1; + uint64_t com_a_f:1; + uint64_t pnc_s_e:1; + uint64_t pnc_a_f:1; + uint64_t rwx_s_e:1; + uint64_t rdx_s_e:1; + uint64_t pcf_p_e:1; + uint64_t pcf_p_f:1; + uint64_t pdf_p_e:1; + uint64_t pdf_p_f:1; + uint64_t q1_s_e:1; + uint64_t q1_a_f:1; + uint64_t reserved_62_63:2; +#endif } cn31xx; struct cvmx_npi_int_enb_s cn38xx; struct cvmx_npi_int_enb_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t iobdma:1; uint64_t p_dperr:1; @@ -734,6 +1140,51 @@ union cvmx_npi_int_enb { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t po1_2sml:1; + uint64_t po2_2sml:1; + uint64_t po3_2sml:1; + uint64_t i0_rtout:1; + uint64_t i1_rtout:1; + uint64_t i2_rtout:1; + uint64_t i3_rtout:1; + uint64_t i0_overf:1; + uint64_t i1_overf:1; + uint64_t i2_overf:1; + uint64_t i3_overf:1; + uint64_t p0_rtout:1; + uint64_t p1_rtout:1; + uint64_t p2_rtout:1; + uint64_t p3_rtout:1; + uint64_t p0_perr:1; + uint64_t p1_perr:1; + uint64_t p2_perr:1; + uint64_t p3_perr:1; + uint64_t g0_rtout:1; + uint64_t g1_rtout:1; + uint64_t g2_rtout:1; + uint64_t g3_rtout:1; + uint64_t p0_pperr:1; + uint64_t p1_pperr:1; + uint64_t p2_pperr:1; + uint64_t p3_pperr:1; + uint64_t p0_ptout:1; + uint64_t p1_ptout:1; + uint64_t p2_ptout:1; + uint64_t p3_ptout:1; + uint64_t i0_pperr:1; + uint64_t i1_pperr:1; + uint64_t i2_pperr:1; + uint64_t i3_pperr:1; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t reserved_42_63:22; +#endif } cn38xxp2; struct cvmx_npi_int_enb_cn31xx cn50xx; struct cvmx_npi_int_enb_s cn58xx; @@ -743,6 +1194,7 @@ union cvmx_npi_int_enb { union cvmx_npi_int_sum { uint64_t u64; struct cvmx_npi_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -806,8 +1258,74 @@ union cvmx_npi_int_sum { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t po1_2sml:1; + uint64_t po2_2sml:1; + uint64_t po3_2sml:1; + uint64_t i0_rtout:1; + uint64_t i1_rtout:1; + uint64_t i2_rtout:1; + uint64_t i3_rtout:1; + uint64_t i0_overf:1; + uint64_t i1_overf:1; + uint64_t i2_overf:1; + uint64_t i3_overf:1; + uint64_t p0_rtout:1; + uint64_t p1_rtout:1; + uint64_t p2_rtout:1; + uint64_t p3_rtout:1; + uint64_t p0_perr:1; + uint64_t p1_perr:1; + uint64_t p2_perr:1; + uint64_t p3_perr:1; + uint64_t g0_rtout:1; + uint64_t g1_rtout:1; + uint64_t g2_rtout:1; + uint64_t g3_rtout:1; + uint64_t p0_pperr:1; + uint64_t p1_pperr:1; + uint64_t p2_pperr:1; + uint64_t p3_pperr:1; + uint64_t p0_ptout:1; + uint64_t p1_ptout:1; + uint64_t p2_ptout:1; + uint64_t p3_ptout:1; + uint64_t i0_pperr:1; + uint64_t i1_pperr:1; + uint64_t i2_pperr:1; + uint64_t i3_pperr:1; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t fcr_s_e:1; + uint64_t fcr_a_f:1; + uint64_t pcr_s_e:1; + uint64_t pcr_a_f:1; + uint64_t q2_s_e:1; + uint64_t q2_a_f:1; + uint64_t q3_s_e:1; + uint64_t q3_a_f:1; + uint64_t com_s_e:1; + uint64_t com_a_f:1; + uint64_t pnc_s_e:1; + uint64_t pnc_a_f:1; + uint64_t rwx_s_e:1; + uint64_t rdx_s_e:1; + uint64_t pcf_p_e:1; + uint64_t pcf_p_f:1; + uint64_t pdf_p_e:1; + uint64_t pdf_p_f:1; + uint64_t q1_s_e:1; + uint64_t q1_a_f:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_npi_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -853,8 +1371,56 @@ union cvmx_npi_int_sum { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t reserved_4_6:3; + uint64_t i0_rtout:1; + uint64_t reserved_8_10:3; + uint64_t i0_overf:1; + uint64_t reserved_12_14:3; + uint64_t p0_rtout:1; + uint64_t reserved_16_18:3; + uint64_t p0_perr:1; + uint64_t reserved_20_22:3; + uint64_t g0_rtout:1; + uint64_t reserved_24_26:3; + uint64_t p0_pperr:1; + uint64_t reserved_28_30:3; + uint64_t p0_ptout:1; + uint64_t reserved_32_34:3; + uint64_t i0_pperr:1; + uint64_t reserved_36_38:3; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t fcr_s_e:1; + uint64_t fcr_a_f:1; + uint64_t pcr_s_e:1; + uint64_t pcr_a_f:1; + uint64_t q2_s_e:1; + uint64_t q2_a_f:1; + uint64_t q3_s_e:1; + uint64_t q3_a_f:1; + uint64_t com_s_e:1; + uint64_t com_a_f:1; + uint64_t pnc_s_e:1; + uint64_t pnc_a_f:1; + uint64_t rwx_s_e:1; + uint64_t rdx_s_e:1; + uint64_t pcf_p_e:1; + uint64_t pcf_p_f:1; + uint64_t pdf_p_e:1; + uint64_t pdf_p_f:1; + uint64_t q1_s_e:1; + uint64_t q1_a_f:1; + uint64_t reserved_62_63:2; +#endif } cn30xx; struct cvmx_npi_int_sum_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -909,9 +1475,66 @@ union cvmx_npi_int_sum { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t po1_2sml:1; + uint64_t reserved_5_6:2; + uint64_t i0_rtout:1; + uint64_t i1_rtout:1; + uint64_t reserved_9_10:2; + uint64_t i0_overf:1; + uint64_t i1_overf:1; + uint64_t reserved_13_14:2; + uint64_t p0_rtout:1; + uint64_t p1_rtout:1; + uint64_t reserved_17_18:2; + uint64_t p0_perr:1; + uint64_t p1_perr:1; + uint64_t reserved_21_22:2; + uint64_t g0_rtout:1; + uint64_t g1_rtout:1; + uint64_t reserved_25_26:2; + uint64_t p0_pperr:1; + uint64_t p1_pperr:1; + uint64_t reserved_29_30:2; + uint64_t p0_ptout:1; + uint64_t p1_ptout:1; + uint64_t reserved_33_34:2; + uint64_t i0_pperr:1; + uint64_t i1_pperr:1; + uint64_t reserved_37_38:2; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t fcr_s_e:1; + uint64_t fcr_a_f:1; + uint64_t pcr_s_e:1; + uint64_t pcr_a_f:1; + uint64_t q2_s_e:1; + uint64_t q2_a_f:1; + uint64_t q3_s_e:1; + uint64_t q3_a_f:1; + uint64_t com_s_e:1; + uint64_t com_a_f:1; + uint64_t pnc_s_e:1; + uint64_t pnc_a_f:1; + uint64_t rwx_s_e:1; + uint64_t rdx_s_e:1; + uint64_t pcf_p_e:1; + uint64_t pcf_p_f:1; + uint64_t pdf_p_e:1; + uint64_t pdf_p_f:1; + uint64_t q1_s_e:1; + uint64_t q1_a_f:1; + uint64_t reserved_62_63:2; +#endif } cn31xx; struct cvmx_npi_int_sum_s cn38xx; struct cvmx_npi_int_sum_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t iobdma:1; uint64_t p_dperr:1; @@ -955,6 +1578,51 @@ union cvmx_npi_int_sum { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t po1_2sml:1; + uint64_t po2_2sml:1; + uint64_t po3_2sml:1; + uint64_t i0_rtout:1; + uint64_t i1_rtout:1; + uint64_t i2_rtout:1; + uint64_t i3_rtout:1; + uint64_t i0_overf:1; + uint64_t i1_overf:1; + uint64_t i2_overf:1; + uint64_t i3_overf:1; + uint64_t p0_rtout:1; + uint64_t p1_rtout:1; + uint64_t p2_rtout:1; + uint64_t p3_rtout:1; + uint64_t p0_perr:1; + uint64_t p1_perr:1; + uint64_t p2_perr:1; + uint64_t p3_perr:1; + uint64_t g0_rtout:1; + uint64_t g1_rtout:1; + uint64_t g2_rtout:1; + uint64_t g3_rtout:1; + uint64_t p0_pperr:1; + uint64_t p1_pperr:1; + uint64_t p2_pperr:1; + uint64_t p3_pperr:1; + uint64_t p0_ptout:1; + uint64_t p1_ptout:1; + uint64_t p2_ptout:1; + uint64_t p3_ptout:1; + uint64_t i0_pperr:1; + uint64_t i1_pperr:1; + uint64_t i2_pperr:1; + uint64_t i3_pperr:1; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t reserved_42_63:22; +#endif } cn38xxp2; struct cvmx_npi_int_sum_cn31xx cn50xx; struct cvmx_npi_int_sum_s cn58xx; @@ -964,8 +1632,13 @@ union cvmx_npi_int_sum { union cvmx_npi_lowp_dbell { uint64_t u64; struct cvmx_npi_lowp_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dbell:16; +#else + uint64_t dbell:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npi_lowp_dbell_s cn30xx; struct cvmx_npi_lowp_dbell_s cn31xx; @@ -979,8 +1652,13 @@ union cvmx_npi_lowp_dbell { union cvmx_npi_lowp_ibuff_saddr { uint64_t u64; struct cvmx_npi_lowp_ibuff_saddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t saddr:36; +#else + uint64_t saddr:36; + uint64_t reserved_36_63:28; +#endif } s; struct cvmx_npi_lowp_ibuff_saddr_s cn30xx; struct cvmx_npi_lowp_ibuff_saddr_s cn31xx; @@ -994,6 +1672,7 @@ union cvmx_npi_lowp_ibuff_saddr { union cvmx_npi_mem_access_subidx { uint64_t u64; struct cvmx_npi_mem_access_subidx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t shortl:1; uint64_t nmerge:1; @@ -1004,9 +1683,22 @@ union cvmx_npi_mem_access_subidx { uint64_t ror:1; uint64_t row:1; uint64_t ba:28; +#else + uint64_t ba:28; + uint64_t row:1; + uint64_t ror:1; + uint64_t nsw:1; + uint64_t nsr:1; + uint64_t esw:2; + uint64_t esr:2; + uint64_t nmerge:1; + uint64_t shortl:1; + uint64_t reserved_38_63:26; +#endif } s; struct cvmx_npi_mem_access_subidx_s cn30xx; struct cvmx_npi_mem_access_subidx_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t esr:2; uint64_t esw:2; @@ -1015,6 +1707,16 @@ union cvmx_npi_mem_access_subidx { uint64_t ror:1; uint64_t row:1; uint64_t ba:28; +#else + uint64_t ba:28; + uint64_t row:1; + uint64_t ror:1; + uint64_t nsw:1; + uint64_t nsr:1; + uint64_t esw:2; + uint64_t esr:2; + uint64_t reserved_36_63:28; +#endif } cn31xx; struct cvmx_npi_mem_access_subidx_s cn38xx; struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2; @@ -1026,7 +1728,11 @@ union cvmx_npi_mem_access_subidx { union cvmx_npi_msi_rcv { uint64_t u64; struct cvmx_npi_msi_rcv_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t int_vec:64; +#else uint64_t int_vec:64; +#endif } s; struct cvmx_npi_msi_rcv_s cn30xx; struct cvmx_npi_msi_rcv_s cn31xx; @@ -1040,8 +1746,13 @@ union cvmx_npi_msi_rcv { union cvmx_npi_num_desc_outputx { uint64_t u64; struct cvmx_npi_num_desc_outputx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t size:32; +#else + uint64_t size:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npi_num_desc_outputx_s cn30xx; struct cvmx_npi_num_desc_outputx_s cn31xx; @@ -1055,6 +1766,7 @@ union cvmx_npi_num_desc_outputx { union cvmx_npi_output_control { uint64_t u64; struct cvmx_npi_output_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t pkt_rr:1; uint64_t p3_bmode:1; @@ -1094,8 +1806,50 @@ union cvmx_npi_output_control { uint64_t esr_sl0:2; uint64_t nsr_sl0:1; uint64_t ror_sl0:1; +#else + uint64_t ror_sl0:1; + uint64_t nsr_sl0:1; + uint64_t esr_sl0:2; + uint64_t ror_sl1:1; + uint64_t nsr_sl1:1; + uint64_t esr_sl1:2; + uint64_t ror_sl2:1; + uint64_t nsr_sl2:1; + uint64_t esr_sl2:2; + uint64_t ror_sl3:1; + uint64_t nsr_sl3:1; + uint64_t esr_sl3:2; + uint64_t iptr_o0:1; + uint64_t iptr_o1:1; + uint64_t iptr_o2:1; + uint64_t iptr_o3:1; + uint64_t reserved_20_23:4; + uint64_t o0_csrm:1; + uint64_t o1_csrm:1; + uint64_t o2_csrm:1; + uint64_t o3_csrm:1; + uint64_t o0_ro:1; + uint64_t o0_ns:1; + uint64_t o0_es:2; + uint64_t o1_ro:1; + uint64_t o1_ns:1; + uint64_t o1_es:2; + uint64_t o2_ro:1; + uint64_t o2_ns:1; + uint64_t o2_es:2; + uint64_t o3_ro:1; + uint64_t o3_ns:1; + uint64_t o3_es:2; + uint64_t p0_bmode:1; + uint64_t p1_bmode:1; + uint64_t p2_bmode:1; + uint64_t p3_bmode:1; + uint64_t pkt_rr:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_npi_output_control_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t p0_bmode:1; uint64_t reserved_32_43:12; @@ -1110,8 +1864,25 @@ union cvmx_npi_output_control { uint64_t esr_sl0:2; uint64_t nsr_sl0:1; uint64_t ror_sl0:1; +#else + uint64_t ror_sl0:1; + uint64_t nsr_sl0:1; + uint64_t esr_sl0:2; + uint64_t reserved_4_15:12; + uint64_t iptr_o0:1; + uint64_t reserved_17_23:7; + uint64_t o0_csrm:1; + uint64_t reserved_25_27:3; + uint64_t o0_ro:1; + uint64_t o0_ns:1; + uint64_t o0_es:2; + uint64_t reserved_32_43:12; + uint64_t p0_bmode:1; + uint64_t reserved_45_63:19; +#endif } cn30xx; struct cvmx_npi_output_control_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_46_63:18; uint64_t p1_bmode:1; uint64_t p0_bmode:1; @@ -1135,9 +1906,35 @@ union cvmx_npi_output_control { uint64_t esr_sl0:2; uint64_t nsr_sl0:1; uint64_t ror_sl0:1; +#else + uint64_t ror_sl0:1; + uint64_t nsr_sl0:1; + uint64_t esr_sl0:2; + uint64_t ror_sl1:1; + uint64_t nsr_sl1:1; + uint64_t esr_sl1:2; + uint64_t reserved_8_15:8; + uint64_t iptr_o0:1; + uint64_t iptr_o1:1; + uint64_t reserved_18_23:6; + uint64_t o0_csrm:1; + uint64_t o1_csrm:1; + uint64_t reserved_26_27:2; + uint64_t o0_ro:1; + uint64_t o0_ns:1; + uint64_t o0_es:2; + uint64_t o1_ro:1; + uint64_t o1_ns:1; + uint64_t o1_es:2; + uint64_t reserved_36_43:8; + uint64_t p0_bmode:1; + uint64_t p1_bmode:1; + uint64_t reserved_46_63:18; +#endif } cn31xx; struct cvmx_npi_output_control_s cn38xx; struct cvmx_npi_output_control_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t p3_bmode:1; uint64_t p2_bmode:1; @@ -1176,8 +1973,49 @@ union cvmx_npi_output_control { uint64_t esr_sl0:2; uint64_t nsr_sl0:1; uint64_t ror_sl0:1; +#else + uint64_t ror_sl0:1; + uint64_t nsr_sl0:1; + uint64_t esr_sl0:2; + uint64_t ror_sl1:1; + uint64_t nsr_sl1:1; + uint64_t esr_sl1:2; + uint64_t ror_sl2:1; + uint64_t nsr_sl2:1; + uint64_t esr_sl2:2; + uint64_t ror_sl3:1; + uint64_t nsr_sl3:1; + uint64_t esr_sl3:2; + uint64_t iptr_o0:1; + uint64_t iptr_o1:1; + uint64_t iptr_o2:1; + uint64_t iptr_o3:1; + uint64_t reserved_20_23:4; + uint64_t o0_csrm:1; + uint64_t o1_csrm:1; + uint64_t o2_csrm:1; + uint64_t o3_csrm:1; + uint64_t o0_ro:1; + uint64_t o0_ns:1; + uint64_t o0_es:2; + uint64_t o1_ro:1; + uint64_t o1_ns:1; + uint64_t o1_es:2; + uint64_t o2_ro:1; + uint64_t o2_ns:1; + uint64_t o2_es:2; + uint64_t o3_ro:1; + uint64_t o3_ns:1; + uint64_t o3_es:2; + uint64_t p0_bmode:1; + uint64_t p1_bmode:1; + uint64_t p2_bmode:1; + uint64_t p3_bmode:1; + uint64_t reserved_48_63:16; +#endif } cn38xxp2; struct cvmx_npi_output_control_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t pkt_rr:1; uint64_t reserved_46_47:2; @@ -1203,6 +2041,33 @@ union cvmx_npi_output_control { uint64_t esr_sl0:2; uint64_t nsr_sl0:1; uint64_t ror_sl0:1; +#else + uint64_t ror_sl0:1; + uint64_t nsr_sl0:1; + uint64_t esr_sl0:2; + uint64_t ror_sl1:1; + uint64_t nsr_sl1:1; + uint64_t esr_sl1:2; + uint64_t reserved_8_15:8; + uint64_t iptr_o0:1; + uint64_t iptr_o1:1; + uint64_t reserved_18_23:6; + uint64_t o0_csrm:1; + uint64_t o1_csrm:1; + uint64_t reserved_26_27:2; + uint64_t o0_ro:1; + uint64_t o0_ns:1; + uint64_t o0_es:2; + uint64_t o1_ro:1; + uint64_t o1_ns:1; + uint64_t o1_es:2; + uint64_t reserved_36_43:8; + uint64_t p0_bmode:1; + uint64_t p1_bmode:1; + uint64_t reserved_46_47:2; + uint64_t pkt_rr:1; + uint64_t reserved_49_63:15; +#endif } cn50xx; struct cvmx_npi_output_control_s cn58xx; struct cvmx_npi_output_control_s cn58xxp1; @@ -1211,9 +2076,15 @@ union cvmx_npi_output_control { union cvmx_npi_px_dbpair_addr { uint64_t u64; struct cvmx_npi_px_dbpair_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_63_63:1; uint64_t state:2; uint64_t naddr:61; +#else + uint64_t naddr:61; + uint64_t state:2; + uint64_t reserved_63_63:1; +#endif } s; struct cvmx_npi_px_dbpair_addr_s cn30xx; struct cvmx_npi_px_dbpair_addr_s cn31xx; @@ -1227,8 +2098,13 @@ union cvmx_npi_px_dbpair_addr { union cvmx_npi_px_instr_addr { uint64_t u64; struct cvmx_npi_px_instr_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t state:3; uint64_t naddr:61; +#else + uint64_t naddr:61; + uint64_t state:3; +#endif } s; struct cvmx_npi_px_instr_addr_s cn30xx; struct cvmx_npi_px_instr_addr_s cn31xx; @@ -1242,9 +2118,15 @@ union cvmx_npi_px_instr_addr { union cvmx_npi_px_instr_cnts { uint64_t u64; struct cvmx_npi_px_instr_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t fcnt:6; uint64_t avail:32; +#else + uint64_t avail:32; + uint64_t fcnt:6; + uint64_t reserved_38_63:26; +#endif } s; struct cvmx_npi_px_instr_cnts_s cn30xx; struct cvmx_npi_px_instr_cnts_s cn31xx; @@ -1258,9 +2140,15 @@ union cvmx_npi_px_instr_cnts { union cvmx_npi_px_pair_cnts { uint64_t u64; struct cvmx_npi_px_pair_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t fcnt:5; uint64_t avail:32; +#else + uint64_t avail:32; + uint64_t fcnt:5; + uint64_t reserved_37_63:27; +#endif } s; struct cvmx_npi_px_pair_cnts_s cn30xx; struct cvmx_npi_px_pair_cnts_s cn31xx; @@ -1274,9 +2162,15 @@ union cvmx_npi_px_pair_cnts { union cvmx_npi_pci_burst_size { uint64_t u64; struct cvmx_npi_pci_burst_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t wr_brst:7; uint64_t rd_brst:7; +#else + uint64_t rd_brst:7; + uint64_t wr_brst:7; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_npi_pci_burst_size_s cn30xx; struct cvmx_npi_pci_burst_size_s cn31xx; @@ -1290,6 +2184,7 @@ union cvmx_npi_pci_burst_size { union cvmx_npi_pci_int_arb_cfg { uint64_t u64; struct cvmx_npi_pci_int_arb_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t hostmode:1; uint64_t pci_ovr:4; @@ -1297,12 +2192,28 @@ union cvmx_npi_pci_int_arb_cfg { uint64_t en:1; uint64_t park_mod:1; uint64_t park_dev:3; +#else + uint64_t park_dev:3; + uint64_t park_mod:1; + uint64_t en:1; + uint64_t reserved_5_7:3; + uint64_t pci_ovr:4; + uint64_t hostmode:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_npi_pci_int_arb_cfg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t en:1; uint64_t park_mod:1; uint64_t park_dev:3; +#else + uint64_t park_dev:3; + uint64_t park_mod:1; + uint64_t en:1; + uint64_t reserved_5_63:59; +#endif } cn30xx; struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx; struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx; @@ -1315,8 +2226,13 @@ union cvmx_npi_pci_int_arb_cfg { union cvmx_npi_pci_read_cmd { uint64_t u64; struct cvmx_npi_pci_read_cmd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t cmd_size:11; +#else + uint64_t cmd_size:11; + uint64_t reserved_11_63:53; +#endif } s; struct cvmx_npi_pci_read_cmd_s cn30xx; struct cvmx_npi_pci_read_cmd_s cn31xx; @@ -1330,6 +2246,7 @@ union cvmx_npi_pci_read_cmd { union cvmx_npi_port32_instr_hdr { uint64_t u64; struct cvmx_npi_port32_instr_hdr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t rsv_f:5; @@ -1343,6 +2260,21 @@ union cvmx_npi_port32_instr_hdr { uint64_t rsv_b:1; uint64_t skp_len:7; uint64_t rsv_a:6; +#else + uint64_t rsv_a:6; + uint64_t skp_len:7; + uint64_t rsv_b:1; + uint64_t par_mode:2; + uint64_t rsv_c:5; + uint64_t use_ihdr:1; + uint64_t rsv_d:6; + uint64_t rskp_len:7; + uint64_t rsv_e:1; + uint64_t rparmode:2; + uint64_t rsv_f:5; + uint64_t pbp:1; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_npi_port32_instr_hdr_s cn30xx; struct cvmx_npi_port32_instr_hdr_s cn31xx; @@ -1356,6 +2288,7 @@ union cvmx_npi_port32_instr_hdr { union cvmx_npi_port33_instr_hdr { uint64_t u64; struct cvmx_npi_port33_instr_hdr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t rsv_f:5; @@ -1369,6 +2302,21 @@ union cvmx_npi_port33_instr_hdr { uint64_t rsv_b:1; uint64_t skp_len:7; uint64_t rsv_a:6; +#else + uint64_t rsv_a:6; + uint64_t skp_len:7; + uint64_t rsv_b:1; + uint64_t par_mode:2; + uint64_t rsv_c:5; + uint64_t use_ihdr:1; + uint64_t rsv_d:6; + uint64_t rskp_len:7; + uint64_t rsv_e:1; + uint64_t rparmode:2; + uint64_t rsv_f:5; + uint64_t pbp:1; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_npi_port33_instr_hdr_s cn31xx; struct cvmx_npi_port33_instr_hdr_s cn38xx; @@ -1381,6 +2329,7 @@ union cvmx_npi_port33_instr_hdr { union cvmx_npi_port34_instr_hdr { uint64_t u64; struct cvmx_npi_port34_instr_hdr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t rsv_f:5; @@ -1394,6 +2343,21 @@ union cvmx_npi_port34_instr_hdr { uint64_t rsv_b:1; uint64_t skp_len:7; uint64_t rsv_a:6; +#else + uint64_t rsv_a:6; + uint64_t skp_len:7; + uint64_t rsv_b:1; + uint64_t par_mode:2; + uint64_t rsv_c:5; + uint64_t use_ihdr:1; + uint64_t rsv_d:6; + uint64_t rskp_len:7; + uint64_t rsv_e:1; + uint64_t rparmode:2; + uint64_t rsv_f:5; + uint64_t pbp:1; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_npi_port34_instr_hdr_s cn38xx; struct cvmx_npi_port34_instr_hdr_s cn38xxp2; @@ -1404,6 +2368,7 @@ union cvmx_npi_port34_instr_hdr { union cvmx_npi_port35_instr_hdr { uint64_t u64; struct cvmx_npi_port35_instr_hdr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t rsv_f:5; @@ -1417,6 +2382,21 @@ union cvmx_npi_port35_instr_hdr { uint64_t rsv_b:1; uint64_t skp_len:7; uint64_t rsv_a:6; +#else + uint64_t rsv_a:6; + uint64_t skp_len:7; + uint64_t rsv_b:1; + uint64_t par_mode:2; + uint64_t rsv_c:5; + uint64_t use_ihdr:1; + uint64_t rsv_d:6; + uint64_t rskp_len:7; + uint64_t rsv_e:1; + uint64_t rparmode:2; + uint64_t rsv_f:5; + uint64_t pbp:1; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_npi_port35_instr_hdr_s cn38xx; struct cvmx_npi_port35_instr_hdr_s cn38xxp2; @@ -1427,9 +2407,15 @@ union cvmx_npi_port35_instr_hdr { union cvmx_npi_port_bp_control { uint64_t u64; struct cvmx_npi_port_bp_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t bp_on:4; uint64_t enb:4; +#else + uint64_t enb:4; + uint64_t bp_on:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_npi_port_bp_control_s cn30xx; struct cvmx_npi_port_bp_control_s cn31xx; @@ -1443,6 +2429,7 @@ union cvmx_npi_port_bp_control { union cvmx_npi_rsl_int_blocks { uint64_t u64; struct cvmx_npi_rsl_int_blocks_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rint_31:1; uint64_t iob:1; @@ -1474,8 +2461,42 @@ union cvmx_npi_rsl_int_blocks { uint64_t gmx1:1; uint64_t gmx0:1; uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t npi:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t rint_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t reserved_13_14:2; + uint64_t rint_15:1; + uint64_t l2c:1; + uint64_t lmc:1; + uint64_t spx0:1; + uint64_t spx1:1; + uint64_t pip:1; + uint64_t rint_21:1; + uint64_t asx0:1; + uint64_t asx1:1; + uint64_t rint_24:1; + uint64_t rint_25:1; + uint64_t rint_26:1; + uint64_t rint_27:1; + uint64_t reserved_28_29:2; + uint64_t iob:1; + uint64_t rint_31:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npi_rsl_int_blocks_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rint_31:1; uint64_t iob:1; @@ -1509,9 +2530,45 @@ union cvmx_npi_rsl_int_blocks { uint64_t gmx1:1; uint64_t gmx0:1; uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t npi:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t rint_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rint_14:1; + uint64_t rint_15:1; + uint64_t l2c:1; + uint64_t lmc:1; + uint64_t spx0:1; + uint64_t spx1:1; + uint64_t pip:1; + uint64_t rint_21:1; + uint64_t asx0:1; + uint64_t asx1:1; + uint64_t rint_24:1; + uint64_t rint_25:1; + uint64_t rint_26:1; + uint64_t rint_27:1; + uint64_t rint_28:1; + uint64_t rint_29:1; + uint64_t iob:1; + uint64_t rint_31:1; + uint64_t reserved_32_63:32; +#endif } cn30xx; struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx; struct cvmx_npi_rsl_int_blocks_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rint_31:1; uint64_t iob:1; @@ -1545,9 +2602,45 @@ union cvmx_npi_rsl_int_blocks { uint64_t gmx1:1; uint64_t gmx0:1; uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t npi:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t rint_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t rint_13:1; + uint64_t rint_14:1; + uint64_t rint_15:1; + uint64_t l2c:1; + uint64_t lmc:1; + uint64_t spx0:1; + uint64_t spx1:1; + uint64_t pip:1; + uint64_t rint_21:1; + uint64_t asx0:1; + uint64_t asx1:1; + uint64_t rint_24:1; + uint64_t rint_25:1; + uint64_t rint_26:1; + uint64_t rint_27:1; + uint64_t rint_28:1; + uint64_t rint_29:1; + uint64_t iob:1; + uint64_t rint_31:1; + uint64_t reserved_32_63:32; +#endif } cn38xx; struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2; struct cvmx_npi_rsl_int_blocks_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t iob:1; uint64_t lmc1:1; @@ -1577,6 +2670,37 @@ union cvmx_npi_rsl_int_blocks { uint64_t gmx1:1; uint64_t gmx0:1; uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t npi:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t reserved_8_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rad:1; + uint64_t reserved_15_15:1; + uint64_t l2c:1; + uint64_t lmc:1; + uint64_t spx0:1; + uint64_t spx1:1; + uint64_t pip:1; + uint64_t reserved_21_21:1; + uint64_t asx0:1; + uint64_t asx1:1; + uint64_t reserved_24_27:4; + uint64_t agl:1; + uint64_t lmc1:1; + uint64_t iob:1; + uint64_t reserved_31_63:33; +#endif } cn50xx; struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx; struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1; @@ -1585,8 +2709,13 @@ union cvmx_npi_rsl_int_blocks { union cvmx_npi_size_inputx { uint64_t u64; struct cvmx_npi_size_inputx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t size:32; +#else + uint64_t size:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npi_size_inputx_s cn30xx; struct cvmx_npi_size_inputx_s cn31xx; @@ -1600,8 +2729,13 @@ union cvmx_npi_size_inputx { union cvmx_npi_win_read_to { uint64_t u64; struct cvmx_npi_win_read_to_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t time:32; +#else + uint64_t time:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npi_win_read_to_s cn30xx; struct cvmx_npi_win_read_to_s cn31xx; diff --git a/arch/mips/include/asm/octeon/cvmx-pci-defs.h b/arch/mips/include/asm/octeon/cvmx-pci-defs.h index 6ff6d9d357ba..25d603f18298 100644 --- a/arch/mips/include/asm/octeon/cvmx-pci-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pci-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -117,11 +117,19 @@ union cvmx_pci_bar1_indexx { uint32_t u32; struct cvmx_pci_bar1_indexx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_18_31:14; uint32_t addr_idx:14; uint32_t ca:1; uint32_t end_swp:2; uint32_t addr_v:1; +#else + uint32_t addr_v:1; + uint32_t end_swp:2; + uint32_t ca:1; + uint32_t addr_idx:14; + uint32_t reserved_18_31:14; +#endif } s; struct cvmx_pci_bar1_indexx_s cn30xx; struct cvmx_pci_bar1_indexx_s cn31xx; @@ -135,6 +143,7 @@ union cvmx_pci_bar1_indexx { union cvmx_pci_bist_reg { uint64_t u64; struct cvmx_pci_bist_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t rsp_bs:1; uint64_t dma0_bs:1; @@ -146,6 +155,19 @@ union cvmx_pci_bist_reg { uint64_t csr2n_bs:1; uint64_t dat2n_bs:1; uint64_t dbg2n_bs:1; +#else + uint64_t dbg2n_bs:1; + uint64_t dat2n_bs:1; + uint64_t csr2n_bs:1; + uint64_t rsp2p_bs:1; + uint64_t csrr_bs:1; + uint64_t csr2p_bs:1; + uint64_t cmd_bs:1; + uint64_t cmd0_bs:1; + uint64_t dma0_bs:1; + uint64_t rsp_bs:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_pci_bist_reg_s cn50xx; }; @@ -153,8 +175,13 @@ union cvmx_pci_bist_reg { union cvmx_pci_cfg00 { uint32_t u32; struct cvmx_pci_cfg00_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t devid:16; uint32_t vendid:16; +#else + uint32_t vendid:16; + uint32_t devid:16; +#endif } s; struct cvmx_pci_cfg00_s cn30xx; struct cvmx_pci_cfg00_s cn31xx; @@ -168,6 +195,7 @@ union cvmx_pci_cfg00 { union cvmx_pci_cfg01 { uint32_t u32; struct cvmx_pci_cfg01_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t dpe:1; uint32_t sse:1; uint32_t rma:1; @@ -192,6 +220,32 @@ union cvmx_pci_cfg01 { uint32_t me:1; uint32_t msae:1; uint32_t isae:1; +#else + uint32_t isae:1; + uint32_t msae:1; + uint32_t me:1; + uint32_t scse:1; + uint32_t mwice:1; + uint32_t vps:1; + uint32_t pee:1; + uint32_t ads:1; + uint32_t see:1; + uint32_t fbbe:1; + uint32_t i_dis:1; + uint32_t reserved_11_18:8; + uint32_t i_stat:1; + uint32_t cle:1; + uint32_t m66:1; + uint32_t reserved_22_22:1; + uint32_t fbb:1; + uint32_t mdpe:1; + uint32_t devt:2; + uint32_t sta:1; + uint32_t rta:1; + uint32_t rma:1; + uint32_t sse:1; + uint32_t dpe:1; +#endif } s; struct cvmx_pci_cfg01_s cn30xx; struct cvmx_pci_cfg01_s cn31xx; @@ -205,8 +259,13 @@ union cvmx_pci_cfg01 { union cvmx_pci_cfg02 { uint32_t u32; struct cvmx_pci_cfg02_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t cc:24; uint32_t rid:8; +#else + uint32_t rid:8; + uint32_t cc:24; +#endif } s; struct cvmx_pci_cfg02_s cn30xx; struct cvmx_pci_cfg02_s cn31xx; @@ -220,6 +279,7 @@ union cvmx_pci_cfg02 { union cvmx_pci_cfg03 { uint32_t u32; struct cvmx_pci_cfg03_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t bcap:1; uint32_t brb:1; uint32_t reserved_28_29:2; @@ -227,6 +287,15 @@ union cvmx_pci_cfg03 { uint32_t ht:8; uint32_t lt:8; uint32_t cls:8; +#else + uint32_t cls:8; + uint32_t lt:8; + uint32_t ht:8; + uint32_t bcod:4; + uint32_t reserved_28_29:2; + uint32_t brb:1; + uint32_t bcap:1; +#endif } s; struct cvmx_pci_cfg03_s cn30xx; struct cvmx_pci_cfg03_s cn31xx; @@ -240,11 +309,19 @@ union cvmx_pci_cfg03 { union cvmx_pci_cfg04 { uint32_t u32; struct cvmx_pci_cfg04_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t lbase:20; uint32_t lbasez:8; uint32_t pf:1; uint32_t typ:2; uint32_t mspc:1; +#else + uint32_t mspc:1; + uint32_t typ:2; + uint32_t pf:1; + uint32_t lbasez:8; + uint32_t lbase:20; +#endif } s; struct cvmx_pci_cfg04_s cn30xx; struct cvmx_pci_cfg04_s cn31xx; @@ -258,7 +335,11 @@ union cvmx_pci_cfg04 { union cvmx_pci_cfg05 { uint32_t u32; struct cvmx_pci_cfg05_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t hbase:32; +#else uint32_t hbase:32; +#endif } s; struct cvmx_pci_cfg05_s cn30xx; struct cvmx_pci_cfg05_s cn31xx; @@ -272,11 +353,19 @@ union cvmx_pci_cfg05 { union cvmx_pci_cfg06 { uint32_t u32; struct cvmx_pci_cfg06_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t lbase:5; uint32_t lbasez:23; uint32_t pf:1; uint32_t typ:2; uint32_t mspc:1; +#else + uint32_t mspc:1; + uint32_t typ:2; + uint32_t pf:1; + uint32_t lbasez:23; + uint32_t lbase:5; +#endif } s; struct cvmx_pci_cfg06_s cn30xx; struct cvmx_pci_cfg06_s cn31xx; @@ -290,7 +379,11 @@ union cvmx_pci_cfg06 { union cvmx_pci_cfg07 { uint32_t u32; struct cvmx_pci_cfg07_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t hbase:32; +#else uint32_t hbase:32; +#endif } s; struct cvmx_pci_cfg07_s cn30xx; struct cvmx_pci_cfg07_s cn31xx; @@ -304,10 +397,17 @@ union cvmx_pci_cfg07 { union cvmx_pci_cfg08 { uint32_t u32; struct cvmx_pci_cfg08_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t lbasez:28; uint32_t pf:1; uint32_t typ:2; uint32_t mspc:1; +#else + uint32_t mspc:1; + uint32_t typ:2; + uint32_t pf:1; + uint32_t lbasez:28; +#endif } s; struct cvmx_pci_cfg08_s cn30xx; struct cvmx_pci_cfg08_s cn31xx; @@ -321,8 +421,13 @@ union cvmx_pci_cfg08 { union cvmx_pci_cfg09 { uint32_t u32; struct cvmx_pci_cfg09_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t hbase:25; uint32_t hbasez:7; +#else + uint32_t hbasez:7; + uint32_t hbase:25; +#endif } s; struct cvmx_pci_cfg09_s cn30xx; struct cvmx_pci_cfg09_s cn31xx; @@ -336,7 +441,11 @@ union cvmx_pci_cfg09 { union cvmx_pci_cfg10 { uint32_t u32; struct cvmx_pci_cfg10_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t cisp:32; +#else uint32_t cisp:32; +#endif } s; struct cvmx_pci_cfg10_s cn30xx; struct cvmx_pci_cfg10_s cn31xx; @@ -350,8 +459,13 @@ union cvmx_pci_cfg10 { union cvmx_pci_cfg11 { uint32_t u32; struct cvmx_pci_cfg11_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t ssid:16; uint32_t ssvid:16; +#else + uint32_t ssvid:16; + uint32_t ssid:16; +#endif } s; struct cvmx_pci_cfg11_s cn30xx; struct cvmx_pci_cfg11_s cn31xx; @@ -365,10 +479,17 @@ union cvmx_pci_cfg11 { union cvmx_pci_cfg12 { uint32_t u32; struct cvmx_pci_cfg12_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t erbar:16; uint32_t erbarz:5; uint32_t reserved_1_10:10; uint32_t erbar_en:1; +#else + uint32_t erbar_en:1; + uint32_t reserved_1_10:10; + uint32_t erbarz:5; + uint32_t erbar:16; +#endif } s; struct cvmx_pci_cfg12_s cn30xx; struct cvmx_pci_cfg12_s cn31xx; @@ -382,8 +503,13 @@ union cvmx_pci_cfg12 { union cvmx_pci_cfg13 { uint32_t u32; struct cvmx_pci_cfg13_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_8_31:24; uint32_t cp:8; +#else + uint32_t cp:8; + uint32_t reserved_8_31:24; +#endif } s; struct cvmx_pci_cfg13_s cn30xx; struct cvmx_pci_cfg13_s cn31xx; @@ -397,10 +523,17 @@ union cvmx_pci_cfg13 { union cvmx_pci_cfg15 { uint32_t u32; struct cvmx_pci_cfg15_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t ml:8; uint32_t mg:8; uint32_t inta:8; uint32_t il:8; +#else + uint32_t il:8; + uint32_t inta:8; + uint32_t mg:8; + uint32_t ml:8; +#endif } s; struct cvmx_pci_cfg15_s cn30xx; struct cvmx_pci_cfg15_s cn31xx; @@ -414,6 +547,7 @@ union cvmx_pci_cfg15 { union cvmx_pci_cfg16 { uint32_t u32; struct cvmx_pci_cfg16_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t trdnpr:1; uint32_t trdard:1; uint32_t rdsati:1; @@ -430,6 +564,24 @@ union cvmx_pci_cfg16 { uint32_t reserved_2_2:1; uint32_t tswc:1; uint32_t mltd:1; +#else + uint32_t mltd:1; + uint32_t tswc:1; + uint32_t reserved_2_2:1; + uint32_t dppmr:1; + uint32_t pbe:12; + uint32_t tilt:4; + uint32_t tslte:3; + uint32_t tmae:1; + uint32_t twtae:1; + uint32_t twsen:1; + uint32_t twsei:1; + uint32_t trtae:1; + uint32_t trdrs:1; + uint32_t rdsati:1; + uint32_t trdard:1; + uint32_t trdnpr:1; +#endif } s; struct cvmx_pci_cfg16_s cn30xx; struct cvmx_pci_cfg16_s cn31xx; @@ -443,7 +595,11 @@ union cvmx_pci_cfg16 { union cvmx_pci_cfg17 { uint32_t u32; struct cvmx_pci_cfg17_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t tscme:32; +#else + uint32_t tscme:32; +#endif } s; struct cvmx_pci_cfg17_s cn30xx; struct cvmx_pci_cfg17_s cn31xx; @@ -457,7 +613,11 @@ union cvmx_pci_cfg17 { union cvmx_pci_cfg18 { uint32_t u32; struct cvmx_pci_cfg18_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t tdsrps:32; +#else uint32_t tdsrps:32; +#endif } s; struct cvmx_pci_cfg18_s cn30xx; struct cvmx_pci_cfg18_s cn31xx; @@ -471,6 +631,7 @@ union cvmx_pci_cfg18 { union cvmx_pci_cfg19 { uint32_t u32; struct cvmx_pci_cfg19_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t mrbcm:1; uint32_t mrbci:1; uint32_t mdwe:1; @@ -489,6 +650,26 @@ union cvmx_pci_cfg19 { uint32_t reserved_6_6:1; uint32_t tidomc:1; uint32_t tdomc:5; +#else + uint32_t tdomc:5; + uint32_t tidomc:1; + uint32_t reserved_6_6:1; + uint32_t tibde:1; + uint32_t tibcd:1; + uint32_t reserved_9_10:2; + uint32_t tmapes:1; + uint32_t tmdpes:1; + uint32_t tmse:1; + uint32_t tmei:1; + uint32_t teci:1; + uint32_t tmes:8; + uint32_t mdrrmc:3; + uint32_t mdrimc:1; + uint32_t mdre:1; + uint32_t mdwe:1; + uint32_t mrbci:1; + uint32_t mrbcm:1; +#endif } s; struct cvmx_pci_cfg19_s cn30xx; struct cvmx_pci_cfg19_s cn31xx; @@ -502,7 +683,11 @@ union cvmx_pci_cfg19 { union cvmx_pci_cfg20 { uint32_t u32; struct cvmx_pci_cfg20_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t mdsp:32; +#else + uint32_t mdsp:32; +#endif } s; struct cvmx_pci_cfg20_s cn30xx; struct cvmx_pci_cfg20_s cn31xx; @@ -516,7 +701,11 @@ union cvmx_pci_cfg20 { union cvmx_pci_cfg21 { uint32_t u32; struct cvmx_pci_cfg21_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t scmre:32; +#else uint32_t scmre:32; +#endif } s; struct cvmx_pci_cfg21_s cn30xx; struct cvmx_pci_cfg21_s cn31xx; @@ -530,6 +719,7 @@ union cvmx_pci_cfg21 { union cvmx_pci_cfg22 { uint32_t u32; struct cvmx_pci_cfg22_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t mac:7; uint32_t reserved_19_24:6; uint32_t flush:1; @@ -537,6 +727,15 @@ union cvmx_pci_cfg22 { uint32_t mtta:1; uint32_t mrv:8; uint32_t mttv:8; +#else + uint32_t mttv:8; + uint32_t mrv:8; + uint32_t mtta:1; + uint32_t mra:1; + uint32_t flush:1; + uint32_t reserved_19_24:6; + uint32_t mac:7; +#endif } s; struct cvmx_pci_cfg22_s cn30xx; struct cvmx_pci_cfg22_s cn31xx; @@ -550,6 +749,7 @@ union cvmx_pci_cfg22 { union cvmx_pci_cfg56 { uint32_t u32; struct cvmx_pci_cfg56_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_23_31:9; uint32_t most:3; uint32_t mmbc:2; @@ -557,6 +757,15 @@ union cvmx_pci_cfg56 { uint32_t dpere:1; uint32_t ncp:8; uint32_t pxcid:8; +#else + uint32_t pxcid:8; + uint32_t ncp:8; + uint32_t dpere:1; + uint32_t roe:1; + uint32_t mmbc:2; + uint32_t most:3; + uint32_t reserved_23_31:9; +#endif } s; struct cvmx_pci_cfg56_s cn30xx; struct cvmx_pci_cfg56_s cn31xx; @@ -570,6 +779,7 @@ union cvmx_pci_cfg56 { union cvmx_pci_cfg57 { uint32_t u32; struct cvmx_pci_cfg57_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_30_31:2; uint32_t scemr:1; uint32_t mcrsd:3; @@ -583,6 +793,21 @@ union cvmx_pci_cfg57 { uint32_t bn:8; uint32_t dn:5; uint32_t fn:3; +#else + uint32_t fn:3; + uint32_t dn:5; + uint32_t bn:8; + uint32_t w64:1; + uint32_t m133:1; + uint32_t scd:1; + uint32_t usc:1; + uint32_t dc:1; + uint32_t mmrbcd:2; + uint32_t mostd:3; + uint32_t mcrsd:3; + uint32_t scemr:1; + uint32_t reserved_30_31:2; +#endif } s; struct cvmx_pci_cfg57_s cn30xx; struct cvmx_pci_cfg57_s cn31xx; @@ -596,6 +821,7 @@ union cvmx_pci_cfg57 { union cvmx_pci_cfg58 { uint32_t u32; struct cvmx_pci_cfg58_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pmes:5; uint32_t d2s:1; uint32_t d1s:1; @@ -606,6 +832,18 @@ union cvmx_pci_cfg58 { uint32_t pcimiv:3; uint32_t ncp:8; uint32_t pmcid:8; +#else + uint32_t pmcid:8; + uint32_t ncp:8; + uint32_t pcimiv:3; + uint32_t pmec:1; + uint32_t reserved_20_20:1; + uint32_t dsi:1; + uint32_t auxc:3; + uint32_t d1s:1; + uint32_t d2s:1; + uint32_t pmes:5; +#endif } s; struct cvmx_pci_cfg58_s cn30xx; struct cvmx_pci_cfg58_s cn31xx; @@ -619,6 +857,7 @@ union cvmx_pci_cfg58 { union cvmx_pci_cfg59 { uint32_t u32; struct cvmx_pci_cfg59_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pmdia:8; uint32_t bpccen:1; uint32_t bd3h:1; @@ -629,6 +868,18 @@ union cvmx_pci_cfg59 { uint32_t pmeens:1; uint32_t reserved_2_7:6; uint32_t ps:2; +#else + uint32_t ps:2; + uint32_t reserved_2_7:6; + uint32_t pmeens:1; + uint32_t pmds:4; + uint32_t pmedsia:2; + uint32_t pmess:1; + uint32_t reserved_16_21:6; + uint32_t bd3h:1; + uint32_t bpccen:1; + uint32_t pmdia:8; +#endif } s; struct cvmx_pci_cfg59_s cn30xx; struct cvmx_pci_cfg59_s cn31xx; @@ -642,6 +893,7 @@ union cvmx_pci_cfg59 { union cvmx_pci_cfg60 { uint32_t u32; struct cvmx_pci_cfg60_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_24_31:8; uint32_t m64:1; uint32_t mme:3; @@ -649,6 +901,15 @@ union cvmx_pci_cfg60 { uint32_t msien:1; uint32_t ncp:8; uint32_t msicid:8; +#else + uint32_t msicid:8; + uint32_t ncp:8; + uint32_t msien:1; + uint32_t mmc:3; + uint32_t mme:3; + uint32_t m64:1; + uint32_t reserved_24_31:8; +#endif } s; struct cvmx_pci_cfg60_s cn30xx; struct cvmx_pci_cfg60_s cn31xx; @@ -662,8 +923,13 @@ union cvmx_pci_cfg60 { union cvmx_pci_cfg61 { uint32_t u32; struct cvmx_pci_cfg61_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t msi31t2:30; uint32_t reserved_0_1:2; +#else + uint32_t reserved_0_1:2; + uint32_t msi31t2:30; +#endif } s; struct cvmx_pci_cfg61_s cn30xx; struct cvmx_pci_cfg61_s cn31xx; @@ -677,7 +943,11 @@ union cvmx_pci_cfg61 { union cvmx_pci_cfg62 { uint32_t u32; struct cvmx_pci_cfg62_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t msi:32; +#else + uint32_t msi:32; +#endif } s; struct cvmx_pci_cfg62_s cn30xx; struct cvmx_pci_cfg62_s cn31xx; @@ -691,8 +961,13 @@ union cvmx_pci_cfg62 { union cvmx_pci_cfg63 { uint32_t u32; struct cvmx_pci_cfg63_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_16_31:16; uint32_t msimd:16; +#else + uint32_t msimd:16; + uint32_t reserved_16_31:16; +#endif } s; struct cvmx_pci_cfg63_s cn30xx; struct cvmx_pci_cfg63_s cn31xx; @@ -706,12 +981,21 @@ union cvmx_pci_cfg63 { union cvmx_pci_cnt_reg { uint64_t u64; struct cvmx_pci_cnt_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t hm_pcix:1; uint64_t hm_speed:2; uint64_t ap_pcix:1; uint64_t ap_speed:2; uint64_t pcicnt:32; +#else + uint64_t pcicnt:32; + uint64_t ap_speed:2; + uint64_t ap_pcix:1; + uint64_t hm_speed:2; + uint64_t hm_pcix:1; + uint64_t reserved_38_63:26; +#endif } s; struct cvmx_pci_cnt_reg_s cn50xx; struct cvmx_pci_cnt_reg_s cn58xx; @@ -721,6 +1005,7 @@ union cvmx_pci_cnt_reg { union cvmx_pci_ctl_status_2 { uint32_t u32; struct cvmx_pci_ctl_status_2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_29_31:3; uint32_t bb1_hole:3; uint32_t bb1_siz:1; @@ -743,9 +1028,34 @@ union cvmx_pci_ctl_status_2 { uint32_t bar2_enb:1; uint32_t bar2_esx:2; uint32_t bar2_cax:1; +#else + uint32_t bar2_cax:1; + uint32_t bar2_esx:2; + uint32_t bar2_enb:1; + uint32_t tsr_hwm:3; + uint32_t pmo_fpc:3; + uint32_t pmo_amod:1; + uint32_t b12_bist:1; + uint32_t ap_64ad:1; + uint32_t ap_pcix:1; + uint32_t reserved_14_14:1; + uint32_t en_wfilt:1; + uint32_t scm:1; + uint32_t scmtyp:1; + uint32_t bar2pres:1; + uint32_t erst_n:1; + uint32_t bb0:1; + uint32_t bb1:1; + uint32_t bb_es:2; + uint32_t bb_ca:1; + uint32_t bb1_siz:1; + uint32_t bb1_hole:3; + uint32_t reserved_29_31:3; +#endif } s; struct cvmx_pci_ctl_status_2_s cn30xx; struct cvmx_pci_ctl_status_2_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_20_31:12; uint32_t erst_n:1; uint32_t bar2pres:1; @@ -762,6 +1072,24 @@ union cvmx_pci_ctl_status_2 { uint32_t bar2_enb:1; uint32_t bar2_esx:2; uint32_t bar2_cax:1; +#else + uint32_t bar2_cax:1; + uint32_t bar2_esx:2; + uint32_t bar2_enb:1; + uint32_t tsr_hwm:3; + uint32_t pmo_fpc:3; + uint32_t pmo_amod:1; + uint32_t b12_bist:1; + uint32_t ap_64ad:1; + uint32_t ap_pcix:1; + uint32_t reserved_14_14:1; + uint32_t en_wfilt:1; + uint32_t scm:1; + uint32_t scmtyp:1; + uint32_t bar2pres:1; + uint32_t erst_n:1; + uint32_t reserved_20_31:12; +#endif } cn31xx; struct cvmx_pci_ctl_status_2_s cn38xx; struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2; @@ -773,8 +1101,13 @@ union cvmx_pci_ctl_status_2 { union cvmx_pci_dbellx { uint32_t u32; struct cvmx_pci_dbellx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_16_31:16; uint32_t inc_val:16; +#else + uint32_t inc_val:16; + uint32_t reserved_16_31:16; +#endif } s; struct cvmx_pci_dbellx_s cn30xx; struct cvmx_pci_dbellx_s cn31xx; @@ -788,7 +1121,11 @@ union cvmx_pci_dbellx { union cvmx_pci_dma_cntx { uint32_t u32; struct cvmx_pci_dma_cntx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t dma_cnt:32; +#else uint32_t dma_cnt:32; +#endif } s; struct cvmx_pci_dma_cntx_s cn30xx; struct cvmx_pci_dma_cntx_s cn31xx; @@ -802,7 +1139,11 @@ union cvmx_pci_dma_cntx { union cvmx_pci_dma_int_levx { uint32_t u32; struct cvmx_pci_dma_int_levx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pkt_cnt:32; +#else + uint32_t pkt_cnt:32; +#endif } s; struct cvmx_pci_dma_int_levx_s cn30xx; struct cvmx_pci_dma_int_levx_s cn31xx; @@ -816,7 +1157,11 @@ union cvmx_pci_dma_int_levx { union cvmx_pci_dma_timex { uint32_t u32; struct cvmx_pci_dma_timex_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t dma_time:32; +#else uint32_t dma_time:32; +#endif } s; struct cvmx_pci_dma_timex_s cn30xx; struct cvmx_pci_dma_timex_s cn31xx; @@ -830,7 +1175,11 @@ union cvmx_pci_dma_timex { union cvmx_pci_instr_countx { uint32_t u32; struct cvmx_pci_instr_countx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t icnt:32; +#else uint32_t icnt:32; +#endif } s; struct cvmx_pci_instr_countx_s cn30xx; struct cvmx_pci_instr_countx_s cn31xx; @@ -844,6 +1193,7 @@ union cvmx_pci_instr_countx { union cvmx_pci_int_enb { uint64_t u64; struct cvmx_pci_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -879,8 +1229,46 @@ union cvmx_pci_int_enb { uint64_t imr_wtto:1; uint64_t imr_wabt:1; uint64_t itr_wabt:1; +#else + uint64_t itr_wabt:1; + uint64_t imr_wabt:1; + uint64_t imr_wtto:1; + uint64_t itr_abt:1; + uint64_t imr_abt:1; + uint64_t imr_tto:1; + uint64_t imsi_per:1; + uint64_t imsi_tabt:1; + uint64_t imsi_mabt:1; + uint64_t imsc_msg:1; + uint64_t itsr_abt:1; + uint64_t iserr:1; + uint64_t iaperr:1; + uint64_t idperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t irsl_int:1; + uint64_t ipcnt0:1; + uint64_t ipcnt1:1; + uint64_t ipcnt2:1; + uint64_t ipcnt3:1; + uint64_t iptime0:1; + uint64_t iptime1:1; + uint64_t iptime2:1; + uint64_t iptime3:1; + uint64_t idcnt0:1; + uint64_t idcnt1:1; + uint64_t idtime0:1; + uint64_t idtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_pci_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -912,8 +1300,42 @@ union cvmx_pci_int_enb { uint64_t imr_wtto:1; uint64_t imr_wabt:1; uint64_t itr_wabt:1; +#else + uint64_t itr_wabt:1; + uint64_t imr_wabt:1; + uint64_t imr_wtto:1; + uint64_t itr_abt:1; + uint64_t imr_abt:1; + uint64_t imr_tto:1; + uint64_t imsi_per:1; + uint64_t imsi_tabt:1; + uint64_t imsi_mabt:1; + uint64_t imsc_msg:1; + uint64_t itsr_abt:1; + uint64_t iserr:1; + uint64_t iaperr:1; + uint64_t idperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t irsl_int:1; + uint64_t ipcnt0:1; + uint64_t reserved_18_20:3; + uint64_t iptime0:1; + uint64_t reserved_22_24:3; + uint64_t idcnt0:1; + uint64_t idcnt1:1; + uint64_t idtime0:1; + uint64_t idtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn30xx; struct cvmx_pci_int_enb_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -947,6 +1369,41 @@ union cvmx_pci_int_enb { uint64_t imr_wtto:1; uint64_t imr_wabt:1; uint64_t itr_wabt:1; +#else + uint64_t itr_wabt:1; + uint64_t imr_wabt:1; + uint64_t imr_wtto:1; + uint64_t itr_abt:1; + uint64_t imr_abt:1; + uint64_t imr_tto:1; + uint64_t imsi_per:1; + uint64_t imsi_tabt:1; + uint64_t imsi_mabt:1; + uint64_t imsc_msg:1; + uint64_t itsr_abt:1; + uint64_t iserr:1; + uint64_t iaperr:1; + uint64_t idperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t irsl_int:1; + uint64_t ipcnt0:1; + uint64_t ipcnt1:1; + uint64_t reserved_19_20:2; + uint64_t iptime0:1; + uint64_t iptime1:1; + uint64_t reserved_23_24:2; + uint64_t idcnt0:1; + uint64_t idcnt1:1; + uint64_t idtime0:1; + uint64_t idtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn31xx; struct cvmx_pci_int_enb_s cn38xx; struct cvmx_pci_int_enb_s cn38xxp2; @@ -958,6 +1415,7 @@ union cvmx_pci_int_enb { union cvmx_pci_int_enb2 { uint64_t u64; struct cvmx_pci_int_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -993,8 +1451,46 @@ union cvmx_pci_int_enb2 { uint64_t rmr_wtto:1; uint64_t rmr_wabt:1; uint64_t rtr_wabt:1; +#else + uint64_t rtr_wabt:1; + uint64_t rmr_wabt:1; + uint64_t rmr_wtto:1; + uint64_t rtr_abt:1; + uint64_t rmr_abt:1; + uint64_t rmr_tto:1; + uint64_t rmsi_per:1; + uint64_t rmsi_tabt:1; + uint64_t rmsi_mabt:1; + uint64_t rmsc_msg:1; + uint64_t rtsr_abt:1; + uint64_t rserr:1; + uint64_t raperr:1; + uint64_t rdperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rrsl_int:1; + uint64_t rpcnt0:1; + uint64_t rpcnt1:1; + uint64_t rpcnt2:1; + uint64_t rpcnt3:1; + uint64_t rptime0:1; + uint64_t rptime1:1; + uint64_t rptime2:1; + uint64_t rptime3:1; + uint64_t rdcnt0:1; + uint64_t rdcnt1:1; + uint64_t rdtime0:1; + uint64_t rdtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_pci_int_enb2_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1026,8 +1522,42 @@ union cvmx_pci_int_enb2 { uint64_t rmr_wtto:1; uint64_t rmr_wabt:1; uint64_t rtr_wabt:1; +#else + uint64_t rtr_wabt:1; + uint64_t rmr_wabt:1; + uint64_t rmr_wtto:1; + uint64_t rtr_abt:1; + uint64_t rmr_abt:1; + uint64_t rmr_tto:1; + uint64_t rmsi_per:1; + uint64_t rmsi_tabt:1; + uint64_t rmsi_mabt:1; + uint64_t rmsc_msg:1; + uint64_t rtsr_abt:1; + uint64_t rserr:1; + uint64_t raperr:1; + uint64_t rdperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rrsl_int:1; + uint64_t rpcnt0:1; + uint64_t reserved_18_20:3; + uint64_t rptime0:1; + uint64_t reserved_22_24:3; + uint64_t rdcnt0:1; + uint64_t rdcnt1:1; + uint64_t rdtime0:1; + uint64_t rdtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn30xx; struct cvmx_pci_int_enb2_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1061,6 +1591,41 @@ union cvmx_pci_int_enb2 { uint64_t rmr_wtto:1; uint64_t rmr_wabt:1; uint64_t rtr_wabt:1; +#else + uint64_t rtr_wabt:1; + uint64_t rmr_wabt:1; + uint64_t rmr_wtto:1; + uint64_t rtr_abt:1; + uint64_t rmr_abt:1; + uint64_t rmr_tto:1; + uint64_t rmsi_per:1; + uint64_t rmsi_tabt:1; + uint64_t rmsi_mabt:1; + uint64_t rmsc_msg:1; + uint64_t rtsr_abt:1; + uint64_t rserr:1; + uint64_t raperr:1; + uint64_t rdperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rrsl_int:1; + uint64_t rpcnt0:1; + uint64_t rpcnt1:1; + uint64_t reserved_19_20:2; + uint64_t rptime0:1; + uint64_t rptime1:1; + uint64_t reserved_23_24:2; + uint64_t rdcnt0:1; + uint64_t rdcnt1:1; + uint64_t rdtime0:1; + uint64_t rdtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn31xx; struct cvmx_pci_int_enb2_s cn38xx; struct cvmx_pci_int_enb2_s cn38xxp2; @@ -1072,6 +1637,7 @@ union cvmx_pci_int_enb2 { union cvmx_pci_int_sum { uint64_t u64; struct cvmx_pci_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1107,8 +1673,46 @@ union cvmx_pci_int_sum { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; +#else + uint64_t tr_wabt:1; + uint64_t mr_wabt:1; + uint64_t mr_wtto:1; + uint64_t tr_abt:1; + uint64_t mr_abt:1; + uint64_t mr_tto:1; + uint64_t msi_per:1; + uint64_t msi_tabt:1; + uint64_t msi_mabt:1; + uint64_t msc_msg:1; + uint64_t tsr_abt:1; + uint64_t serr:1; + uint64_t aperr:1; + uint64_t dperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rsl_int:1; + uint64_t pcnt0:1; + uint64_t pcnt1:1; + uint64_t pcnt2:1; + uint64_t pcnt3:1; + uint64_t ptime0:1; + uint64_t ptime1:1; + uint64_t ptime2:1; + uint64_t ptime3:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_pci_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1140,8 +1744,42 @@ union cvmx_pci_int_sum { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; +#else + uint64_t tr_wabt:1; + uint64_t mr_wabt:1; + uint64_t mr_wtto:1; + uint64_t tr_abt:1; + uint64_t mr_abt:1; + uint64_t mr_tto:1; + uint64_t msi_per:1; + uint64_t msi_tabt:1; + uint64_t msi_mabt:1; + uint64_t msc_msg:1; + uint64_t tsr_abt:1; + uint64_t serr:1; + uint64_t aperr:1; + uint64_t dperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rsl_int:1; + uint64_t pcnt0:1; + uint64_t reserved_18_20:3; + uint64_t ptime0:1; + uint64_t reserved_22_24:3; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn30xx; struct cvmx_pci_int_sum_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1175,6 +1813,41 @@ union cvmx_pci_int_sum { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; +#else + uint64_t tr_wabt:1; + uint64_t mr_wabt:1; + uint64_t mr_wtto:1; + uint64_t tr_abt:1; + uint64_t mr_abt:1; + uint64_t mr_tto:1; + uint64_t msi_per:1; + uint64_t msi_tabt:1; + uint64_t msi_mabt:1; + uint64_t msc_msg:1; + uint64_t tsr_abt:1; + uint64_t serr:1; + uint64_t aperr:1; + uint64_t dperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rsl_int:1; + uint64_t pcnt0:1; + uint64_t pcnt1:1; + uint64_t reserved_19_20:2; + uint64_t ptime0:1; + uint64_t ptime1:1; + uint64_t reserved_23_24:2; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn31xx; struct cvmx_pci_int_sum_s cn38xx; struct cvmx_pci_int_sum_s cn38xxp2; @@ -1186,6 +1859,7 @@ union cvmx_pci_int_sum { union cvmx_pci_int_sum2 { uint64_t u64; struct cvmx_pci_int_sum2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1221,8 +1895,46 @@ union cvmx_pci_int_sum2 { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; +#else + uint64_t tr_wabt:1; + uint64_t mr_wabt:1; + uint64_t mr_wtto:1; + uint64_t tr_abt:1; + uint64_t mr_abt:1; + uint64_t mr_tto:1; + uint64_t msi_per:1; + uint64_t msi_tabt:1; + uint64_t msi_mabt:1; + uint64_t msc_msg:1; + uint64_t tsr_abt:1; + uint64_t serr:1; + uint64_t aperr:1; + uint64_t dperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rsl_int:1; + uint64_t pcnt0:1; + uint64_t pcnt1:1; + uint64_t pcnt2:1; + uint64_t pcnt3:1; + uint64_t ptime0:1; + uint64_t ptime1:1; + uint64_t ptime2:1; + uint64_t ptime3:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_pci_int_sum2_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1254,8 +1966,42 @@ union cvmx_pci_int_sum2 { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; +#else + uint64_t tr_wabt:1; + uint64_t mr_wabt:1; + uint64_t mr_wtto:1; + uint64_t tr_abt:1; + uint64_t mr_abt:1; + uint64_t mr_tto:1; + uint64_t msi_per:1; + uint64_t msi_tabt:1; + uint64_t msi_mabt:1; + uint64_t msc_msg:1; + uint64_t tsr_abt:1; + uint64_t serr:1; + uint64_t aperr:1; + uint64_t dperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rsl_int:1; + uint64_t pcnt0:1; + uint64_t reserved_18_20:3; + uint64_t ptime0:1; + uint64_t reserved_22_24:3; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn30xx; struct cvmx_pci_int_sum2_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1289,6 +2035,41 @@ union cvmx_pci_int_sum2 { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; +#else + uint64_t tr_wabt:1; + uint64_t mr_wabt:1; + uint64_t mr_wtto:1; + uint64_t tr_abt:1; + uint64_t mr_abt:1; + uint64_t mr_tto:1; + uint64_t msi_per:1; + uint64_t msi_tabt:1; + uint64_t msi_mabt:1; + uint64_t msc_msg:1; + uint64_t tsr_abt:1; + uint64_t serr:1; + uint64_t aperr:1; + uint64_t dperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rsl_int:1; + uint64_t pcnt0:1; + uint64_t pcnt1:1; + uint64_t reserved_19_20:2; + uint64_t ptime0:1; + uint64_t ptime1:1; + uint64_t reserved_23_24:2; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn31xx; struct cvmx_pci_int_sum2_s cn38xx; struct cvmx_pci_int_sum2_s cn38xxp2; @@ -1300,8 +2081,13 @@ union cvmx_pci_int_sum2 { union cvmx_pci_msi_rcv { uint32_t u32; struct cvmx_pci_msi_rcv_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_6_31:26; uint32_t intr:6; +#else + uint32_t intr:6; + uint32_t reserved_6_31:26; +#endif } s; struct cvmx_pci_msi_rcv_s cn30xx; struct cvmx_pci_msi_rcv_s cn31xx; @@ -1315,8 +2101,13 @@ union cvmx_pci_msi_rcv { union cvmx_pci_pkt_creditsx { uint32_t u32; struct cvmx_pci_pkt_creditsx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pkt_cnt:16; uint32_t ptr_cnt:16; +#else + uint32_t ptr_cnt:16; + uint32_t pkt_cnt:16; +#endif } s; struct cvmx_pci_pkt_creditsx_s cn30xx; struct cvmx_pci_pkt_creditsx_s cn31xx; @@ -1330,7 +2121,11 @@ union cvmx_pci_pkt_creditsx { union cvmx_pci_pkts_sentx { uint32_t u32; struct cvmx_pci_pkts_sentx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pkt_cnt:32; +#else + uint32_t pkt_cnt:32; +#endif } s; struct cvmx_pci_pkts_sentx_s cn30xx; struct cvmx_pci_pkts_sentx_s cn31xx; @@ -1344,7 +2139,11 @@ union cvmx_pci_pkts_sentx { union cvmx_pci_pkts_sent_int_levx { uint32_t u32; struct cvmx_pci_pkts_sent_int_levx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t pkt_cnt:32; +#else uint32_t pkt_cnt:32; +#endif } s; struct cvmx_pci_pkts_sent_int_levx_s cn30xx; struct cvmx_pci_pkts_sent_int_levx_s cn31xx; @@ -1358,7 +2157,11 @@ union cvmx_pci_pkts_sent_int_levx { union cvmx_pci_pkts_sent_timex { uint32_t u32; struct cvmx_pci_pkts_sent_timex_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t pkt_time:32; +#else uint32_t pkt_time:32; +#endif } s; struct cvmx_pci_pkts_sent_timex_s cn30xx; struct cvmx_pci_pkts_sent_timex_s cn31xx; @@ -1372,9 +2175,15 @@ union cvmx_pci_pkts_sent_timex { union cvmx_pci_read_cmd_6 { uint32_t u32; struct cvmx_pci_read_cmd_6_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_9_31:23; uint32_t min_data:6; uint32_t prefetch:3; +#else + uint32_t prefetch:3; + uint32_t min_data:6; + uint32_t reserved_9_31:23; +#endif } s; struct cvmx_pci_read_cmd_6_s cn30xx; struct cvmx_pci_read_cmd_6_s cn31xx; @@ -1388,9 +2197,15 @@ union cvmx_pci_read_cmd_6 { union cvmx_pci_read_cmd_c { uint32_t u32; struct cvmx_pci_read_cmd_c_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_9_31:23; uint32_t min_data:6; uint32_t prefetch:3; +#else + uint32_t prefetch:3; + uint32_t min_data:6; + uint32_t reserved_9_31:23; +#endif } s; struct cvmx_pci_read_cmd_c_s cn30xx; struct cvmx_pci_read_cmd_c_s cn31xx; @@ -1404,9 +2219,15 @@ union cvmx_pci_read_cmd_c { union cvmx_pci_read_cmd_e { uint32_t u32; struct cvmx_pci_read_cmd_e_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_9_31:23; uint32_t min_data:6; uint32_t prefetch:3; +#else + uint32_t prefetch:3; + uint32_t min_data:6; + uint32_t reserved_9_31:23; +#endif } s; struct cvmx_pci_read_cmd_e_s cn30xx; struct cvmx_pci_read_cmd_e_s cn31xx; @@ -1420,9 +2241,15 @@ union cvmx_pci_read_cmd_e { union cvmx_pci_read_timeout { uint64_t u64; struct cvmx_pci_read_timeout_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enb:1; uint64_t cnt:31; +#else + uint64_t cnt:31; + uint64_t enb:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pci_read_timeout_s cn30xx; struct cvmx_pci_read_timeout_s cn31xx; @@ -1436,8 +2263,13 @@ union cvmx_pci_read_timeout { union cvmx_pci_scm_reg { uint64_t u64; struct cvmx_pci_scm_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t scm:32; +#else + uint64_t scm:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pci_scm_reg_s cn30xx; struct cvmx_pci_scm_reg_s cn31xx; @@ -1451,8 +2283,13 @@ union cvmx_pci_scm_reg { union cvmx_pci_tsr_reg { uint64_t u64; struct cvmx_pci_tsr_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t tsr:36; +#else + uint64_t tsr:36; + uint64_t reserved_36_63:28; +#endif } s; struct cvmx_pci_tsr_reg_s cn30xx; struct cvmx_pci_tsr_reg_s cn31xx; @@ -1466,22 +2303,42 @@ union cvmx_pci_tsr_reg { union cvmx_pci_win_rd_addr { uint64_t u64; struct cvmx_pci_win_rd_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t reserved_0_47:48; +#else + uint64_t reserved_0_47:48; + uint64_t iobit:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_pci_win_rd_addr_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t rd_addr:46; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t rd_addr:46; + uint64_t iobit:1; + uint64_t reserved_49_63:15; +#endif } cn30xx; struct cvmx_pci_win_rd_addr_cn30xx cn31xx; struct cvmx_pci_win_rd_addr_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t rd_addr:45; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t rd_addr:45; + uint64_t iobit:1; + uint64_t reserved_49_63:15; +#endif } cn38xx; struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2; struct cvmx_pci_win_rd_addr_cn30xx cn50xx; @@ -1492,7 +2349,11 @@ union cvmx_pci_win_rd_addr { union cvmx_pci_win_rd_data { uint64_t u64; struct cvmx_pci_win_rd_data_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rd_data:64; +#else uint64_t rd_data:64; +#endif } s; struct cvmx_pci_win_rd_data_s cn30xx; struct cvmx_pci_win_rd_data_s cn31xx; @@ -1506,10 +2367,17 @@ union cvmx_pci_win_rd_data { union cvmx_pci_win_wr_addr { uint64_t u64; struct cvmx_pci_win_wr_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t wr_addr:45; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t wr_addr:45; + uint64_t iobit:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_pci_win_wr_addr_s cn30xx; struct cvmx_pci_win_wr_addr_s cn31xx; @@ -1523,7 +2391,11 @@ union cvmx_pci_win_wr_addr { union cvmx_pci_win_wr_data { uint64_t u64; struct cvmx_pci_win_wr_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_data:64; +#else + uint64_t wr_data:64; +#endif } s; struct cvmx_pci_win_wr_data_s cn30xx; struct cvmx_pci_win_wr_data_s cn31xx; @@ -1537,8 +2409,13 @@ union cvmx_pci_win_wr_data { union cvmx_pci_win_wr_mask { uint64_t u64; struct cvmx_pci_win_wr_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t wr_mask:8; +#else + uint64_t wr_mask:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_pci_win_wr_mask_s cn30xx; struct cvmx_pci_win_wr_mask_s cn31xx; diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h index 7b1dc8b74e5b..4bce393391e2 100644 --- a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2011 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -109,8 +109,13 @@ union cvmx_pciercx_cfg000 { uint32_t u32; struct cvmx_pciercx_cfg000_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t devid:16; uint32_t vendid:16; +#else + uint32_t vendid:16; + uint32_t devid:16; +#endif } s; struct cvmx_pciercx_cfg000_s cn52xx; struct cvmx_pciercx_cfg000_s cn52xxp1; @@ -122,11 +127,13 @@ union cvmx_pciercx_cfg000 { struct cvmx_pciercx_cfg000_s cn66xx; struct cvmx_pciercx_cfg000_s cn68xx; struct cvmx_pciercx_cfg000_s cn68xxp1; + struct cvmx_pciercx_cfg000_s cnf71xx; }; union cvmx_pciercx_cfg001 { uint32_t u32; struct cvmx_pciercx_cfg001_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t dpe:1; uint32_t sse:1; uint32_t rma:1; @@ -151,6 +158,32 @@ union cvmx_pciercx_cfg001 { uint32_t me:1; uint32_t msae:1; uint32_t isae:1; +#else + uint32_t isae:1; + uint32_t msae:1; + uint32_t me:1; + uint32_t scse:1; + uint32_t mwice:1; + uint32_t vps:1; + uint32_t per:1; + uint32_t ids_wcc:1; + uint32_t see:1; + uint32_t fbbe:1; + uint32_t i_dis:1; + uint32_t reserved_11_18:8; + uint32_t i_stat:1; + uint32_t cl:1; + uint32_t m66:1; + uint32_t reserved_22_22:1; + uint32_t fbb:1; + uint32_t mdpe:1; + uint32_t devt:2; + uint32_t sta:1; + uint32_t rta:1; + uint32_t rma:1; + uint32_t sse:1; + uint32_t dpe:1; +#endif } s; struct cvmx_pciercx_cfg001_s cn52xx; struct cvmx_pciercx_cfg001_s cn52xxp1; @@ -162,15 +195,23 @@ union cvmx_pciercx_cfg001 { struct cvmx_pciercx_cfg001_s cn66xx; struct cvmx_pciercx_cfg001_s cn68xx; struct cvmx_pciercx_cfg001_s cn68xxp1; + struct cvmx_pciercx_cfg001_s cnf71xx; }; union cvmx_pciercx_cfg002 { uint32_t u32; struct cvmx_pciercx_cfg002_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t bcc:8; uint32_t sc:8; uint32_t pi:8; uint32_t rid:8; +#else + uint32_t rid:8; + uint32_t pi:8; + uint32_t sc:8; + uint32_t bcc:8; +#endif } s; struct cvmx_pciercx_cfg002_s cn52xx; struct cvmx_pciercx_cfg002_s cn52xxp1; @@ -182,16 +223,25 @@ union cvmx_pciercx_cfg002 { struct cvmx_pciercx_cfg002_s cn66xx; struct cvmx_pciercx_cfg002_s cn68xx; struct cvmx_pciercx_cfg002_s cn68xxp1; + struct cvmx_pciercx_cfg002_s cnf71xx; }; union cvmx_pciercx_cfg003 { uint32_t u32; struct cvmx_pciercx_cfg003_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t bist:8; uint32_t mfd:1; uint32_t chf:7; uint32_t lt:8; uint32_t cls:8; +#else + uint32_t cls:8; + uint32_t lt:8; + uint32_t chf:7; + uint32_t mfd:1; + uint32_t bist:8; +#endif } s; struct cvmx_pciercx_cfg003_s cn52xx; struct cvmx_pciercx_cfg003_s cn52xxp1; @@ -203,12 +253,17 @@ union cvmx_pciercx_cfg003 { struct cvmx_pciercx_cfg003_s cn66xx; struct cvmx_pciercx_cfg003_s cn68xx; struct cvmx_pciercx_cfg003_s cn68xxp1; + struct cvmx_pciercx_cfg003_s cnf71xx; }; union cvmx_pciercx_cfg004 { uint32_t u32; struct cvmx_pciercx_cfg004_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_0_31:32; +#else uint32_t reserved_0_31:32; +#endif } s; struct cvmx_pciercx_cfg004_s cn52xx; struct cvmx_pciercx_cfg004_s cn52xxp1; @@ -220,12 +275,17 @@ union cvmx_pciercx_cfg004 { struct cvmx_pciercx_cfg004_s cn66xx; struct cvmx_pciercx_cfg004_s cn68xx; struct cvmx_pciercx_cfg004_s cn68xxp1; + struct cvmx_pciercx_cfg004_s cnf71xx; }; union cvmx_pciercx_cfg005 { uint32_t u32; struct cvmx_pciercx_cfg005_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_0_31:32; +#else uint32_t reserved_0_31:32; +#endif } s; struct cvmx_pciercx_cfg005_s cn52xx; struct cvmx_pciercx_cfg005_s cn52xxp1; @@ -237,15 +297,23 @@ union cvmx_pciercx_cfg005 { struct cvmx_pciercx_cfg005_s cn66xx; struct cvmx_pciercx_cfg005_s cn68xx; struct cvmx_pciercx_cfg005_s cn68xxp1; + struct cvmx_pciercx_cfg005_s cnf71xx; }; union cvmx_pciercx_cfg006 { uint32_t u32; struct cvmx_pciercx_cfg006_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t slt:8; uint32_t subbnum:8; uint32_t sbnum:8; uint32_t pbnum:8; +#else + uint32_t pbnum:8; + uint32_t sbnum:8; + uint32_t subbnum:8; + uint32_t slt:8; +#endif } s; struct cvmx_pciercx_cfg006_s cn52xx; struct cvmx_pciercx_cfg006_s cn52xxp1; @@ -257,11 +325,13 @@ union cvmx_pciercx_cfg006 { struct cvmx_pciercx_cfg006_s cn66xx; struct cvmx_pciercx_cfg006_s cn68xx; struct cvmx_pciercx_cfg006_s cn68xxp1; + struct cvmx_pciercx_cfg006_s cnf71xx; }; union cvmx_pciercx_cfg007 { uint32_t u32; struct cvmx_pciercx_cfg007_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t dpe:1; uint32_t sse:1; uint32_t rma:1; @@ -279,6 +349,25 @@ union cvmx_pciercx_cfg007 { uint32_t lio_base:4; uint32_t reserved_1_3:3; uint32_t io32a:1; +#else + uint32_t io32a:1; + uint32_t reserved_1_3:3; + uint32_t lio_base:4; + uint32_t io32b:1; + uint32_t reserved_9_11:3; + uint32_t lio_limi:4; + uint32_t reserved_16_20:5; + uint32_t m66:1; + uint32_t reserved_22_22:1; + uint32_t fbb:1; + uint32_t mdpe:1; + uint32_t devt:2; + uint32_t sta:1; + uint32_t rta:1; + uint32_t rma:1; + uint32_t sse:1; + uint32_t dpe:1; +#endif } s; struct cvmx_pciercx_cfg007_s cn52xx; struct cvmx_pciercx_cfg007_s cn52xxp1; @@ -290,15 +379,23 @@ union cvmx_pciercx_cfg007 { struct cvmx_pciercx_cfg007_s cn66xx; struct cvmx_pciercx_cfg007_s cn68xx; struct cvmx_pciercx_cfg007_s cn68xxp1; + struct cvmx_pciercx_cfg007_s cnf71xx; }; union cvmx_pciercx_cfg008 { uint32_t u32; struct cvmx_pciercx_cfg008_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t ml_addr:12; uint32_t reserved_16_19:4; uint32_t mb_addr:12; uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t mb_addr:12; + uint32_t reserved_16_19:4; + uint32_t ml_addr:12; +#endif } s; struct cvmx_pciercx_cfg008_s cn52xx; struct cvmx_pciercx_cfg008_s cn52xxp1; @@ -310,17 +407,27 @@ union cvmx_pciercx_cfg008 { struct cvmx_pciercx_cfg008_s cn66xx; struct cvmx_pciercx_cfg008_s cn68xx; struct cvmx_pciercx_cfg008_s cn68xxp1; + struct cvmx_pciercx_cfg008_s cnf71xx; }; union cvmx_pciercx_cfg009 { uint32_t u32; struct cvmx_pciercx_cfg009_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t lmem_limit:12; uint32_t reserved_17_19:3; uint32_t mem64b:1; uint32_t lmem_base:12; uint32_t reserved_1_3:3; uint32_t mem64a:1; +#else + uint32_t mem64a:1; + uint32_t reserved_1_3:3; + uint32_t lmem_base:12; + uint32_t mem64b:1; + uint32_t reserved_17_19:3; + uint32_t lmem_limit:12; +#endif } s; struct cvmx_pciercx_cfg009_s cn52xx; struct cvmx_pciercx_cfg009_s cn52xxp1; @@ -332,12 +439,17 @@ union cvmx_pciercx_cfg009 { struct cvmx_pciercx_cfg009_s cn66xx; struct cvmx_pciercx_cfg009_s cn68xx; struct cvmx_pciercx_cfg009_s cn68xxp1; + struct cvmx_pciercx_cfg009_s cnf71xx; }; union cvmx_pciercx_cfg010 { uint32_t u32; struct cvmx_pciercx_cfg010_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t umem_base:32; +#else + uint32_t umem_base:32; +#endif } s; struct cvmx_pciercx_cfg010_s cn52xx; struct cvmx_pciercx_cfg010_s cn52xxp1; @@ -349,12 +461,17 @@ union cvmx_pciercx_cfg010 { struct cvmx_pciercx_cfg010_s cn66xx; struct cvmx_pciercx_cfg010_s cn68xx; struct cvmx_pciercx_cfg010_s cn68xxp1; + struct cvmx_pciercx_cfg010_s cnf71xx; }; union cvmx_pciercx_cfg011 { uint32_t u32; struct cvmx_pciercx_cfg011_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t umem_limit:32; +#else + uint32_t umem_limit:32; +#endif } s; struct cvmx_pciercx_cfg011_s cn52xx; struct cvmx_pciercx_cfg011_s cn52xxp1; @@ -366,13 +483,19 @@ union cvmx_pciercx_cfg011 { struct cvmx_pciercx_cfg011_s cn66xx; struct cvmx_pciercx_cfg011_s cn68xx; struct cvmx_pciercx_cfg011_s cn68xxp1; + struct cvmx_pciercx_cfg011_s cnf71xx; }; union cvmx_pciercx_cfg012 { uint32_t u32; struct cvmx_pciercx_cfg012_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t uio_limit:16; uint32_t uio_base:16; +#else + uint32_t uio_base:16; + uint32_t uio_limit:16; +#endif } s; struct cvmx_pciercx_cfg012_s cn52xx; struct cvmx_pciercx_cfg012_s cn52xxp1; @@ -384,13 +507,19 @@ union cvmx_pciercx_cfg012 { struct cvmx_pciercx_cfg012_s cn66xx; struct cvmx_pciercx_cfg012_s cn68xx; struct cvmx_pciercx_cfg012_s cn68xxp1; + struct cvmx_pciercx_cfg012_s cnf71xx; }; union cvmx_pciercx_cfg013 { uint32_t u32; struct cvmx_pciercx_cfg013_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_8_31:24; uint32_t cp:8; +#else + uint32_t cp:8; + uint32_t reserved_8_31:24; +#endif } s; struct cvmx_pciercx_cfg013_s cn52xx; struct cvmx_pciercx_cfg013_s cn52xxp1; @@ -402,12 +531,17 @@ union cvmx_pciercx_cfg013 { struct cvmx_pciercx_cfg013_s cn66xx; struct cvmx_pciercx_cfg013_s cn68xx; struct cvmx_pciercx_cfg013_s cn68xxp1; + struct cvmx_pciercx_cfg013_s cnf71xx; }; union cvmx_pciercx_cfg014 { uint32_t u32; struct cvmx_pciercx_cfg014_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_0_31:32; +#else uint32_t reserved_0_31:32; +#endif } s; struct cvmx_pciercx_cfg014_s cn52xx; struct cvmx_pciercx_cfg014_s cn52xxp1; @@ -419,11 +553,13 @@ union cvmx_pciercx_cfg014 { struct cvmx_pciercx_cfg014_s cn66xx; struct cvmx_pciercx_cfg014_s cn68xx; struct cvmx_pciercx_cfg014_s cn68xxp1; + struct cvmx_pciercx_cfg014_s cnf71xx; }; union cvmx_pciercx_cfg015 { uint32_t u32; struct cvmx_pciercx_cfg015_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_28_31:4; uint32_t dtsees:1; uint32_t dts:1; @@ -439,6 +575,23 @@ union cvmx_pciercx_cfg015 { uint32_t pere:1; uint32_t inta:8; uint32_t il:8; +#else + uint32_t il:8; + uint32_t inta:8; + uint32_t pere:1; + uint32_t see:1; + uint32_t isae:1; + uint32_t vgae:1; + uint32_t vga16d:1; + uint32_t mam:1; + uint32_t sbrst:1; + uint32_t fbbe:1; + uint32_t pdt:1; + uint32_t sdt:1; + uint32_t dts:1; + uint32_t dtsees:1; + uint32_t reserved_28_31:4; +#endif } s; struct cvmx_pciercx_cfg015_s cn52xx; struct cvmx_pciercx_cfg015_s cn52xxp1; @@ -450,11 +603,13 @@ union cvmx_pciercx_cfg015 { struct cvmx_pciercx_cfg015_s cn66xx; struct cvmx_pciercx_cfg015_s cn68xx; struct cvmx_pciercx_cfg015_s cn68xxp1; + struct cvmx_pciercx_cfg015_s cnf71xx; }; union cvmx_pciercx_cfg016 { uint32_t u32; struct cvmx_pciercx_cfg016_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pmes:5; uint32_t d2s:1; uint32_t d1s:1; @@ -465,6 +620,18 @@ union cvmx_pciercx_cfg016 { uint32_t pmsv:3; uint32_t ncp:8; uint32_t pmcid:8; +#else + uint32_t pmcid:8; + uint32_t ncp:8; + uint32_t pmsv:3; + uint32_t pme_clock:1; + uint32_t reserved_20_20:1; + uint32_t dsi:1; + uint32_t auxc:3; + uint32_t d1s:1; + uint32_t d2s:1; + uint32_t pmes:5; +#endif } s; struct cvmx_pciercx_cfg016_s cn52xx; struct cvmx_pciercx_cfg016_s cn52xxp1; @@ -476,11 +643,13 @@ union cvmx_pciercx_cfg016 { struct cvmx_pciercx_cfg016_s cn66xx; struct cvmx_pciercx_cfg016_s cn68xx; struct cvmx_pciercx_cfg016_s cn68xxp1; + struct cvmx_pciercx_cfg016_s cnf71xx; }; union cvmx_pciercx_cfg017 { uint32_t u32; struct cvmx_pciercx_cfg017_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pmdia:8; uint32_t bpccee:1; uint32_t bd3h:1; @@ -493,6 +662,20 @@ union cvmx_pciercx_cfg017 { uint32_t nsr:1; uint32_t reserved_2_2:1; uint32_t ps:2; +#else + uint32_t ps:2; + uint32_t reserved_2_2:1; + uint32_t nsr:1; + uint32_t reserved_4_7:4; + uint32_t pmeens:1; + uint32_t pmds:4; + uint32_t pmedsia:2; + uint32_t pmess:1; + uint32_t reserved_16_21:6; + uint32_t bd3h:1; + uint32_t bpccee:1; + uint32_t pmdia:8; +#endif } s; struct cvmx_pciercx_cfg017_s cn52xx; struct cvmx_pciercx_cfg017_s cn52xxp1; @@ -504,11 +687,13 @@ union cvmx_pciercx_cfg017 { struct cvmx_pciercx_cfg017_s cn66xx; struct cvmx_pciercx_cfg017_s cn68xx; struct cvmx_pciercx_cfg017_s cn68xxp1; + struct cvmx_pciercx_cfg017_s cnf71xx; }; union cvmx_pciercx_cfg020 { uint32_t u32; struct cvmx_pciercx_cfg020_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_25_31:7; uint32_t pvm:1; uint32_t m64:1; @@ -517,8 +702,19 @@ union cvmx_pciercx_cfg020 { uint32_t msien:1; uint32_t ncp:8; uint32_t msicid:8; +#else + uint32_t msicid:8; + uint32_t ncp:8; + uint32_t msien:1; + uint32_t mmc:3; + uint32_t mme:3; + uint32_t m64:1; + uint32_t pvm:1; + uint32_t reserved_25_31:7; +#endif } s; struct cvmx_pciercx_cfg020_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_24_31:8; uint32_t m64:1; uint32_t mme:3; @@ -526,6 +722,15 @@ union cvmx_pciercx_cfg020 { uint32_t msien:1; uint32_t ncp:8; uint32_t msicid:8; +#else + uint32_t msicid:8; + uint32_t ncp:8; + uint32_t msien:1; + uint32_t mmc:3; + uint32_t mme:3; + uint32_t m64:1; + uint32_t reserved_24_31:8; +#endif } cn52xx; struct cvmx_pciercx_cfg020_cn52xx cn52xxp1; struct cvmx_pciercx_cfg020_cn52xx cn56xx; @@ -536,13 +741,19 @@ union cvmx_pciercx_cfg020 { struct cvmx_pciercx_cfg020_cn52xx cn66xx; struct cvmx_pciercx_cfg020_cn52xx cn68xx; struct cvmx_pciercx_cfg020_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg020_s cnf71xx; }; union cvmx_pciercx_cfg021 { uint32_t u32; struct cvmx_pciercx_cfg021_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t lmsi:30; uint32_t reserved_0_1:2; +#else + uint32_t reserved_0_1:2; + uint32_t lmsi:30; +#endif } s; struct cvmx_pciercx_cfg021_s cn52xx; struct cvmx_pciercx_cfg021_s cn52xxp1; @@ -554,12 +765,17 @@ union cvmx_pciercx_cfg021 { struct cvmx_pciercx_cfg021_s cn66xx; struct cvmx_pciercx_cfg021_s cn68xx; struct cvmx_pciercx_cfg021_s cn68xxp1; + struct cvmx_pciercx_cfg021_s cnf71xx; }; union cvmx_pciercx_cfg022 { uint32_t u32; struct cvmx_pciercx_cfg022_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t umsi:32; +#else + uint32_t umsi:32; +#endif } s; struct cvmx_pciercx_cfg022_s cn52xx; struct cvmx_pciercx_cfg022_s cn52xxp1; @@ -571,13 +787,19 @@ union cvmx_pciercx_cfg022 { struct cvmx_pciercx_cfg022_s cn66xx; struct cvmx_pciercx_cfg022_s cn68xx; struct cvmx_pciercx_cfg022_s cn68xxp1; + struct cvmx_pciercx_cfg022_s cnf71xx; }; union cvmx_pciercx_cfg023 { uint32_t u32; struct cvmx_pciercx_cfg023_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_16_31:16; uint32_t msimd:16; +#else + uint32_t msimd:16; + uint32_t reserved_16_31:16; +#endif } s; struct cvmx_pciercx_cfg023_s cn52xx; struct cvmx_pciercx_cfg023_s cn52xxp1; @@ -589,11 +811,13 @@ union cvmx_pciercx_cfg023 { struct cvmx_pciercx_cfg023_s cn66xx; struct cvmx_pciercx_cfg023_s cn68xx; struct cvmx_pciercx_cfg023_s cn68xxp1; + struct cvmx_pciercx_cfg023_s cnf71xx; }; union cvmx_pciercx_cfg028 { uint32_t u32; struct cvmx_pciercx_cfg028_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_30_31:2; uint32_t imn:5; uint32_t si:1; @@ -601,6 +825,15 @@ union cvmx_pciercx_cfg028 { uint32_t pciecv:4; uint32_t ncp:8; uint32_t pcieid:8; +#else + uint32_t pcieid:8; + uint32_t ncp:8; + uint32_t pciecv:4; + uint32_t dpt:4; + uint32_t si:1; + uint32_t imn:5; + uint32_t reserved_30_31:2; +#endif } s; struct cvmx_pciercx_cfg028_s cn52xx; struct cvmx_pciercx_cfg028_s cn52xxp1; @@ -612,11 +845,13 @@ union cvmx_pciercx_cfg028 { struct cvmx_pciercx_cfg028_s cn66xx; struct cvmx_pciercx_cfg028_s cn68xx; struct cvmx_pciercx_cfg028_s cn68xxp1; + struct cvmx_pciercx_cfg028_s cnf71xx; }; union cvmx_pciercx_cfg029 { uint32_t u32; struct cvmx_pciercx_cfg029_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_28_31:4; uint32_t cspls:2; uint32_t csplv:8; @@ -628,6 +863,19 @@ union cvmx_pciercx_cfg029 { uint32_t etfs:1; uint32_t pfs:2; uint32_t mpss:3; +#else + uint32_t mpss:3; + uint32_t pfs:2; + uint32_t etfs:1; + uint32_t el0al:3; + uint32_t el1al:3; + uint32_t reserved_12_14:3; + uint32_t rber:1; + uint32_t reserved_16_17:2; + uint32_t csplv:8; + uint32_t cspls:2; + uint32_t reserved_28_31:4; +#endif } s; struct cvmx_pciercx_cfg029_s cn52xx; struct cvmx_pciercx_cfg029_s cn52xxp1; @@ -639,11 +887,13 @@ union cvmx_pciercx_cfg029 { struct cvmx_pciercx_cfg029_s cn66xx; struct cvmx_pciercx_cfg029_s cn68xx; struct cvmx_pciercx_cfg029_s cn68xxp1; + struct cvmx_pciercx_cfg029_s cnf71xx; }; union cvmx_pciercx_cfg030 { uint32_t u32; struct cvmx_pciercx_cfg030_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_22_31:10; uint32_t tp:1; uint32_t ap_d:1; @@ -663,6 +913,27 @@ union cvmx_pciercx_cfg030 { uint32_t fe_en:1; uint32_t nfe_en:1; uint32_t ce_en:1; +#else + uint32_t ce_en:1; + uint32_t nfe_en:1; + uint32_t fe_en:1; + uint32_t ur_en:1; + uint32_t ro_en:1; + uint32_t mps:3; + uint32_t etf_en:1; + uint32_t pf_en:1; + uint32_t ap_en:1; + uint32_t ns_en:1; + uint32_t mrrs:3; + uint32_t reserved_15_15:1; + uint32_t ce_d:1; + uint32_t nfe_d:1; + uint32_t fe_d:1; + uint32_t ur_d:1; + uint32_t ap_d:1; + uint32_t tp:1; + uint32_t reserved_22_31:10; +#endif } s; struct cvmx_pciercx_cfg030_s cn52xx; struct cvmx_pciercx_cfg030_s cn52xxp1; @@ -674,11 +945,13 @@ union cvmx_pciercx_cfg030 { struct cvmx_pciercx_cfg030_s cn66xx; struct cvmx_pciercx_cfg030_s cn68xx; struct cvmx_pciercx_cfg030_s cn68xxp1; + struct cvmx_pciercx_cfg030_s cnf71xx; }; union cvmx_pciercx_cfg031 { uint32_t u32; struct cvmx_pciercx_cfg031_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pnum:8; uint32_t reserved_23_23:1; uint32_t aspm:1; @@ -691,8 +964,23 @@ union cvmx_pciercx_cfg031 { uint32_t aslpms:2; uint32_t mlw:6; uint32_t mls:4; +#else + uint32_t mls:4; + uint32_t mlw:6; + uint32_t aslpms:2; + uint32_t l0el:3; + uint32_t l1el:3; + uint32_t cpm:1; + uint32_t sderc:1; + uint32_t dllarc:1; + uint32_t lbnc:1; + uint32_t aspm:1; + uint32_t reserved_23_23:1; + uint32_t pnum:8; +#endif } s; struct cvmx_pciercx_cfg031_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pnum:8; uint32_t reserved_22_23:2; uint32_t lbnc:1; @@ -704,6 +992,19 @@ union cvmx_pciercx_cfg031 { uint32_t aslpms:2; uint32_t mlw:6; uint32_t mls:4; +#else + uint32_t mls:4; + uint32_t mlw:6; + uint32_t aslpms:2; + uint32_t l0el:3; + uint32_t l1el:3; + uint32_t cpm:1; + uint32_t sderc:1; + uint32_t dllarc:1; + uint32_t lbnc:1; + uint32_t reserved_22_23:2; + uint32_t pnum:8; +#endif } cn52xx; struct cvmx_pciercx_cfg031_cn52xx cn52xxp1; struct cvmx_pciercx_cfg031_cn52xx cn56xx; @@ -714,11 +1015,13 @@ union cvmx_pciercx_cfg031 { struct cvmx_pciercx_cfg031_s cn66xx; struct cvmx_pciercx_cfg031_s cn68xx; struct cvmx_pciercx_cfg031_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg031_s cnf71xx; }; union cvmx_pciercx_cfg032 { uint32_t u32; struct cvmx_pciercx_cfg032_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t lab:1; uint32_t lbm:1; uint32_t dlla:1; @@ -739,6 +1042,28 @@ union cvmx_pciercx_cfg032 { uint32_t rcb:1; uint32_t reserved_2_2:1; uint32_t aslpc:2; +#else + uint32_t aslpc:2; + uint32_t reserved_2_2:1; + uint32_t rcb:1; + uint32_t ld:1; + uint32_t rl:1; + uint32_t ccc:1; + uint32_t es:1; + uint32_t ecpm:1; + uint32_t hawd:1; + uint32_t lbm_int_enb:1; + uint32_t lab_int_enb:1; + uint32_t reserved_12_15:4; + uint32_t ls:4; + uint32_t nlw:6; + uint32_t reserved_26_26:1; + uint32_t lt:1; + uint32_t scc:1; + uint32_t dlla:1; + uint32_t lbm:1; + uint32_t lab:1; +#endif } s; struct cvmx_pciercx_cfg032_s cn52xx; struct cvmx_pciercx_cfg032_s cn52xxp1; @@ -750,11 +1075,13 @@ union cvmx_pciercx_cfg032 { struct cvmx_pciercx_cfg032_s cn66xx; struct cvmx_pciercx_cfg032_s cn68xx; struct cvmx_pciercx_cfg032_s cn68xxp1; + struct cvmx_pciercx_cfg032_s cnf71xx; }; union cvmx_pciercx_cfg033 { uint32_t u32; struct cvmx_pciercx_cfg033_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t ps_num:13; uint32_t nccs:1; uint32_t emip:1; @@ -767,6 +1094,20 @@ union cvmx_pciercx_cfg033 { uint32_t mrlsp:1; uint32_t pcp:1; uint32_t abp:1; +#else + uint32_t abp:1; + uint32_t pcp:1; + uint32_t mrlsp:1; + uint32_t aip:1; + uint32_t pip:1; + uint32_t hp_s:1; + uint32_t hp_c:1; + uint32_t sp_lv:8; + uint32_t sp_ls:2; + uint32_t emip:1; + uint32_t nccs:1; + uint32_t ps_num:13; +#endif } s; struct cvmx_pciercx_cfg033_s cn52xx; struct cvmx_pciercx_cfg033_s cn52xxp1; @@ -778,11 +1119,13 @@ union cvmx_pciercx_cfg033 { struct cvmx_pciercx_cfg033_s cn66xx; struct cvmx_pciercx_cfg033_s cn68xx; struct cvmx_pciercx_cfg033_s cn68xxp1; + struct cvmx_pciercx_cfg033_s cnf71xx; }; union cvmx_pciercx_cfg034 { uint32_t u32; struct cvmx_pciercx_cfg034_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_25_31:7; uint32_t dlls_c:1; uint32_t emis:1; @@ -805,6 +1148,30 @@ union cvmx_pciercx_cfg034 { uint32_t mrls_en:1; uint32_t pf_en:1; uint32_t abp_en:1; +#else + uint32_t abp_en:1; + uint32_t pf_en:1; + uint32_t mrls_en:1; + uint32_t pd_en:1; + uint32_t ccint_en:1; + uint32_t hpint_en:1; + uint32_t aic:2; + uint32_t pic:2; + uint32_t pcc:1; + uint32_t emic:1; + uint32_t dlls_en:1; + uint32_t reserved_13_15:3; + uint32_t abp_d:1; + uint32_t pf_d:1; + uint32_t mrls_c:1; + uint32_t pd_c:1; + uint32_t ccint_d:1; + uint32_t mrlss:1; + uint32_t pds:1; + uint32_t emis:1; + uint32_t dlls_c:1; + uint32_t reserved_25_31:7; +#endif } s; struct cvmx_pciercx_cfg034_s cn52xx; struct cvmx_pciercx_cfg034_s cn52xxp1; @@ -816,11 +1183,13 @@ union cvmx_pciercx_cfg034 { struct cvmx_pciercx_cfg034_s cn66xx; struct cvmx_pciercx_cfg034_s cn68xx; struct cvmx_pciercx_cfg034_s cn68xxp1; + struct cvmx_pciercx_cfg034_s cnf71xx; }; union cvmx_pciercx_cfg035 { uint32_t u32; struct cvmx_pciercx_cfg035_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_17_31:15; uint32_t crssv:1; uint32_t reserved_5_15:11; @@ -829,6 +1198,16 @@ union cvmx_pciercx_cfg035 { uint32_t sefee:1; uint32_t senfee:1; uint32_t secee:1; +#else + uint32_t secee:1; + uint32_t senfee:1; + uint32_t sefee:1; + uint32_t pmeie:1; + uint32_t crssve:1; + uint32_t reserved_5_15:11; + uint32_t crssv:1; + uint32_t reserved_17_31:15; +#endif } s; struct cvmx_pciercx_cfg035_s cn52xx; struct cvmx_pciercx_cfg035_s cn52xxp1; @@ -840,15 +1219,23 @@ union cvmx_pciercx_cfg035 { struct cvmx_pciercx_cfg035_s cn66xx; struct cvmx_pciercx_cfg035_s cn68xx; struct cvmx_pciercx_cfg035_s cn68xxp1; + struct cvmx_pciercx_cfg035_s cnf71xx; }; union cvmx_pciercx_cfg036 { uint32_t u32; struct cvmx_pciercx_cfg036_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_18_31:14; uint32_t pme_pend:1; uint32_t pme_stat:1; uint32_t pme_rid:16; +#else + uint32_t pme_rid:16; + uint32_t pme_stat:1; + uint32_t pme_pend:1; + uint32_t reserved_18_31:14; +#endif } s; struct cvmx_pciercx_cfg036_s cn52xx; struct cvmx_pciercx_cfg036_s cn52xxp1; @@ -860,14 +1247,17 @@ union cvmx_pciercx_cfg036 { struct cvmx_pciercx_cfg036_s cn66xx; struct cvmx_pciercx_cfg036_s cn68xx; struct cvmx_pciercx_cfg036_s cn68xxp1; + struct cvmx_pciercx_cfg036_s cnf71xx; }; union cvmx_pciercx_cfg037 { uint32_t u32; struct cvmx_pciercx_cfg037_s { - uint32_t reserved_14_31:18; - uint32_t tph:2; - uint32_t reserved_11_11:1; +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_20_31:12; + uint32_t obffs:2; + uint32_t reserved_12_17:6; + uint32_t ltrs:1; uint32_t noroprpr:1; uint32_t atom128s:1; uint32_t atom64s:1; @@ -876,16 +1266,37 @@ union cvmx_pciercx_cfg037 { uint32_t reserved_5_5:1; uint32_t ctds:1; uint32_t ctrs:4; +#else + uint32_t ctrs:4; + uint32_t ctds:1; + uint32_t reserved_5_5:1; + uint32_t atom_ops:1; + uint32_t atom32s:1; + uint32_t atom64s:1; + uint32_t atom128s:1; + uint32_t noroprpr:1; + uint32_t ltrs:1; + uint32_t reserved_12_17:6; + uint32_t obffs:2; + uint32_t reserved_20_31:12; +#endif } s; struct cvmx_pciercx_cfg037_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_5_31:27; uint32_t ctds:1; uint32_t ctrs:4; +#else + uint32_t ctrs:4; + uint32_t ctds:1; + uint32_t reserved_5_31:27; +#endif } cn52xx; struct cvmx_pciercx_cfg037_cn52xx cn52xxp1; struct cvmx_pciercx_cfg037_cn52xx cn56xx; struct cvmx_pciercx_cfg037_cn52xx cn56xxp1; struct cvmx_pciercx_cfg037_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_14_31:18; uint32_t tph:2; uint32_t reserved_11_11:1; @@ -897,10 +1308,24 @@ union cvmx_pciercx_cfg037 { uint32_t ari_fw:1; uint32_t ctds:1; uint32_t ctrs:4; +#else + uint32_t ctrs:4; + uint32_t ctds:1; + uint32_t ari_fw:1; + uint32_t atom_ops:1; + uint32_t atom32s:1; + uint32_t atom64s:1; + uint32_t atom128s:1; + uint32_t noroprpr:1; + uint32_t reserved_11_11:1; + uint32_t tph:2; + uint32_t reserved_14_31:18; +#endif } cn61xx; struct cvmx_pciercx_cfg037_cn52xx cn63xx; struct cvmx_pciercx_cfg037_cn52xx cn63xxp1; struct cvmx_pciercx_cfg037_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_14_31:18; uint32_t tph:2; uint32_t reserved_11_11:1; @@ -912,15 +1337,63 @@ union cvmx_pciercx_cfg037 { uint32_t ari:1; uint32_t ctds:1; uint32_t ctrs:4; +#else + uint32_t ctrs:4; + uint32_t ctds:1; + uint32_t ari:1; + uint32_t atom_ops:1; + uint32_t atom32s:1; + uint32_t atom64s:1; + uint32_t atom128s:1; + uint32_t noroprpr:1; + uint32_t reserved_11_11:1; + uint32_t tph:2; + uint32_t reserved_14_31:18; +#endif } cn66xx; struct cvmx_pciercx_cfg037_cn66xx cn68xx; struct cvmx_pciercx_cfg037_cn66xx cn68xxp1; + struct cvmx_pciercx_cfg037_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_20_31:12; + uint32_t obffs:2; + uint32_t reserved_14_17:4; + uint32_t tphs:2; + uint32_t ltrs:1; + uint32_t noroprpr:1; + uint32_t atom128s:1; + uint32_t atom64s:1; + uint32_t atom32s:1; + uint32_t atom_ops:1; + uint32_t ari_fw:1; + uint32_t ctds:1; + uint32_t ctrs:4; +#else + uint32_t ctrs:4; + uint32_t ctds:1; + uint32_t ari_fw:1; + uint32_t atom_ops:1; + uint32_t atom32s:1; + uint32_t atom64s:1; + uint32_t atom128s:1; + uint32_t noroprpr:1; + uint32_t ltrs:1; + uint32_t tphs:2; + uint32_t reserved_14_17:4; + uint32_t obffs:2; + uint32_t reserved_20_31:12; +#endif + } cnf71xx; }; union cvmx_pciercx_cfg038 { uint32_t u32; struct cvmx_pciercx_cfg038_s { - uint32_t reserved_10_31:22; +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_15_31:17; + uint32_t obffe:2; + uint32_t reserved_11_12:2; + uint32_t ltre:1; uint32_t id0_cp:1; uint32_t id0_rq:1; uint32_t atom_op_eb:1; @@ -928,33 +1401,84 @@ union cvmx_pciercx_cfg038 { uint32_t ari:1; uint32_t ctd:1; uint32_t ctv:4; +#else + uint32_t ctv:4; + uint32_t ctd:1; + uint32_t ari:1; + uint32_t atom_op:1; + uint32_t atom_op_eb:1; + uint32_t id0_rq:1; + uint32_t id0_cp:1; + uint32_t ltre:1; + uint32_t reserved_11_12:2; + uint32_t obffe:2; + uint32_t reserved_15_31:17; +#endif } s; struct cvmx_pciercx_cfg038_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_5_31:27; uint32_t ctd:1; uint32_t ctv:4; +#else + uint32_t ctv:4; + uint32_t ctd:1; + uint32_t reserved_5_31:27; +#endif } cn52xx; struct cvmx_pciercx_cfg038_cn52xx cn52xxp1; struct cvmx_pciercx_cfg038_cn52xx cn56xx; struct cvmx_pciercx_cfg038_cn52xx cn56xxp1; - struct cvmx_pciercx_cfg038_s cn61xx; + struct cvmx_pciercx_cfg038_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_10_31:22; + uint32_t id0_cp:1; + uint32_t id0_rq:1; + uint32_t atom_op_eb:1; + uint32_t atom_op:1; + uint32_t ari:1; + uint32_t ctd:1; + uint32_t ctv:4; +#else + uint32_t ctv:4; + uint32_t ctd:1; + uint32_t ari:1; + uint32_t atom_op:1; + uint32_t atom_op_eb:1; + uint32_t id0_rq:1; + uint32_t id0_cp:1; + uint32_t reserved_10_31:22; +#endif + } cn61xx; struct cvmx_pciercx_cfg038_cn52xx cn63xx; struct cvmx_pciercx_cfg038_cn52xx cn63xxp1; - struct cvmx_pciercx_cfg038_s cn66xx; - struct cvmx_pciercx_cfg038_s cn68xx; - struct cvmx_pciercx_cfg038_s cn68xxp1; + struct cvmx_pciercx_cfg038_cn61xx cn66xx; + struct cvmx_pciercx_cfg038_cn61xx cn68xx; + struct cvmx_pciercx_cfg038_cn61xx cn68xxp1; + struct cvmx_pciercx_cfg038_s cnf71xx; }; union cvmx_pciercx_cfg039 { uint32_t u32; struct cvmx_pciercx_cfg039_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_9_31:23; uint32_t cls:1; uint32_t slsv:7; uint32_t reserved_0_0:1; +#else + uint32_t reserved_0_0:1; + uint32_t slsv:7; + uint32_t cls:1; + uint32_t reserved_9_31:23; +#endif } s; struct cvmx_pciercx_cfg039_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_0_31:32; +#else uint32_t reserved_0_31:32; +#endif } cn52xx; struct cvmx_pciercx_cfg039_cn52xx cn52xxp1; struct cvmx_pciercx_cfg039_cn52xx cn56xx; @@ -965,11 +1489,13 @@ union cvmx_pciercx_cfg039 { struct cvmx_pciercx_cfg039_s cn66xx; struct cvmx_pciercx_cfg039_s cn68xx; struct cvmx_pciercx_cfg039_s cn68xxp1; + struct cvmx_pciercx_cfg039_s cnf71xx; }; union cvmx_pciercx_cfg040 { uint32_t u32; struct cvmx_pciercx_cfg040_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_17_31:15; uint32_t cdl:1; uint32_t reserved_13_15:3; @@ -981,9 +1507,26 @@ union cvmx_pciercx_cfg040 { uint32_t hasd:1; uint32_t ec:1; uint32_t tls:4; +#else + uint32_t tls:4; + uint32_t ec:1; + uint32_t hasd:1; + uint32_t sde:1; + uint32_t tm:3; + uint32_t emc:1; + uint32_t csos:1; + uint32_t cde:1; + uint32_t reserved_13_15:3; + uint32_t cdl:1; + uint32_t reserved_17_31:15; +#endif } s; struct cvmx_pciercx_cfg040_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_0_31:32; +#else uint32_t reserved_0_31:32; +#endif } cn52xx; struct cvmx_pciercx_cfg040_cn52xx cn52xxp1; struct cvmx_pciercx_cfg040_cn52xx cn56xx; @@ -994,12 +1537,17 @@ union cvmx_pciercx_cfg040 { struct cvmx_pciercx_cfg040_s cn66xx; struct cvmx_pciercx_cfg040_s cn68xx; struct cvmx_pciercx_cfg040_s cn68xxp1; + struct cvmx_pciercx_cfg040_s cnf71xx; }; union cvmx_pciercx_cfg041 { uint32_t u32; struct cvmx_pciercx_cfg041_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_0_31:32; +#else uint32_t reserved_0_31:32; +#endif } s; struct cvmx_pciercx_cfg041_s cn52xx; struct cvmx_pciercx_cfg041_s cn52xxp1; @@ -1011,12 +1559,17 @@ union cvmx_pciercx_cfg041 { struct cvmx_pciercx_cfg041_s cn66xx; struct cvmx_pciercx_cfg041_s cn68xx; struct cvmx_pciercx_cfg041_s cn68xxp1; + struct cvmx_pciercx_cfg041_s cnf71xx; }; union cvmx_pciercx_cfg042 { uint32_t u32; struct cvmx_pciercx_cfg042_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_0_31:32; +#else uint32_t reserved_0_31:32; +#endif } s; struct cvmx_pciercx_cfg042_s cn52xx; struct cvmx_pciercx_cfg042_s cn52xxp1; @@ -1028,14 +1581,21 @@ union cvmx_pciercx_cfg042 { struct cvmx_pciercx_cfg042_s cn66xx; struct cvmx_pciercx_cfg042_s cn68xx; struct cvmx_pciercx_cfg042_s cn68xxp1; + struct cvmx_pciercx_cfg042_s cnf71xx; }; union cvmx_pciercx_cfg064 { uint32_t u32; struct cvmx_pciercx_cfg064_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t nco:12; uint32_t cv:4; uint32_t pcieec:16; +#else + uint32_t pcieec:16; + uint32_t cv:4; + uint32_t nco:12; +#endif } s; struct cvmx_pciercx_cfg064_s cn52xx; struct cvmx_pciercx_cfg064_s cn52xxp1; @@ -1047,14 +1607,18 @@ union cvmx_pciercx_cfg064 { struct cvmx_pciercx_cfg064_s cn66xx; struct cvmx_pciercx_cfg064_s cn68xx; struct cvmx_pciercx_cfg064_s cn68xxp1; + struct cvmx_pciercx_cfg064_s cnf71xx; }; union cvmx_pciercx_cfg065 { uint32_t u32; struct cvmx_pciercx_cfg065_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_25_31:7; uint32_t uatombs:1; - uint32_t reserved_21_23:3; + uint32_t reserved_23_23:1; + uint32_t ucies:1; + uint32_t reserved_21_21:1; uint32_t ures:1; uint32_t ecrces:1; uint32_t mtlps:1; @@ -1068,8 +1632,29 @@ union cvmx_pciercx_cfg065 { uint32_t sdes:1; uint32_t dlpes:1; uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpes:1; + uint32_t sdes:1; + uint32_t reserved_6_11:6; + uint32_t ptlps:1; + uint32_t fcpes:1; + uint32_t cts:1; + uint32_t cas:1; + uint32_t ucs:1; + uint32_t ros:1; + uint32_t mtlps:1; + uint32_t ecrces:1; + uint32_t ures:1; + uint32_t reserved_21_21:1; + uint32_t ucies:1; + uint32_t reserved_23_23:1; + uint32_t uatombs:1; + uint32_t reserved_25_31:7; +#endif } s; struct cvmx_pciercx_cfg065_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_21_31:11; uint32_t ures:1; uint32_t ecrces:1; @@ -1084,24 +1669,80 @@ union cvmx_pciercx_cfg065 { uint32_t sdes:1; uint32_t dlpes:1; uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpes:1; + uint32_t sdes:1; + uint32_t reserved_6_11:6; + uint32_t ptlps:1; + uint32_t fcpes:1; + uint32_t cts:1; + uint32_t cas:1; + uint32_t ucs:1; + uint32_t ros:1; + uint32_t mtlps:1; + uint32_t ecrces:1; + uint32_t ures:1; + uint32_t reserved_21_31:11; +#endif } cn52xx; struct cvmx_pciercx_cfg065_cn52xx cn52xxp1; struct cvmx_pciercx_cfg065_cn52xx cn56xx; struct cvmx_pciercx_cfg065_cn52xx cn56xxp1; - struct cvmx_pciercx_cfg065_s cn61xx; + struct cvmx_pciercx_cfg065_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_25_31:7; + uint32_t uatombs:1; + uint32_t reserved_21_23:3; + uint32_t ures:1; + uint32_t ecrces:1; + uint32_t mtlps:1; + uint32_t ros:1; + uint32_t ucs:1; + uint32_t cas:1; + uint32_t cts:1; + uint32_t fcpes:1; + uint32_t ptlps:1; + uint32_t reserved_6_11:6; + uint32_t sdes:1; + uint32_t dlpes:1; + uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpes:1; + uint32_t sdes:1; + uint32_t reserved_6_11:6; + uint32_t ptlps:1; + uint32_t fcpes:1; + uint32_t cts:1; + uint32_t cas:1; + uint32_t ucs:1; + uint32_t ros:1; + uint32_t mtlps:1; + uint32_t ecrces:1; + uint32_t ures:1; + uint32_t reserved_21_23:3; + uint32_t uatombs:1; + uint32_t reserved_25_31:7; +#endif + } cn61xx; struct cvmx_pciercx_cfg065_cn52xx cn63xx; struct cvmx_pciercx_cfg065_cn52xx cn63xxp1; - struct cvmx_pciercx_cfg065_s cn66xx; - struct cvmx_pciercx_cfg065_s cn68xx; + struct cvmx_pciercx_cfg065_cn61xx cn66xx; + struct cvmx_pciercx_cfg065_cn61xx cn68xx; struct cvmx_pciercx_cfg065_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg065_s cnf71xx; }; union cvmx_pciercx_cfg066 { uint32_t u32; struct cvmx_pciercx_cfg066_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_25_31:7; uint32_t uatombm:1; - uint32_t reserved_21_23:3; + uint32_t reserved_23_23:1; + uint32_t uciem:1; + uint32_t reserved_21_21:1; uint32_t urem:1; uint32_t ecrcem:1; uint32_t mtlpm:1; @@ -1115,8 +1756,29 @@ union cvmx_pciercx_cfg066 { uint32_t sdem:1; uint32_t dlpem:1; uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpem:1; + uint32_t sdem:1; + uint32_t reserved_6_11:6; + uint32_t ptlpm:1; + uint32_t fcpem:1; + uint32_t ctm:1; + uint32_t cam:1; + uint32_t ucm:1; + uint32_t rom:1; + uint32_t mtlpm:1; + uint32_t ecrcem:1; + uint32_t urem:1; + uint32_t reserved_21_21:1; + uint32_t uciem:1; + uint32_t reserved_23_23:1; + uint32_t uatombm:1; + uint32_t reserved_25_31:7; +#endif } s; struct cvmx_pciercx_cfg066_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_21_31:11; uint32_t urem:1; uint32_t ecrcem:1; @@ -1131,24 +1793,80 @@ union cvmx_pciercx_cfg066 { uint32_t sdem:1; uint32_t dlpem:1; uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpem:1; + uint32_t sdem:1; + uint32_t reserved_6_11:6; + uint32_t ptlpm:1; + uint32_t fcpem:1; + uint32_t ctm:1; + uint32_t cam:1; + uint32_t ucm:1; + uint32_t rom:1; + uint32_t mtlpm:1; + uint32_t ecrcem:1; + uint32_t urem:1; + uint32_t reserved_21_31:11; +#endif } cn52xx; struct cvmx_pciercx_cfg066_cn52xx cn52xxp1; struct cvmx_pciercx_cfg066_cn52xx cn56xx; struct cvmx_pciercx_cfg066_cn52xx cn56xxp1; - struct cvmx_pciercx_cfg066_s cn61xx; + struct cvmx_pciercx_cfg066_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_25_31:7; + uint32_t uatombm:1; + uint32_t reserved_21_23:3; + uint32_t urem:1; + uint32_t ecrcem:1; + uint32_t mtlpm:1; + uint32_t rom:1; + uint32_t ucm:1; + uint32_t cam:1; + uint32_t ctm:1; + uint32_t fcpem:1; + uint32_t ptlpm:1; + uint32_t reserved_6_11:6; + uint32_t sdem:1; + uint32_t dlpem:1; + uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpem:1; + uint32_t sdem:1; + uint32_t reserved_6_11:6; + uint32_t ptlpm:1; + uint32_t fcpem:1; + uint32_t ctm:1; + uint32_t cam:1; + uint32_t ucm:1; + uint32_t rom:1; + uint32_t mtlpm:1; + uint32_t ecrcem:1; + uint32_t urem:1; + uint32_t reserved_21_23:3; + uint32_t uatombm:1; + uint32_t reserved_25_31:7; +#endif + } cn61xx; struct cvmx_pciercx_cfg066_cn52xx cn63xx; struct cvmx_pciercx_cfg066_cn52xx cn63xxp1; - struct cvmx_pciercx_cfg066_s cn66xx; - struct cvmx_pciercx_cfg066_s cn68xx; + struct cvmx_pciercx_cfg066_cn61xx cn66xx; + struct cvmx_pciercx_cfg066_cn61xx cn68xx; struct cvmx_pciercx_cfg066_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg066_s cnf71xx; }; union cvmx_pciercx_cfg067 { uint32_t u32; struct cvmx_pciercx_cfg067_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_25_31:7; uint32_t uatombs:1; - uint32_t reserved_21_23:3; + uint32_t reserved_23_23:1; + uint32_t ucies:1; + uint32_t reserved_21_21:1; uint32_t ures:1; uint32_t ecrces:1; uint32_t mtlps:1; @@ -1162,8 +1880,29 @@ union cvmx_pciercx_cfg067 { uint32_t sdes:1; uint32_t dlpes:1; uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpes:1; + uint32_t sdes:1; + uint32_t reserved_6_11:6; + uint32_t ptlps:1; + uint32_t fcpes:1; + uint32_t cts:1; + uint32_t cas:1; + uint32_t ucs:1; + uint32_t ros:1; + uint32_t mtlps:1; + uint32_t ecrces:1; + uint32_t ures:1; + uint32_t reserved_21_21:1; + uint32_t ucies:1; + uint32_t reserved_23_23:1; + uint32_t uatombs:1; + uint32_t reserved_25_31:7; +#endif } s; struct cvmx_pciercx_cfg067_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_21_31:11; uint32_t ures:1; uint32_t ecrces:1; @@ -1178,22 +1917,77 @@ union cvmx_pciercx_cfg067 { uint32_t sdes:1; uint32_t dlpes:1; uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpes:1; + uint32_t sdes:1; + uint32_t reserved_6_11:6; + uint32_t ptlps:1; + uint32_t fcpes:1; + uint32_t cts:1; + uint32_t cas:1; + uint32_t ucs:1; + uint32_t ros:1; + uint32_t mtlps:1; + uint32_t ecrces:1; + uint32_t ures:1; + uint32_t reserved_21_31:11; +#endif } cn52xx; struct cvmx_pciercx_cfg067_cn52xx cn52xxp1; struct cvmx_pciercx_cfg067_cn52xx cn56xx; struct cvmx_pciercx_cfg067_cn52xx cn56xxp1; - struct cvmx_pciercx_cfg067_s cn61xx; + struct cvmx_pciercx_cfg067_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_25_31:7; + uint32_t uatombs:1; + uint32_t reserved_21_23:3; + uint32_t ures:1; + uint32_t ecrces:1; + uint32_t mtlps:1; + uint32_t ros:1; + uint32_t ucs:1; + uint32_t cas:1; + uint32_t cts:1; + uint32_t fcpes:1; + uint32_t ptlps:1; + uint32_t reserved_6_11:6; + uint32_t sdes:1; + uint32_t dlpes:1; + uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpes:1; + uint32_t sdes:1; + uint32_t reserved_6_11:6; + uint32_t ptlps:1; + uint32_t fcpes:1; + uint32_t cts:1; + uint32_t cas:1; + uint32_t ucs:1; + uint32_t ros:1; + uint32_t mtlps:1; + uint32_t ecrces:1; + uint32_t ures:1; + uint32_t reserved_21_23:3; + uint32_t uatombs:1; + uint32_t reserved_25_31:7; +#endif + } cn61xx; struct cvmx_pciercx_cfg067_cn52xx cn63xx; struct cvmx_pciercx_cfg067_cn52xx cn63xxp1; - struct cvmx_pciercx_cfg067_s cn66xx; - struct cvmx_pciercx_cfg067_s cn68xx; + struct cvmx_pciercx_cfg067_cn61xx cn66xx; + struct cvmx_pciercx_cfg067_cn61xx cn68xx; struct cvmx_pciercx_cfg067_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg067_s cnf71xx; }; union cvmx_pciercx_cfg068 { uint32_t u32; struct cvmx_pciercx_cfg068_s { - uint32_t reserved_14_31:18; +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_15_31:17; + uint32_t cies:1; uint32_t anfes:1; uint32_t rtts:1; uint32_t reserved_9_11:3; @@ -1202,23 +1996,60 @@ union cvmx_pciercx_cfg068 { uint32_t btlps:1; uint32_t reserved_1_5:5; uint32_t res:1; +#else + uint32_t res:1; + uint32_t reserved_1_5:5; + uint32_t btlps:1; + uint32_t bdllps:1; + uint32_t rnrs:1; + uint32_t reserved_9_11:3; + uint32_t rtts:1; + uint32_t anfes:1; + uint32_t cies:1; + uint32_t reserved_15_31:17; +#endif } s; - struct cvmx_pciercx_cfg068_s cn52xx; - struct cvmx_pciercx_cfg068_s cn52xxp1; - struct cvmx_pciercx_cfg068_s cn56xx; - struct cvmx_pciercx_cfg068_s cn56xxp1; - struct cvmx_pciercx_cfg068_s cn61xx; - struct cvmx_pciercx_cfg068_s cn63xx; - struct cvmx_pciercx_cfg068_s cn63xxp1; - struct cvmx_pciercx_cfg068_s cn66xx; - struct cvmx_pciercx_cfg068_s cn68xx; - struct cvmx_pciercx_cfg068_s cn68xxp1; + struct cvmx_pciercx_cfg068_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_14_31:18; + uint32_t anfes:1; + uint32_t rtts:1; + uint32_t reserved_9_11:3; + uint32_t rnrs:1; + uint32_t bdllps:1; + uint32_t btlps:1; + uint32_t reserved_1_5:5; + uint32_t res:1; +#else + uint32_t res:1; + uint32_t reserved_1_5:5; + uint32_t btlps:1; + uint32_t bdllps:1; + uint32_t rnrs:1; + uint32_t reserved_9_11:3; + uint32_t rtts:1; + uint32_t anfes:1; + uint32_t reserved_14_31:18; +#endif + } cn52xx; + struct cvmx_pciercx_cfg068_cn52xx cn52xxp1; + struct cvmx_pciercx_cfg068_cn52xx cn56xx; + struct cvmx_pciercx_cfg068_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg068_cn52xx cn61xx; + struct cvmx_pciercx_cfg068_cn52xx cn63xx; + struct cvmx_pciercx_cfg068_cn52xx cn63xxp1; + struct cvmx_pciercx_cfg068_cn52xx cn66xx; + struct cvmx_pciercx_cfg068_cn52xx cn68xx; + struct cvmx_pciercx_cfg068_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg068_s cnf71xx; }; union cvmx_pciercx_cfg069 { uint32_t u32; struct cvmx_pciercx_cfg069_s { - uint32_t reserved_14_31:18; +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_15_31:17; + uint32_t ciem:1; uint32_t anfem:1; uint32_t rttm:1; uint32_t reserved_9_11:3; @@ -1227,28 +2058,72 @@ union cvmx_pciercx_cfg069 { uint32_t btlpm:1; uint32_t reserved_1_5:5; uint32_t rem:1; +#else + uint32_t rem:1; + uint32_t reserved_1_5:5; + uint32_t btlpm:1; + uint32_t bdllpm:1; + uint32_t rnrm:1; + uint32_t reserved_9_11:3; + uint32_t rttm:1; + uint32_t anfem:1; + uint32_t ciem:1; + uint32_t reserved_15_31:17; +#endif } s; - struct cvmx_pciercx_cfg069_s cn52xx; - struct cvmx_pciercx_cfg069_s cn52xxp1; - struct cvmx_pciercx_cfg069_s cn56xx; - struct cvmx_pciercx_cfg069_s cn56xxp1; - struct cvmx_pciercx_cfg069_s cn61xx; - struct cvmx_pciercx_cfg069_s cn63xx; - struct cvmx_pciercx_cfg069_s cn63xxp1; - struct cvmx_pciercx_cfg069_s cn66xx; - struct cvmx_pciercx_cfg069_s cn68xx; - struct cvmx_pciercx_cfg069_s cn68xxp1; + struct cvmx_pciercx_cfg069_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_14_31:18; + uint32_t anfem:1; + uint32_t rttm:1; + uint32_t reserved_9_11:3; + uint32_t rnrm:1; + uint32_t bdllpm:1; + uint32_t btlpm:1; + uint32_t reserved_1_5:5; + uint32_t rem:1; +#else + uint32_t rem:1; + uint32_t reserved_1_5:5; + uint32_t btlpm:1; + uint32_t bdllpm:1; + uint32_t rnrm:1; + uint32_t reserved_9_11:3; + uint32_t rttm:1; + uint32_t anfem:1; + uint32_t reserved_14_31:18; +#endif + } cn52xx; + struct cvmx_pciercx_cfg069_cn52xx cn52xxp1; + struct cvmx_pciercx_cfg069_cn52xx cn56xx; + struct cvmx_pciercx_cfg069_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg069_cn52xx cn61xx; + struct cvmx_pciercx_cfg069_cn52xx cn63xx; + struct cvmx_pciercx_cfg069_cn52xx cn63xxp1; + struct cvmx_pciercx_cfg069_cn52xx cn66xx; + struct cvmx_pciercx_cfg069_cn52xx cn68xx; + struct cvmx_pciercx_cfg069_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg069_s cnf71xx; }; union cvmx_pciercx_cfg070 { uint32_t u32; struct cvmx_pciercx_cfg070_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_9_31:23; uint32_t ce:1; uint32_t cc:1; uint32_t ge:1; uint32_t gc:1; uint32_t fep:5; +#else + uint32_t fep:5; + uint32_t gc:1; + uint32_t ge:1; + uint32_t cc:1; + uint32_t ce:1; + uint32_t reserved_9_31:23; +#endif } s; struct cvmx_pciercx_cfg070_s cn52xx; struct cvmx_pciercx_cfg070_s cn52xxp1; @@ -1260,12 +2135,17 @@ union cvmx_pciercx_cfg070 { struct cvmx_pciercx_cfg070_s cn66xx; struct cvmx_pciercx_cfg070_s cn68xx; struct cvmx_pciercx_cfg070_s cn68xxp1; + struct cvmx_pciercx_cfg070_s cnf71xx; }; union cvmx_pciercx_cfg071 { uint32_t u32; struct cvmx_pciercx_cfg071_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t dword1:32; +#else + uint32_t dword1:32; +#endif } s; struct cvmx_pciercx_cfg071_s cn52xx; struct cvmx_pciercx_cfg071_s cn52xxp1; @@ -1277,12 +2157,17 @@ union cvmx_pciercx_cfg071 { struct cvmx_pciercx_cfg071_s cn66xx; struct cvmx_pciercx_cfg071_s cn68xx; struct cvmx_pciercx_cfg071_s cn68xxp1; + struct cvmx_pciercx_cfg071_s cnf71xx; }; union cvmx_pciercx_cfg072 { uint32_t u32; struct cvmx_pciercx_cfg072_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t dword2:32; +#else + uint32_t dword2:32; +#endif } s; struct cvmx_pciercx_cfg072_s cn52xx; struct cvmx_pciercx_cfg072_s cn52xxp1; @@ -1294,12 +2179,17 @@ union cvmx_pciercx_cfg072 { struct cvmx_pciercx_cfg072_s cn66xx; struct cvmx_pciercx_cfg072_s cn68xx; struct cvmx_pciercx_cfg072_s cn68xxp1; + struct cvmx_pciercx_cfg072_s cnf71xx; }; union cvmx_pciercx_cfg073 { uint32_t u32; struct cvmx_pciercx_cfg073_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t dword3:32; +#else + uint32_t dword3:32; +#endif } s; struct cvmx_pciercx_cfg073_s cn52xx; struct cvmx_pciercx_cfg073_s cn52xxp1; @@ -1311,12 +2201,17 @@ union cvmx_pciercx_cfg073 { struct cvmx_pciercx_cfg073_s cn66xx; struct cvmx_pciercx_cfg073_s cn68xx; struct cvmx_pciercx_cfg073_s cn68xxp1; + struct cvmx_pciercx_cfg073_s cnf71xx; }; union cvmx_pciercx_cfg074 { uint32_t u32; struct cvmx_pciercx_cfg074_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t dword4:32; +#else uint32_t dword4:32; +#endif } s; struct cvmx_pciercx_cfg074_s cn52xx; struct cvmx_pciercx_cfg074_s cn52xxp1; @@ -1328,15 +2223,23 @@ union cvmx_pciercx_cfg074 { struct cvmx_pciercx_cfg074_s cn66xx; struct cvmx_pciercx_cfg074_s cn68xx; struct cvmx_pciercx_cfg074_s cn68xxp1; + struct cvmx_pciercx_cfg074_s cnf71xx; }; union cvmx_pciercx_cfg075 { uint32_t u32; struct cvmx_pciercx_cfg075_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_3_31:29; uint32_t fere:1; uint32_t nfere:1; uint32_t cere:1; +#else + uint32_t cere:1; + uint32_t nfere:1; + uint32_t fere:1; + uint32_t reserved_3_31:29; +#endif } s; struct cvmx_pciercx_cfg075_s cn52xx; struct cvmx_pciercx_cfg075_s cn52xxp1; @@ -1348,11 +2251,13 @@ union cvmx_pciercx_cfg075 { struct cvmx_pciercx_cfg075_s cn66xx; struct cvmx_pciercx_cfg075_s cn68xx; struct cvmx_pciercx_cfg075_s cn68xxp1; + struct cvmx_pciercx_cfg075_s cnf71xx; }; union cvmx_pciercx_cfg076 { uint32_t u32; struct cvmx_pciercx_cfg076_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t aeimn:5; uint32_t reserved_7_26:20; uint32_t femr:1; @@ -1362,6 +2267,17 @@ union cvmx_pciercx_cfg076 { uint32_t efnfr:1; uint32_t multi_ecr:1; uint32_t ecr:1; +#else + uint32_t ecr:1; + uint32_t multi_ecr:1; + uint32_t efnfr:1; + uint32_t multi_efnfr:1; + uint32_t fuf:1; + uint32_t nfemr:1; + uint32_t femr:1; + uint32_t reserved_7_26:20; + uint32_t aeimn:5; +#endif } s; struct cvmx_pciercx_cfg076_s cn52xx; struct cvmx_pciercx_cfg076_s cn52xxp1; @@ -1373,13 +2289,19 @@ union cvmx_pciercx_cfg076 { struct cvmx_pciercx_cfg076_s cn66xx; struct cvmx_pciercx_cfg076_s cn68xx; struct cvmx_pciercx_cfg076_s cn68xxp1; + struct cvmx_pciercx_cfg076_s cnf71xx; }; union cvmx_pciercx_cfg077 { uint32_t u32; struct cvmx_pciercx_cfg077_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t efnfsi:16; uint32_t ecsi:16; +#else + uint32_t ecsi:16; + uint32_t efnfsi:16; +#endif } s; struct cvmx_pciercx_cfg077_s cn52xx; struct cvmx_pciercx_cfg077_s cn52xxp1; @@ -1391,13 +2313,19 @@ union cvmx_pciercx_cfg077 { struct cvmx_pciercx_cfg077_s cn66xx; struct cvmx_pciercx_cfg077_s cn68xx; struct cvmx_pciercx_cfg077_s cn68xxp1; + struct cvmx_pciercx_cfg077_s cnf71xx; }; union cvmx_pciercx_cfg448 { uint32_t u32; struct cvmx_pciercx_cfg448_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t rtl:16; uint32_t rtltl:16; +#else + uint32_t rtltl:16; + uint32_t rtl:16; +#endif } s; struct cvmx_pciercx_cfg448_s cn52xx; struct cvmx_pciercx_cfg448_s cn52xxp1; @@ -1409,12 +2337,17 @@ union cvmx_pciercx_cfg448 { struct cvmx_pciercx_cfg448_s cn66xx; struct cvmx_pciercx_cfg448_s cn68xx; struct cvmx_pciercx_cfg448_s cn68xxp1; + struct cvmx_pciercx_cfg448_s cnf71xx; }; union cvmx_pciercx_cfg449 { uint32_t u32; struct cvmx_pciercx_cfg449_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t omr:32; +#else uint32_t omr:32; +#endif } s; struct cvmx_pciercx_cfg449_s cn52xx; struct cvmx_pciercx_cfg449_s cn52xxp1; @@ -1426,17 +2359,27 @@ union cvmx_pciercx_cfg449 { struct cvmx_pciercx_cfg449_s cn66xx; struct cvmx_pciercx_cfg449_s cn68xx; struct cvmx_pciercx_cfg449_s cn68xxp1; + struct cvmx_pciercx_cfg449_s cnf71xx; }; union cvmx_pciercx_cfg450 { uint32_t u32; struct cvmx_pciercx_cfg450_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t lpec:8; uint32_t reserved_22_23:2; uint32_t link_state:6; uint32_t force_link:1; uint32_t reserved_8_14:7; uint32_t link_num:8; +#else + uint32_t link_num:8; + uint32_t reserved_8_14:7; + uint32_t force_link:1; + uint32_t link_state:6; + uint32_t reserved_22_23:2; + uint32_t lpec:8; +#endif } s; struct cvmx_pciercx_cfg450_s cn52xx; struct cvmx_pciercx_cfg450_s cn52xxp1; @@ -1448,11 +2391,13 @@ union cvmx_pciercx_cfg450 { struct cvmx_pciercx_cfg450_s cn66xx; struct cvmx_pciercx_cfg450_s cn68xx; struct cvmx_pciercx_cfg450_s cn68xxp1; + struct cvmx_pciercx_cfg450_s cnf71xx; }; union cvmx_pciercx_cfg451 { uint32_t u32; struct cvmx_pciercx_cfg451_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_31_31:1; uint32_t easpml1:1; uint32_t l1el:3; @@ -1460,14 +2405,32 @@ union cvmx_pciercx_cfg451 { uint32_t n_fts_cc:8; uint32_t n_fts:8; uint32_t ack_freq:8; +#else + uint32_t ack_freq:8; + uint32_t n_fts:8; + uint32_t n_fts_cc:8; + uint32_t l0el:3; + uint32_t l1el:3; + uint32_t easpml1:1; + uint32_t reserved_31_31:1; +#endif } s; struct cvmx_pciercx_cfg451_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_30_31:2; uint32_t l1el:3; uint32_t l0el:3; uint32_t n_fts_cc:8; uint32_t n_fts:8; uint32_t ack_freq:8; +#else + uint32_t ack_freq:8; + uint32_t n_fts:8; + uint32_t n_fts_cc:8; + uint32_t l0el:3; + uint32_t l1el:3; + uint32_t reserved_30_31:2; +#endif } cn52xx; struct cvmx_pciercx_cfg451_cn52xx cn52xxp1; struct cvmx_pciercx_cfg451_cn52xx cn56xx; @@ -1478,11 +2441,13 @@ union cvmx_pciercx_cfg451 { struct cvmx_pciercx_cfg451_s cn66xx; struct cvmx_pciercx_cfg451_s cn68xx; struct cvmx_pciercx_cfg451_s cn68xxp1; + struct cvmx_pciercx_cfg451_s cnf71xx; }; union cvmx_pciercx_cfg452 { uint32_t u32; struct cvmx_pciercx_cfg452_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_26_31:6; uint32_t eccrc:1; uint32_t reserved_22_24:3; @@ -1496,12 +2461,28 @@ union cvmx_pciercx_cfg452 { uint32_t le:1; uint32_t sd:1; uint32_t omr:1; +#else + uint32_t omr:1; + uint32_t sd:1; + uint32_t le:1; + uint32_t ra:1; + uint32_t reserved_4_4:1; + uint32_t dllle:1; + uint32_t reserved_6_6:1; + uint32_t flm:1; + uint32_t reserved_8_15:8; + uint32_t lme:6; + uint32_t reserved_22_24:3; + uint32_t eccrc:1; + uint32_t reserved_26_31:6; +#endif } s; struct cvmx_pciercx_cfg452_s cn52xx; struct cvmx_pciercx_cfg452_s cn52xxp1; struct cvmx_pciercx_cfg452_s cn56xx; struct cvmx_pciercx_cfg452_s cn56xxp1; struct cvmx_pciercx_cfg452_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_22_31:10; uint32_t lme:6; uint32_t reserved_8_15:8; @@ -1513,22 +2494,44 @@ union cvmx_pciercx_cfg452 { uint32_t le:1; uint32_t sd:1; uint32_t omr:1; +#else + uint32_t omr:1; + uint32_t sd:1; + uint32_t le:1; + uint32_t ra:1; + uint32_t reserved_4_4:1; + uint32_t dllle:1; + uint32_t reserved_6_6:1; + uint32_t flm:1; + uint32_t reserved_8_15:8; + uint32_t lme:6; + uint32_t reserved_22_31:10; +#endif } cn61xx; struct cvmx_pciercx_cfg452_s cn63xx; struct cvmx_pciercx_cfg452_s cn63xxp1; struct cvmx_pciercx_cfg452_cn61xx cn66xx; struct cvmx_pciercx_cfg452_cn61xx cn68xx; struct cvmx_pciercx_cfg452_cn61xx cn68xxp1; + struct cvmx_pciercx_cfg452_cn61xx cnf71xx; }; union cvmx_pciercx_cfg453 { uint32_t u32; struct cvmx_pciercx_cfg453_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t dlld:1; uint32_t reserved_26_30:5; uint32_t ack_nak:1; uint32_t fcd:1; uint32_t ilst:24; +#else + uint32_t ilst:24; + uint32_t fcd:1; + uint32_t ack_nak:1; + uint32_t reserved_26_30:5; + uint32_t dlld:1; +#endif } s; struct cvmx_pciercx_cfg453_s cn52xx; struct cvmx_pciercx_cfg453_s cn52xxp1; @@ -1540,11 +2543,13 @@ union cvmx_pciercx_cfg453 { struct cvmx_pciercx_cfg453_s cn66xx; struct cvmx_pciercx_cfg453_s cn68xx; struct cvmx_pciercx_cfg453_s cn68xxp1; + struct cvmx_pciercx_cfg453_s cnf71xx; }; union cvmx_pciercx_cfg454 { uint32_t u32; struct cvmx_pciercx_cfg454_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t cx_nfunc:3; uint32_t tmfcwt:5; uint32_t tmanlt:5; @@ -1552,8 +2557,18 @@ union cvmx_pciercx_cfg454 { uint32_t reserved_11_13:3; uint32_t nskps:3; uint32_t reserved_0_7:8; +#else + uint32_t reserved_0_7:8; + uint32_t nskps:3; + uint32_t reserved_11_13:3; + uint32_t tmrt:5; + uint32_t tmanlt:5; + uint32_t tmfcwt:5; + uint32_t cx_nfunc:3; +#endif } s; struct cvmx_pciercx_cfg454_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_29_31:3; uint32_t tmfcwt:5; uint32_t tmanlt:5; @@ -1562,28 +2577,49 @@ union cvmx_pciercx_cfg454 { uint32_t nskps:3; uint32_t reserved_4_7:4; uint32_t ntss:4; +#else + uint32_t ntss:4; + uint32_t reserved_4_7:4; + uint32_t nskps:3; + uint32_t reserved_11_13:3; + uint32_t tmrt:5; + uint32_t tmanlt:5; + uint32_t tmfcwt:5; + uint32_t reserved_29_31:3; +#endif } cn52xx; struct cvmx_pciercx_cfg454_cn52xx cn52xxp1; struct cvmx_pciercx_cfg454_cn52xx cn56xx; struct cvmx_pciercx_cfg454_cn52xx cn56xxp1; struct cvmx_pciercx_cfg454_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t cx_nfunc:3; uint32_t tmfcwt:5; uint32_t tmanlt:5; uint32_t tmrt:5; uint32_t reserved_8_13:6; uint32_t mfuncn:8; +#else + uint32_t mfuncn:8; + uint32_t reserved_8_13:6; + uint32_t tmrt:5; + uint32_t tmanlt:5; + uint32_t tmfcwt:5; + uint32_t cx_nfunc:3; +#endif } cn61xx; struct cvmx_pciercx_cfg454_cn52xx cn63xx; struct cvmx_pciercx_cfg454_cn52xx cn63xxp1; struct cvmx_pciercx_cfg454_cn61xx cn66xx; struct cvmx_pciercx_cfg454_cn61xx cn68xx; struct cvmx_pciercx_cfg454_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg454_cn61xx cnf71xx; }; union cvmx_pciercx_cfg455 { uint32_t u32; struct cvmx_pciercx_cfg455_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t m_cfg0_filt:1; uint32_t m_io_filt:1; uint32_t msg_ctrl:1; @@ -1603,6 +2639,27 @@ union cvmx_pciercx_cfg455 { uint32_t dfcwt:1; uint32_t reserved_11_14:4; uint32_t skpiv:11; +#else + uint32_t skpiv:11; + uint32_t reserved_11_14:4; + uint32_t dfcwt:1; + uint32_t m_fun:1; + uint32_t m_pois_filt:1; + uint32_t m_bar_match:1; + uint32_t m_cfg1_filt:1; + uint32_t m_lk_filt:1; + uint32_t m_cpl_tag_err:1; + uint32_t m_cpl_rid_err:1; + uint32_t m_cpl_fun_err:1; + uint32_t m_cpl_tc_err:1; + uint32_t m_cpl_attr_err:1; + uint32_t m_cpl_len_err:1; + uint32_t m_ecrc_filt:1; + uint32_t m_cpl_ecrc_filt:1; + uint32_t msg_ctrl:1; + uint32_t m_io_filt:1; + uint32_t m_cfg0_filt:1; +#endif } s; struct cvmx_pciercx_cfg455_s cn52xx; struct cvmx_pciercx_cfg455_s cn52xxp1; @@ -1614,21 +2671,36 @@ union cvmx_pciercx_cfg455 { struct cvmx_pciercx_cfg455_s cn66xx; struct cvmx_pciercx_cfg455_s cn68xx; struct cvmx_pciercx_cfg455_s cn68xxp1; + struct cvmx_pciercx_cfg455_s cnf71xx; }; union cvmx_pciercx_cfg456 { uint32_t u32; struct cvmx_pciercx_cfg456_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_4_31:28; uint32_t m_handle_flush:1; uint32_t m_dabort_4ucpl:1; uint32_t m_vend1_drp:1; uint32_t m_vend0_drp:1; +#else + uint32_t m_vend0_drp:1; + uint32_t m_vend1_drp:1; + uint32_t m_dabort_4ucpl:1; + uint32_t m_handle_flush:1; + uint32_t reserved_4_31:28; +#endif } s; struct cvmx_pciercx_cfg456_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_2_31:30; uint32_t m_vend1_drp:1; uint32_t m_vend0_drp:1; +#else + uint32_t m_vend0_drp:1; + uint32_t m_vend1_drp:1; + uint32_t reserved_2_31:30; +#endif } cn52xx; struct cvmx_pciercx_cfg456_cn52xx cn52xxp1; struct cvmx_pciercx_cfg456_cn52xx cn56xx; @@ -1639,12 +2711,17 @@ union cvmx_pciercx_cfg456 { struct cvmx_pciercx_cfg456_s cn66xx; struct cvmx_pciercx_cfg456_s cn68xx; struct cvmx_pciercx_cfg456_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg456_s cnf71xx; }; union cvmx_pciercx_cfg458 { uint32_t u32; struct cvmx_pciercx_cfg458_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t dbg_info_l32:32; +#else uint32_t dbg_info_l32:32; +#endif } s; struct cvmx_pciercx_cfg458_s cn52xx; struct cvmx_pciercx_cfg458_s cn52xxp1; @@ -1656,12 +2733,17 @@ union cvmx_pciercx_cfg458 { struct cvmx_pciercx_cfg458_s cn66xx; struct cvmx_pciercx_cfg458_s cn68xx; struct cvmx_pciercx_cfg458_s cn68xxp1; + struct cvmx_pciercx_cfg458_s cnf71xx; }; union cvmx_pciercx_cfg459 { uint32_t u32; struct cvmx_pciercx_cfg459_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t dbg_info_u32:32; +#else uint32_t dbg_info_u32:32; +#endif } s; struct cvmx_pciercx_cfg459_s cn52xx; struct cvmx_pciercx_cfg459_s cn52xxp1; @@ -1673,14 +2755,21 @@ union cvmx_pciercx_cfg459 { struct cvmx_pciercx_cfg459_s cn66xx; struct cvmx_pciercx_cfg459_s cn68xx; struct cvmx_pciercx_cfg459_s cn68xxp1; + struct cvmx_pciercx_cfg459_s cnf71xx; }; union cvmx_pciercx_cfg460 { uint32_t u32; struct cvmx_pciercx_cfg460_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_20_31:12; uint32_t tphfcc:8; uint32_t tpdfcc:12; +#else + uint32_t tpdfcc:12; + uint32_t tphfcc:8; + uint32_t reserved_20_31:12; +#endif } s; struct cvmx_pciercx_cfg460_s cn52xx; struct cvmx_pciercx_cfg460_s cn52xxp1; @@ -1692,14 +2781,21 @@ union cvmx_pciercx_cfg460 { struct cvmx_pciercx_cfg460_s cn66xx; struct cvmx_pciercx_cfg460_s cn68xx; struct cvmx_pciercx_cfg460_s cn68xxp1; + struct cvmx_pciercx_cfg460_s cnf71xx; }; union cvmx_pciercx_cfg461 { uint32_t u32; struct cvmx_pciercx_cfg461_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_20_31:12; uint32_t tchfcc:8; uint32_t tcdfcc:12; +#else + uint32_t tcdfcc:12; + uint32_t tchfcc:8; + uint32_t reserved_20_31:12; +#endif } s; struct cvmx_pciercx_cfg461_s cn52xx; struct cvmx_pciercx_cfg461_s cn52xxp1; @@ -1711,14 +2807,21 @@ union cvmx_pciercx_cfg461 { struct cvmx_pciercx_cfg461_s cn66xx; struct cvmx_pciercx_cfg461_s cn68xx; struct cvmx_pciercx_cfg461_s cn68xxp1; + struct cvmx_pciercx_cfg461_s cnf71xx; }; union cvmx_pciercx_cfg462 { uint32_t u32; struct cvmx_pciercx_cfg462_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_20_31:12; uint32_t tchfcc:8; uint32_t tcdfcc:12; +#else + uint32_t tcdfcc:12; + uint32_t tchfcc:8; + uint32_t reserved_20_31:12; +#endif } s; struct cvmx_pciercx_cfg462_s cn52xx; struct cvmx_pciercx_cfg462_s cn52xxp1; @@ -1730,15 +2833,23 @@ union cvmx_pciercx_cfg462 { struct cvmx_pciercx_cfg462_s cn66xx; struct cvmx_pciercx_cfg462_s cn68xx; struct cvmx_pciercx_cfg462_s cn68xxp1; + struct cvmx_pciercx_cfg462_s cnf71xx; }; union cvmx_pciercx_cfg463 { uint32_t u32; struct cvmx_pciercx_cfg463_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_3_31:29; uint32_t rqne:1; uint32_t trbne:1; uint32_t rtlpfccnr:1; +#else + uint32_t rtlpfccnr:1; + uint32_t trbne:1; + uint32_t rqne:1; + uint32_t reserved_3_31:29; +#endif } s; struct cvmx_pciercx_cfg463_s cn52xx; struct cvmx_pciercx_cfg463_s cn52xxp1; @@ -1750,15 +2861,23 @@ union cvmx_pciercx_cfg463 { struct cvmx_pciercx_cfg463_s cn66xx; struct cvmx_pciercx_cfg463_s cn68xx; struct cvmx_pciercx_cfg463_s cn68xxp1; + struct cvmx_pciercx_cfg463_s cnf71xx; }; union cvmx_pciercx_cfg464 { uint32_t u32; struct cvmx_pciercx_cfg464_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t wrr_vc3:8; uint32_t wrr_vc2:8; uint32_t wrr_vc1:8; uint32_t wrr_vc0:8; +#else + uint32_t wrr_vc0:8; + uint32_t wrr_vc1:8; + uint32_t wrr_vc2:8; + uint32_t wrr_vc3:8; +#endif } s; struct cvmx_pciercx_cfg464_s cn52xx; struct cvmx_pciercx_cfg464_s cn52xxp1; @@ -1770,15 +2889,23 @@ union cvmx_pciercx_cfg464 { struct cvmx_pciercx_cfg464_s cn66xx; struct cvmx_pciercx_cfg464_s cn68xx; struct cvmx_pciercx_cfg464_s cn68xxp1; + struct cvmx_pciercx_cfg464_s cnf71xx; }; union cvmx_pciercx_cfg465 { uint32_t u32; struct cvmx_pciercx_cfg465_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t wrr_vc7:8; uint32_t wrr_vc6:8; uint32_t wrr_vc5:8; uint32_t wrr_vc4:8; +#else + uint32_t wrr_vc4:8; + uint32_t wrr_vc5:8; + uint32_t wrr_vc6:8; + uint32_t wrr_vc7:8; +#endif } s; struct cvmx_pciercx_cfg465_s cn52xx; struct cvmx_pciercx_cfg465_s cn52xxp1; @@ -1790,11 +2917,13 @@ union cvmx_pciercx_cfg465 { struct cvmx_pciercx_cfg465_s cn66xx; struct cvmx_pciercx_cfg465_s cn68xx; struct cvmx_pciercx_cfg465_s cn68xxp1; + struct cvmx_pciercx_cfg465_s cnf71xx; }; union cvmx_pciercx_cfg466 { uint32_t u32; struct cvmx_pciercx_cfg466_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t rx_queue_order:1; uint32_t type_ordering:1; uint32_t reserved_24_29:6; @@ -1802,6 +2931,15 @@ union cvmx_pciercx_cfg466 { uint32_t reserved_20_20:1; uint32_t header_credits:8; uint32_t data_credits:12; +#else + uint32_t data_credits:12; + uint32_t header_credits:8; + uint32_t reserved_20_20:1; + uint32_t queue_mode:3; + uint32_t reserved_24_29:6; + uint32_t type_ordering:1; + uint32_t rx_queue_order:1; +#endif } s; struct cvmx_pciercx_cfg466_s cn52xx; struct cvmx_pciercx_cfg466_s cn52xxp1; @@ -1813,16 +2951,25 @@ union cvmx_pciercx_cfg466 { struct cvmx_pciercx_cfg466_s cn66xx; struct cvmx_pciercx_cfg466_s cn68xx; struct cvmx_pciercx_cfg466_s cn68xxp1; + struct cvmx_pciercx_cfg466_s cnf71xx; }; union cvmx_pciercx_cfg467 { uint32_t u32; struct cvmx_pciercx_cfg467_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_24_31:8; uint32_t queue_mode:3; uint32_t reserved_20_20:1; uint32_t header_credits:8; uint32_t data_credits:12; +#else + uint32_t data_credits:12; + uint32_t header_credits:8; + uint32_t reserved_20_20:1; + uint32_t queue_mode:3; + uint32_t reserved_24_31:8; +#endif } s; struct cvmx_pciercx_cfg467_s cn52xx; struct cvmx_pciercx_cfg467_s cn52xxp1; @@ -1834,16 +2981,25 @@ union cvmx_pciercx_cfg467 { struct cvmx_pciercx_cfg467_s cn66xx; struct cvmx_pciercx_cfg467_s cn68xx; struct cvmx_pciercx_cfg467_s cn68xxp1; + struct cvmx_pciercx_cfg467_s cnf71xx; }; union cvmx_pciercx_cfg468 { uint32_t u32; struct cvmx_pciercx_cfg468_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_24_31:8; uint32_t queue_mode:3; uint32_t reserved_20_20:1; uint32_t header_credits:8; uint32_t data_credits:12; +#else + uint32_t data_credits:12; + uint32_t header_credits:8; + uint32_t reserved_20_20:1; + uint32_t queue_mode:3; + uint32_t reserved_24_31:8; +#endif } s; struct cvmx_pciercx_cfg468_s cn52xx; struct cvmx_pciercx_cfg468_s cn52xxp1; @@ -1855,15 +3011,23 @@ union cvmx_pciercx_cfg468 { struct cvmx_pciercx_cfg468_s cn66xx; struct cvmx_pciercx_cfg468_s cn68xx; struct cvmx_pciercx_cfg468_s cn68xxp1; + struct cvmx_pciercx_cfg468_s cnf71xx; }; union cvmx_pciercx_cfg490 { uint32_t u32; struct cvmx_pciercx_cfg490_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_26_31:6; uint32_t header_depth:10; uint32_t reserved_14_15:2; uint32_t data_depth:14; +#else + uint32_t data_depth:14; + uint32_t reserved_14_15:2; + uint32_t header_depth:10; + uint32_t reserved_26_31:6; +#endif } s; struct cvmx_pciercx_cfg490_s cn52xx; struct cvmx_pciercx_cfg490_s cn52xxp1; @@ -1875,15 +3039,23 @@ union cvmx_pciercx_cfg490 { struct cvmx_pciercx_cfg490_s cn66xx; struct cvmx_pciercx_cfg490_s cn68xx; struct cvmx_pciercx_cfg490_s cn68xxp1; + struct cvmx_pciercx_cfg490_s cnf71xx; }; union cvmx_pciercx_cfg491 { uint32_t u32; struct cvmx_pciercx_cfg491_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_26_31:6; uint32_t header_depth:10; uint32_t reserved_14_15:2; uint32_t data_depth:14; +#else + uint32_t data_depth:14; + uint32_t reserved_14_15:2; + uint32_t header_depth:10; + uint32_t reserved_26_31:6; +#endif } s; struct cvmx_pciercx_cfg491_s cn52xx; struct cvmx_pciercx_cfg491_s cn52xxp1; @@ -1895,15 +3067,23 @@ union cvmx_pciercx_cfg491 { struct cvmx_pciercx_cfg491_s cn66xx; struct cvmx_pciercx_cfg491_s cn68xx; struct cvmx_pciercx_cfg491_s cn68xxp1; + struct cvmx_pciercx_cfg491_s cnf71xx; }; union cvmx_pciercx_cfg492 { uint32_t u32; struct cvmx_pciercx_cfg492_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_26_31:6; uint32_t header_depth:10; uint32_t reserved_14_15:2; uint32_t data_depth:14; +#else + uint32_t data_depth:14; + uint32_t reserved_14_15:2; + uint32_t header_depth:10; + uint32_t reserved_26_31:6; +#endif } s; struct cvmx_pciercx_cfg492_s cn52xx; struct cvmx_pciercx_cfg492_s cn52xxp1; @@ -1915,11 +3095,13 @@ union cvmx_pciercx_cfg492 { struct cvmx_pciercx_cfg492_s cn66xx; struct cvmx_pciercx_cfg492_s cn68xx; struct cvmx_pciercx_cfg492_s cn68xxp1; + struct cvmx_pciercx_cfg492_s cnf71xx; }; union cvmx_pciercx_cfg515 { uint32_t u32; struct cvmx_pciercx_cfg515_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_21_31:11; uint32_t s_d_e:1; uint32_t ctcrb:1; @@ -1927,6 +3109,15 @@ union cvmx_pciercx_cfg515 { uint32_t dsc:1; uint32_t le:9; uint32_t n_fts:8; +#else + uint32_t n_fts:8; + uint32_t le:9; + uint32_t dsc:1; + uint32_t cpyts:1; + uint32_t ctcrb:1; + uint32_t s_d_e:1; + uint32_t reserved_21_31:11; +#endif } s; struct cvmx_pciercx_cfg515_s cn61xx; struct cvmx_pciercx_cfg515_s cn63xx; @@ -1934,12 +3125,17 @@ union cvmx_pciercx_cfg515 { struct cvmx_pciercx_cfg515_s cn66xx; struct cvmx_pciercx_cfg515_s cn68xx; struct cvmx_pciercx_cfg515_s cn68xxp1; + struct cvmx_pciercx_cfg515_s cnf71xx; }; union cvmx_pciercx_cfg516 { uint32_t u32; struct cvmx_pciercx_cfg516_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t phy_stat:32; +#else uint32_t phy_stat:32; +#endif } s; struct cvmx_pciercx_cfg516_s cn52xx; struct cvmx_pciercx_cfg516_s cn52xxp1; @@ -1951,12 +3147,17 @@ union cvmx_pciercx_cfg516 { struct cvmx_pciercx_cfg516_s cn66xx; struct cvmx_pciercx_cfg516_s cn68xx; struct cvmx_pciercx_cfg516_s cn68xxp1; + struct cvmx_pciercx_cfg516_s cnf71xx; }; union cvmx_pciercx_cfg517 { uint32_t u32; struct cvmx_pciercx_cfg517_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t phy_ctrl:32; +#else uint32_t phy_ctrl:32; +#endif } s; struct cvmx_pciercx_cfg517_s cn52xx; struct cvmx_pciercx_cfg517_s cn52xxp1; @@ -1968,6 +3169,7 @@ union cvmx_pciercx_cfg517 { struct cvmx_pciercx_cfg517_s cn66xx; struct cvmx_pciercx_cfg517_s cn68xx; struct cvmx_pciercx_cfg517_s cn68xxp1; + struct cvmx_pciercx_cfg517_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h index d45952df5f5b..a5e8fd861c37 100644 --- a/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,44 +28,316 @@ #ifndef __CVMX_PCSX_DEFS_H__ #define __CVMX_PCSX_DEFS_H__ -#define CVMX_PCSX_ANX_ADV_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001010ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001028ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001018ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001020ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_INTX_EN_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001088ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_INTX_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001080ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001040ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001090ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001078ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001000ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001008ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_RXX_STATES_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001058ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001050ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001068ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001070ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_TXX_STATES_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001060ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001048ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} union cvmx_pcsx_anx_adv_reg { uint64_t u64; struct cvmx_pcsx_anx_adv_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t np:1; uint64_t reserved_14_14:1; @@ -75,32 +347,67 @@ union cvmx_pcsx_anx_adv_reg { uint64_t hfd:1; uint64_t fd:1; uint64_t reserved_0_4:5; +#else + uint64_t reserved_0_4:5; + uint64_t fd:1; + uint64_t hfd:1; + uint64_t pause:2; + uint64_t reserved_9_11:3; + uint64_t rem_flt:2; + uint64_t reserved_14_14:1; + uint64_t np:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_anx_adv_reg_s cn52xx; struct cvmx_pcsx_anx_adv_reg_s cn52xxp1; struct cvmx_pcsx_anx_adv_reg_s cn56xx; struct cvmx_pcsx_anx_adv_reg_s cn56xxp1; + struct cvmx_pcsx_anx_adv_reg_s cn61xx; + struct cvmx_pcsx_anx_adv_reg_s cn63xx; + struct cvmx_pcsx_anx_adv_reg_s cn63xxp1; + struct cvmx_pcsx_anx_adv_reg_s cn66xx; + struct cvmx_pcsx_anx_adv_reg_s cn68xx; + struct cvmx_pcsx_anx_adv_reg_s cn68xxp1; + struct cvmx_pcsx_anx_adv_reg_s cnf71xx; }; union cvmx_pcsx_anx_ext_st_reg { uint64_t u64; struct cvmx_pcsx_anx_ext_st_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t thou_xfd:1; uint64_t thou_xhd:1; uint64_t thou_tfd:1; uint64_t thou_thd:1; uint64_t reserved_0_11:12; +#else + uint64_t reserved_0_11:12; + uint64_t thou_thd:1; + uint64_t thou_tfd:1; + uint64_t thou_xhd:1; + uint64_t thou_xfd:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_anx_ext_st_reg_s cn52xx; struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1; struct cvmx_pcsx_anx_ext_st_reg_s cn56xx; struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1; + struct cvmx_pcsx_anx_ext_st_reg_s cn61xx; + struct cvmx_pcsx_anx_ext_st_reg_s cn63xx; + struct cvmx_pcsx_anx_ext_st_reg_s cn63xxp1; + struct cvmx_pcsx_anx_ext_st_reg_s cn66xx; + struct cvmx_pcsx_anx_ext_st_reg_s cn68xx; + struct cvmx_pcsx_anx_ext_st_reg_s cn68xxp1; + struct cvmx_pcsx_anx_ext_st_reg_s cnf71xx; }; union cvmx_pcsx_anx_lp_abil_reg { uint64_t u64; struct cvmx_pcsx_anx_lp_abil_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t np:1; uint64_t ack:1; @@ -110,33 +417,69 @@ union cvmx_pcsx_anx_lp_abil_reg { uint64_t hfd:1; uint64_t fd:1; uint64_t reserved_0_4:5; +#else + uint64_t reserved_0_4:5; + uint64_t fd:1; + uint64_t hfd:1; + uint64_t pause:2; + uint64_t reserved_9_11:3; + uint64_t rem_flt:2; + uint64_t ack:1; + uint64_t np:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx; struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1; struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx; struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1; + struct cvmx_pcsx_anx_lp_abil_reg_s cn61xx; + struct cvmx_pcsx_anx_lp_abil_reg_s cn63xx; + struct cvmx_pcsx_anx_lp_abil_reg_s cn63xxp1; + struct cvmx_pcsx_anx_lp_abil_reg_s cn66xx; + struct cvmx_pcsx_anx_lp_abil_reg_s cn68xx; + struct cvmx_pcsx_anx_lp_abil_reg_s cn68xxp1; + struct cvmx_pcsx_anx_lp_abil_reg_s cnf71xx; }; union cvmx_pcsx_anx_results_reg { uint64_t u64; struct cvmx_pcsx_anx_results_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t pause:2; uint64_t spd:2; uint64_t an_cpt:1; uint64_t dup:1; uint64_t link_ok:1; +#else + uint64_t link_ok:1; + uint64_t dup:1; + uint64_t an_cpt:1; + uint64_t spd:2; + uint64_t pause:2; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_pcsx_anx_results_reg_s cn52xx; struct cvmx_pcsx_anx_results_reg_s cn52xxp1; struct cvmx_pcsx_anx_results_reg_s cn56xx; struct cvmx_pcsx_anx_results_reg_s cn56xxp1; + struct cvmx_pcsx_anx_results_reg_s cn61xx; + struct cvmx_pcsx_anx_results_reg_s cn63xx; + struct cvmx_pcsx_anx_results_reg_s cn63xxp1; + struct cvmx_pcsx_anx_results_reg_s cn66xx; + struct cvmx_pcsx_anx_results_reg_s cn68xx; + struct cvmx_pcsx_anx_results_reg_s cn68xxp1; + struct cvmx_pcsx_anx_results_reg_s cnf71xx; }; union cvmx_pcsx_intx_en_reg { uint64_t u64; struct cvmx_pcsx_intx_en_reg_s { - uint64_t reserved_12_63:52; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_13_63:51; + uint64_t dbg_sync_en:1; uint64_t dup:1; uint64_t sync_bad_en:1; uint64_t an_bad_en:1; @@ -149,17 +492,72 @@ union cvmx_pcsx_intx_en_reg { uint64_t an_err_en:1; uint64_t xmit_en:1; uint64_t lnkspd_en:1; +#else + uint64_t lnkspd_en:1; + uint64_t xmit_en:1; + uint64_t an_err_en:1; + uint64_t txfifu_en:1; + uint64_t txfifo_en:1; + uint64_t txbad_en:1; + uint64_t rxerr_en:1; + uint64_t rxbad_en:1; + uint64_t rxlock_en:1; + uint64_t an_bad_en:1; + uint64_t sync_bad_en:1; + uint64_t dup:1; + uint64_t dbg_sync_en:1; + uint64_t reserved_13_63:51; +#endif } s; - struct cvmx_pcsx_intx_en_reg_s cn52xx; - struct cvmx_pcsx_intx_en_reg_s cn52xxp1; - struct cvmx_pcsx_intx_en_reg_s cn56xx; - struct cvmx_pcsx_intx_en_reg_s cn56xxp1; + struct cvmx_pcsx_intx_en_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t dup:1; + uint64_t sync_bad_en:1; + uint64_t an_bad_en:1; + uint64_t rxlock_en:1; + uint64_t rxbad_en:1; + uint64_t rxerr_en:1; + uint64_t txbad_en:1; + uint64_t txfifo_en:1; + uint64_t txfifu_en:1; + uint64_t an_err_en:1; + uint64_t xmit_en:1; + uint64_t lnkspd_en:1; +#else + uint64_t lnkspd_en:1; + uint64_t xmit_en:1; + uint64_t an_err_en:1; + uint64_t txfifu_en:1; + uint64_t txfifo_en:1; + uint64_t txbad_en:1; + uint64_t rxerr_en:1; + uint64_t rxbad_en:1; + uint64_t rxlock_en:1; + uint64_t an_bad_en:1; + uint64_t sync_bad_en:1; + uint64_t dup:1; + uint64_t reserved_12_63:52; +#endif + } cn52xx; + struct cvmx_pcsx_intx_en_reg_cn52xx cn52xxp1; + struct cvmx_pcsx_intx_en_reg_cn52xx cn56xx; + struct cvmx_pcsx_intx_en_reg_cn52xx cn56xxp1; + struct cvmx_pcsx_intx_en_reg_s cn61xx; + struct cvmx_pcsx_intx_en_reg_s cn63xx; + struct cvmx_pcsx_intx_en_reg_s cn63xxp1; + struct cvmx_pcsx_intx_en_reg_s cn66xx; + struct cvmx_pcsx_intx_en_reg_s cn68xx; + struct cvmx_pcsx_intx_en_reg_s cn68xxp1; + struct cvmx_pcsx_intx_en_reg_s cnf71xx; }; union cvmx_pcsx_intx_reg { uint64_t u64; struct cvmx_pcsx_intx_reg_s { - uint64_t reserved_12_63:52; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_13_63:51; + uint64_t dbg_sync:1; uint64_t dup:1; uint64_t sync_bad:1; uint64_t an_bad:1; @@ -172,42 +570,122 @@ union cvmx_pcsx_intx_reg { uint64_t an_err:1; uint64_t xmit:1; uint64_t lnkspd:1; +#else + uint64_t lnkspd:1; + uint64_t xmit:1; + uint64_t an_err:1; + uint64_t txfifu:1; + uint64_t txfifo:1; + uint64_t txbad:1; + uint64_t rxerr:1; + uint64_t rxbad:1; + uint64_t rxlock:1; + uint64_t an_bad:1; + uint64_t sync_bad:1; + uint64_t dup:1; + uint64_t dbg_sync:1; + uint64_t reserved_13_63:51; +#endif } s; - struct cvmx_pcsx_intx_reg_s cn52xx; - struct cvmx_pcsx_intx_reg_s cn52xxp1; - struct cvmx_pcsx_intx_reg_s cn56xx; - struct cvmx_pcsx_intx_reg_s cn56xxp1; + struct cvmx_pcsx_intx_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t dup:1; + uint64_t sync_bad:1; + uint64_t an_bad:1; + uint64_t rxlock:1; + uint64_t rxbad:1; + uint64_t rxerr:1; + uint64_t txbad:1; + uint64_t txfifo:1; + uint64_t txfifu:1; + uint64_t an_err:1; + uint64_t xmit:1; + uint64_t lnkspd:1; +#else + uint64_t lnkspd:1; + uint64_t xmit:1; + uint64_t an_err:1; + uint64_t txfifu:1; + uint64_t txfifo:1; + uint64_t txbad:1; + uint64_t rxerr:1; + uint64_t rxbad:1; + uint64_t rxlock:1; + uint64_t an_bad:1; + uint64_t sync_bad:1; + uint64_t dup:1; + uint64_t reserved_12_63:52; +#endif + } cn52xx; + struct cvmx_pcsx_intx_reg_cn52xx cn52xxp1; + struct cvmx_pcsx_intx_reg_cn52xx cn56xx; + struct cvmx_pcsx_intx_reg_cn52xx cn56xxp1; + struct cvmx_pcsx_intx_reg_s cn61xx; + struct cvmx_pcsx_intx_reg_s cn63xx; + struct cvmx_pcsx_intx_reg_s cn63xxp1; + struct cvmx_pcsx_intx_reg_s cn66xx; + struct cvmx_pcsx_intx_reg_s cn68xx; + struct cvmx_pcsx_intx_reg_s cn68xxp1; + struct cvmx_pcsx_intx_reg_s cnf71xx; }; union cvmx_pcsx_linkx_timer_count_reg { uint64_t u64; struct cvmx_pcsx_linkx_timer_count_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t count:16; +#else + uint64_t count:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx; struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1; struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx; struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1; + struct cvmx_pcsx_linkx_timer_count_reg_s cn61xx; + struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx; + struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1; + struct cvmx_pcsx_linkx_timer_count_reg_s cn66xx; + struct cvmx_pcsx_linkx_timer_count_reg_s cn68xx; + struct cvmx_pcsx_linkx_timer_count_reg_s cn68xxp1; + struct cvmx_pcsx_linkx_timer_count_reg_s cnf71xx; }; union cvmx_pcsx_log_anlx_reg { uint64_t u64; struct cvmx_pcsx_log_anlx_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t lafifovfl:1; uint64_t la_en:1; uint64_t pkt_sz:2; +#else + uint64_t pkt_sz:2; + uint64_t la_en:1; + uint64_t lafifovfl:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pcsx_log_anlx_reg_s cn52xx; struct cvmx_pcsx_log_anlx_reg_s cn52xxp1; struct cvmx_pcsx_log_anlx_reg_s cn56xx; struct cvmx_pcsx_log_anlx_reg_s cn56xxp1; + struct cvmx_pcsx_log_anlx_reg_s cn61xx; + struct cvmx_pcsx_log_anlx_reg_s cn63xx; + struct cvmx_pcsx_log_anlx_reg_s cn63xxp1; + struct cvmx_pcsx_log_anlx_reg_s cn66xx; + struct cvmx_pcsx_log_anlx_reg_s cn68xx; + struct cvmx_pcsx_log_anlx_reg_s cn68xxp1; + struct cvmx_pcsx_log_anlx_reg_s cnf71xx; }; union cvmx_pcsx_miscx_ctl_reg { uint64_t u64; struct cvmx_pcsx_miscx_ctl_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t sgmii:1; uint64_t gmxeno:1; @@ -216,16 +694,34 @@ union cvmx_pcsx_miscx_ctl_reg { uint64_t mode:1; uint64_t an_ovrd:1; uint64_t samp_pt:7; +#else + uint64_t samp_pt:7; + uint64_t an_ovrd:1; + uint64_t mode:1; + uint64_t mac_phy:1; + uint64_t loopbck2:1; + uint64_t gmxeno:1; + uint64_t sgmii:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_pcsx_miscx_ctl_reg_s cn52xx; struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1; struct cvmx_pcsx_miscx_ctl_reg_s cn56xx; struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1; + struct cvmx_pcsx_miscx_ctl_reg_s cn61xx; + struct cvmx_pcsx_miscx_ctl_reg_s cn63xx; + struct cvmx_pcsx_miscx_ctl_reg_s cn63xxp1; + struct cvmx_pcsx_miscx_ctl_reg_s cn66xx; + struct cvmx_pcsx_miscx_ctl_reg_s cn68xx; + struct cvmx_pcsx_miscx_ctl_reg_s cn68xxp1; + struct cvmx_pcsx_miscx_ctl_reg_s cnf71xx; }; union cvmx_pcsx_mrx_control_reg { uint64_t u64; struct cvmx_pcsx_mrx_control_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t reset:1; uint64_t loopbck1:1; @@ -239,16 +735,39 @@ union cvmx_pcsx_mrx_control_reg { uint64_t spdmsb:1; uint64_t uni:1; uint64_t reserved_0_4:5; +#else + uint64_t reserved_0_4:5; + uint64_t uni:1; + uint64_t spdmsb:1; + uint64_t coltst:1; + uint64_t dup:1; + uint64_t rst_an:1; + uint64_t reserved_10_10:1; + uint64_t pwr_dn:1; + uint64_t an_en:1; + uint64_t spdlsb:1; + uint64_t loopbck1:1; + uint64_t reset:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_mrx_control_reg_s cn52xx; struct cvmx_pcsx_mrx_control_reg_s cn52xxp1; struct cvmx_pcsx_mrx_control_reg_s cn56xx; struct cvmx_pcsx_mrx_control_reg_s cn56xxp1; + struct cvmx_pcsx_mrx_control_reg_s cn61xx; + struct cvmx_pcsx_mrx_control_reg_s cn63xx; + struct cvmx_pcsx_mrx_control_reg_s cn63xxp1; + struct cvmx_pcsx_mrx_control_reg_s cn66xx; + struct cvmx_pcsx_mrx_control_reg_s cn68xx; + struct cvmx_pcsx_mrx_control_reg_s cn68xxp1; + struct cvmx_pcsx_mrx_control_reg_s cnf71xx; }; union cvmx_pcsx_mrx_status_reg { uint64_t u64; struct cvmx_pcsx_mrx_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t hun_t4:1; uint64_t hun_xfd:1; @@ -266,16 +785,43 @@ union cvmx_pcsx_mrx_status_reg { uint64_t lnk_st:1; uint64_t reserved_1_1:1; uint64_t extnd:1; +#else + uint64_t extnd:1; + uint64_t reserved_1_1:1; + uint64_t lnk_st:1; + uint64_t an_abil:1; + uint64_t rm_flt:1; + uint64_t an_cpt:1; + uint64_t prb_sup:1; + uint64_t reserved_7_7:1; + uint64_t ext_st:1; + uint64_t hun_t2hd:1; + uint64_t hun_t2fd:1; + uint64_t ten_hd:1; + uint64_t ten_fd:1; + uint64_t hun_xhd:1; + uint64_t hun_xfd:1; + uint64_t hun_t4:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_mrx_status_reg_s cn52xx; struct cvmx_pcsx_mrx_status_reg_s cn52xxp1; struct cvmx_pcsx_mrx_status_reg_s cn56xx; struct cvmx_pcsx_mrx_status_reg_s cn56xxp1; + struct cvmx_pcsx_mrx_status_reg_s cn61xx; + struct cvmx_pcsx_mrx_status_reg_s cn63xx; + struct cvmx_pcsx_mrx_status_reg_s cn63xxp1; + struct cvmx_pcsx_mrx_status_reg_s cn66xx; + struct cvmx_pcsx_mrx_status_reg_s cn68xx; + struct cvmx_pcsx_mrx_status_reg_s cn68xxp1; + struct cvmx_pcsx_mrx_status_reg_s cnf71xx; }; union cvmx_pcsx_rxx_states_reg { uint64_t u64; struct cvmx_pcsx_rxx_states_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t rx_bad:1; uint64_t rx_st:5; @@ -283,29 +829,59 @@ union cvmx_pcsx_rxx_states_reg { uint64_t sync:4; uint64_t an_bad:1; uint64_t an_st:4; +#else + uint64_t an_st:4; + uint64_t an_bad:1; + uint64_t sync:4; + uint64_t sync_bad:1; + uint64_t rx_st:5; + uint64_t rx_bad:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_rxx_states_reg_s cn52xx; struct cvmx_pcsx_rxx_states_reg_s cn52xxp1; struct cvmx_pcsx_rxx_states_reg_s cn56xx; struct cvmx_pcsx_rxx_states_reg_s cn56xxp1; + struct cvmx_pcsx_rxx_states_reg_s cn61xx; + struct cvmx_pcsx_rxx_states_reg_s cn63xx; + struct cvmx_pcsx_rxx_states_reg_s cn63xxp1; + struct cvmx_pcsx_rxx_states_reg_s cn66xx; + struct cvmx_pcsx_rxx_states_reg_s cn68xx; + struct cvmx_pcsx_rxx_states_reg_s cn68xxp1; + struct cvmx_pcsx_rxx_states_reg_s cnf71xx; }; union cvmx_pcsx_rxx_sync_reg { uint64_t u64; struct cvmx_pcsx_rxx_sync_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t sync:1; uint64_t bit_lock:1; +#else + uint64_t bit_lock:1; + uint64_t sync:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pcsx_rxx_sync_reg_s cn52xx; struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1; struct cvmx_pcsx_rxx_sync_reg_s cn56xx; struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1; + struct cvmx_pcsx_rxx_sync_reg_s cn61xx; + struct cvmx_pcsx_rxx_sync_reg_s cn63xx; + struct cvmx_pcsx_rxx_sync_reg_s cn63xxp1; + struct cvmx_pcsx_rxx_sync_reg_s cn66xx; + struct cvmx_pcsx_rxx_sync_reg_s cn68xx; + struct cvmx_pcsx_rxx_sync_reg_s cn68xxp1; + struct cvmx_pcsx_rxx_sync_reg_s cnf71xx; }; union cvmx_pcsx_sgmx_an_adv_reg { uint64_t u64; struct cvmx_pcsx_sgmx_an_adv_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t link:1; uint64_t ack:1; @@ -314,16 +890,34 @@ union cvmx_pcsx_sgmx_an_adv_reg { uint64_t speed:2; uint64_t reserved_1_9:9; uint64_t one:1; +#else + uint64_t one:1; + uint64_t reserved_1_9:9; + uint64_t speed:2; + uint64_t dup:1; + uint64_t reserved_13_13:1; + uint64_t ack:1; + uint64_t link:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx; struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1; struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx; struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn61xx; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xx; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xxp1; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn66xx; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xx; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xxp1; + struct cvmx_pcsx_sgmx_an_adv_reg_s cnf71xx; }; union cvmx_pcsx_sgmx_lp_adv_reg { uint64_t u64; struct cvmx_pcsx_sgmx_lp_adv_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t link:1; uint64_t reserved_13_14:2; @@ -331,40 +925,85 @@ union cvmx_pcsx_sgmx_lp_adv_reg { uint64_t speed:2; uint64_t reserved_1_9:9; uint64_t one:1; +#else + uint64_t one:1; + uint64_t reserved_1_9:9; + uint64_t speed:2; + uint64_t dup:1; + uint64_t reserved_13_14:2; + uint64_t link:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx; struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1; struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx; struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn61xx; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xx; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xxp1; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn66xx; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xx; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xxp1; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cnf71xx; }; union cvmx_pcsx_txx_states_reg { uint64_t u64; struct cvmx_pcsx_txx_states_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t xmit:2; uint64_t tx_bad:1; uint64_t ord_st:4; +#else + uint64_t ord_st:4; + uint64_t tx_bad:1; + uint64_t xmit:2; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_pcsx_txx_states_reg_s cn52xx; struct cvmx_pcsx_txx_states_reg_s cn52xxp1; struct cvmx_pcsx_txx_states_reg_s cn56xx; struct cvmx_pcsx_txx_states_reg_s cn56xxp1; + struct cvmx_pcsx_txx_states_reg_s cn61xx; + struct cvmx_pcsx_txx_states_reg_s cn63xx; + struct cvmx_pcsx_txx_states_reg_s cn63xxp1; + struct cvmx_pcsx_txx_states_reg_s cn66xx; + struct cvmx_pcsx_txx_states_reg_s cn68xx; + struct cvmx_pcsx_txx_states_reg_s cn68xxp1; + struct cvmx_pcsx_txx_states_reg_s cnf71xx; }; union cvmx_pcsx_tx_rxx_polarity_reg { uint64_t u64; struct cvmx_pcsx_tx_rxx_polarity_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t rxovrd:1; uint64_t autorxpl:1; uint64_t rxplrt:1; uint64_t txplrt:1; +#else + uint64_t txplrt:1; + uint64_t rxplrt:1; + uint64_t autorxpl:1; + uint64_t rxovrd:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx; struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1; struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx; struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn61xx; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn66xx; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xx; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xxp1; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h index 55d120fe8aed..b5b45d26f1c5 100644 --- a/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,40 +28,250 @@ #ifndef __CVMX_PCSXX_DEFS_H__ #define __CVMX_PCSXX_DEFS_H__ -#define CVMX_PCSXX_10GBX_STATUS_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000828ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_BIST_STATUS_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000870ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000850ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_CONTROL1_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000800ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_CONTROL2_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000818ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_INT_EN_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000860ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_INT_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000858ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_LOG_ANL_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000868ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_MISC_CTL_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000848ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000838ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_SPD_ABIL_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000810ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_STATUS1_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000808ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_STATUS2_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000820ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000840ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_TX_RX_STATES_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000830ull + (((block_id) & 1) * 0x8000000ull)) +static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull; +} union cvmx_pcsxx_10gbx_status_reg { uint64_t u64; struct cvmx_pcsxx_10gbx_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t alignd:1; uint64_t pattst:1; @@ -70,43 +280,85 @@ union cvmx_pcsxx_10gbx_status_reg { uint64_t l2sync:1; uint64_t l1sync:1; uint64_t l0sync:1; +#else + uint64_t l0sync:1; + uint64_t l1sync:1; + uint64_t l2sync:1; + uint64_t l3sync:1; + uint64_t reserved_4_10:7; + uint64_t pattst:1; + uint64_t alignd:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_pcsxx_10gbx_status_reg_s cn52xx; struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1; struct cvmx_pcsxx_10gbx_status_reg_s cn56xx; struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1; + struct cvmx_pcsxx_10gbx_status_reg_s cn61xx; + struct cvmx_pcsxx_10gbx_status_reg_s cn63xx; + struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1; + struct cvmx_pcsxx_10gbx_status_reg_s cn66xx; + struct cvmx_pcsxx_10gbx_status_reg_s cn68xx; + struct cvmx_pcsxx_10gbx_status_reg_s cn68xxp1; }; union cvmx_pcsxx_bist_status_reg { uint64_t u64; struct cvmx_pcsxx_bist_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t bist_status:1; +#else + uint64_t bist_status:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_pcsxx_bist_status_reg_s cn52xx; struct cvmx_pcsxx_bist_status_reg_s cn52xxp1; struct cvmx_pcsxx_bist_status_reg_s cn56xx; struct cvmx_pcsxx_bist_status_reg_s cn56xxp1; + struct cvmx_pcsxx_bist_status_reg_s cn61xx; + struct cvmx_pcsxx_bist_status_reg_s cn63xx; + struct cvmx_pcsxx_bist_status_reg_s cn63xxp1; + struct cvmx_pcsxx_bist_status_reg_s cn66xx; + struct cvmx_pcsxx_bist_status_reg_s cn68xx; + struct cvmx_pcsxx_bist_status_reg_s cn68xxp1; }; union cvmx_pcsxx_bit_lock_status_reg { uint64_t u64; struct cvmx_pcsxx_bit_lock_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t bitlck3:1; uint64_t bitlck2:1; uint64_t bitlck1:1; uint64_t bitlck0:1; +#else + uint64_t bitlck0:1; + uint64_t bitlck1:1; + uint64_t bitlck2:1; + uint64_t bitlck3:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx; struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1; struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx; struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1; + struct cvmx_pcsxx_bit_lock_status_reg_s cn61xx; + struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx; + struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1; + struct cvmx_pcsxx_bit_lock_status_reg_s cn66xx; + struct cvmx_pcsxx_bit_lock_status_reg_s cn68xx; + struct cvmx_pcsxx_bit_lock_status_reg_s cn68xxp1; }; union cvmx_pcsxx_control1_reg { uint64_t u64; struct cvmx_pcsxx_control1_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t reset:1; uint64_t loopbck1:1; @@ -117,137 +369,309 @@ union cvmx_pcsxx_control1_reg { uint64_t spdsel0:1; uint64_t spd:4; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t spd:4; + uint64_t spdsel0:1; + uint64_t reserved_7_10:4; + uint64_t lo_pwr:1; + uint64_t reserved_12_12:1; + uint64_t spdsel1:1; + uint64_t loopbck1:1; + uint64_t reset:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsxx_control1_reg_s cn52xx; struct cvmx_pcsxx_control1_reg_s cn52xxp1; struct cvmx_pcsxx_control1_reg_s cn56xx; struct cvmx_pcsxx_control1_reg_s cn56xxp1; + struct cvmx_pcsxx_control1_reg_s cn61xx; + struct cvmx_pcsxx_control1_reg_s cn63xx; + struct cvmx_pcsxx_control1_reg_s cn63xxp1; + struct cvmx_pcsxx_control1_reg_s cn66xx; + struct cvmx_pcsxx_control1_reg_s cn68xx; + struct cvmx_pcsxx_control1_reg_s cn68xxp1; }; union cvmx_pcsxx_control2_reg { uint64_t u64; struct cvmx_pcsxx_control2_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t type:2; +#else + uint64_t type:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pcsxx_control2_reg_s cn52xx; struct cvmx_pcsxx_control2_reg_s cn52xxp1; struct cvmx_pcsxx_control2_reg_s cn56xx; struct cvmx_pcsxx_control2_reg_s cn56xxp1; + struct cvmx_pcsxx_control2_reg_s cn61xx; + struct cvmx_pcsxx_control2_reg_s cn63xx; + struct cvmx_pcsxx_control2_reg_s cn63xxp1; + struct cvmx_pcsxx_control2_reg_s cn66xx; + struct cvmx_pcsxx_control2_reg_s cn68xx; + struct cvmx_pcsxx_control2_reg_s cn68xxp1; }; union cvmx_pcsxx_int_en_reg { uint64_t u64; struct cvmx_pcsxx_int_en_reg_s { - uint64_t reserved_6_63:58; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t dbg_sync_en:1; uint64_t algnlos_en:1; uint64_t synlos_en:1; uint64_t bitlckls_en:1; uint64_t rxsynbad_en:1; uint64_t rxbad_en:1; uint64_t txflt_en:1; +#else + uint64_t txflt_en:1; + uint64_t rxbad_en:1; + uint64_t rxsynbad_en:1; + uint64_t bitlckls_en:1; + uint64_t synlos_en:1; + uint64_t algnlos_en:1; + uint64_t dbg_sync_en:1; + uint64_t reserved_7_63:57; +#endif } s; - struct cvmx_pcsxx_int_en_reg_s cn52xx; - struct cvmx_pcsxx_int_en_reg_s cn52xxp1; - struct cvmx_pcsxx_int_en_reg_s cn56xx; - struct cvmx_pcsxx_int_en_reg_s cn56xxp1; + struct cvmx_pcsxx_int_en_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_63:58; + uint64_t algnlos_en:1; + uint64_t synlos_en:1; + uint64_t bitlckls_en:1; + uint64_t rxsynbad_en:1; + uint64_t rxbad_en:1; + uint64_t txflt_en:1; +#else + uint64_t txflt_en:1; + uint64_t rxbad_en:1; + uint64_t rxsynbad_en:1; + uint64_t bitlckls_en:1; + uint64_t synlos_en:1; + uint64_t algnlos_en:1; + uint64_t reserved_6_63:58; +#endif + } cn52xx; + struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1; + struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx; + struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1; + struct cvmx_pcsxx_int_en_reg_s cn61xx; + struct cvmx_pcsxx_int_en_reg_s cn63xx; + struct cvmx_pcsxx_int_en_reg_s cn63xxp1; + struct cvmx_pcsxx_int_en_reg_s cn66xx; + struct cvmx_pcsxx_int_en_reg_s cn68xx; + struct cvmx_pcsxx_int_en_reg_s cn68xxp1; }; union cvmx_pcsxx_int_reg { uint64_t u64; struct cvmx_pcsxx_int_reg_s { - uint64_t reserved_6_63:58; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t dbg_sync:1; uint64_t algnlos:1; uint64_t synlos:1; uint64_t bitlckls:1; uint64_t rxsynbad:1; uint64_t rxbad:1; uint64_t txflt:1; +#else + uint64_t txflt:1; + uint64_t rxbad:1; + uint64_t rxsynbad:1; + uint64_t bitlckls:1; + uint64_t synlos:1; + uint64_t algnlos:1; + uint64_t dbg_sync:1; + uint64_t reserved_7_63:57; +#endif } s; - struct cvmx_pcsxx_int_reg_s cn52xx; - struct cvmx_pcsxx_int_reg_s cn52xxp1; - struct cvmx_pcsxx_int_reg_s cn56xx; - struct cvmx_pcsxx_int_reg_s cn56xxp1; + struct cvmx_pcsxx_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_63:58; + uint64_t algnlos:1; + uint64_t synlos:1; + uint64_t bitlckls:1; + uint64_t rxsynbad:1; + uint64_t rxbad:1; + uint64_t txflt:1; +#else + uint64_t txflt:1; + uint64_t rxbad:1; + uint64_t rxsynbad:1; + uint64_t bitlckls:1; + uint64_t synlos:1; + uint64_t algnlos:1; + uint64_t reserved_6_63:58; +#endif + } cn52xx; + struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1; + struct cvmx_pcsxx_int_reg_cn52xx cn56xx; + struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1; + struct cvmx_pcsxx_int_reg_s cn61xx; + struct cvmx_pcsxx_int_reg_s cn63xx; + struct cvmx_pcsxx_int_reg_s cn63xxp1; + struct cvmx_pcsxx_int_reg_s cn66xx; + struct cvmx_pcsxx_int_reg_s cn68xx; + struct cvmx_pcsxx_int_reg_s cn68xxp1; }; union cvmx_pcsxx_log_anl_reg { uint64_t u64; struct cvmx_pcsxx_log_anl_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t enc_mode:1; uint64_t drop_ln:2; uint64_t lafifovfl:1; uint64_t la_en:1; uint64_t pkt_sz:2; +#else + uint64_t pkt_sz:2; + uint64_t la_en:1; + uint64_t lafifovfl:1; + uint64_t drop_ln:2; + uint64_t enc_mode:1; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_pcsxx_log_anl_reg_s cn52xx; struct cvmx_pcsxx_log_anl_reg_s cn52xxp1; struct cvmx_pcsxx_log_anl_reg_s cn56xx; struct cvmx_pcsxx_log_anl_reg_s cn56xxp1; + struct cvmx_pcsxx_log_anl_reg_s cn61xx; + struct cvmx_pcsxx_log_anl_reg_s cn63xx; + struct cvmx_pcsxx_log_anl_reg_s cn63xxp1; + struct cvmx_pcsxx_log_anl_reg_s cn66xx; + struct cvmx_pcsxx_log_anl_reg_s cn68xx; + struct cvmx_pcsxx_log_anl_reg_s cn68xxp1; }; union cvmx_pcsxx_misc_ctl_reg { uint64_t u64; struct cvmx_pcsxx_misc_ctl_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t tx_swap:1; uint64_t rx_swap:1; uint64_t xaui:1; uint64_t gmxeno:1; +#else + uint64_t gmxeno:1; + uint64_t xaui:1; + uint64_t rx_swap:1; + uint64_t tx_swap:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pcsxx_misc_ctl_reg_s cn52xx; struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1; struct cvmx_pcsxx_misc_ctl_reg_s cn56xx; struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1; + struct cvmx_pcsxx_misc_ctl_reg_s cn61xx; + struct cvmx_pcsxx_misc_ctl_reg_s cn63xx; + struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1; + struct cvmx_pcsxx_misc_ctl_reg_s cn66xx; + struct cvmx_pcsxx_misc_ctl_reg_s cn68xx; + struct cvmx_pcsxx_misc_ctl_reg_s cn68xxp1; }; union cvmx_pcsxx_rx_sync_states_reg { uint64_t u64; struct cvmx_pcsxx_rx_sync_states_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t sync3st:4; uint64_t sync2st:4; uint64_t sync1st:4; uint64_t sync0st:4; +#else + uint64_t sync0st:4; + uint64_t sync1st:4; + uint64_t sync2st:4; + uint64_t sync3st:4; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx; struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1; struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx; struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1; + struct cvmx_pcsxx_rx_sync_states_reg_s cn61xx; + struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx; + struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1; + struct cvmx_pcsxx_rx_sync_states_reg_s cn66xx; + struct cvmx_pcsxx_rx_sync_states_reg_s cn68xx; + struct cvmx_pcsxx_rx_sync_states_reg_s cn68xxp1; }; union cvmx_pcsxx_spd_abil_reg { uint64_t u64; struct cvmx_pcsxx_spd_abil_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t tenpasst:1; uint64_t tengb:1; +#else + uint64_t tengb:1; + uint64_t tenpasst:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pcsxx_spd_abil_reg_s cn52xx; struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1; struct cvmx_pcsxx_spd_abil_reg_s cn56xx; struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1; + struct cvmx_pcsxx_spd_abil_reg_s cn61xx; + struct cvmx_pcsxx_spd_abil_reg_s cn63xx; + struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1; + struct cvmx_pcsxx_spd_abil_reg_s cn66xx; + struct cvmx_pcsxx_spd_abil_reg_s cn68xx; + struct cvmx_pcsxx_spd_abil_reg_s cn68xxp1; }; union cvmx_pcsxx_status1_reg { uint64_t u64; struct cvmx_pcsxx_status1_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t flt:1; uint64_t reserved_3_6:4; uint64_t rcv_lnk:1; uint64_t lpable:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t lpable:1; + uint64_t rcv_lnk:1; + uint64_t reserved_3_6:4; + uint64_t flt:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_pcsxx_status1_reg_s cn52xx; struct cvmx_pcsxx_status1_reg_s cn52xxp1; struct cvmx_pcsxx_status1_reg_s cn56xx; struct cvmx_pcsxx_status1_reg_s cn56xxp1; + struct cvmx_pcsxx_status1_reg_s cn61xx; + struct cvmx_pcsxx_status1_reg_s cn63xx; + struct cvmx_pcsxx_status1_reg_s cn63xxp1; + struct cvmx_pcsxx_status1_reg_s cn66xx; + struct cvmx_pcsxx_status1_reg_s cn68xx; + struct cvmx_pcsxx_status1_reg_s cn68xxp1; }; union cvmx_pcsxx_status2_reg { uint64_t u64; struct cvmx_pcsxx_status2_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dev:2; uint64_t reserved_12_13:2; @@ -257,35 +681,73 @@ union cvmx_pcsxx_status2_reg { uint64_t tengb_w:1; uint64_t tengb_x:1; uint64_t tengb_r:1; +#else + uint64_t tengb_r:1; + uint64_t tengb_x:1; + uint64_t tengb_w:1; + uint64_t reserved_3_9:7; + uint64_t rcvflt:1; + uint64_t xmtflt:1; + uint64_t reserved_12_13:2; + uint64_t dev:2; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsxx_status2_reg_s cn52xx; struct cvmx_pcsxx_status2_reg_s cn52xxp1; struct cvmx_pcsxx_status2_reg_s cn56xx; struct cvmx_pcsxx_status2_reg_s cn56xxp1; + struct cvmx_pcsxx_status2_reg_s cn61xx; + struct cvmx_pcsxx_status2_reg_s cn63xx; + struct cvmx_pcsxx_status2_reg_s cn63xxp1; + struct cvmx_pcsxx_status2_reg_s cn66xx; + struct cvmx_pcsxx_status2_reg_s cn68xx; + struct cvmx_pcsxx_status2_reg_s cn68xxp1; }; union cvmx_pcsxx_tx_rx_polarity_reg { uint64_t u64; struct cvmx_pcsxx_tx_rx_polarity_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t xor_rxplrt:4; uint64_t xor_txplrt:4; uint64_t rxplrt:1; uint64_t txplrt:1; +#else + uint64_t txplrt:1; + uint64_t rxplrt:1; + uint64_t xor_txplrt:4; + uint64_t xor_rxplrt:4; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx; struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t rxplrt:1; uint64_t txplrt:1; +#else + uint64_t txplrt:1; + uint64_t rxplrt:1; + uint64_t reserved_2_63:62; +#endif } cn52xxp1; struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx; struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn61xx; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn66xx; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xx; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xxp1; }; union cvmx_pcsxx_tx_rx_states_reg { uint64_t u64; struct cvmx_pcsxx_tx_rx_states_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t term_err:1; uint64_t syn3bad:1; @@ -296,9 +758,22 @@ union cvmx_pcsxx_tx_rx_states_reg { uint64_t algn_st:3; uint64_t rx_st:2; uint64_t tx_st:3; +#else + uint64_t tx_st:3; + uint64_t rx_st:2; + uint64_t algn_st:3; + uint64_t rxbad:1; + uint64_t syn0bad:1; + uint64_t syn1bad:1; + uint64_t syn2bad:1; + uint64_t syn3bad:1; + uint64_t term_err:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx; struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t syn3bad:1; uint64_t syn2bad:1; @@ -308,9 +783,26 @@ union cvmx_pcsxx_tx_rx_states_reg { uint64_t algn_st:3; uint64_t rx_st:2; uint64_t tx_st:3; +#else + uint64_t tx_st:3; + uint64_t rx_st:2; + uint64_t algn_st:3; + uint64_t rxbad:1; + uint64_t syn0bad:1; + uint64_t syn1bad:1; + uint64_t syn2bad:1; + uint64_t syn3bad:1; + uint64_t reserved_13_63:51; +#endif } cn52xxp1; struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx; struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1; + struct cvmx_pcsxx_tx_rx_states_reg_s cn61xx; + struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx; + struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1; + struct cvmx_pcsxx_tx_rx_states_reg_s cn66xx; + struct cvmx_pcsxx_tx_rx_states_reg_s cn68xx; + struct cvmx_pcsxx_tx_rx_states_reg_s cn68xxp1; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h index be189a2585e0..50a916f892fa 100644 --- a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2011 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -54,11 +54,19 @@ union cvmx_pemx_bar1_indexx { uint64_t u64; struct cvmx_pemx_bar1_indexx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t addr_idx:16; uint64_t ca:1; uint64_t end_swp:2; uint64_t addr_v:1; +#else + uint64_t addr_v:1; + uint64_t end_swp:2; + uint64_t ca:1; + uint64_t addr_idx:16; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_pemx_bar1_indexx_s cn61xx; struct cvmx_pemx_bar1_indexx_s cn63xx; @@ -66,29 +74,45 @@ union cvmx_pemx_bar1_indexx { struct cvmx_pemx_bar1_indexx_s cn66xx; struct cvmx_pemx_bar1_indexx_s cn68xx; struct cvmx_pemx_bar1_indexx_s cn68xxp1; + struct cvmx_pemx_bar1_indexx_s cnf71xx; }; union cvmx_pemx_bar2_mask { uint64_t u64; struct cvmx_pemx_bar2_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t mask:35; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t mask:35; + uint64_t reserved_38_63:26; +#endif } s; struct cvmx_pemx_bar2_mask_s cn61xx; struct cvmx_pemx_bar2_mask_s cn66xx; struct cvmx_pemx_bar2_mask_s cn68xx; struct cvmx_pemx_bar2_mask_s cn68xxp1; + struct cvmx_pemx_bar2_mask_s cnf71xx; }; union cvmx_pemx_bar_ctl { uint64_t u64; struct cvmx_pemx_bar_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t bar1_siz:3; uint64_t bar2_enb:1; uint64_t bar2_esx:2; uint64_t bar2_cax:1; +#else + uint64_t bar2_cax:1; + uint64_t bar2_esx:2; + uint64_t bar2_enb:1; + uint64_t bar1_siz:3; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_pemx_bar_ctl_s cn61xx; struct cvmx_pemx_bar_ctl_s cn63xx; @@ -96,11 +120,13 @@ union cvmx_pemx_bar_ctl { struct cvmx_pemx_bar_ctl_s cn66xx; struct cvmx_pemx_bar_ctl_s cn68xx; struct cvmx_pemx_bar_ctl_s cn68xxp1; + struct cvmx_pemx_bar_ctl_s cnf71xx; }; union cvmx_pemx_bist_status { uint64_t u64; struct cvmx_pemx_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t retry:1; uint64_t rqdata0:1; @@ -110,6 +136,17 @@ union cvmx_pemx_bist_status { uint64_t rqhdr1:1; uint64_t rqhdr0:1; uint64_t sot:1; +#else + uint64_t sot:1; + uint64_t rqhdr0:1; + uint64_t rqhdr1:1; + uint64_t rqdata3:1; + uint64_t rqdata2:1; + uint64_t rqdata1:1; + uint64_t rqdata0:1; + uint64_t retry:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_pemx_bist_status_s cn61xx; struct cvmx_pemx_bist_status_s cn63xx; @@ -117,11 +154,13 @@ union cvmx_pemx_bist_status { struct cvmx_pemx_bist_status_s cn66xx; struct cvmx_pemx_bist_status_s cn68xx; struct cvmx_pemx_bist_status_s cn68xxp1; + struct cvmx_pemx_bist_status_s cnf71xx; }; union cvmx_pemx_bist_status2 { uint64_t u64; struct cvmx_pemx_bist_status2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t e2p_cpl:1; uint64_t e2p_n:1; @@ -133,6 +172,19 @@ union cvmx_pemx_bist_status2 { uint64_t pef_tcf1:1; uint64_t pef_tc0:1; uint64_t ppf:1; +#else + uint64_t ppf:1; + uint64_t pef_tc0:1; + uint64_t pef_tcf1:1; + uint64_t pef_tnf:1; + uint64_t pef_tpf0:1; + uint64_t pef_tpf1:1; + uint64_t peai_p2e:1; + uint64_t e2p_p:1; + uint64_t e2p_n:1; + uint64_t e2p_cpl:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_pemx_bist_status2_s cn61xx; struct cvmx_pemx_bist_status2_s cn63xx; @@ -140,13 +192,19 @@ union cvmx_pemx_bist_status2 { struct cvmx_pemx_bist_status2_s cn66xx; struct cvmx_pemx_bist_status2_s cn68xx; struct cvmx_pemx_bist_status2_s cn68xxp1; + struct cvmx_pemx_bist_status2_s cnf71xx; }; union cvmx_pemx_cfg_rd { uint64_t u64; struct cvmx_pemx_cfg_rd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:32; uint64_t addr:32; +#else + uint64_t addr:32; + uint64_t data:32; +#endif } s; struct cvmx_pemx_cfg_rd_s cn61xx; struct cvmx_pemx_cfg_rd_s cn63xx; @@ -154,13 +212,19 @@ union cvmx_pemx_cfg_rd { struct cvmx_pemx_cfg_rd_s cn66xx; struct cvmx_pemx_cfg_rd_s cn68xx; struct cvmx_pemx_cfg_rd_s cn68xxp1; + struct cvmx_pemx_cfg_rd_s cnf71xx; }; union cvmx_pemx_cfg_wr { uint64_t u64; struct cvmx_pemx_cfg_wr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:32; uint64_t addr:32; +#else + uint64_t addr:32; + uint64_t data:32; +#endif } s; struct cvmx_pemx_cfg_wr_s cn61xx; struct cvmx_pemx_cfg_wr_s cn63xx; @@ -168,13 +232,19 @@ union cvmx_pemx_cfg_wr { struct cvmx_pemx_cfg_wr_s cn66xx; struct cvmx_pemx_cfg_wr_s cn68xx; struct cvmx_pemx_cfg_wr_s cn68xxp1; + struct cvmx_pemx_cfg_wr_s cnf71xx; }; union cvmx_pemx_cpl_lut_valid { uint64_t u64; struct cvmx_pemx_cpl_lut_valid_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t tag:32; +#else + uint64_t tag:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pemx_cpl_lut_valid_s cn61xx; struct cvmx_pemx_cpl_lut_valid_s cn63xx; @@ -182,11 +252,13 @@ union cvmx_pemx_cpl_lut_valid { struct cvmx_pemx_cpl_lut_valid_s cn66xx; struct cvmx_pemx_cpl_lut_valid_s cn68xx; struct cvmx_pemx_cpl_lut_valid_s cn68xxp1; + struct cvmx_pemx_cpl_lut_valid_s cnf71xx; }; union cvmx_pemx_ctl_status { uint64_t u64; struct cvmx_pemx_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t auto_sd:1; uint64_t dnum:5; @@ -205,6 +277,26 @@ union cvmx_pemx_ctl_status { uint64_t fast_lm:1; uint64_t inv_ecrc:1; uint64_t inv_lcrc:1; +#else + uint64_t inv_lcrc:1; + uint64_t inv_ecrc:1; + uint64_t fast_lm:1; + uint64_t ro_ctlp:1; + uint64_t lnk_enb:1; + uint64_t dly_one:1; + uint64_t nf_ecrc:1; + uint64_t reserved_7_8:2; + uint64_t ob_p_cmd:1; + uint64_t pm_xpme:1; + uint64_t pm_xtoff:1; + uint64_t reserved_12_15:4; + uint64_t cfg_rtry:16; + uint64_t reserved_32_33:2; + uint64_t pbus:8; + uint64_t dnum:5; + uint64_t auto_sd:1; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_pemx_ctl_status_s cn61xx; struct cvmx_pemx_ctl_status_s cn63xx; @@ -212,11 +304,13 @@ union cvmx_pemx_ctl_status { struct cvmx_pemx_ctl_status_s cn66xx; struct cvmx_pemx_ctl_status_s cn68xx; struct cvmx_pemx_ctl_status_s cn68xxp1; + struct cvmx_pemx_ctl_status_s cnf71xx; }; union cvmx_pemx_dbg_info { uint64_t u64; struct cvmx_pemx_dbg_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t ecrc_e:1; uint64_t rawwpp:1; @@ -249,6 +343,40 @@ union cvmx_pemx_dbg_info { uint64_t rtlplle:1; uint64_t rtlpmal:1; uint64_t spoison:1; +#else + uint64_t spoison:1; + uint64_t rtlpmal:1; + uint64_t rtlplle:1; + uint64_t recrce:1; + uint64_t rpoison:1; + uint64_t rcemrc:1; + uint64_t rnfemrc:1; + uint64_t rfemrc:1; + uint64_t rpmerc:1; + uint64_t rptamrc:1; + uint64_t rumep:1; + uint64_t rvdm:1; + uint64_t acto:1; + uint64_t rte:1; + uint64_t mre:1; + uint64_t rdwdle:1; + uint64_t rtwdle:1; + uint64_t dpeoosd:1; + uint64_t fcpvwt:1; + uint64_t rpe:1; + uint64_t fcuv:1; + uint64_t rqo:1; + uint64_t rauc:1; + uint64_t racur:1; + uint64_t racca:1; + uint64_t caar:1; + uint64_t rarwdns:1; + uint64_t ramtlp:1; + uint64_t racpp:1; + uint64_t rawwpp:1; + uint64_t ecrc_e:1; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_pemx_dbg_info_s cn61xx; struct cvmx_pemx_dbg_info_s cn63xx; @@ -256,11 +384,13 @@ union cvmx_pemx_dbg_info { struct cvmx_pemx_dbg_info_s cn66xx; struct cvmx_pemx_dbg_info_s cn68xx; struct cvmx_pemx_dbg_info_s cn68xxp1; + struct cvmx_pemx_dbg_info_s cnf71xx; }; union cvmx_pemx_dbg_info_en { uint64_t u64; struct cvmx_pemx_dbg_info_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t ecrc_e:1; uint64_t rawwpp:1; @@ -293,6 +423,40 @@ union cvmx_pemx_dbg_info_en { uint64_t rtlplle:1; uint64_t rtlpmal:1; uint64_t spoison:1; +#else + uint64_t spoison:1; + uint64_t rtlpmal:1; + uint64_t rtlplle:1; + uint64_t recrce:1; + uint64_t rpoison:1; + uint64_t rcemrc:1; + uint64_t rnfemrc:1; + uint64_t rfemrc:1; + uint64_t rpmerc:1; + uint64_t rptamrc:1; + uint64_t rumep:1; + uint64_t rvdm:1; + uint64_t acto:1; + uint64_t rte:1; + uint64_t mre:1; + uint64_t rdwdle:1; + uint64_t rtwdle:1; + uint64_t dpeoosd:1; + uint64_t fcpvwt:1; + uint64_t rpe:1; + uint64_t fcuv:1; + uint64_t rqo:1; + uint64_t rauc:1; + uint64_t racur:1; + uint64_t racca:1; + uint64_t caar:1; + uint64_t rarwdns:1; + uint64_t ramtlp:1; + uint64_t racpp:1; + uint64_t rawwpp:1; + uint64_t ecrc_e:1; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_pemx_dbg_info_en_s cn61xx; struct cvmx_pemx_dbg_info_en_s cn63xx; @@ -300,16 +464,25 @@ union cvmx_pemx_dbg_info_en { struct cvmx_pemx_dbg_info_en_s cn66xx; struct cvmx_pemx_dbg_info_en_s cn68xx; struct cvmx_pemx_dbg_info_en_s cn68xxp1; + struct cvmx_pemx_dbg_info_en_s cnf71xx; }; union cvmx_pemx_diag_status { uint64_t u64; struct cvmx_pemx_diag_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t pm_dst:1; uint64_t pm_stat:1; uint64_t pm_en:1; uint64_t aux_en:1; +#else + uint64_t aux_en:1; + uint64_t pm_en:1; + uint64_t pm_stat:1; + uint64_t pm_dst:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pemx_diag_status_s cn61xx; struct cvmx_pemx_diag_status_s cn63xx; @@ -317,22 +490,30 @@ union cvmx_pemx_diag_status { struct cvmx_pemx_diag_status_s cn66xx; struct cvmx_pemx_diag_status_s cn68xx; struct cvmx_pemx_diag_status_s cn68xxp1; + struct cvmx_pemx_diag_status_s cnf71xx; }; union cvmx_pemx_inb_read_credits { uint64_t u64; struct cvmx_pemx_inb_read_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t num:6; +#else + uint64_t num:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_pemx_inb_read_credits_s cn61xx; struct cvmx_pemx_inb_read_credits_s cn66xx; struct cvmx_pemx_inb_read_credits_s cn68xx; + struct cvmx_pemx_inb_read_credits_s cnf71xx; }; union cvmx_pemx_int_enb { uint64_t u64; struct cvmx_pemx_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t crs_dr:1; uint64_t crs_er:1; @@ -348,6 +529,23 @@ union cvmx_pemx_int_enb { uint64_t pmei:1; uint64_t se:1; uint64_t aeri:1; +#else + uint64_t aeri:1; + uint64_t se:1; + uint64_t pmei:1; + uint64_t pmem:1; + uint64_t up_b1:1; + uint64_t up_b2:1; + uint64_t up_bx:1; + uint64_t un_b1:1; + uint64_t un_b2:1; + uint64_t un_bx:1; + uint64_t exc:1; + uint64_t rdlk:1; + uint64_t crs_er:1; + uint64_t crs_dr:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_pemx_int_enb_s cn61xx; struct cvmx_pemx_int_enb_s cn63xx; @@ -355,11 +553,13 @@ union cvmx_pemx_int_enb { struct cvmx_pemx_int_enb_s cn66xx; struct cvmx_pemx_int_enb_s cn68xx; struct cvmx_pemx_int_enb_s cn68xxp1; + struct cvmx_pemx_int_enb_s cnf71xx; }; union cvmx_pemx_int_enb_int { uint64_t u64; struct cvmx_pemx_int_enb_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t crs_dr:1; uint64_t crs_er:1; @@ -375,6 +575,23 @@ union cvmx_pemx_int_enb_int { uint64_t pmei:1; uint64_t se:1; uint64_t aeri:1; +#else + uint64_t aeri:1; + uint64_t se:1; + uint64_t pmei:1; + uint64_t pmem:1; + uint64_t up_b1:1; + uint64_t up_b2:1; + uint64_t up_bx:1; + uint64_t un_b1:1; + uint64_t un_b2:1; + uint64_t un_bx:1; + uint64_t exc:1; + uint64_t rdlk:1; + uint64_t crs_er:1; + uint64_t crs_dr:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_pemx_int_enb_int_s cn61xx; struct cvmx_pemx_int_enb_int_s cn63xx; @@ -382,11 +599,13 @@ union cvmx_pemx_int_enb_int { struct cvmx_pemx_int_enb_int_s cn66xx; struct cvmx_pemx_int_enb_int_s cn68xx; struct cvmx_pemx_int_enb_int_s cn68xxp1; + struct cvmx_pemx_int_enb_int_s cnf71xx; }; union cvmx_pemx_int_sum { uint64_t u64; struct cvmx_pemx_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t crs_dr:1; uint64_t crs_er:1; @@ -402,6 +621,23 @@ union cvmx_pemx_int_sum { uint64_t pmei:1; uint64_t se:1; uint64_t aeri:1; +#else + uint64_t aeri:1; + uint64_t se:1; + uint64_t pmei:1; + uint64_t pmem:1; + uint64_t up_b1:1; + uint64_t up_b2:1; + uint64_t up_bx:1; + uint64_t un_b1:1; + uint64_t un_b2:1; + uint64_t un_bx:1; + uint64_t exc:1; + uint64_t rdlk:1; + uint64_t crs_er:1; + uint64_t crs_dr:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_pemx_int_sum_s cn61xx; struct cvmx_pemx_int_sum_s cn63xx; @@ -409,13 +645,19 @@ union cvmx_pemx_int_sum { struct cvmx_pemx_int_sum_s cn66xx; struct cvmx_pemx_int_sum_s cn68xx; struct cvmx_pemx_int_sum_s cn68xxp1; + struct cvmx_pemx_int_sum_s cnf71xx; }; union cvmx_pemx_p2n_bar0_start { uint64_t u64; struct cvmx_pemx_p2n_bar0_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:50; uint64_t reserved_0_13:14; +#else + uint64_t reserved_0_13:14; + uint64_t addr:50; +#endif } s; struct cvmx_pemx_p2n_bar0_start_s cn61xx; struct cvmx_pemx_p2n_bar0_start_s cn63xx; @@ -423,13 +665,19 @@ union cvmx_pemx_p2n_bar0_start { struct cvmx_pemx_p2n_bar0_start_s cn66xx; struct cvmx_pemx_p2n_bar0_start_s cn68xx; struct cvmx_pemx_p2n_bar0_start_s cn68xxp1; + struct cvmx_pemx_p2n_bar0_start_s cnf71xx; }; union cvmx_pemx_p2n_bar1_start { uint64_t u64; struct cvmx_pemx_p2n_bar1_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:38; uint64_t reserved_0_25:26; +#else + uint64_t reserved_0_25:26; + uint64_t addr:38; +#endif } s; struct cvmx_pemx_p2n_bar1_start_s cn61xx; struct cvmx_pemx_p2n_bar1_start_s cn63xx; @@ -437,13 +685,19 @@ union cvmx_pemx_p2n_bar1_start { struct cvmx_pemx_p2n_bar1_start_s cn66xx; struct cvmx_pemx_p2n_bar1_start_s cn68xx; struct cvmx_pemx_p2n_bar1_start_s cn68xxp1; + struct cvmx_pemx_p2n_bar1_start_s cnf71xx; }; union cvmx_pemx_p2n_bar2_start { uint64_t u64; struct cvmx_pemx_p2n_bar2_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:23; uint64_t reserved_0_40:41; +#else + uint64_t reserved_0_40:41; + uint64_t addr:23; +#endif } s; struct cvmx_pemx_p2n_bar2_start_s cn61xx; struct cvmx_pemx_p2n_bar2_start_s cn63xx; @@ -451,13 +705,19 @@ union cvmx_pemx_p2n_bar2_start { struct cvmx_pemx_p2n_bar2_start_s cn66xx; struct cvmx_pemx_p2n_bar2_start_s cn68xx; struct cvmx_pemx_p2n_bar2_start_s cn68xxp1; + struct cvmx_pemx_p2n_bar2_start_s cnf71xx; }; union cvmx_pemx_p2p_barx_end { uint64_t u64; struct cvmx_pemx_p2p_barx_end_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:52; uint64_t reserved_0_11:12; +#else + uint64_t reserved_0_11:12; + uint64_t addr:52; +#endif } s; struct cvmx_pemx_p2p_barx_end_s cn63xx; struct cvmx_pemx_p2p_barx_end_s cn63xxp1; @@ -469,8 +729,13 @@ union cvmx_pemx_p2p_barx_end { union cvmx_pemx_p2p_barx_start { uint64_t u64; struct cvmx_pemx_p2p_barx_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:52; uint64_t reserved_0_11:12; +#else + uint64_t reserved_0_11:12; + uint64_t addr:52; +#endif } s; struct cvmx_pemx_p2p_barx_start_s cn63xx; struct cvmx_pemx_p2p_barx_start_s cn63xxp1; @@ -482,6 +747,7 @@ union cvmx_pemx_p2p_barx_start { union cvmx_pemx_tlp_credits { uint64_t u64; struct cvmx_pemx_tlp_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t peai_ppf:8; uint64_t pem_cpl:8; @@ -490,20 +756,40 @@ union cvmx_pemx_tlp_credits { uint64_t sli_cpl:8; uint64_t sli_np:8; uint64_t sli_p:8; +#else + uint64_t sli_p:8; + uint64_t sli_np:8; + uint64_t sli_cpl:8; + uint64_t pem_p:8; + uint64_t pem_np:8; + uint64_t pem_cpl:8; + uint64_t peai_ppf:8; + uint64_t reserved_56_63:8; +#endif } s; struct cvmx_pemx_tlp_credits_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t peai_ppf:8; uint64_t reserved_24_47:24; uint64_t sli_cpl:8; uint64_t sli_np:8; uint64_t sli_p:8; +#else + uint64_t sli_p:8; + uint64_t sli_np:8; + uint64_t sli_cpl:8; + uint64_t reserved_24_47:24; + uint64_t peai_ppf:8; + uint64_t reserved_56_63:8; +#endif } cn61xx; struct cvmx_pemx_tlp_credits_s cn63xx; struct cvmx_pemx_tlp_credits_s cn63xxp1; struct cvmx_pemx_tlp_credits_s cn66xx; struct cvmx_pemx_tlp_credits_s cn68xx; struct cvmx_pemx_tlp_credits_s cn68xxp1; + struct cvmx_pemx_tlp_credits_cn61xx cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h index aef84851a94c..59b3dc565442 100644 --- a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -48,6 +48,7 @@ union cvmx_pescx_bist_status { uint64_t u64; struct cvmx_pescx_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t rqdata5:1; uint64_t ctlp_or:1; @@ -62,9 +63,26 @@ union cvmx_pescx_bist_status { uint64_t rqhdr1:1; uint64_t rqhdr0:1; uint64_t sot:1; +#else + uint64_t sot:1; + uint64_t rqhdr0:1; + uint64_t rqhdr1:1; + uint64_t rqdata4:1; + uint64_t rqdata3:1; + uint64_t rqdata2:1; + uint64_t rqdata1:1; + uint64_t rqdata0:1; + uint64_t retry:1; + uint64_t ptlp_or:1; + uint64_t ntlp_or:1; + uint64_t ctlp_or:1; + uint64_t rqdata5:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_pescx_bist_status_s cn52xx; struct cvmx_pescx_bist_status_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t ctlp_or:1; uint64_t ntlp_or:1; @@ -78,6 +96,21 @@ union cvmx_pescx_bist_status { uint64_t rqhdr1:1; uint64_t rqhdr0:1; uint64_t sot:1; +#else + uint64_t sot:1; + uint64_t rqhdr0:1; + uint64_t rqhdr1:1; + uint64_t rqdata4:1; + uint64_t rqdata3:1; + uint64_t rqdata2:1; + uint64_t rqdata1:1; + uint64_t rqdata0:1; + uint64_t retry:1; + uint64_t ptlp_or:1; + uint64_t ntlp_or:1; + uint64_t ctlp_or:1; + uint64_t reserved_12_63:52; +#endif } cn52xxp1; struct cvmx_pescx_bist_status_s cn56xx; struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1; @@ -86,6 +119,7 @@ union cvmx_pescx_bist_status { union cvmx_pescx_bist_status2 { uint64_t u64; struct cvmx_pescx_bist_status2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t cto_p2e:1; uint64_t e2p_cpl:1; @@ -101,6 +135,23 @@ union cvmx_pescx_bist_status2 { uint64_t pef_tcf1:1; uint64_t pef_tc0:1; uint64_t ppf:1; +#else + uint64_t ppf:1; + uint64_t pef_tc0:1; + uint64_t pef_tcf1:1; + uint64_t pef_tnf:1; + uint64_t pef_tpf0:1; + uint64_t pef_tpf1:1; + uint64_t rsl_p2e:1; + uint64_t peai_p2e:1; + uint64_t dbg_p2e:1; + uint64_t e2p_rsl:1; + uint64_t e2p_p:1; + uint64_t e2p_n:1; + uint64_t e2p_cpl:1; + uint64_t cto_p2e:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_pescx_bist_status2_s cn52xx; struct cvmx_pescx_bist_status2_s cn52xxp1; @@ -111,8 +162,13 @@ union cvmx_pescx_bist_status2 { union cvmx_pescx_cfg_rd { uint64_t u64; struct cvmx_pescx_cfg_rd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:32; uint64_t addr:32; +#else + uint64_t addr:32; + uint64_t data:32; +#endif } s; struct cvmx_pescx_cfg_rd_s cn52xx; struct cvmx_pescx_cfg_rd_s cn52xxp1; @@ -123,8 +179,13 @@ union cvmx_pescx_cfg_rd { union cvmx_pescx_cfg_wr { uint64_t u64; struct cvmx_pescx_cfg_wr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:32; uint64_t addr:32; +#else + uint64_t addr:32; + uint64_t data:32; +#endif } s; struct cvmx_pescx_cfg_wr_s cn52xx; struct cvmx_pescx_cfg_wr_s cn52xxp1; @@ -135,8 +196,13 @@ union cvmx_pescx_cfg_wr { union cvmx_pescx_cpl_lut_valid { uint64_t u64; struct cvmx_pescx_cpl_lut_valid_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t tag:32; +#else + uint64_t tag:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pescx_cpl_lut_valid_s cn52xx; struct cvmx_pescx_cpl_lut_valid_s cn52xxp1; @@ -147,6 +213,7 @@ union cvmx_pescx_cpl_lut_valid { union cvmx_pescx_ctl_status { uint64_t u64; struct cvmx_pescx_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t dnum:5; uint64_t pbus:8; @@ -163,10 +230,29 @@ union cvmx_pescx_ctl_status { uint64_t reserved_2_2:1; uint64_t inv_ecrc:1; uint64_t inv_lcrc:1; +#else + uint64_t inv_lcrc:1; + uint64_t inv_ecrc:1; + uint64_t reserved_2_2:1; + uint64_t ro_ctlp:1; + uint64_t lnk_enb:1; + uint64_t dly_one:1; + uint64_t nf_ecrc:1; + uint64_t reserved_7_8:2; + uint64_t ob_p_cmd:1; + uint64_t pm_xpme:1; + uint64_t pm_xtoff:1; + uint64_t lane_swp:1; + uint64_t qlm_cfg:2; + uint64_t pbus:8; + uint64_t dnum:5; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_pescx_ctl_status_s cn52xx; struct cvmx_pescx_ctl_status_s cn52xxp1; struct cvmx_pescx_ctl_status_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t dnum:5; uint64_t pbus:8; @@ -183,6 +269,24 @@ union cvmx_pescx_ctl_status { uint64_t reserved_2_2:1; uint64_t inv_ecrc:1; uint64_t inv_lcrc:1; +#else + uint64_t inv_lcrc:1; + uint64_t inv_ecrc:1; + uint64_t reserved_2_2:1; + uint64_t ro_ctlp:1; + uint64_t lnk_enb:1; + uint64_t dly_one:1; + uint64_t nf_ecrc:1; + uint64_t reserved_7_8:2; + uint64_t ob_p_cmd:1; + uint64_t pm_xpme:1; + uint64_t pm_xtoff:1; + uint64_t reserved_12_12:1; + uint64_t qlm_cfg:2; + uint64_t pbus:8; + uint64_t dnum:5; + uint64_t reserved_28_63:36; +#endif } cn56xx; struct cvmx_pescx_ctl_status_cn56xx cn56xxp1; }; @@ -190,14 +294,25 @@ union cvmx_pescx_ctl_status { union cvmx_pescx_ctl_status2 { uint64_t u64; struct cvmx_pescx_ctl_status2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t pclk_run:1; uint64_t pcierst:1; +#else + uint64_t pcierst:1; + uint64_t pclk_run:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pescx_ctl_status2_s cn52xx; struct cvmx_pescx_ctl_status2_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t pcierst:1; +#else + uint64_t pcierst:1; + uint64_t reserved_1_63:63; +#endif } cn52xxp1; struct cvmx_pescx_ctl_status2_s cn56xx; struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1; @@ -206,6 +321,7 @@ union cvmx_pescx_ctl_status2 { union cvmx_pescx_dbg_info { uint64_t u64; struct cvmx_pescx_dbg_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t ecrc_e:1; uint64_t rawwpp:1; @@ -238,6 +354,40 @@ union cvmx_pescx_dbg_info { uint64_t rtlplle:1; uint64_t rtlpmal:1; uint64_t spoison:1; +#else + uint64_t spoison:1; + uint64_t rtlpmal:1; + uint64_t rtlplle:1; + uint64_t recrce:1; + uint64_t rpoison:1; + uint64_t rcemrc:1; + uint64_t rnfemrc:1; + uint64_t rfemrc:1; + uint64_t rpmerc:1; + uint64_t rptamrc:1; + uint64_t rumep:1; + uint64_t rvdm:1; + uint64_t acto:1; + uint64_t rte:1; + uint64_t mre:1; + uint64_t rdwdle:1; + uint64_t rtwdle:1; + uint64_t dpeoosd:1; + uint64_t fcpvwt:1; + uint64_t rpe:1; + uint64_t fcuv:1; + uint64_t rqo:1; + uint64_t rauc:1; + uint64_t racur:1; + uint64_t racca:1; + uint64_t caar:1; + uint64_t rarwdns:1; + uint64_t ramtlp:1; + uint64_t racpp:1; + uint64_t rawwpp:1; + uint64_t ecrc_e:1; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_pescx_dbg_info_s cn52xx; struct cvmx_pescx_dbg_info_s cn52xxp1; @@ -248,6 +398,7 @@ union cvmx_pescx_dbg_info { union cvmx_pescx_dbg_info_en { uint64_t u64; struct cvmx_pescx_dbg_info_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t ecrc_e:1; uint64_t rawwpp:1; @@ -280,6 +431,40 @@ union cvmx_pescx_dbg_info_en { uint64_t rtlplle:1; uint64_t rtlpmal:1; uint64_t spoison:1; +#else + uint64_t spoison:1; + uint64_t rtlpmal:1; + uint64_t rtlplle:1; + uint64_t recrce:1; + uint64_t rpoison:1; + uint64_t rcemrc:1; + uint64_t rnfemrc:1; + uint64_t rfemrc:1; + uint64_t rpmerc:1; + uint64_t rptamrc:1; + uint64_t rumep:1; + uint64_t rvdm:1; + uint64_t acto:1; + uint64_t rte:1; + uint64_t mre:1; + uint64_t rdwdle:1; + uint64_t rtwdle:1; + uint64_t dpeoosd:1; + uint64_t fcpvwt:1; + uint64_t rpe:1; + uint64_t fcuv:1; + uint64_t rqo:1; + uint64_t rauc:1; + uint64_t racur:1; + uint64_t racca:1; + uint64_t caar:1; + uint64_t rarwdns:1; + uint64_t ramtlp:1; + uint64_t racpp:1; + uint64_t rawwpp:1; + uint64_t ecrc_e:1; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_pescx_dbg_info_en_s cn52xx; struct cvmx_pescx_dbg_info_en_s cn52xxp1; @@ -290,11 +475,19 @@ union cvmx_pescx_dbg_info_en { union cvmx_pescx_diag_status { uint64_t u64; struct cvmx_pescx_diag_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t pm_dst:1; uint64_t pm_stat:1; uint64_t pm_en:1; uint64_t aux_en:1; +#else + uint64_t aux_en:1; + uint64_t pm_en:1; + uint64_t pm_stat:1; + uint64_t pm_dst:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pescx_diag_status_s cn52xx; struct cvmx_pescx_diag_status_s cn52xxp1; @@ -305,8 +498,13 @@ union cvmx_pescx_diag_status { union cvmx_pescx_p2n_bar0_start { uint64_t u64; struct cvmx_pescx_p2n_bar0_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:50; uint64_t reserved_0_13:14; +#else + uint64_t reserved_0_13:14; + uint64_t addr:50; +#endif } s; struct cvmx_pescx_p2n_bar0_start_s cn52xx; struct cvmx_pescx_p2n_bar0_start_s cn52xxp1; @@ -317,8 +515,13 @@ union cvmx_pescx_p2n_bar0_start { union cvmx_pescx_p2n_bar1_start { uint64_t u64; struct cvmx_pescx_p2n_bar1_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:38; uint64_t reserved_0_25:26; +#else + uint64_t reserved_0_25:26; + uint64_t addr:38; +#endif } s; struct cvmx_pescx_p2n_bar1_start_s cn52xx; struct cvmx_pescx_p2n_bar1_start_s cn52xxp1; @@ -329,8 +532,13 @@ union cvmx_pescx_p2n_bar1_start { union cvmx_pescx_p2n_bar2_start { uint64_t u64; struct cvmx_pescx_p2n_bar2_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:25; uint64_t reserved_0_38:39; +#else + uint64_t reserved_0_38:39; + uint64_t addr:25; +#endif } s; struct cvmx_pescx_p2n_bar2_start_s cn52xx; struct cvmx_pescx_p2n_bar2_start_s cn52xxp1; @@ -341,8 +549,13 @@ union cvmx_pescx_p2n_bar2_start { union cvmx_pescx_p2p_barx_end { uint64_t u64; struct cvmx_pescx_p2p_barx_end_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:52; uint64_t reserved_0_11:12; +#else + uint64_t reserved_0_11:12; + uint64_t addr:52; +#endif } s; struct cvmx_pescx_p2p_barx_end_s cn52xx; struct cvmx_pescx_p2p_barx_end_s cn52xxp1; @@ -353,8 +566,13 @@ union cvmx_pescx_p2p_barx_end { union cvmx_pescx_p2p_barx_start { uint64_t u64; struct cvmx_pescx_p2p_barx_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:52; uint64_t reserved_0_11:12; +#else + uint64_t reserved_0_11:12; + uint64_t addr:52; +#endif } s; struct cvmx_pescx_p2p_barx_start_s cn52xx; struct cvmx_pescx_p2p_barx_start_s cn52xxp1; @@ -365,9 +583,14 @@ union cvmx_pescx_p2p_barx_start { union cvmx_pescx_tlp_credits { uint64_t u64; struct cvmx_pescx_tlp_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pescx_tlp_credits_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t peai_ppf:8; uint64_t pesc_cpl:8; @@ -376,8 +599,19 @@ union cvmx_pescx_tlp_credits { uint64_t npei_cpl:8; uint64_t npei_np:8; uint64_t npei_p:8; +#else + uint64_t npei_p:8; + uint64_t npei_np:8; + uint64_t npei_cpl:8; + uint64_t pesc_p:8; + uint64_t pesc_np:8; + uint64_t pesc_cpl:8; + uint64_t peai_ppf:8; + uint64_t reserved_56_63:8; +#endif } cn52xx; struct cvmx_pescx_tlp_credits_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t peai_ppf:8; uint64_t pesc_cpl:5; @@ -386,6 +620,16 @@ union cvmx_pescx_tlp_credits { uint64_t npei_cpl:5; uint64_t npei_np:5; uint64_t npei_p:5; +#else + uint64_t npei_p:5; + uint64_t npei_np:5; + uint64_t npei_cpl:5; + uint64_t pesc_p:5; + uint64_t pesc_np:5; + uint64_t pesc_cpl:5; + uint64_t peai_ppf:8; + uint64_t reserved_38_63:26; +#endif } cn52xxp1; struct cvmx_pescx_tlp_credits_cn52xx cn56xx; struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1; diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h index 4438d211988b..eb673f3514de 100644 --- a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2011 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as diff --git a/arch/mips/include/asm/octeon/cvmx-pip-defs.h b/arch/mips/include/asm/octeon/cvmx-pip-defs.h index 5a369100ca68..05a917d6ebe5 100644 --- a/arch/mips/include/asm/octeon/cvmx-pip-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pip-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -51,93 +51,137 @@ enum cvmx_pip_port_parse_mode { CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull }; -#define CVMX_PIP_BCK_PRS \ - CVMX_ADD_IO_SEG(0x00011800A0000038ull) -#define CVMX_PIP_BIST_STATUS \ - CVMX_ADD_IO_SEG(0x00011800A0000000ull) -#define CVMX_PIP_CRC_CTLX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000040ull + (((offset) & 1) * 8)) -#define CVMX_PIP_CRC_IVX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000050ull + (((offset) & 1) * 8)) -#define CVMX_PIP_DEC_IPSECX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000080ull + (((offset) & 3) * 8)) -#define CVMX_PIP_DSA_SRC_GRP \ - CVMX_ADD_IO_SEG(0x00011800A0000190ull) -#define CVMX_PIP_DSA_VID_GRP \ - CVMX_ADD_IO_SEG(0x00011800A0000198ull) -#define CVMX_PIP_FRM_LEN_CHKX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000180ull + (((offset) & 1) * 8)) -#define CVMX_PIP_GBL_CFG \ - CVMX_ADD_IO_SEG(0x00011800A0000028ull) -#define CVMX_PIP_GBL_CTL \ - CVMX_ADD_IO_SEG(0x00011800A0000020ull) -#define CVMX_PIP_HG_PRI_QOS \ - CVMX_ADD_IO_SEG(0x00011800A00001A0ull) -#define CVMX_PIP_INT_EN \ - CVMX_ADD_IO_SEG(0x00011800A0000010ull) -#define CVMX_PIP_INT_REG \ - CVMX_ADD_IO_SEG(0x00011800A0000008ull) -#define CVMX_PIP_IP_OFFSET \ - CVMX_ADD_IO_SEG(0x00011800A0000060ull) -#define CVMX_PIP_PRT_CFGX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000200ull + (((offset) & 63) * 8)) -#define CVMX_PIP_PRT_TAGX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000400ull + (((offset) & 63) * 8)) -#define CVMX_PIP_QOS_DIFFX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000600ull + (((offset) & 63) * 8)) -#define CVMX_PIP_QOS_VLANX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A00000C0ull + (((offset) & 7) * 8)) -#define CVMX_PIP_QOS_WATCHX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000100ull + (((offset) & 7) * 8)) -#define CVMX_PIP_RAW_WORD \ - CVMX_ADD_IO_SEG(0x00011800A00000B0ull) -#define CVMX_PIP_SFT_RST \ - CVMX_ADD_IO_SEG(0x00011800A0000030ull) -#define CVMX_PIP_STAT0_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000800ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT1_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000808ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT2_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000810ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT3_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000818ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT4_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000820ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT5_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000828ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT6_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000830ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT7_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000838ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT8_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000840ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT9_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000848ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT_CTL \ - CVMX_ADD_IO_SEG(0x00011800A0000018ull) -#define CVMX_PIP_STAT_INB_ERRSX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0001A10ull + (((offset) & 63) * 32)) -#define CVMX_PIP_STAT_INB_OCTSX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0001A08ull + (((offset) & 63) * 32)) -#define CVMX_PIP_STAT_INB_PKTSX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0001A00ull + (((offset) & 63) * 32)) -#define CVMX_PIP_TAG_INCX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0001800ull + (((offset) & 63) * 8)) -#define CVMX_PIP_TAG_MASK \ - CVMX_ADD_IO_SEG(0x00011800A0000070ull) -#define CVMX_PIP_TAG_SECRET \ - CVMX_ADD_IO_SEG(0x00011800A0000068ull) -#define CVMX_PIP_TODO_ENTRY \ - CVMX_ADD_IO_SEG(0x00011800A0000078ull) +#define CVMX_PIP_ALT_SKIP_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8) +#define CVMX_PIP_BCK_PRS (CVMX_ADD_IO_SEG(0x00011800A0000038ull)) +#define CVMX_PIP_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A0000000ull)) +#define CVMX_PIP_BSEL_EXT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16) +#define CVMX_PIP_BSEL_EXT_POSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16) +#define CVMX_PIP_BSEL_TBL_ENTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8) +#define CVMX_PIP_CLKEN (CVMX_ADD_IO_SEG(0x00011800A0000040ull)) +#define CVMX_PIP_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8) +#define CVMX_PIP_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8) +#define CVMX_PIP_DEC_IPSECX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8) +#define CVMX_PIP_DSA_SRC_GRP (CVMX_ADD_IO_SEG(0x00011800A0000190ull)) +#define CVMX_PIP_DSA_VID_GRP (CVMX_ADD_IO_SEG(0x00011800A0000198ull)) +#define CVMX_PIP_FRM_LEN_CHKX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8) +#define CVMX_PIP_GBL_CFG (CVMX_ADD_IO_SEG(0x00011800A0000028ull)) +#define CVMX_PIP_GBL_CTL (CVMX_ADD_IO_SEG(0x00011800A0000020ull)) +#define CVMX_PIP_HG_PRI_QOS (CVMX_ADD_IO_SEG(0x00011800A00001A0ull)) +#define CVMX_PIP_INT_EN (CVMX_ADD_IO_SEG(0x00011800A0000010ull)) +#define CVMX_PIP_INT_REG (CVMX_ADD_IO_SEG(0x00011800A0000008ull)) +#define CVMX_PIP_IP_OFFSET (CVMX_ADD_IO_SEG(0x00011800A0000060ull)) +#define CVMX_PIP_PRI_TBLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8) +#define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8) +#define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8) +#define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8) +#define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8) +#define CVMX_PIP_QOS_VLANX(offset) (CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8) +#define CVMX_PIP_QOS_WATCHX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8) +#define CVMX_PIP_RAW_WORD (CVMX_ADD_IO_SEG(0x00011800A00000B0ull)) +#define CVMX_PIP_SFT_RST (CVMX_ADD_IO_SEG(0x00011800A0000030ull)) +#define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16) +#define CVMX_PIP_STAT10_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16) +#define CVMX_PIP_STAT11_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT1_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT2_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT3_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT4_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT5_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT6_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT7_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT8_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT9_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT_CTL (CVMX_ADD_IO_SEG(0x00011800A0000018ull)) +#define CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32) +#define CVMX_PIP_STAT_INB_ERRS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32) +#define CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32) +#define CVMX_PIP_STAT_INB_OCTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32) +#define CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32) +#define CVMX_PIP_STAT_INB_PKTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32) +#define CVMX_PIP_SUB_PKIND_FCSX(block_id) (CVMX_ADD_IO_SEG(0x00011800A0080000ull)) +#define CVMX_PIP_TAG_INCX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8) +#define CVMX_PIP_TAG_MASK (CVMX_ADD_IO_SEG(0x00011800A0000070ull)) +#define CVMX_PIP_TAG_SECRET (CVMX_ADD_IO_SEG(0x00011800A0000068ull)) +#define CVMX_PIP_TODO_ENTRY (CVMX_ADD_IO_SEG(0x00011800A0000078ull)) +#define CVMX_PIP_VLAN_ETYPESX(offset) (CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8) +#define CVMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40) +#define CVMX_PIP_XSTAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40) +#define CVMX_PIP_XSTAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40) + +union cvmx_pip_alt_skip_cfgx { + uint64_t u64; + struct cvmx_pip_alt_skip_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_57_63:7; + uint64_t len:1; + uint64_t reserved_46_55:10; + uint64_t bit1:6; + uint64_t reserved_38_39:2; + uint64_t bit0:6; + uint64_t reserved_23_31:9; + uint64_t skip3:7; + uint64_t reserved_15_15:1; + uint64_t skip2:7; + uint64_t reserved_7_7:1; + uint64_t skip1:7; +#else + uint64_t skip1:7; + uint64_t reserved_7_7:1; + uint64_t skip2:7; + uint64_t reserved_15_15:1; + uint64_t skip3:7; + uint64_t reserved_23_31:9; + uint64_t bit0:6; + uint64_t reserved_38_39:2; + uint64_t bit1:6; + uint64_t reserved_46_55:10; + uint64_t len:1; + uint64_t reserved_57_63:7; +#endif + } s; + struct cvmx_pip_alt_skip_cfgx_s cn61xx; + struct cvmx_pip_alt_skip_cfgx_s cn66xx; + struct cvmx_pip_alt_skip_cfgx_s cn68xx; + struct cvmx_pip_alt_skip_cfgx_s cnf71xx; +}; union cvmx_pip_bck_prs { uint64_t u64; struct cvmx_pip_bck_prs_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bckprs:1; uint64_t reserved_13_62:50; uint64_t hiwater:5; uint64_t reserved_5_7:3; uint64_t lowater:5; +#else + uint64_t lowater:5; + uint64_t reserved_5_7:3; + uint64_t hiwater:5; + uint64_t reserved_13_62:50; + uint64_t bckprs:1; +#endif } s; struct cvmx_pip_bck_prs_s cn38xx; struct cvmx_pip_bck_prs_s cn38xxp2; @@ -145,36 +189,236 @@ union cvmx_pip_bck_prs { struct cvmx_pip_bck_prs_s cn56xxp1; struct cvmx_pip_bck_prs_s cn58xx; struct cvmx_pip_bck_prs_s cn58xxp1; + struct cvmx_pip_bck_prs_s cn61xx; + struct cvmx_pip_bck_prs_s cn63xx; + struct cvmx_pip_bck_prs_s cn63xxp1; + struct cvmx_pip_bck_prs_s cn66xx; + struct cvmx_pip_bck_prs_s cn68xx; + struct cvmx_pip_bck_prs_s cn68xxp1; + struct cvmx_pip_bck_prs_s cnf71xx; }; union cvmx_pip_bist_status { uint64_t u64; struct cvmx_pip_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_22_63:42; + uint64_t bist:22; +#else + uint64_t bist:22; + uint64_t reserved_22_63:42; +#endif + } s; + struct cvmx_pip_bist_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t bist:18; - } s; - struct cvmx_pip_bist_status_s cn30xx; - struct cvmx_pip_bist_status_s cn31xx; - struct cvmx_pip_bist_status_s cn38xx; - struct cvmx_pip_bist_status_s cn38xxp2; +#else + uint64_t bist:18; + uint64_t reserved_18_63:46; +#endif + } cn30xx; + struct cvmx_pip_bist_status_cn30xx cn31xx; + struct cvmx_pip_bist_status_cn30xx cn38xx; + struct cvmx_pip_bist_status_cn30xx cn38xxp2; struct cvmx_pip_bist_status_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t bist:17; +#else + uint64_t bist:17; + uint64_t reserved_17_63:47; +#endif } cn50xx; - struct cvmx_pip_bist_status_s cn52xx; - struct cvmx_pip_bist_status_s cn52xxp1; - struct cvmx_pip_bist_status_s cn56xx; - struct cvmx_pip_bist_status_s cn56xxp1; - struct cvmx_pip_bist_status_s cn58xx; - struct cvmx_pip_bist_status_s cn58xxp1; + struct cvmx_pip_bist_status_cn30xx cn52xx; + struct cvmx_pip_bist_status_cn30xx cn52xxp1; + struct cvmx_pip_bist_status_cn30xx cn56xx; + struct cvmx_pip_bist_status_cn30xx cn56xxp1; + struct cvmx_pip_bist_status_cn30xx cn58xx; + struct cvmx_pip_bist_status_cn30xx cn58xxp1; + struct cvmx_pip_bist_status_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t bist:20; +#else + uint64_t bist:20; + uint64_t reserved_20_63:44; +#endif + } cn61xx; + struct cvmx_pip_bist_status_cn30xx cn63xx; + struct cvmx_pip_bist_status_cn30xx cn63xxp1; + struct cvmx_pip_bist_status_cn61xx cn66xx; + struct cvmx_pip_bist_status_s cn68xx; + struct cvmx_pip_bist_status_cn61xx cn68xxp1; + struct cvmx_pip_bist_status_cn61xx cnf71xx; +}; + +union cvmx_pip_bsel_ext_cfgx { + uint64_t u64; + struct cvmx_pip_bsel_ext_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t upper_tag:16; + uint64_t tag:8; + uint64_t reserved_25_31:7; + uint64_t offset:9; + uint64_t reserved_7_15:9; + uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_15:9; + uint64_t offset:9; + uint64_t reserved_25_31:7; + uint64_t tag:8; + uint64_t upper_tag:16; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_pip_bsel_ext_cfgx_s cn61xx; + struct cvmx_pip_bsel_ext_cfgx_s cn68xx; + struct cvmx_pip_bsel_ext_cfgx_s cnf71xx; +}; + +union cvmx_pip_bsel_ext_posx { + uint64_t u64; + struct cvmx_pip_bsel_ext_posx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t pos7_val:1; + uint64_t pos7:7; + uint64_t pos6_val:1; + uint64_t pos6:7; + uint64_t pos5_val:1; + uint64_t pos5:7; + uint64_t pos4_val:1; + uint64_t pos4:7; + uint64_t pos3_val:1; + uint64_t pos3:7; + uint64_t pos2_val:1; + uint64_t pos2:7; + uint64_t pos1_val:1; + uint64_t pos1:7; + uint64_t pos0_val:1; + uint64_t pos0:7; +#else + uint64_t pos0:7; + uint64_t pos0_val:1; + uint64_t pos1:7; + uint64_t pos1_val:1; + uint64_t pos2:7; + uint64_t pos2_val:1; + uint64_t pos3:7; + uint64_t pos3_val:1; + uint64_t pos4:7; + uint64_t pos4_val:1; + uint64_t pos5:7; + uint64_t pos5_val:1; + uint64_t pos6:7; + uint64_t pos6_val:1; + uint64_t pos7:7; + uint64_t pos7_val:1; +#endif + } s; + struct cvmx_pip_bsel_ext_posx_s cn61xx; + struct cvmx_pip_bsel_ext_posx_s cn68xx; + struct cvmx_pip_bsel_ext_posx_s cnf71xx; +}; + +union cvmx_pip_bsel_tbl_entx { + uint64_t u64; + struct cvmx_pip_bsel_tbl_entx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t tag_en:1; + uint64_t grp_en:1; + uint64_t tt_en:1; + uint64_t qos_en:1; + uint64_t reserved_40_59:20; + uint64_t tag:8; + uint64_t reserved_22_31:10; + uint64_t grp:6; + uint64_t reserved_10_15:6; + uint64_t tt:2; + uint64_t reserved_3_7:5; + uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t reserved_3_7:5; + uint64_t tt:2; + uint64_t reserved_10_15:6; + uint64_t grp:6; + uint64_t reserved_22_31:10; + uint64_t tag:8; + uint64_t reserved_40_59:20; + uint64_t qos_en:1; + uint64_t tt_en:1; + uint64_t grp_en:1; + uint64_t tag_en:1; +#endif + } s; + struct cvmx_pip_bsel_tbl_entx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t tag_en:1; + uint64_t grp_en:1; + uint64_t tt_en:1; + uint64_t qos_en:1; + uint64_t reserved_40_59:20; + uint64_t tag:8; + uint64_t reserved_20_31:12; + uint64_t grp:4; + uint64_t reserved_10_15:6; + uint64_t tt:2; + uint64_t reserved_3_7:5; + uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t reserved_3_7:5; + uint64_t tt:2; + uint64_t reserved_10_15:6; + uint64_t grp:4; + uint64_t reserved_20_31:12; + uint64_t tag:8; + uint64_t reserved_40_59:20; + uint64_t qos_en:1; + uint64_t tt_en:1; + uint64_t grp_en:1; + uint64_t tag_en:1; +#endif + } cn61xx; + struct cvmx_pip_bsel_tbl_entx_s cn68xx; + struct cvmx_pip_bsel_tbl_entx_cn61xx cnf71xx; +}; + +union cvmx_pip_clken { + uint64_t u64; + struct cvmx_pip_clken_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t clken:1; +#else + uint64_t clken:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_pip_clken_s cn61xx; + struct cvmx_pip_clken_s cn63xx; + struct cvmx_pip_clken_s cn63xxp1; + struct cvmx_pip_clken_s cn66xx; + struct cvmx_pip_clken_s cn68xx; + struct cvmx_pip_clken_s cn68xxp1; + struct cvmx_pip_clken_s cnf71xx; }; union cvmx_pip_crc_ctlx { uint64_t u64; struct cvmx_pip_crc_ctlx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t invres:1; uint64_t reflect:1; +#else + uint64_t reflect:1; + uint64_t invres:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pip_crc_ctlx_s cn38xx; struct cvmx_pip_crc_ctlx_s cn38xxp2; @@ -185,8 +429,13 @@ union cvmx_pip_crc_ctlx { union cvmx_pip_crc_ivx { uint64_t u64; struct cvmx_pip_crc_ivx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iv:32; +#else + uint64_t iv:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pip_crc_ivx_s cn38xx; struct cvmx_pip_crc_ivx_s cn38xxp2; @@ -197,10 +446,17 @@ union cvmx_pip_crc_ivx { union cvmx_pip_dec_ipsecx { uint64_t u64; struct cvmx_pip_dec_ipsecx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t tcp:1; uint64_t udp:1; uint64_t dprt:16; +#else + uint64_t dprt:16; + uint64_t udp:1; + uint64_t tcp:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_pip_dec_ipsecx_s cn30xx; struct cvmx_pip_dec_ipsecx_s cn31xx; @@ -213,11 +469,19 @@ union cvmx_pip_dec_ipsecx { struct cvmx_pip_dec_ipsecx_s cn56xxp1; struct cvmx_pip_dec_ipsecx_s cn58xx; struct cvmx_pip_dec_ipsecx_s cn58xxp1; + struct cvmx_pip_dec_ipsecx_s cn61xx; + struct cvmx_pip_dec_ipsecx_s cn63xx; + struct cvmx_pip_dec_ipsecx_s cn63xxp1; + struct cvmx_pip_dec_ipsecx_s cn66xx; + struct cvmx_pip_dec_ipsecx_s cn68xx; + struct cvmx_pip_dec_ipsecx_s cn68xxp1; + struct cvmx_pip_dec_ipsecx_s cnf71xx; }; union cvmx_pip_dsa_src_grp { uint64_t u64; struct cvmx_pip_dsa_src_grp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t map15:4; uint64_t map14:4; uint64_t map13:4; @@ -234,15 +498,41 @@ union cvmx_pip_dsa_src_grp { uint64_t map2:4; uint64_t map1:4; uint64_t map0:4; +#else + uint64_t map0:4; + uint64_t map1:4; + uint64_t map2:4; + uint64_t map3:4; + uint64_t map4:4; + uint64_t map5:4; + uint64_t map6:4; + uint64_t map7:4; + uint64_t map8:4; + uint64_t map9:4; + uint64_t map10:4; + uint64_t map11:4; + uint64_t map12:4; + uint64_t map13:4; + uint64_t map14:4; + uint64_t map15:4; +#endif } s; struct cvmx_pip_dsa_src_grp_s cn52xx; struct cvmx_pip_dsa_src_grp_s cn52xxp1; struct cvmx_pip_dsa_src_grp_s cn56xx; + struct cvmx_pip_dsa_src_grp_s cn61xx; + struct cvmx_pip_dsa_src_grp_s cn63xx; + struct cvmx_pip_dsa_src_grp_s cn63xxp1; + struct cvmx_pip_dsa_src_grp_s cn66xx; + struct cvmx_pip_dsa_src_grp_s cn68xx; + struct cvmx_pip_dsa_src_grp_s cn68xxp1; + struct cvmx_pip_dsa_src_grp_s cnf71xx; }; union cvmx_pip_dsa_vid_grp { uint64_t u64; struct cvmx_pip_dsa_vid_grp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t map15:4; uint64_t map14:4; uint64_t map13:4; @@ -259,29 +549,68 @@ union cvmx_pip_dsa_vid_grp { uint64_t map2:4; uint64_t map1:4; uint64_t map0:4; +#else + uint64_t map0:4; + uint64_t map1:4; + uint64_t map2:4; + uint64_t map3:4; + uint64_t map4:4; + uint64_t map5:4; + uint64_t map6:4; + uint64_t map7:4; + uint64_t map8:4; + uint64_t map9:4; + uint64_t map10:4; + uint64_t map11:4; + uint64_t map12:4; + uint64_t map13:4; + uint64_t map14:4; + uint64_t map15:4; +#endif } s; struct cvmx_pip_dsa_vid_grp_s cn52xx; struct cvmx_pip_dsa_vid_grp_s cn52xxp1; struct cvmx_pip_dsa_vid_grp_s cn56xx; + struct cvmx_pip_dsa_vid_grp_s cn61xx; + struct cvmx_pip_dsa_vid_grp_s cn63xx; + struct cvmx_pip_dsa_vid_grp_s cn63xxp1; + struct cvmx_pip_dsa_vid_grp_s cn66xx; + struct cvmx_pip_dsa_vid_grp_s cn68xx; + struct cvmx_pip_dsa_vid_grp_s cn68xxp1; + struct cvmx_pip_dsa_vid_grp_s cnf71xx; }; union cvmx_pip_frm_len_chkx { uint64_t u64; struct cvmx_pip_frm_len_chkx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t maxlen:16; uint64_t minlen:16; +#else + uint64_t minlen:16; + uint64_t maxlen:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pip_frm_len_chkx_s cn50xx; struct cvmx_pip_frm_len_chkx_s cn52xx; struct cvmx_pip_frm_len_chkx_s cn52xxp1; struct cvmx_pip_frm_len_chkx_s cn56xx; struct cvmx_pip_frm_len_chkx_s cn56xxp1; + struct cvmx_pip_frm_len_chkx_s cn61xx; + struct cvmx_pip_frm_len_chkx_s cn63xx; + struct cvmx_pip_frm_len_chkx_s cn63xxp1; + struct cvmx_pip_frm_len_chkx_s cn66xx; + struct cvmx_pip_frm_len_chkx_s cn68xx; + struct cvmx_pip_frm_len_chkx_s cn68xxp1; + struct cvmx_pip_frm_len_chkx_s cnf71xx; }; union cvmx_pip_gbl_cfg { uint64_t u64; struct cvmx_pip_gbl_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t tag_syn:1; uint64_t ip6_udp:1; @@ -290,6 +619,16 @@ union cvmx_pip_gbl_cfg { uint64_t raw_shf:3; uint64_t reserved_3_7:5; uint64_t nip_shf:3; +#else + uint64_t nip_shf:3; + uint64_t reserved_3_7:5; + uint64_t raw_shf:3; + uint64_t reserved_11_15:5; + uint64_t max_l2:1; + uint64_t ip6_udp:1; + uint64_t tag_syn:1; + uint64_t reserved_19_63:45; +#endif } s; struct cvmx_pip_gbl_cfg_s cn30xx; struct cvmx_pip_gbl_cfg_s cn31xx; @@ -302,12 +641,22 @@ union cvmx_pip_gbl_cfg { struct cvmx_pip_gbl_cfg_s cn56xxp1; struct cvmx_pip_gbl_cfg_s cn58xx; struct cvmx_pip_gbl_cfg_s cn58xxp1; + struct cvmx_pip_gbl_cfg_s cn61xx; + struct cvmx_pip_gbl_cfg_s cn63xx; + struct cvmx_pip_gbl_cfg_s cn63xxp1; + struct cvmx_pip_gbl_cfg_s cn66xx; + struct cvmx_pip_gbl_cfg_s cn68xx; + struct cvmx_pip_gbl_cfg_s cn68xxp1; + struct cvmx_pip_gbl_cfg_s cnf71xx; }; union cvmx_pip_gbl_ctl { uint64_t u64; struct cvmx_pip_gbl_ctl_s { - uint64_t reserved_27_63:37; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t egrp_dis:1; + uint64_t ihmsk_dis:1; uint64_t dsa_grp_tvid:1; uint64_t dsa_grp_scmd:1; uint64_t dsa_grp_sid:1; @@ -329,8 +678,35 @@ union cvmx_pip_gbl_ctl { uint64_t ip_hop:1; uint64_t ip_mal:1; uint64_t ip_chk:1; +#else + uint64_t ip_chk:1; + uint64_t ip_mal:1; + uint64_t ip_hop:1; + uint64_t ip4_opts:1; + uint64_t ip6_eext:2; + uint64_t reserved_6_7:2; + uint64_t l4_mal:1; + uint64_t l4_prt:1; + uint64_t l4_chk:1; + uint64_t l4_len:1; + uint64_t tcp_flag:1; + uint64_t l2_mal:1; + uint64_t vs_qos:1; + uint64_t vs_wqe:1; + uint64_t ignrs:1; + uint64_t reserved_17_19:3; + uint64_t ring_en:1; + uint64_t reserved_21_23:3; + uint64_t dsa_grp_sid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_tvid:1; + uint64_t ihmsk_dis:1; + uint64_t egrp_dis:1; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_pip_gbl_ctl_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t ignrs:1; uint64_t vs_wqe:1; @@ -347,15 +723,82 @@ union cvmx_pip_gbl_ctl { uint64_t ip_hop:1; uint64_t ip_mal:1; uint64_t ip_chk:1; +#else + uint64_t ip_chk:1; + uint64_t ip_mal:1; + uint64_t ip_hop:1; + uint64_t ip4_opts:1; + uint64_t ip6_eext:2; + uint64_t reserved_6_7:2; + uint64_t l4_mal:1; + uint64_t l4_prt:1; + uint64_t l4_chk:1; + uint64_t l4_len:1; + uint64_t tcp_flag:1; + uint64_t l2_mal:1; + uint64_t vs_qos:1; + uint64_t vs_wqe:1; + uint64_t ignrs:1; + uint64_t reserved_17_63:47; +#endif } cn30xx; struct cvmx_pip_gbl_ctl_cn30xx cn31xx; struct cvmx_pip_gbl_ctl_cn30xx cn38xx; struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2; struct cvmx_pip_gbl_ctl_cn30xx cn50xx; - struct cvmx_pip_gbl_ctl_s cn52xx; - struct cvmx_pip_gbl_ctl_s cn52xxp1; - struct cvmx_pip_gbl_ctl_s cn56xx; + struct cvmx_pip_gbl_ctl_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_27_63:37; + uint64_t dsa_grp_tvid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_sid:1; + uint64_t reserved_21_23:3; + uint64_t ring_en:1; + uint64_t reserved_17_19:3; + uint64_t ignrs:1; + uint64_t vs_wqe:1; + uint64_t vs_qos:1; + uint64_t l2_mal:1; + uint64_t tcp_flag:1; + uint64_t l4_len:1; + uint64_t l4_chk:1; + uint64_t l4_prt:1; + uint64_t l4_mal:1; + uint64_t reserved_6_7:2; + uint64_t ip6_eext:2; + uint64_t ip4_opts:1; + uint64_t ip_hop:1; + uint64_t ip_mal:1; + uint64_t ip_chk:1; +#else + uint64_t ip_chk:1; + uint64_t ip_mal:1; + uint64_t ip_hop:1; + uint64_t ip4_opts:1; + uint64_t ip6_eext:2; + uint64_t reserved_6_7:2; + uint64_t l4_mal:1; + uint64_t l4_prt:1; + uint64_t l4_chk:1; + uint64_t l4_len:1; + uint64_t tcp_flag:1; + uint64_t l2_mal:1; + uint64_t vs_qos:1; + uint64_t vs_wqe:1; + uint64_t ignrs:1; + uint64_t reserved_17_19:3; + uint64_t ring_en:1; + uint64_t reserved_21_23:3; + uint64_t dsa_grp_sid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_tvid:1; + uint64_t reserved_27_63:37; +#endif + } cn52xx; + struct cvmx_pip_gbl_ctl_cn52xx cn52xxp1; + struct cvmx_pip_gbl_ctl_cn52xx cn56xx; struct cvmx_pip_gbl_ctl_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t ring_en:1; uint64_t reserved_17_19:3; @@ -374,27 +817,215 @@ union cvmx_pip_gbl_ctl { uint64_t ip_hop:1; uint64_t ip_mal:1; uint64_t ip_chk:1; +#else + uint64_t ip_chk:1; + uint64_t ip_mal:1; + uint64_t ip_hop:1; + uint64_t ip4_opts:1; + uint64_t ip6_eext:2; + uint64_t reserved_6_7:2; + uint64_t l4_mal:1; + uint64_t l4_prt:1; + uint64_t l4_chk:1; + uint64_t l4_len:1; + uint64_t tcp_flag:1; + uint64_t l2_mal:1; + uint64_t vs_qos:1; + uint64_t vs_wqe:1; + uint64_t ignrs:1; + uint64_t reserved_17_19:3; + uint64_t ring_en:1; + uint64_t reserved_21_63:43; +#endif } cn56xxp1; struct cvmx_pip_gbl_ctl_cn30xx cn58xx; struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1; + struct cvmx_pip_gbl_ctl_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_28_63:36; + uint64_t ihmsk_dis:1; + uint64_t dsa_grp_tvid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_sid:1; + uint64_t reserved_21_23:3; + uint64_t ring_en:1; + uint64_t reserved_17_19:3; + uint64_t ignrs:1; + uint64_t vs_wqe:1; + uint64_t vs_qos:1; + uint64_t l2_mal:1; + uint64_t tcp_flag:1; + uint64_t l4_len:1; + uint64_t l4_chk:1; + uint64_t l4_prt:1; + uint64_t l4_mal:1; + uint64_t reserved_6_7:2; + uint64_t ip6_eext:2; + uint64_t ip4_opts:1; + uint64_t ip_hop:1; + uint64_t ip_mal:1; + uint64_t ip_chk:1; +#else + uint64_t ip_chk:1; + uint64_t ip_mal:1; + uint64_t ip_hop:1; + uint64_t ip4_opts:1; + uint64_t ip6_eext:2; + uint64_t reserved_6_7:2; + uint64_t l4_mal:1; + uint64_t l4_prt:1; + uint64_t l4_chk:1; + uint64_t l4_len:1; + uint64_t tcp_flag:1; + uint64_t l2_mal:1; + uint64_t vs_qos:1; + uint64_t vs_wqe:1; + uint64_t ignrs:1; + uint64_t reserved_17_19:3; + uint64_t ring_en:1; + uint64_t reserved_21_23:3; + uint64_t dsa_grp_sid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_tvid:1; + uint64_t ihmsk_dis:1; + uint64_t reserved_28_63:36; +#endif + } cn61xx; + struct cvmx_pip_gbl_ctl_cn61xx cn63xx; + struct cvmx_pip_gbl_ctl_cn61xx cn63xxp1; + struct cvmx_pip_gbl_ctl_cn61xx cn66xx; + struct cvmx_pip_gbl_ctl_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t egrp_dis:1; + uint64_t ihmsk_dis:1; + uint64_t dsa_grp_tvid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_sid:1; + uint64_t reserved_17_23:7; + uint64_t ignrs:1; + uint64_t vs_wqe:1; + uint64_t vs_qos:1; + uint64_t l2_mal:1; + uint64_t tcp_flag:1; + uint64_t l4_len:1; + uint64_t l4_chk:1; + uint64_t l4_prt:1; + uint64_t l4_mal:1; + uint64_t reserved_6_7:2; + uint64_t ip6_eext:2; + uint64_t ip4_opts:1; + uint64_t ip_hop:1; + uint64_t ip_mal:1; + uint64_t ip_chk:1; +#else + uint64_t ip_chk:1; + uint64_t ip_mal:1; + uint64_t ip_hop:1; + uint64_t ip4_opts:1; + uint64_t ip6_eext:2; + uint64_t reserved_6_7:2; + uint64_t l4_mal:1; + uint64_t l4_prt:1; + uint64_t l4_chk:1; + uint64_t l4_len:1; + uint64_t tcp_flag:1; + uint64_t l2_mal:1; + uint64_t vs_qos:1; + uint64_t vs_wqe:1; + uint64_t ignrs:1; + uint64_t reserved_17_23:7; + uint64_t dsa_grp_sid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_tvid:1; + uint64_t ihmsk_dis:1; + uint64_t egrp_dis:1; + uint64_t reserved_29_63:35; +#endif + } cn68xx; + struct cvmx_pip_gbl_ctl_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_28_63:36; + uint64_t ihmsk_dis:1; + uint64_t dsa_grp_tvid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_sid:1; + uint64_t reserved_17_23:7; + uint64_t ignrs:1; + uint64_t vs_wqe:1; + uint64_t vs_qos:1; + uint64_t l2_mal:1; + uint64_t tcp_flag:1; + uint64_t l4_len:1; + uint64_t l4_chk:1; + uint64_t l4_prt:1; + uint64_t l4_mal:1; + uint64_t reserved_6_7:2; + uint64_t ip6_eext:2; + uint64_t ip4_opts:1; + uint64_t ip_hop:1; + uint64_t ip_mal:1; + uint64_t ip_chk:1; +#else + uint64_t ip_chk:1; + uint64_t ip_mal:1; + uint64_t ip_hop:1; + uint64_t ip4_opts:1; + uint64_t ip6_eext:2; + uint64_t reserved_6_7:2; + uint64_t l4_mal:1; + uint64_t l4_prt:1; + uint64_t l4_chk:1; + uint64_t l4_len:1; + uint64_t tcp_flag:1; + uint64_t l2_mal:1; + uint64_t vs_qos:1; + uint64_t vs_wqe:1; + uint64_t ignrs:1; + uint64_t reserved_17_23:7; + uint64_t dsa_grp_sid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_tvid:1; + uint64_t ihmsk_dis:1; + uint64_t reserved_28_63:36; +#endif + } cn68xxp1; + struct cvmx_pip_gbl_ctl_cn61xx cnf71xx; }; union cvmx_pip_hg_pri_qos { uint64_t u64; struct cvmx_pip_hg_pri_qos_s { - uint64_t reserved_11_63:53; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_13_63:51; + uint64_t up_qos:1; + uint64_t reserved_11_11:1; uint64_t qos:3; uint64_t reserved_6_7:2; uint64_t pri:6; +#else + uint64_t pri:6; + uint64_t reserved_6_7:2; + uint64_t qos:3; + uint64_t reserved_11_11:1; + uint64_t up_qos:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_pip_hg_pri_qos_s cn52xx; struct cvmx_pip_hg_pri_qos_s cn52xxp1; struct cvmx_pip_hg_pri_qos_s cn56xx; + struct cvmx_pip_hg_pri_qos_s cn61xx; + struct cvmx_pip_hg_pri_qos_s cn63xx; + struct cvmx_pip_hg_pri_qos_s cn63xxp1; + struct cvmx_pip_hg_pri_qos_s cn66xx; + struct cvmx_pip_hg_pri_qos_s cnf71xx; }; union cvmx_pip_int_en { uint64_t u64; struct cvmx_pip_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t lenerr:1; @@ -409,8 +1040,25 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t punyerr:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_pip_int_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t beperr:1; uint64_t feperr:1; @@ -421,11 +1069,24 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t reserved_9_63:55; +#endif } cn30xx; struct cvmx_pip_int_en_cn30xx cn31xx; struct cvmx_pip_int_en_cn30xx cn38xx; struct cvmx_pip_int_en_cn30xx cn38xxp2; struct cvmx_pip_int_en_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t lenerr:1; uint64_t maxerr:1; @@ -439,8 +1100,24 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t reserved_1_1:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t reserved_1_1:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t reserved_12_63:52; +#endif } cn50xx; struct cvmx_pip_int_en_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t lenerr:1; @@ -455,10 +1132,27 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t reserved_1_1:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t reserved_1_1:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t punyerr:1; + uint64_t reserved_13_63:51; +#endif } cn52xx; struct cvmx_pip_int_en_cn52xx cn52xxp1; struct cvmx_pip_int_en_s cn56xx; struct cvmx_pip_int_en_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t lenerr:1; uint64_t maxerr:1; @@ -472,8 +1166,24 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t reserved_12_63:52; +#endif } cn56xxp1; struct cvmx_pip_int_en_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t reserved_9_11:3; @@ -486,13 +1196,35 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t reserved_9_11:3; + uint64_t punyerr:1; + uint64_t reserved_13_63:51; +#endif } cn58xx; struct cvmx_pip_int_en_cn30xx cn58xxp1; + struct cvmx_pip_int_en_s cn61xx; + struct cvmx_pip_int_en_s cn63xx; + struct cvmx_pip_int_en_s cn63xxp1; + struct cvmx_pip_int_en_s cn66xx; + struct cvmx_pip_int_en_s cn68xx; + struct cvmx_pip_int_en_s cn68xxp1; + struct cvmx_pip_int_en_s cnf71xx; }; union cvmx_pip_int_reg { uint64_t u64; struct cvmx_pip_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t lenerr:1; @@ -507,8 +1239,25 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t punyerr:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_pip_int_reg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t beperr:1; uint64_t feperr:1; @@ -519,11 +1268,24 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t reserved_9_63:55; +#endif } cn30xx; struct cvmx_pip_int_reg_cn30xx cn31xx; struct cvmx_pip_int_reg_cn30xx cn38xx; struct cvmx_pip_int_reg_cn30xx cn38xxp2; struct cvmx_pip_int_reg_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t lenerr:1; uint64_t maxerr:1; @@ -537,8 +1299,24 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t reserved_1_1:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t reserved_1_1:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t reserved_12_63:52; +#endif } cn50xx; struct cvmx_pip_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t lenerr:1; @@ -553,10 +1331,27 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t reserved_1_1:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t reserved_1_1:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t punyerr:1; + uint64_t reserved_13_63:51; +#endif } cn52xx; struct cvmx_pip_int_reg_cn52xx cn52xxp1; struct cvmx_pip_int_reg_s cn56xx; struct cvmx_pip_int_reg_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t lenerr:1; uint64_t maxerr:1; @@ -570,8 +1365,24 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t reserved_12_63:52; +#endif } cn56xxp1; struct cvmx_pip_int_reg_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t reserved_9_11:3; @@ -584,15 +1395,41 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t reserved_9_11:3; + uint64_t punyerr:1; + uint64_t reserved_13_63:51; +#endif } cn58xx; struct cvmx_pip_int_reg_cn30xx cn58xxp1; + struct cvmx_pip_int_reg_s cn61xx; + struct cvmx_pip_int_reg_s cn63xx; + struct cvmx_pip_int_reg_s cn63xxp1; + struct cvmx_pip_int_reg_s cn66xx; + struct cvmx_pip_int_reg_s cn68xx; + struct cvmx_pip_int_reg_s cn68xxp1; + struct cvmx_pip_int_reg_s cnf71xx; }; union cvmx_pip_ip_offset { uint64_t u64; struct cvmx_pip_ip_offset_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t offset:3; +#else + uint64_t offset:3; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_pip_ip_offset_s cn30xx; struct cvmx_pip_ip_offset_s cn31xx; @@ -605,12 +1442,63 @@ union cvmx_pip_ip_offset { struct cvmx_pip_ip_offset_s cn56xxp1; struct cvmx_pip_ip_offset_s cn58xx; struct cvmx_pip_ip_offset_s cn58xxp1; + struct cvmx_pip_ip_offset_s cn61xx; + struct cvmx_pip_ip_offset_s cn63xx; + struct cvmx_pip_ip_offset_s cn63xxp1; + struct cvmx_pip_ip_offset_s cn66xx; + struct cvmx_pip_ip_offset_s cn68xx; + struct cvmx_pip_ip_offset_s cn68xxp1; + struct cvmx_pip_ip_offset_s cnf71xx; +}; + +union cvmx_pip_pri_tblx { + uint64_t u64; + struct cvmx_pip_pri_tblx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t diff2_padd:8; + uint64_t hg2_padd:8; + uint64_t vlan2_padd:8; + uint64_t reserved_38_39:2; + uint64_t diff2_bpid:6; + uint64_t reserved_30_31:2; + uint64_t hg2_bpid:6; + uint64_t reserved_22_23:2; + uint64_t vlan2_bpid:6; + uint64_t reserved_11_15:5; + uint64_t diff2_qos:3; + uint64_t reserved_7_7:1; + uint64_t hg2_qos:3; + uint64_t reserved_3_3:1; + uint64_t vlan2_qos:3; +#else + uint64_t vlan2_qos:3; + uint64_t reserved_3_3:1; + uint64_t hg2_qos:3; + uint64_t reserved_7_7:1; + uint64_t diff2_qos:3; + uint64_t reserved_11_15:5; + uint64_t vlan2_bpid:6; + uint64_t reserved_22_23:2; + uint64_t hg2_bpid:6; + uint64_t reserved_30_31:2; + uint64_t diff2_bpid:6; + uint64_t reserved_38_39:2; + uint64_t vlan2_padd:8; + uint64_t hg2_padd:8; + uint64_t diff2_padd:8; +#endif + } s; + struct cvmx_pip_pri_tblx_s cn68xx; + struct cvmx_pip_pri_tblx_s cn68xxp1; }; union cvmx_pip_prt_cfgx { uint64_t u64; struct cvmx_pip_prt_cfgx_s { - uint64_t reserved_53_63:11; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_55_63:9; + uint64_t ih_pri:1; + uint64_t len_chk_sel:1; uint64_t pad_len:1; uint64_t vlan_len:1; uint64_t lenerr_en:1; @@ -638,8 +1526,41 @@ union cvmx_pip_prt_cfgx { uint64_t mode:2; uint64_t reserved_7_7:1; uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_7:1; + uint64_t mode:2; + uint64_t dsa_en:1; + uint64_t higig_en:1; + uint64_t crc_en:1; + uint64_t reserved_13_15:3; + uint64_t qos_vlan:1; + uint64_t qos_diff:1; + uint64_t qos_vod:1; + uint64_t qos_vsel:1; + uint64_t qos_wat:4; + uint64_t qos:3; + uint64_t hg_qos:1; + uint64_t grp_wat:4; + uint64_t inst_hdr:1; + uint64_t dyn_rs:1; + uint64_t tag_inc:2; + uint64_t rawdrp:1; + uint64_t reserved_37_39:3; + uint64_t qos_wat_47:4; + uint64_t grp_wat_47:4; + uint64_t minerr_en:1; + uint64_t maxerr_en:1; + uint64_t lenerr_en:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t len_chk_sel:1; + uint64_t ih_pri:1; + uint64_t reserved_55_63:9; +#endif } s; struct cvmx_pip_prt_cfgx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t rawdrp:1; uint64_t tag_inc:2; @@ -656,9 +1577,28 @@ union cvmx_pip_prt_cfgx { uint64_t mode:2; uint64_t reserved_7_7:1; uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_7:1; + uint64_t mode:2; + uint64_t reserved_10_15:6; + uint64_t qos_vlan:1; + uint64_t qos_diff:1; + uint64_t reserved_18_19:2; + uint64_t qos_wat:4; + uint64_t qos:3; + uint64_t reserved_27_27:1; + uint64_t grp_wat:4; + uint64_t inst_hdr:1; + uint64_t dyn_rs:1; + uint64_t tag_inc:2; + uint64_t rawdrp:1; + uint64_t reserved_37_63:27; +#endif } cn30xx; struct cvmx_pip_prt_cfgx_cn30xx cn31xx; struct cvmx_pip_prt_cfgx_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t rawdrp:1; uint64_t tag_inc:2; @@ -677,9 +1617,30 @@ union cvmx_pip_prt_cfgx { uint64_t mode:2; uint64_t reserved_7_7:1; uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_7:1; + uint64_t mode:2; + uint64_t reserved_10_11:2; + uint64_t crc_en:1; + uint64_t reserved_13_15:3; + uint64_t qos_vlan:1; + uint64_t qos_diff:1; + uint64_t reserved_18_19:2; + uint64_t qos_wat:4; + uint64_t qos:3; + uint64_t reserved_27_27:1; + uint64_t grp_wat:4; + uint64_t inst_hdr:1; + uint64_t dyn_rs:1; + uint64_t tag_inc:2; + uint64_t rawdrp:1; + uint64_t reserved_37_63:27; +#endif } cn38xx; struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2; struct cvmx_pip_prt_cfgx_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_53_63:11; uint64_t pad_len:1; uint64_t vlan_len:1; @@ -707,12 +1668,102 @@ union cvmx_pip_prt_cfgx { uint64_t mode:2; uint64_t reserved_7_7:1; uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_7:1; + uint64_t mode:2; + uint64_t reserved_10_11:2; + uint64_t crc_en:1; + uint64_t reserved_13_15:3; + uint64_t qos_vlan:1; + uint64_t qos_diff:1; + uint64_t qos_vod:1; + uint64_t reserved_19_19:1; + uint64_t qos_wat:4; + uint64_t qos:3; + uint64_t reserved_27_27:1; + uint64_t grp_wat:4; + uint64_t inst_hdr:1; + uint64_t dyn_rs:1; + uint64_t tag_inc:2; + uint64_t rawdrp:1; + uint64_t reserved_37_39:3; + uint64_t qos_wat_47:4; + uint64_t grp_wat_47:4; + uint64_t minerr_en:1; + uint64_t maxerr_en:1; + uint64_t lenerr_en:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t reserved_53_63:11; +#endif } cn50xx; - struct cvmx_pip_prt_cfgx_s cn52xx; - struct cvmx_pip_prt_cfgx_s cn52xxp1; - struct cvmx_pip_prt_cfgx_s cn56xx; + struct cvmx_pip_prt_cfgx_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_53_63:11; + uint64_t pad_len:1; + uint64_t vlan_len:1; + uint64_t lenerr_en:1; + uint64_t maxerr_en:1; + uint64_t minerr_en:1; + uint64_t grp_wat_47:4; + uint64_t qos_wat_47:4; + uint64_t reserved_37_39:3; + uint64_t rawdrp:1; + uint64_t tag_inc:2; + uint64_t dyn_rs:1; + uint64_t inst_hdr:1; + uint64_t grp_wat:4; + uint64_t hg_qos:1; + uint64_t qos:3; + uint64_t qos_wat:4; + uint64_t qos_vsel:1; + uint64_t qos_vod:1; + uint64_t qos_diff:1; + uint64_t qos_vlan:1; + uint64_t reserved_13_15:3; + uint64_t crc_en:1; + uint64_t higig_en:1; + uint64_t dsa_en:1; + uint64_t mode:2; + uint64_t reserved_7_7:1; + uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_7:1; + uint64_t mode:2; + uint64_t dsa_en:1; + uint64_t higig_en:1; + uint64_t crc_en:1; + uint64_t reserved_13_15:3; + uint64_t qos_vlan:1; + uint64_t qos_diff:1; + uint64_t qos_vod:1; + uint64_t qos_vsel:1; + uint64_t qos_wat:4; + uint64_t qos:3; + uint64_t hg_qos:1; + uint64_t grp_wat:4; + uint64_t inst_hdr:1; + uint64_t dyn_rs:1; + uint64_t tag_inc:2; + uint64_t rawdrp:1; + uint64_t reserved_37_39:3; + uint64_t qos_wat_47:4; + uint64_t grp_wat_47:4; + uint64_t minerr_en:1; + uint64_t maxerr_en:1; + uint64_t lenerr_en:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t reserved_53_63:11; +#endif + } cn52xx; + struct cvmx_pip_prt_cfgx_cn52xx cn52xxp1; + struct cvmx_pip_prt_cfgx_cn52xx cn56xx; struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1; struct cvmx_pip_prt_cfgx_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t rawdrp:1; uint64_t tag_inc:2; @@ -732,14 +1783,191 @@ union cvmx_pip_prt_cfgx { uint64_t mode:2; uint64_t reserved_7_7:1; uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_7:1; + uint64_t mode:2; + uint64_t reserved_10_11:2; + uint64_t crc_en:1; + uint64_t reserved_13_15:3; + uint64_t qos_vlan:1; + uint64_t qos_diff:1; + uint64_t qos_vod:1; + uint64_t reserved_19_19:1; + uint64_t qos_wat:4; + uint64_t qos:3; + uint64_t reserved_27_27:1; + uint64_t grp_wat:4; + uint64_t inst_hdr:1; + uint64_t dyn_rs:1; + uint64_t tag_inc:2; + uint64_t rawdrp:1; + uint64_t reserved_37_63:27; +#endif } cn58xx; struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1; + struct cvmx_pip_prt_cfgx_cn52xx cn61xx; + struct cvmx_pip_prt_cfgx_cn52xx cn63xx; + struct cvmx_pip_prt_cfgx_cn52xx cn63xxp1; + struct cvmx_pip_prt_cfgx_cn52xx cn66xx; + struct cvmx_pip_prt_cfgx_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_55_63:9; + uint64_t ih_pri:1; + uint64_t len_chk_sel:1; + uint64_t pad_len:1; + uint64_t vlan_len:1; + uint64_t lenerr_en:1; + uint64_t maxerr_en:1; + uint64_t minerr_en:1; + uint64_t grp_wat_47:4; + uint64_t qos_wat_47:4; + uint64_t reserved_37_39:3; + uint64_t rawdrp:1; + uint64_t tag_inc:2; + uint64_t dyn_rs:1; + uint64_t inst_hdr:1; + uint64_t grp_wat:4; + uint64_t hg_qos:1; + uint64_t qos:3; + uint64_t qos_wat:4; + uint64_t reserved_19_19:1; + uint64_t qos_vod:1; + uint64_t qos_diff:1; + uint64_t qos_vlan:1; + uint64_t reserved_13_15:3; + uint64_t crc_en:1; + uint64_t higig_en:1; + uint64_t dsa_en:1; + uint64_t mode:2; + uint64_t reserved_7_7:1; + uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_7:1; + uint64_t mode:2; + uint64_t dsa_en:1; + uint64_t higig_en:1; + uint64_t crc_en:1; + uint64_t reserved_13_15:3; + uint64_t qos_vlan:1; + uint64_t qos_diff:1; + uint64_t qos_vod:1; + uint64_t reserved_19_19:1; + uint64_t qos_wat:4; + uint64_t qos:3; + uint64_t hg_qos:1; + uint64_t grp_wat:4; + uint64_t inst_hdr:1; + uint64_t dyn_rs:1; + uint64_t tag_inc:2; + uint64_t rawdrp:1; + uint64_t reserved_37_39:3; + uint64_t qos_wat_47:4; + uint64_t grp_wat_47:4; + uint64_t minerr_en:1; + uint64_t maxerr_en:1; + uint64_t lenerr_en:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t len_chk_sel:1; + uint64_t ih_pri:1; + uint64_t reserved_55_63:9; +#endif + } cn68xx; + struct cvmx_pip_prt_cfgx_cn68xx cn68xxp1; + struct cvmx_pip_prt_cfgx_cn52xx cnf71xx; +}; + +union cvmx_pip_prt_cfgbx { + uint64_t u64; + struct cvmx_pip_prt_cfgbx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_39_63:25; + uint64_t alt_skp_sel:2; + uint64_t alt_skp_en:1; + uint64_t reserved_35_35:1; + uint64_t bsel_num:2; + uint64_t bsel_en:1; + uint64_t reserved_24_31:8; + uint64_t base:8; + uint64_t reserved_6_15:10; + uint64_t bpid:6; +#else + uint64_t bpid:6; + uint64_t reserved_6_15:10; + uint64_t base:8; + uint64_t reserved_24_31:8; + uint64_t bsel_en:1; + uint64_t bsel_num:2; + uint64_t reserved_35_35:1; + uint64_t alt_skp_en:1; + uint64_t alt_skp_sel:2; + uint64_t reserved_39_63:25; +#endif + } s; + struct cvmx_pip_prt_cfgbx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_39_63:25; + uint64_t alt_skp_sel:2; + uint64_t alt_skp_en:1; + uint64_t reserved_35_35:1; + uint64_t bsel_num:2; + uint64_t bsel_en:1; + uint64_t reserved_0_31:32; +#else + uint64_t reserved_0_31:32; + uint64_t bsel_en:1; + uint64_t bsel_num:2; + uint64_t reserved_35_35:1; + uint64_t alt_skp_en:1; + uint64_t alt_skp_sel:2; + uint64_t reserved_39_63:25; +#endif + } cn61xx; + struct cvmx_pip_prt_cfgbx_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_39_63:25; + uint64_t alt_skp_sel:2; + uint64_t alt_skp_en:1; + uint64_t reserved_0_35:36; +#else + uint64_t reserved_0_35:36; + uint64_t alt_skp_en:1; + uint64_t alt_skp_sel:2; + uint64_t reserved_39_63:25; +#endif + } cn66xx; + struct cvmx_pip_prt_cfgbx_s cn68xx; + struct cvmx_pip_prt_cfgbx_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_24_63:40; + uint64_t base:8; + uint64_t reserved_6_15:10; + uint64_t bpid:6; +#else + uint64_t bpid:6; + uint64_t reserved_6_15:10; + uint64_t base:8; + uint64_t reserved_24_63:40; +#endif + } cn68xxp1; + struct cvmx_pip_prt_cfgbx_cn61xx cnf71xx; }; union cvmx_pip_prt_tagx { uint64_t u64; struct cvmx_pip_prt_tagx_s { - uint64_t reserved_40_63:24; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t portadd_en:1; + uint64_t inc_hwchk:1; + uint64_t reserved_50_51:2; + uint64_t grptagbase_msb:2; + uint64_t reserved_46_47:2; + uint64_t grptagmask_msb:2; + uint64_t reserved_42_43:2; + uint64_t grp_msb:2; uint64_t grptagbase:4; uint64_t grptagmask:4; uint64_t grptag:1; @@ -764,8 +1992,44 @@ union cvmx_pip_prt_tagx { uint64_t ip4_tag_type:2; uint64_t non_tag_type:2; uint64_t grp:4; +#else + uint64_t grp:4; + uint64_t non_tag_type:2; + uint64_t ip4_tag_type:2; + uint64_t ip6_tag_type:2; + uint64_t tcp4_tag_type:2; + uint64_t tcp6_tag_type:2; + uint64_t ip4_src_flag:1; + uint64_t ip6_src_flag:1; + uint64_t ip4_dst_flag:1; + uint64_t ip6_dst_flag:1; + uint64_t ip4_pctl_flag:1; + uint64_t ip6_nxth_flag:1; + uint64_t ip4_sprt_flag:1; + uint64_t ip6_sprt_flag:1; + uint64_t ip4_dprt_flag:1; + uint64_t ip6_dprt_flag:1; + uint64_t inc_prt_flag:1; + uint64_t inc_vlan:1; + uint64_t inc_vs:2; + uint64_t tag_mode:2; + uint64_t grptag_mskip:1; + uint64_t grptag:1; + uint64_t grptagmask:4; + uint64_t grptagbase:4; + uint64_t grp_msb:2; + uint64_t reserved_42_43:2; + uint64_t grptagmask_msb:2; + uint64_t reserved_46_47:2; + uint64_t grptagbase_msb:2; + uint64_t reserved_50_51:2; + uint64_t inc_hwchk:1; + uint64_t portadd_en:1; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_pip_prt_tagx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t grptagbase:4; uint64_t grptagmask:4; @@ -791,24 +2055,117 @@ union cvmx_pip_prt_tagx { uint64_t ip4_tag_type:2; uint64_t non_tag_type:2; uint64_t grp:4; +#else + uint64_t grp:4; + uint64_t non_tag_type:2; + uint64_t ip4_tag_type:2; + uint64_t ip6_tag_type:2; + uint64_t tcp4_tag_type:2; + uint64_t tcp6_tag_type:2; + uint64_t ip4_src_flag:1; + uint64_t ip6_src_flag:1; + uint64_t ip4_dst_flag:1; + uint64_t ip6_dst_flag:1; + uint64_t ip4_pctl_flag:1; + uint64_t ip6_nxth_flag:1; + uint64_t ip4_sprt_flag:1; + uint64_t ip6_sprt_flag:1; + uint64_t ip4_dprt_flag:1; + uint64_t ip6_dprt_flag:1; + uint64_t inc_prt_flag:1; + uint64_t inc_vlan:1; + uint64_t inc_vs:2; + uint64_t tag_mode:2; + uint64_t reserved_30_30:1; + uint64_t grptag:1; + uint64_t grptagmask:4; + uint64_t grptagbase:4; + uint64_t reserved_40_63:24; +#endif } cn30xx; struct cvmx_pip_prt_tagx_cn30xx cn31xx; struct cvmx_pip_prt_tagx_cn30xx cn38xx; struct cvmx_pip_prt_tagx_cn30xx cn38xxp2; - struct cvmx_pip_prt_tagx_s cn50xx; - struct cvmx_pip_prt_tagx_s cn52xx; - struct cvmx_pip_prt_tagx_s cn52xxp1; - struct cvmx_pip_prt_tagx_s cn56xx; - struct cvmx_pip_prt_tagx_s cn56xxp1; + struct cvmx_pip_prt_tagx_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_40_63:24; + uint64_t grptagbase:4; + uint64_t grptagmask:4; + uint64_t grptag:1; + uint64_t grptag_mskip:1; + uint64_t tag_mode:2; + uint64_t inc_vs:2; + uint64_t inc_vlan:1; + uint64_t inc_prt_flag:1; + uint64_t ip6_dprt_flag:1; + uint64_t ip4_dprt_flag:1; + uint64_t ip6_sprt_flag:1; + uint64_t ip4_sprt_flag:1; + uint64_t ip6_nxth_flag:1; + uint64_t ip4_pctl_flag:1; + uint64_t ip6_dst_flag:1; + uint64_t ip4_dst_flag:1; + uint64_t ip6_src_flag:1; + uint64_t ip4_src_flag:1; + uint64_t tcp6_tag_type:2; + uint64_t tcp4_tag_type:2; + uint64_t ip6_tag_type:2; + uint64_t ip4_tag_type:2; + uint64_t non_tag_type:2; + uint64_t grp:4; +#else + uint64_t grp:4; + uint64_t non_tag_type:2; + uint64_t ip4_tag_type:2; + uint64_t ip6_tag_type:2; + uint64_t tcp4_tag_type:2; + uint64_t tcp6_tag_type:2; + uint64_t ip4_src_flag:1; + uint64_t ip6_src_flag:1; + uint64_t ip4_dst_flag:1; + uint64_t ip6_dst_flag:1; + uint64_t ip4_pctl_flag:1; + uint64_t ip6_nxth_flag:1; + uint64_t ip4_sprt_flag:1; + uint64_t ip6_sprt_flag:1; + uint64_t ip4_dprt_flag:1; + uint64_t ip6_dprt_flag:1; + uint64_t inc_prt_flag:1; + uint64_t inc_vlan:1; + uint64_t inc_vs:2; + uint64_t tag_mode:2; + uint64_t grptag_mskip:1; + uint64_t grptag:1; + uint64_t grptagmask:4; + uint64_t grptagbase:4; + uint64_t reserved_40_63:24; +#endif + } cn50xx; + struct cvmx_pip_prt_tagx_cn50xx cn52xx; + struct cvmx_pip_prt_tagx_cn50xx cn52xxp1; + struct cvmx_pip_prt_tagx_cn50xx cn56xx; + struct cvmx_pip_prt_tagx_cn50xx cn56xxp1; struct cvmx_pip_prt_tagx_cn30xx cn58xx; struct cvmx_pip_prt_tagx_cn30xx cn58xxp1; + struct cvmx_pip_prt_tagx_cn50xx cn61xx; + struct cvmx_pip_prt_tagx_cn50xx cn63xx; + struct cvmx_pip_prt_tagx_cn50xx cn63xxp1; + struct cvmx_pip_prt_tagx_cn50xx cn66xx; + struct cvmx_pip_prt_tagx_s cn68xx; + struct cvmx_pip_prt_tagx_s cn68xxp1; + struct cvmx_pip_prt_tagx_cn50xx cnf71xx; }; union cvmx_pip_qos_diffx { uint64_t u64; struct cvmx_pip_qos_diffx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_pip_qos_diffx_s cn30xx; struct cvmx_pip_qos_diffx_s cn31xx; @@ -821,19 +2178,36 @@ union cvmx_pip_qos_diffx { struct cvmx_pip_qos_diffx_s cn56xxp1; struct cvmx_pip_qos_diffx_s cn58xx; struct cvmx_pip_qos_diffx_s cn58xxp1; + struct cvmx_pip_qos_diffx_s cn61xx; + struct cvmx_pip_qos_diffx_s cn63xx; + struct cvmx_pip_qos_diffx_s cn63xxp1; + struct cvmx_pip_qos_diffx_s cn66xx; + struct cvmx_pip_qos_diffx_s cnf71xx; }; union cvmx_pip_qos_vlanx { uint64_t u64; struct cvmx_pip_qos_vlanx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t qos1:3; uint64_t reserved_3_3:1; uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t reserved_3_3:1; + uint64_t qos1:3; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_pip_qos_vlanx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_pip_qos_vlanx_cn30xx cn31xx; struct cvmx_pip_qos_vlanx_cn30xx cn38xx; @@ -845,22 +2219,40 @@ union cvmx_pip_qos_vlanx { struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1; struct cvmx_pip_qos_vlanx_cn30xx cn58xx; struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1; + struct cvmx_pip_qos_vlanx_s cn61xx; + struct cvmx_pip_qos_vlanx_s cn63xx; + struct cvmx_pip_qos_vlanx_s cn63xxp1; + struct cvmx_pip_qos_vlanx_s cn66xx; + struct cvmx_pip_qos_vlanx_s cnf71xx; }; union cvmx_pip_qos_watchx { uint64_t u64; struct cvmx_pip_qos_watchx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t mask:16; - uint64_t reserved_28_31:4; - uint64_t grp:4; + uint64_t reserved_30_31:2; + uint64_t grp:6; uint64_t reserved_23_23:1; uint64_t qos:3; uint64_t reserved_19_19:1; uint64_t match_type:3; uint64_t match_value:16; +#else + uint64_t match_value:16; + uint64_t match_type:3; + uint64_t reserved_19_19:1; + uint64_t qos:3; + uint64_t reserved_23_23:1; + uint64_t grp:6; + uint64_t reserved_30_31:2; + uint64_t mask:16; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_pip_qos_watchx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t mask:16; uint64_t reserved_28_31:4; @@ -870,24 +2262,69 @@ union cvmx_pip_qos_watchx { uint64_t reserved_18_19:2; uint64_t match_type:2; uint64_t match_value:16; +#else + uint64_t match_value:16; + uint64_t match_type:2; + uint64_t reserved_18_19:2; + uint64_t qos:3; + uint64_t reserved_23_23:1; + uint64_t grp:4; + uint64_t reserved_28_31:4; + uint64_t mask:16; + uint64_t reserved_48_63:16; +#endif } cn30xx; struct cvmx_pip_qos_watchx_cn30xx cn31xx; struct cvmx_pip_qos_watchx_cn30xx cn38xx; struct cvmx_pip_qos_watchx_cn30xx cn38xxp2; - struct cvmx_pip_qos_watchx_s cn50xx; - struct cvmx_pip_qos_watchx_s cn52xx; - struct cvmx_pip_qos_watchx_s cn52xxp1; - struct cvmx_pip_qos_watchx_s cn56xx; - struct cvmx_pip_qos_watchx_s cn56xxp1; + struct cvmx_pip_qos_watchx_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t mask:16; + uint64_t reserved_28_31:4; + uint64_t grp:4; + uint64_t reserved_23_23:1; + uint64_t qos:3; + uint64_t reserved_19_19:1; + uint64_t match_type:3; + uint64_t match_value:16; +#else + uint64_t match_value:16; + uint64_t match_type:3; + uint64_t reserved_19_19:1; + uint64_t qos:3; + uint64_t reserved_23_23:1; + uint64_t grp:4; + uint64_t reserved_28_31:4; + uint64_t mask:16; + uint64_t reserved_48_63:16; +#endif + } cn50xx; + struct cvmx_pip_qos_watchx_cn50xx cn52xx; + struct cvmx_pip_qos_watchx_cn50xx cn52xxp1; + struct cvmx_pip_qos_watchx_cn50xx cn56xx; + struct cvmx_pip_qos_watchx_cn50xx cn56xxp1; struct cvmx_pip_qos_watchx_cn30xx cn58xx; struct cvmx_pip_qos_watchx_cn30xx cn58xxp1; + struct cvmx_pip_qos_watchx_cn50xx cn61xx; + struct cvmx_pip_qos_watchx_cn50xx cn63xx; + struct cvmx_pip_qos_watchx_cn50xx cn63xxp1; + struct cvmx_pip_qos_watchx_cn50xx cn66xx; + struct cvmx_pip_qos_watchx_s cn68xx; + struct cvmx_pip_qos_watchx_s cn68xxp1; + struct cvmx_pip_qos_watchx_cn50xx cnf71xx; }; union cvmx_pip_raw_word { uint64_t u64; struct cvmx_pip_raw_word_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t word:56; +#else + uint64_t word:56; + uint64_t reserved_56_63:8; +#endif } s; struct cvmx_pip_raw_word_s cn30xx; struct cvmx_pip_raw_word_s cn31xx; @@ -900,13 +2337,25 @@ union cvmx_pip_raw_word { struct cvmx_pip_raw_word_s cn56xxp1; struct cvmx_pip_raw_word_s cn58xx; struct cvmx_pip_raw_word_s cn58xxp1; + struct cvmx_pip_raw_word_s cn61xx; + struct cvmx_pip_raw_word_s cn63xx; + struct cvmx_pip_raw_word_s cn63xxp1; + struct cvmx_pip_raw_word_s cn66xx; + struct cvmx_pip_raw_word_s cn68xx; + struct cvmx_pip_raw_word_s cn68xxp1; + struct cvmx_pip_raw_word_s cnf71xx; }; union cvmx_pip_sft_rst { uint64_t u64; struct cvmx_pip_sft_rst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rst:1; +#else + uint64_t rst:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_pip_sft_rst_s cn30xx; struct cvmx_pip_sft_rst_s cn31xx; @@ -918,13 +2367,40 @@ union cvmx_pip_sft_rst { struct cvmx_pip_sft_rst_s cn56xxp1; struct cvmx_pip_sft_rst_s cn58xx; struct cvmx_pip_sft_rst_s cn58xxp1; + struct cvmx_pip_sft_rst_s cn61xx; + struct cvmx_pip_sft_rst_s cn63xx; + struct cvmx_pip_sft_rst_s cn63xxp1; + struct cvmx_pip_sft_rst_s cn66xx; + struct cvmx_pip_sft_rst_s cn68xx; + struct cvmx_pip_sft_rst_s cn68xxp1; + struct cvmx_pip_sft_rst_s cnf71xx; +}; + +union cvmx_pip_stat0_x { + uint64_t u64; + struct cvmx_pip_stat0_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t drp_pkts:32; + uint64_t drp_octs:32; +#else + uint64_t drp_octs:32; + uint64_t drp_pkts:32; +#endif + } s; + struct cvmx_pip_stat0_x_s cn68xx; + struct cvmx_pip_stat0_x_s cn68xxp1; }; union cvmx_pip_stat0_prtx { uint64_t u64; struct cvmx_pip_stat0_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t drp_pkts:32; uint64_t drp_octs:32; +#else + uint64_t drp_octs:32; + uint64_t drp_pkts:32; +#endif } s; struct cvmx_pip_stat0_prtx_s cn30xx; struct cvmx_pip_stat0_prtx_s cn31xx; @@ -937,13 +2413,112 @@ union cvmx_pip_stat0_prtx { struct cvmx_pip_stat0_prtx_s cn56xxp1; struct cvmx_pip_stat0_prtx_s cn58xx; struct cvmx_pip_stat0_prtx_s cn58xxp1; + struct cvmx_pip_stat0_prtx_s cn61xx; + struct cvmx_pip_stat0_prtx_s cn63xx; + struct cvmx_pip_stat0_prtx_s cn63xxp1; + struct cvmx_pip_stat0_prtx_s cn66xx; + struct cvmx_pip_stat0_prtx_s cnf71xx; +}; + +union cvmx_pip_stat10_x { + uint64_t u64; + struct cvmx_pip_stat10_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcast:32; + uint64_t mcast:32; +#else + uint64_t mcast:32; + uint64_t bcast:32; +#endif + } s; + struct cvmx_pip_stat10_x_s cn68xx; + struct cvmx_pip_stat10_x_s cn68xxp1; +}; + +union cvmx_pip_stat10_prtx { + uint64_t u64; + struct cvmx_pip_stat10_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcast:32; + uint64_t mcast:32; +#else + uint64_t mcast:32; + uint64_t bcast:32; +#endif + } s; + struct cvmx_pip_stat10_prtx_s cn52xx; + struct cvmx_pip_stat10_prtx_s cn52xxp1; + struct cvmx_pip_stat10_prtx_s cn56xx; + struct cvmx_pip_stat10_prtx_s cn56xxp1; + struct cvmx_pip_stat10_prtx_s cn61xx; + struct cvmx_pip_stat10_prtx_s cn63xx; + struct cvmx_pip_stat10_prtx_s cn63xxp1; + struct cvmx_pip_stat10_prtx_s cn66xx; + struct cvmx_pip_stat10_prtx_s cnf71xx; +}; + +union cvmx_pip_stat11_x { + uint64_t u64; + struct cvmx_pip_stat11_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcast:32; + uint64_t mcast:32; +#else + uint64_t mcast:32; + uint64_t bcast:32; +#endif + } s; + struct cvmx_pip_stat11_x_s cn68xx; + struct cvmx_pip_stat11_x_s cn68xxp1; +}; + +union cvmx_pip_stat11_prtx { + uint64_t u64; + struct cvmx_pip_stat11_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcast:32; + uint64_t mcast:32; +#else + uint64_t mcast:32; + uint64_t bcast:32; +#endif + } s; + struct cvmx_pip_stat11_prtx_s cn52xx; + struct cvmx_pip_stat11_prtx_s cn52xxp1; + struct cvmx_pip_stat11_prtx_s cn56xx; + struct cvmx_pip_stat11_prtx_s cn56xxp1; + struct cvmx_pip_stat11_prtx_s cn61xx; + struct cvmx_pip_stat11_prtx_s cn63xx; + struct cvmx_pip_stat11_prtx_s cn63xxp1; + struct cvmx_pip_stat11_prtx_s cn66xx; + struct cvmx_pip_stat11_prtx_s cnf71xx; +}; + +union cvmx_pip_stat1_x { + uint64_t u64; + struct cvmx_pip_stat1_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t octs:48; +#else + uint64_t octs:48; + uint64_t reserved_48_63:16; +#endif + } s; + struct cvmx_pip_stat1_x_s cn68xx; + struct cvmx_pip_stat1_x_s cn68xxp1; }; union cvmx_pip_stat1_prtx { uint64_t u64; struct cvmx_pip_stat1_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t octs:48; +#else + uint64_t octs:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_pip_stat1_prtx_s cn30xx; struct cvmx_pip_stat1_prtx_s cn31xx; @@ -956,13 +2531,38 @@ union cvmx_pip_stat1_prtx { struct cvmx_pip_stat1_prtx_s cn56xxp1; struct cvmx_pip_stat1_prtx_s cn58xx; struct cvmx_pip_stat1_prtx_s cn58xxp1; + struct cvmx_pip_stat1_prtx_s cn61xx; + struct cvmx_pip_stat1_prtx_s cn63xx; + struct cvmx_pip_stat1_prtx_s cn63xxp1; + struct cvmx_pip_stat1_prtx_s cn66xx; + struct cvmx_pip_stat1_prtx_s cnf71xx; +}; + +union cvmx_pip_stat2_x { + uint64_t u64; + struct cvmx_pip_stat2_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t pkts:32; + uint64_t raw:32; +#else + uint64_t raw:32; + uint64_t pkts:32; +#endif + } s; + struct cvmx_pip_stat2_x_s cn68xx; + struct cvmx_pip_stat2_x_s cn68xxp1; }; union cvmx_pip_stat2_prtx { uint64_t u64; struct cvmx_pip_stat2_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t pkts:32; uint64_t raw:32; +#else + uint64_t raw:32; + uint64_t pkts:32; +#endif } s; struct cvmx_pip_stat2_prtx_s cn30xx; struct cvmx_pip_stat2_prtx_s cn31xx; @@ -975,13 +2575,38 @@ union cvmx_pip_stat2_prtx { struct cvmx_pip_stat2_prtx_s cn56xxp1; struct cvmx_pip_stat2_prtx_s cn58xx; struct cvmx_pip_stat2_prtx_s cn58xxp1; + struct cvmx_pip_stat2_prtx_s cn61xx; + struct cvmx_pip_stat2_prtx_s cn63xx; + struct cvmx_pip_stat2_prtx_s cn63xxp1; + struct cvmx_pip_stat2_prtx_s cn66xx; + struct cvmx_pip_stat2_prtx_s cnf71xx; +}; + +union cvmx_pip_stat3_x { + uint64_t u64; + struct cvmx_pip_stat3_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcst:32; + uint64_t mcst:32; +#else + uint64_t mcst:32; + uint64_t bcst:32; +#endif + } s; + struct cvmx_pip_stat3_x_s cn68xx; + struct cvmx_pip_stat3_x_s cn68xxp1; }; union cvmx_pip_stat3_prtx { uint64_t u64; struct cvmx_pip_stat3_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bcst:32; uint64_t mcst:32; +#else + uint64_t mcst:32; + uint64_t bcst:32; +#endif } s; struct cvmx_pip_stat3_prtx_s cn30xx; struct cvmx_pip_stat3_prtx_s cn31xx; @@ -994,13 +2619,38 @@ union cvmx_pip_stat3_prtx { struct cvmx_pip_stat3_prtx_s cn56xxp1; struct cvmx_pip_stat3_prtx_s cn58xx; struct cvmx_pip_stat3_prtx_s cn58xxp1; + struct cvmx_pip_stat3_prtx_s cn61xx; + struct cvmx_pip_stat3_prtx_s cn63xx; + struct cvmx_pip_stat3_prtx_s cn63xxp1; + struct cvmx_pip_stat3_prtx_s cn66xx; + struct cvmx_pip_stat3_prtx_s cnf71xx; +}; + +union cvmx_pip_stat4_x { + uint64_t u64; + struct cvmx_pip_stat4_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t h65to127:32; + uint64_t h64:32; +#else + uint64_t h64:32; + uint64_t h65to127:32; +#endif + } s; + struct cvmx_pip_stat4_x_s cn68xx; + struct cvmx_pip_stat4_x_s cn68xxp1; }; union cvmx_pip_stat4_prtx { uint64_t u64; struct cvmx_pip_stat4_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t h65to127:32; uint64_t h64:32; +#else + uint64_t h64:32; + uint64_t h65to127:32; +#endif } s; struct cvmx_pip_stat4_prtx_s cn30xx; struct cvmx_pip_stat4_prtx_s cn31xx; @@ -1013,13 +2663,38 @@ union cvmx_pip_stat4_prtx { struct cvmx_pip_stat4_prtx_s cn56xxp1; struct cvmx_pip_stat4_prtx_s cn58xx; struct cvmx_pip_stat4_prtx_s cn58xxp1; + struct cvmx_pip_stat4_prtx_s cn61xx; + struct cvmx_pip_stat4_prtx_s cn63xx; + struct cvmx_pip_stat4_prtx_s cn63xxp1; + struct cvmx_pip_stat4_prtx_s cn66xx; + struct cvmx_pip_stat4_prtx_s cnf71xx; +}; + +union cvmx_pip_stat5_x { + uint64_t u64; + struct cvmx_pip_stat5_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t h256to511:32; + uint64_t h128to255:32; +#else + uint64_t h128to255:32; + uint64_t h256to511:32; +#endif + } s; + struct cvmx_pip_stat5_x_s cn68xx; + struct cvmx_pip_stat5_x_s cn68xxp1; }; union cvmx_pip_stat5_prtx { uint64_t u64; struct cvmx_pip_stat5_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t h256to511:32; uint64_t h128to255:32; +#else + uint64_t h128to255:32; + uint64_t h256to511:32; +#endif } s; struct cvmx_pip_stat5_prtx_s cn30xx; struct cvmx_pip_stat5_prtx_s cn31xx; @@ -1032,13 +2707,38 @@ union cvmx_pip_stat5_prtx { struct cvmx_pip_stat5_prtx_s cn56xxp1; struct cvmx_pip_stat5_prtx_s cn58xx; struct cvmx_pip_stat5_prtx_s cn58xxp1; + struct cvmx_pip_stat5_prtx_s cn61xx; + struct cvmx_pip_stat5_prtx_s cn63xx; + struct cvmx_pip_stat5_prtx_s cn63xxp1; + struct cvmx_pip_stat5_prtx_s cn66xx; + struct cvmx_pip_stat5_prtx_s cnf71xx; +}; + +union cvmx_pip_stat6_x { + uint64_t u64; + struct cvmx_pip_stat6_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t h1024to1518:32; + uint64_t h512to1023:32; +#else + uint64_t h512to1023:32; + uint64_t h1024to1518:32; +#endif + } s; + struct cvmx_pip_stat6_x_s cn68xx; + struct cvmx_pip_stat6_x_s cn68xxp1; }; union cvmx_pip_stat6_prtx { uint64_t u64; struct cvmx_pip_stat6_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t h1024to1518:32; uint64_t h512to1023:32; +#else + uint64_t h512to1023:32; + uint64_t h1024to1518:32; +#endif } s; struct cvmx_pip_stat6_prtx_s cn30xx; struct cvmx_pip_stat6_prtx_s cn31xx; @@ -1051,13 +2751,38 @@ union cvmx_pip_stat6_prtx { struct cvmx_pip_stat6_prtx_s cn56xxp1; struct cvmx_pip_stat6_prtx_s cn58xx; struct cvmx_pip_stat6_prtx_s cn58xxp1; + struct cvmx_pip_stat6_prtx_s cn61xx; + struct cvmx_pip_stat6_prtx_s cn63xx; + struct cvmx_pip_stat6_prtx_s cn63xxp1; + struct cvmx_pip_stat6_prtx_s cn66xx; + struct cvmx_pip_stat6_prtx_s cnf71xx; +}; + +union cvmx_pip_stat7_x { + uint64_t u64; + struct cvmx_pip_stat7_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t fcs:32; + uint64_t h1519:32; +#else + uint64_t h1519:32; + uint64_t fcs:32; +#endif + } s; + struct cvmx_pip_stat7_x_s cn68xx; + struct cvmx_pip_stat7_x_s cn68xxp1; }; union cvmx_pip_stat7_prtx { uint64_t u64; struct cvmx_pip_stat7_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t fcs:32; uint64_t h1519:32; +#else + uint64_t h1519:32; + uint64_t fcs:32; +#endif } s; struct cvmx_pip_stat7_prtx_s cn30xx; struct cvmx_pip_stat7_prtx_s cn31xx; @@ -1070,13 +2795,38 @@ union cvmx_pip_stat7_prtx { struct cvmx_pip_stat7_prtx_s cn56xxp1; struct cvmx_pip_stat7_prtx_s cn58xx; struct cvmx_pip_stat7_prtx_s cn58xxp1; + struct cvmx_pip_stat7_prtx_s cn61xx; + struct cvmx_pip_stat7_prtx_s cn63xx; + struct cvmx_pip_stat7_prtx_s cn63xxp1; + struct cvmx_pip_stat7_prtx_s cn66xx; + struct cvmx_pip_stat7_prtx_s cnf71xx; +}; + +union cvmx_pip_stat8_x { + uint64_t u64; + struct cvmx_pip_stat8_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t frag:32; + uint64_t undersz:32; +#else + uint64_t undersz:32; + uint64_t frag:32; +#endif + } s; + struct cvmx_pip_stat8_x_s cn68xx; + struct cvmx_pip_stat8_x_s cn68xxp1; }; union cvmx_pip_stat8_prtx { uint64_t u64; struct cvmx_pip_stat8_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t frag:32; uint64_t undersz:32; +#else + uint64_t undersz:32; + uint64_t frag:32; +#endif } s; struct cvmx_pip_stat8_prtx_s cn30xx; struct cvmx_pip_stat8_prtx_s cn31xx; @@ -1089,13 +2839,38 @@ union cvmx_pip_stat8_prtx { struct cvmx_pip_stat8_prtx_s cn56xxp1; struct cvmx_pip_stat8_prtx_s cn58xx; struct cvmx_pip_stat8_prtx_s cn58xxp1; + struct cvmx_pip_stat8_prtx_s cn61xx; + struct cvmx_pip_stat8_prtx_s cn63xx; + struct cvmx_pip_stat8_prtx_s cn63xxp1; + struct cvmx_pip_stat8_prtx_s cn66xx; + struct cvmx_pip_stat8_prtx_s cnf71xx; +}; + +union cvmx_pip_stat9_x { + uint64_t u64; + struct cvmx_pip_stat9_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t jabber:32; + uint64_t oversz:32; +#else + uint64_t oversz:32; + uint64_t jabber:32; +#endif + } s; + struct cvmx_pip_stat9_x_s cn68xx; + struct cvmx_pip_stat9_x_s cn68xxp1; }; union cvmx_pip_stat9_prtx { uint64_t u64; struct cvmx_pip_stat9_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t jabber:32; uint64_t oversz:32; +#else + uint64_t oversz:32; + uint64_t jabber:32; +#endif } s; struct cvmx_pip_stat9_prtx_s cn30xx; struct cvmx_pip_stat9_prtx_s cn31xx; @@ -1108,32 +2883,66 @@ union cvmx_pip_stat9_prtx { struct cvmx_pip_stat9_prtx_s cn56xxp1; struct cvmx_pip_stat9_prtx_s cn58xx; struct cvmx_pip_stat9_prtx_s cn58xxp1; + struct cvmx_pip_stat9_prtx_s cn61xx; + struct cvmx_pip_stat9_prtx_s cn63xx; + struct cvmx_pip_stat9_prtx_s cn63xxp1; + struct cvmx_pip_stat9_prtx_s cn66xx; + struct cvmx_pip_stat9_prtx_s cnf71xx; }; union cvmx_pip_stat_ctl { uint64_t u64; struct cvmx_pip_stat_ctl_s { - uint64_t reserved_1_63:63; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t mode:1; + uint64_t reserved_1_7:7; + uint64_t rdclr:1; +#else uint64_t rdclr:1; + uint64_t reserved_1_7:7; + uint64_t mode:1; + uint64_t reserved_9_63:55; +#endif } s; - struct cvmx_pip_stat_ctl_s cn30xx; - struct cvmx_pip_stat_ctl_s cn31xx; - struct cvmx_pip_stat_ctl_s cn38xx; - struct cvmx_pip_stat_ctl_s cn38xxp2; - struct cvmx_pip_stat_ctl_s cn50xx; - struct cvmx_pip_stat_ctl_s cn52xx; - struct cvmx_pip_stat_ctl_s cn52xxp1; - struct cvmx_pip_stat_ctl_s cn56xx; - struct cvmx_pip_stat_ctl_s cn56xxp1; - struct cvmx_pip_stat_ctl_s cn58xx; - struct cvmx_pip_stat_ctl_s cn58xxp1; + struct cvmx_pip_stat_ctl_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t rdclr:1; +#else + uint64_t rdclr:1; + uint64_t reserved_1_63:63; +#endif + } cn30xx; + struct cvmx_pip_stat_ctl_cn30xx cn31xx; + struct cvmx_pip_stat_ctl_cn30xx cn38xx; + struct cvmx_pip_stat_ctl_cn30xx cn38xxp2; + struct cvmx_pip_stat_ctl_cn30xx cn50xx; + struct cvmx_pip_stat_ctl_cn30xx cn52xx; + struct cvmx_pip_stat_ctl_cn30xx cn52xxp1; + struct cvmx_pip_stat_ctl_cn30xx cn56xx; + struct cvmx_pip_stat_ctl_cn30xx cn56xxp1; + struct cvmx_pip_stat_ctl_cn30xx cn58xx; + struct cvmx_pip_stat_ctl_cn30xx cn58xxp1; + struct cvmx_pip_stat_ctl_cn30xx cn61xx; + struct cvmx_pip_stat_ctl_cn30xx cn63xx; + struct cvmx_pip_stat_ctl_cn30xx cn63xxp1; + struct cvmx_pip_stat_ctl_cn30xx cn66xx; + struct cvmx_pip_stat_ctl_s cn68xx; + struct cvmx_pip_stat_ctl_s cn68xxp1; + struct cvmx_pip_stat_ctl_cn30xx cnf71xx; }; union cvmx_pip_stat_inb_errsx { uint64_t u64; struct cvmx_pip_stat_inb_errsx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t errs:16; +#else + uint64_t errs:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pip_stat_inb_errsx_s cn30xx; struct cvmx_pip_stat_inb_errsx_s cn31xx; @@ -1146,13 +2955,38 @@ union cvmx_pip_stat_inb_errsx { struct cvmx_pip_stat_inb_errsx_s cn56xxp1; struct cvmx_pip_stat_inb_errsx_s cn58xx; struct cvmx_pip_stat_inb_errsx_s cn58xxp1; + struct cvmx_pip_stat_inb_errsx_s cn61xx; + struct cvmx_pip_stat_inb_errsx_s cn63xx; + struct cvmx_pip_stat_inb_errsx_s cn63xxp1; + struct cvmx_pip_stat_inb_errsx_s cn66xx; + struct cvmx_pip_stat_inb_errsx_s cnf71xx; +}; + +union cvmx_pip_stat_inb_errs_pkndx { + uint64_t u64; + struct cvmx_pip_stat_inb_errs_pkndx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t errs:16; +#else + uint64_t errs:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_pip_stat_inb_errs_pkndx_s cn68xx; + struct cvmx_pip_stat_inb_errs_pkndx_s cn68xxp1; }; union cvmx_pip_stat_inb_octsx { uint64_t u64; struct cvmx_pip_stat_inb_octsx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t octs:48; +#else + uint64_t octs:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_pip_stat_inb_octsx_s cn30xx; struct cvmx_pip_stat_inb_octsx_s cn31xx; @@ -1165,13 +2999,38 @@ union cvmx_pip_stat_inb_octsx { struct cvmx_pip_stat_inb_octsx_s cn56xxp1; struct cvmx_pip_stat_inb_octsx_s cn58xx; struct cvmx_pip_stat_inb_octsx_s cn58xxp1; + struct cvmx_pip_stat_inb_octsx_s cn61xx; + struct cvmx_pip_stat_inb_octsx_s cn63xx; + struct cvmx_pip_stat_inb_octsx_s cn63xxp1; + struct cvmx_pip_stat_inb_octsx_s cn66xx; + struct cvmx_pip_stat_inb_octsx_s cnf71xx; +}; + +union cvmx_pip_stat_inb_octs_pkndx { + uint64_t u64; + struct cvmx_pip_stat_inb_octs_pkndx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t octs:48; +#else + uint64_t octs:48; + uint64_t reserved_48_63:16; +#endif + } s; + struct cvmx_pip_stat_inb_octs_pkndx_s cn68xx; + struct cvmx_pip_stat_inb_octs_pkndx_s cn68xxp1; }; union cvmx_pip_stat_inb_pktsx { uint64_t u64; struct cvmx_pip_stat_inb_pktsx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pkts:32; +#else + uint64_t pkts:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pip_stat_inb_pktsx_s cn30xx; struct cvmx_pip_stat_inb_pktsx_s cn31xx; @@ -1184,13 +3043,51 @@ union cvmx_pip_stat_inb_pktsx { struct cvmx_pip_stat_inb_pktsx_s cn56xxp1; struct cvmx_pip_stat_inb_pktsx_s cn58xx; struct cvmx_pip_stat_inb_pktsx_s cn58xxp1; + struct cvmx_pip_stat_inb_pktsx_s cn61xx; + struct cvmx_pip_stat_inb_pktsx_s cn63xx; + struct cvmx_pip_stat_inb_pktsx_s cn63xxp1; + struct cvmx_pip_stat_inb_pktsx_s cn66xx; + struct cvmx_pip_stat_inb_pktsx_s cnf71xx; +}; + +union cvmx_pip_stat_inb_pkts_pkndx { + uint64_t u64; + struct cvmx_pip_stat_inb_pkts_pkndx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t pkts:32; +#else + uint64_t pkts:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xx; + struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xxp1; +}; + +union cvmx_pip_sub_pkind_fcsx { + uint64_t u64; + struct cvmx_pip_sub_pkind_fcsx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t port_bit:64; +#else + uint64_t port_bit:64; +#endif + } s; + struct cvmx_pip_sub_pkind_fcsx_s cn68xx; + struct cvmx_pip_sub_pkind_fcsx_s cn68xxp1; }; union cvmx_pip_tag_incx { uint64_t u64; struct cvmx_pip_tag_incx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t en:8; +#else + uint64_t en:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_pip_tag_incx_s cn30xx; struct cvmx_pip_tag_incx_s cn31xx; @@ -1203,13 +3100,25 @@ union cvmx_pip_tag_incx { struct cvmx_pip_tag_incx_s cn56xxp1; struct cvmx_pip_tag_incx_s cn58xx; struct cvmx_pip_tag_incx_s cn58xxp1; + struct cvmx_pip_tag_incx_s cn61xx; + struct cvmx_pip_tag_incx_s cn63xx; + struct cvmx_pip_tag_incx_s cn63xxp1; + struct cvmx_pip_tag_incx_s cn66xx; + struct cvmx_pip_tag_incx_s cn68xx; + struct cvmx_pip_tag_incx_s cn68xxp1; + struct cvmx_pip_tag_incx_s cnf71xx; }; union cvmx_pip_tag_mask { uint64_t u64; struct cvmx_pip_tag_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mask:16; +#else + uint64_t mask:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pip_tag_mask_s cn30xx; struct cvmx_pip_tag_mask_s cn31xx; @@ -1222,14 +3131,27 @@ union cvmx_pip_tag_mask { struct cvmx_pip_tag_mask_s cn56xxp1; struct cvmx_pip_tag_mask_s cn58xx; struct cvmx_pip_tag_mask_s cn58xxp1; + struct cvmx_pip_tag_mask_s cn61xx; + struct cvmx_pip_tag_mask_s cn63xx; + struct cvmx_pip_tag_mask_s cn63xxp1; + struct cvmx_pip_tag_mask_s cn66xx; + struct cvmx_pip_tag_mask_s cn68xx; + struct cvmx_pip_tag_mask_s cn68xxp1; + struct cvmx_pip_tag_mask_s cnf71xx; }; union cvmx_pip_tag_secret { uint64_t u64; struct cvmx_pip_tag_secret_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t dst:16; uint64_t src:16; +#else + uint64_t src:16; + uint64_t dst:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pip_tag_secret_s cn30xx; struct cvmx_pip_tag_secret_s cn31xx; @@ -1242,14 +3164,27 @@ union cvmx_pip_tag_secret { struct cvmx_pip_tag_secret_s cn56xxp1; struct cvmx_pip_tag_secret_s cn58xx; struct cvmx_pip_tag_secret_s cn58xxp1; + struct cvmx_pip_tag_secret_s cn61xx; + struct cvmx_pip_tag_secret_s cn63xx; + struct cvmx_pip_tag_secret_s cn63xxp1; + struct cvmx_pip_tag_secret_s cn66xx; + struct cvmx_pip_tag_secret_s cn68xx; + struct cvmx_pip_tag_secret_s cn68xxp1; + struct cvmx_pip_tag_secret_s cnf71xx; }; union cvmx_pip_todo_entry { uint64_t u64; struct cvmx_pip_todo_entry_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t val:1; uint64_t reserved_62_62:1; uint64_t entry:62; +#else + uint64_t entry:62; + uint64_t reserved_62_62:1; + uint64_t val:1; +#endif } s; struct cvmx_pip_todo_entry_s cn30xx; struct cvmx_pip_todo_entry_s cn31xx; @@ -1262,6 +3197,226 @@ union cvmx_pip_todo_entry { struct cvmx_pip_todo_entry_s cn56xxp1; struct cvmx_pip_todo_entry_s cn58xx; struct cvmx_pip_todo_entry_s cn58xxp1; + struct cvmx_pip_todo_entry_s cn61xx; + struct cvmx_pip_todo_entry_s cn63xx; + struct cvmx_pip_todo_entry_s cn63xxp1; + struct cvmx_pip_todo_entry_s cn66xx; + struct cvmx_pip_todo_entry_s cn68xx; + struct cvmx_pip_todo_entry_s cn68xxp1; + struct cvmx_pip_todo_entry_s cnf71xx; +}; + +union cvmx_pip_vlan_etypesx { + uint64_t u64; + struct cvmx_pip_vlan_etypesx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t type3:16; + uint64_t type2:16; + uint64_t type1:16; + uint64_t type0:16; +#else + uint64_t type0:16; + uint64_t type1:16; + uint64_t type2:16; + uint64_t type3:16; +#endif + } s; + struct cvmx_pip_vlan_etypesx_s cn61xx; + struct cvmx_pip_vlan_etypesx_s cn66xx; + struct cvmx_pip_vlan_etypesx_s cn68xx; + struct cvmx_pip_vlan_etypesx_s cnf71xx; +}; + +union cvmx_pip_xstat0_prtx { + uint64_t u64; + struct cvmx_pip_xstat0_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t drp_pkts:32; + uint64_t drp_octs:32; +#else + uint64_t drp_octs:32; + uint64_t drp_pkts:32; +#endif + } s; + struct cvmx_pip_xstat0_prtx_s cn63xx; + struct cvmx_pip_xstat0_prtx_s cn63xxp1; + struct cvmx_pip_xstat0_prtx_s cn66xx; +}; + +union cvmx_pip_xstat10_prtx { + uint64_t u64; + struct cvmx_pip_xstat10_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcast:32; + uint64_t mcast:32; +#else + uint64_t mcast:32; + uint64_t bcast:32; +#endif + } s; + struct cvmx_pip_xstat10_prtx_s cn63xx; + struct cvmx_pip_xstat10_prtx_s cn63xxp1; + struct cvmx_pip_xstat10_prtx_s cn66xx; +}; + +union cvmx_pip_xstat11_prtx { + uint64_t u64; + struct cvmx_pip_xstat11_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcast:32; + uint64_t mcast:32; +#else + uint64_t mcast:32; + uint64_t bcast:32; +#endif + } s; + struct cvmx_pip_xstat11_prtx_s cn63xx; + struct cvmx_pip_xstat11_prtx_s cn63xxp1; + struct cvmx_pip_xstat11_prtx_s cn66xx; +}; + +union cvmx_pip_xstat1_prtx { + uint64_t u64; + struct cvmx_pip_xstat1_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t octs:48; +#else + uint64_t octs:48; + uint64_t reserved_48_63:16; +#endif + } s; + struct cvmx_pip_xstat1_prtx_s cn63xx; + struct cvmx_pip_xstat1_prtx_s cn63xxp1; + struct cvmx_pip_xstat1_prtx_s cn66xx; +}; + +union cvmx_pip_xstat2_prtx { + uint64_t u64; + struct cvmx_pip_xstat2_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t pkts:32; + uint64_t raw:32; +#else + uint64_t raw:32; + uint64_t pkts:32; +#endif + } s; + struct cvmx_pip_xstat2_prtx_s cn63xx; + struct cvmx_pip_xstat2_prtx_s cn63xxp1; + struct cvmx_pip_xstat2_prtx_s cn66xx; +}; + +union cvmx_pip_xstat3_prtx { + uint64_t u64; + struct cvmx_pip_xstat3_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcst:32; + uint64_t mcst:32; +#else + uint64_t mcst:32; + uint64_t bcst:32; +#endif + } s; + struct cvmx_pip_xstat3_prtx_s cn63xx; + struct cvmx_pip_xstat3_prtx_s cn63xxp1; + struct cvmx_pip_xstat3_prtx_s cn66xx; +}; + +union cvmx_pip_xstat4_prtx { + uint64_t u64; + struct cvmx_pip_xstat4_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t h65to127:32; + uint64_t h64:32; +#else + uint64_t h64:32; + uint64_t h65to127:32; +#endif + } s; + struct cvmx_pip_xstat4_prtx_s cn63xx; + struct cvmx_pip_xstat4_prtx_s cn63xxp1; + struct cvmx_pip_xstat4_prtx_s cn66xx; +}; + +union cvmx_pip_xstat5_prtx { + uint64_t u64; + struct cvmx_pip_xstat5_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t h256to511:32; + uint64_t h128to255:32; +#else + uint64_t h128to255:32; + uint64_t h256to511:32; +#endif + } s; + struct cvmx_pip_xstat5_prtx_s cn63xx; + struct cvmx_pip_xstat5_prtx_s cn63xxp1; + struct cvmx_pip_xstat5_prtx_s cn66xx; +}; + +union cvmx_pip_xstat6_prtx { + uint64_t u64; + struct cvmx_pip_xstat6_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t h1024to1518:32; + uint64_t h512to1023:32; +#else + uint64_t h512to1023:32; + uint64_t h1024to1518:32; +#endif + } s; + struct cvmx_pip_xstat6_prtx_s cn63xx; + struct cvmx_pip_xstat6_prtx_s cn63xxp1; + struct cvmx_pip_xstat6_prtx_s cn66xx; +}; + +union cvmx_pip_xstat7_prtx { + uint64_t u64; + struct cvmx_pip_xstat7_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t fcs:32; + uint64_t h1519:32; +#else + uint64_t h1519:32; + uint64_t fcs:32; +#endif + } s; + struct cvmx_pip_xstat7_prtx_s cn63xx; + struct cvmx_pip_xstat7_prtx_s cn63xxp1; + struct cvmx_pip_xstat7_prtx_s cn66xx; +}; + +union cvmx_pip_xstat8_prtx { + uint64_t u64; + struct cvmx_pip_xstat8_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t frag:32; + uint64_t undersz:32; +#else + uint64_t undersz:32; + uint64_t frag:32; +#endif + } s; + struct cvmx_pip_xstat8_prtx_s cn63xx; + struct cvmx_pip_xstat8_prtx_s cn63xxp1; + struct cvmx_pip_xstat8_prtx_s cn66xx; +}; + +union cvmx_pip_xstat9_prtx { + uint64_t u64; + struct cvmx_pip_xstat9_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t jabber:32; + uint64_t oversz:32; +#else + uint64_t oversz:32; + uint64_t jabber:32; +#endif + } s; + struct cvmx_pip_xstat9_prtx_s cn63xx; + struct cvmx_pip_xstat9_prtx_s cn63xxp1; + struct cvmx_pip_xstat9_prtx_s cn66xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-pko-defs.h b/arch/mips/include/asm/octeon/cvmx-pko-defs.h index 50e779cf1ad8..87c3b970cad4 100644 --- a/arch/mips/include/asm/octeon/cvmx-pko-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pko-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,94 +28,74 @@ #ifndef __CVMX_PKO_DEFS_H__ #define __CVMX_PKO_DEFS_H__ -#define CVMX_PKO_MEM_COUNT0 \ - CVMX_ADD_IO_SEG(0x0001180050001080ull) -#define CVMX_PKO_MEM_COUNT1 \ - CVMX_ADD_IO_SEG(0x0001180050001088ull) -#define CVMX_PKO_MEM_DEBUG0 \ - CVMX_ADD_IO_SEG(0x0001180050001100ull) -#define CVMX_PKO_MEM_DEBUG1 \ - CVMX_ADD_IO_SEG(0x0001180050001108ull) -#define CVMX_PKO_MEM_DEBUG10 \ - CVMX_ADD_IO_SEG(0x0001180050001150ull) -#define CVMX_PKO_MEM_DEBUG11 \ - CVMX_ADD_IO_SEG(0x0001180050001158ull) -#define CVMX_PKO_MEM_DEBUG12 \ - CVMX_ADD_IO_SEG(0x0001180050001160ull) -#define CVMX_PKO_MEM_DEBUG13 \ - CVMX_ADD_IO_SEG(0x0001180050001168ull) -#define CVMX_PKO_MEM_DEBUG14 \ - CVMX_ADD_IO_SEG(0x0001180050001170ull) -#define CVMX_PKO_MEM_DEBUG2 \ - CVMX_ADD_IO_SEG(0x0001180050001110ull) -#define CVMX_PKO_MEM_DEBUG3 \ - CVMX_ADD_IO_SEG(0x0001180050001118ull) -#define CVMX_PKO_MEM_DEBUG4 \ - CVMX_ADD_IO_SEG(0x0001180050001120ull) -#define CVMX_PKO_MEM_DEBUG5 \ - CVMX_ADD_IO_SEG(0x0001180050001128ull) -#define CVMX_PKO_MEM_DEBUG6 \ - CVMX_ADD_IO_SEG(0x0001180050001130ull) -#define CVMX_PKO_MEM_DEBUG7 \ - CVMX_ADD_IO_SEG(0x0001180050001138ull) -#define CVMX_PKO_MEM_DEBUG8 \ - CVMX_ADD_IO_SEG(0x0001180050001140ull) -#define CVMX_PKO_MEM_DEBUG9 \ - CVMX_ADD_IO_SEG(0x0001180050001148ull) -#define CVMX_PKO_MEM_PORT_PTRS \ - CVMX_ADD_IO_SEG(0x0001180050001010ull) -#define CVMX_PKO_MEM_PORT_QOS \ - CVMX_ADD_IO_SEG(0x0001180050001018ull) -#define CVMX_PKO_MEM_PORT_RATE0 \ - CVMX_ADD_IO_SEG(0x0001180050001020ull) -#define CVMX_PKO_MEM_PORT_RATE1 \ - CVMX_ADD_IO_SEG(0x0001180050001028ull) -#define CVMX_PKO_MEM_QUEUE_PTRS \ - CVMX_ADD_IO_SEG(0x0001180050001000ull) -#define CVMX_PKO_MEM_QUEUE_QOS \ - CVMX_ADD_IO_SEG(0x0001180050001008ull) -#define CVMX_PKO_REG_BIST_RESULT \ - CVMX_ADD_IO_SEG(0x0001180050000080ull) -#define CVMX_PKO_REG_CMD_BUF \ - CVMX_ADD_IO_SEG(0x0001180050000010ull) -#define CVMX_PKO_REG_CRC_CTLX(offset) \ - CVMX_ADD_IO_SEG(0x0001180050000028ull + (((offset) & 1) * 8)) -#define CVMX_PKO_REG_CRC_ENABLE \ - CVMX_ADD_IO_SEG(0x0001180050000020ull) -#define CVMX_PKO_REG_CRC_IVX(offset) \ - CVMX_ADD_IO_SEG(0x0001180050000038ull + (((offset) & 1) * 8)) -#define CVMX_PKO_REG_DEBUG0 \ - CVMX_ADD_IO_SEG(0x0001180050000098ull) -#define CVMX_PKO_REG_DEBUG1 \ - CVMX_ADD_IO_SEG(0x00011800500000A0ull) -#define CVMX_PKO_REG_DEBUG2 \ - CVMX_ADD_IO_SEG(0x00011800500000A8ull) -#define CVMX_PKO_REG_DEBUG3 \ - CVMX_ADD_IO_SEG(0x00011800500000B0ull) -#define CVMX_PKO_REG_ENGINE_INFLIGHT \ - CVMX_ADD_IO_SEG(0x0001180050000050ull) -#define CVMX_PKO_REG_ENGINE_THRESH \ - CVMX_ADD_IO_SEG(0x0001180050000058ull) -#define CVMX_PKO_REG_ERROR \ - CVMX_ADD_IO_SEG(0x0001180050000088ull) -#define CVMX_PKO_REG_FLAGS \ - CVMX_ADD_IO_SEG(0x0001180050000000ull) -#define CVMX_PKO_REG_GMX_PORT_MODE \ - CVMX_ADD_IO_SEG(0x0001180050000018ull) -#define CVMX_PKO_REG_INT_MASK \ - CVMX_ADD_IO_SEG(0x0001180050000090ull) -#define CVMX_PKO_REG_QUEUE_MODE \ - CVMX_ADD_IO_SEG(0x0001180050000048ull) -#define CVMX_PKO_REG_QUEUE_PTRS1 \ - CVMX_ADD_IO_SEG(0x0001180050000100ull) -#define CVMX_PKO_REG_READ_IDX \ - CVMX_ADD_IO_SEG(0x0001180050000008ull) +#define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull)) +#define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull)) +#define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull)) +#define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull)) +#define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull)) +#define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull)) +#define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull)) +#define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull)) +#define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull)) +#define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull)) +#define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull)) +#define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull)) +#define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull)) +#define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull)) +#define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull)) +#define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull)) +#define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull)) +#define CVMX_PKO_MEM_IPORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001030ull)) +#define CVMX_PKO_MEM_IPORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001038ull)) +#define CVMX_PKO_MEM_IQUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001040ull)) +#define CVMX_PKO_MEM_IQUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001048ull)) +#define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull)) +#define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull)) +#define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull)) +#define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull)) +#define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull)) +#define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull)) +#define CVMX_PKO_MEM_THROTTLE_INT (CVMX_ADD_IO_SEG(0x0001180050001058ull)) +#define CVMX_PKO_MEM_THROTTLE_PIPE (CVMX_ADD_IO_SEG(0x0001180050001050ull)) +#define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull)) +#define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull)) +#define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8) +#define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull)) +#define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8) +#define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull)) +#define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull)) +#define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull)) +#define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull)) +#define CVMX_PKO_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x00011800500000B8ull)) +#define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull)) +#define CVMX_PKO_REG_ENGINE_INFLIGHT1 (CVMX_ADD_IO_SEG(0x0001180050000318ull)) +#define CVMX_PKO_REG_ENGINE_STORAGEX(offset) (CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8) +#define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull)) +#define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull)) +#define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull)) +#define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull)) +#define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull)) +#define CVMX_PKO_REG_LOOPBACK_BPID (CVMX_ADD_IO_SEG(0x0001180050000118ull)) +#define CVMX_PKO_REG_LOOPBACK_PKIND (CVMX_ADD_IO_SEG(0x0001180050000068ull)) +#define CVMX_PKO_REG_MIN_PKT (CVMX_ADD_IO_SEG(0x0001180050000070ull)) +#define CVMX_PKO_REG_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000110ull)) +#define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull)) +#define CVMX_PKO_REG_QUEUE_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000108ull)) +#define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull)) +#define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull)) +#define CVMX_PKO_REG_THROTTLE (CVMX_ADD_IO_SEG(0x0001180050000078ull)) +#define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull)) union cvmx_pko_mem_count0 { uint64_t u64; struct cvmx_pko_mem_count0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t count:32; +#else + uint64_t count:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pko_mem_count0_s cn30xx; struct cvmx_pko_mem_count0_s cn31xx; @@ -128,13 +108,25 @@ union cvmx_pko_mem_count0 { struct cvmx_pko_mem_count0_s cn56xxp1; struct cvmx_pko_mem_count0_s cn58xx; struct cvmx_pko_mem_count0_s cn58xxp1; + struct cvmx_pko_mem_count0_s cn61xx; + struct cvmx_pko_mem_count0_s cn63xx; + struct cvmx_pko_mem_count0_s cn63xxp1; + struct cvmx_pko_mem_count0_s cn66xx; + struct cvmx_pko_mem_count0_s cn68xx; + struct cvmx_pko_mem_count0_s cn68xxp1; + struct cvmx_pko_mem_count0_s cnf71xx; }; union cvmx_pko_mem_count1 { uint64_t u64; struct cvmx_pko_mem_count1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t count:48; +#else + uint64_t count:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_pko_mem_count1_s cn30xx; struct cvmx_pko_mem_count1_s cn31xx; @@ -147,15 +139,29 @@ union cvmx_pko_mem_count1 { struct cvmx_pko_mem_count1_s cn56xxp1; struct cvmx_pko_mem_count1_s cn58xx; struct cvmx_pko_mem_count1_s cn58xxp1; + struct cvmx_pko_mem_count1_s cn61xx; + struct cvmx_pko_mem_count1_s cn63xx; + struct cvmx_pko_mem_count1_s cn63xxp1; + struct cvmx_pko_mem_count1_s cn66xx; + struct cvmx_pko_mem_count1_s cn68xx; + struct cvmx_pko_mem_count1_s cn68xxp1; + struct cvmx_pko_mem_count1_s cnf71xx; }; union cvmx_pko_mem_debug0 { uint64_t u64; struct cvmx_pko_mem_debug0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t fau:28; uint64_t cmd:14; uint64_t segs:6; uint64_t size:16; +#else + uint64_t size:16; + uint64_t segs:6; + uint64_t cmd:14; + uint64_t fau:28; +#endif } s; struct cvmx_pko_mem_debug0_s cn30xx; struct cvmx_pko_mem_debug0_s cn31xx; @@ -168,16 +174,31 @@ union cvmx_pko_mem_debug0 { struct cvmx_pko_mem_debug0_s cn56xxp1; struct cvmx_pko_mem_debug0_s cn58xx; struct cvmx_pko_mem_debug0_s cn58xxp1; + struct cvmx_pko_mem_debug0_s cn61xx; + struct cvmx_pko_mem_debug0_s cn63xx; + struct cvmx_pko_mem_debug0_s cn63xxp1; + struct cvmx_pko_mem_debug0_s cn66xx; + struct cvmx_pko_mem_debug0_s cn68xx; + struct cvmx_pko_mem_debug0_s cn68xxp1; + struct cvmx_pko_mem_debug0_s cnf71xx; }; union cvmx_pko_mem_debug1 { uint64_t u64; struct cvmx_pko_mem_debug1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t ptr:40; +#else + uint64_t ptr:40; + uint64_t size:16; + uint64_t pool:3; + uint64_t back:4; + uint64_t i:1; +#endif } s; struct cvmx_pko_mem_debug1_s cn30xx; struct cvmx_pko_mem_debug1_s cn31xx; @@ -190,27 +211,52 @@ union cvmx_pko_mem_debug1 { struct cvmx_pko_mem_debug1_s cn56xxp1; struct cvmx_pko_mem_debug1_s cn58xx; struct cvmx_pko_mem_debug1_s cn58xxp1; + struct cvmx_pko_mem_debug1_s cn61xx; + struct cvmx_pko_mem_debug1_s cn63xx; + struct cvmx_pko_mem_debug1_s cn63xxp1; + struct cvmx_pko_mem_debug1_s cn66xx; + struct cvmx_pko_mem_debug1_s cn68xx; + struct cvmx_pko_mem_debug1_s cn68xxp1; + struct cvmx_pko_mem_debug1_s cnf71xx; }; union cvmx_pko_mem_debug10 { uint64_t u64; struct cvmx_pko_mem_debug10_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug10_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t fau:28; uint64_t cmd:14; uint64_t segs:6; uint64_t size:16; +#else + uint64_t size:16; + uint64_t segs:6; + uint64_t cmd:14; + uint64_t fau:28; +#endif } cn30xx; struct cvmx_pko_mem_debug10_cn30xx cn31xx; struct cvmx_pko_mem_debug10_cn30xx cn38xx; struct cvmx_pko_mem_debug10_cn30xx cn38xxp2; struct cvmx_pko_mem_debug10_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t ptrs1:17; uint64_t reserved_17_31:15; uint64_t ptrs2:17; +#else + uint64_t ptrs2:17; + uint64_t reserved_17_31:15; + uint64_t ptrs1:17; + uint64_t reserved_49_63:15; +#endif } cn50xx; struct cvmx_pko_mem_debug10_cn50xx cn52xx; struct cvmx_pko_mem_debug10_cn50xx cn52xxp1; @@ -218,28 +264,52 @@ union cvmx_pko_mem_debug10 { struct cvmx_pko_mem_debug10_cn50xx cn56xxp1; struct cvmx_pko_mem_debug10_cn50xx cn58xx; struct cvmx_pko_mem_debug10_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug10_cn50xx cn61xx; + struct cvmx_pko_mem_debug10_cn50xx cn63xx; + struct cvmx_pko_mem_debug10_cn50xx cn63xxp1; + struct cvmx_pko_mem_debug10_cn50xx cn66xx; + struct cvmx_pko_mem_debug10_cn50xx cn68xx; + struct cvmx_pko_mem_debug10_cn50xx cn68xxp1; + struct cvmx_pko_mem_debug10_cn50xx cnf71xx; }; union cvmx_pko_mem_debug11 { uint64_t u64; struct cvmx_pko_mem_debug11_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t reserved_0_39:40; +#else + uint64_t reserved_0_39:40; + uint64_t size:16; + uint64_t pool:3; + uint64_t back:4; + uint64_t i:1; +#endif } s; struct cvmx_pko_mem_debug11_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t ptr:40; +#else + uint64_t ptr:40; + uint64_t size:16; + uint64_t pool:3; + uint64_t back:4; + uint64_t i:1; +#endif } cn30xx; struct cvmx_pko_mem_debug11_cn30xx cn31xx; struct cvmx_pko_mem_debug11_cn30xx cn38xx; struct cvmx_pko_mem_debug11_cn30xx cn38xxp2; struct cvmx_pko_mem_debug11_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t maj:1; uint64_t uid:3; @@ -248,6 +318,16 @@ union cvmx_pko_mem_debug11 { uint64_t chk:1; uint64_t cnt:13; uint64_t mod:3; +#else + uint64_t mod:3; + uint64_t cnt:13; + uint64_t chk:1; + uint64_t len:1; + uint64_t sop:1; + uint64_t uid:3; + uint64_t maj:1; + uint64_t reserved_23_63:41; +#endif } cn50xx; struct cvmx_pko_mem_debug11_cn50xx cn52xx; struct cvmx_pko_mem_debug11_cn50xx cn52xxp1; @@ -255,24 +335,46 @@ union cvmx_pko_mem_debug11 { struct cvmx_pko_mem_debug11_cn50xx cn56xxp1; struct cvmx_pko_mem_debug11_cn50xx cn58xx; struct cvmx_pko_mem_debug11_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug11_cn50xx cn61xx; + struct cvmx_pko_mem_debug11_cn50xx cn63xx; + struct cvmx_pko_mem_debug11_cn50xx cn63xxp1; + struct cvmx_pko_mem_debug11_cn50xx cn66xx; + struct cvmx_pko_mem_debug11_cn50xx cn68xx; + struct cvmx_pko_mem_debug11_cn50xx cn68xxp1; + struct cvmx_pko_mem_debug11_cn50xx cnf71xx; }; union cvmx_pko_mem_debug12 { uint64_t u64; struct cvmx_pko_mem_debug12_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug12_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; +#else + uint64_t data:64; +#endif } cn30xx; struct cvmx_pko_mem_debug12_cn30xx cn31xx; struct cvmx_pko_mem_debug12_cn30xx cn38xx; struct cvmx_pko_mem_debug12_cn30xx cn38xxp2; struct cvmx_pko_mem_debug12_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t fau:28; uint64_t cmd:14; uint64_t segs:6; uint64_t size:16; +#else + uint64_t size:16; + uint64_t segs:6; + uint64_t cmd:14; + uint64_t fau:28; +#endif } cn50xx; struct cvmx_pko_mem_debug12_cn50xx cn52xx; struct cvmx_pko_mem_debug12_cn50xx cn52xxp1; @@ -280,31 +382,60 @@ union cvmx_pko_mem_debug12 { struct cvmx_pko_mem_debug12_cn50xx cn56xxp1; struct cvmx_pko_mem_debug12_cn50xx cn58xx; struct cvmx_pko_mem_debug12_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug12_cn50xx cn61xx; + struct cvmx_pko_mem_debug12_cn50xx cn63xx; + struct cvmx_pko_mem_debug12_cn50xx cn63xxp1; + struct cvmx_pko_mem_debug12_cn50xx cn66xx; + struct cvmx_pko_mem_debug12_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t state:64; +#else + uint64_t state:64; +#endif + } cn68xx; + struct cvmx_pko_mem_debug12_cn68xx cn68xxp1; + struct cvmx_pko_mem_debug12_cn50xx cnf71xx; }; union cvmx_pko_mem_debug13 { uint64_t u64; struct cvmx_pko_mem_debug13_s { - uint64_t i:1; - uint64_t back:4; - uint64_t pool:3; - uint64_t reserved_0_55:56; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug13_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_51_63:13; uint64_t widx:17; uint64_t ridx2:17; uint64_t widx2:17; +#else + uint64_t widx2:17; + uint64_t ridx2:17; + uint64_t widx:17; + uint64_t reserved_51_63:13; +#endif } cn30xx; struct cvmx_pko_mem_debug13_cn30xx cn31xx; struct cvmx_pko_mem_debug13_cn30xx cn38xx; struct cvmx_pko_mem_debug13_cn30xx cn38xxp2; struct cvmx_pko_mem_debug13_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t ptr:40; +#else + uint64_t ptr:40; + uint64_t size:16; + uint64_t pool:3; + uint64_t back:4; + uint64_t i:1; +#endif } cn50xx; struct cvmx_pko_mem_debug13_cn50xx cn52xx; struct cvmx_pko_mem_debug13_cn50xx cn52xxp1; @@ -312,36 +443,75 @@ union cvmx_pko_mem_debug13 { struct cvmx_pko_mem_debug13_cn50xx cn56xxp1; struct cvmx_pko_mem_debug13_cn50xx cn58xx; struct cvmx_pko_mem_debug13_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug13_cn50xx cn61xx; + struct cvmx_pko_mem_debug13_cn50xx cn63xx; + struct cvmx_pko_mem_debug13_cn50xx cn63xxp1; + struct cvmx_pko_mem_debug13_cn50xx cn66xx; + struct cvmx_pko_mem_debug13_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t state:64; +#else + uint64_t state:64; +#endif + } cn68xx; + struct cvmx_pko_mem_debug13_cn68xx cn68xxp1; + struct cvmx_pko_mem_debug13_cn50xx cnf71xx; }; union cvmx_pko_mem_debug14 { uint64_t u64; struct cvmx_pko_mem_debug14_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug14_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t ridx:17; +#else + uint64_t ridx:17; + uint64_t reserved_17_63:47; +#endif } cn30xx; struct cvmx_pko_mem_debug14_cn30xx cn31xx; struct cvmx_pko_mem_debug14_cn30xx cn38xx; struct cvmx_pko_mem_debug14_cn30xx cn38xxp2; struct cvmx_pko_mem_debug14_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } cn52xx; struct cvmx_pko_mem_debug14_cn52xx cn52xxp1; struct cvmx_pko_mem_debug14_cn52xx cn56xx; struct cvmx_pko_mem_debug14_cn52xx cn56xxp1; + struct cvmx_pko_mem_debug14_cn52xx cn61xx; + struct cvmx_pko_mem_debug14_cn52xx cn63xx; + struct cvmx_pko_mem_debug14_cn52xx cn63xxp1; + struct cvmx_pko_mem_debug14_cn52xx cn66xx; + struct cvmx_pko_mem_debug14_cn52xx cnf71xx; }; union cvmx_pko_mem_debug2 { uint64_t u64; struct cvmx_pko_mem_debug2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t ptr:40; +#else + uint64_t ptr:40; + uint64_t size:16; + uint64_t pool:3; + uint64_t back:4; + uint64_t i:1; +#endif } s; struct cvmx_pko_mem_debug2_s cn30xx; struct cvmx_pko_mem_debug2_s cn31xx; @@ -354,25 +524,48 @@ union cvmx_pko_mem_debug2 { struct cvmx_pko_mem_debug2_s cn56xxp1; struct cvmx_pko_mem_debug2_s cn58xx; struct cvmx_pko_mem_debug2_s cn58xxp1; + struct cvmx_pko_mem_debug2_s cn61xx; + struct cvmx_pko_mem_debug2_s cn63xx; + struct cvmx_pko_mem_debug2_s cn63xxp1; + struct cvmx_pko_mem_debug2_s cn66xx; + struct cvmx_pko_mem_debug2_s cn68xx; + struct cvmx_pko_mem_debug2_s cn68xxp1; + struct cvmx_pko_mem_debug2_s cnf71xx; }; union cvmx_pko_mem_debug3 { uint64_t u64; struct cvmx_pko_mem_debug3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug3_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t ptr:40; +#else + uint64_t ptr:40; + uint64_t size:16; + uint64_t pool:3; + uint64_t back:4; + uint64_t i:1; +#endif } cn30xx; struct cvmx_pko_mem_debug3_cn30xx cn31xx; struct cvmx_pko_mem_debug3_cn30xx cn38xx; struct cvmx_pko_mem_debug3_cn30xx cn38xxp2; struct cvmx_pko_mem_debug3_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } cn50xx; struct cvmx_pko_mem_debug3_cn50xx cn52xx; struct cvmx_pko_mem_debug3_cn50xx cn52xxp1; @@ -380,20 +573,36 @@ union cvmx_pko_mem_debug3 { struct cvmx_pko_mem_debug3_cn50xx cn56xxp1; struct cvmx_pko_mem_debug3_cn50xx cn58xx; struct cvmx_pko_mem_debug3_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug3_cn50xx cn61xx; + struct cvmx_pko_mem_debug3_cn50xx cn63xx; + struct cvmx_pko_mem_debug3_cn50xx cn63xxp1; + struct cvmx_pko_mem_debug3_cn50xx cn66xx; + struct cvmx_pko_mem_debug3_cn50xx cn68xx; + struct cvmx_pko_mem_debug3_cn50xx cn68xxp1; + struct cvmx_pko_mem_debug3_cn50xx cnf71xx; }; union cvmx_pko_mem_debug4 { uint64_t u64; struct cvmx_pko_mem_debug4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug4_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; +#else + uint64_t data:64; +#endif } cn30xx; struct cvmx_pko_mem_debug4_cn30xx cn31xx; struct cvmx_pko_mem_debug4_cn30xx cn38xx; struct cvmx_pko_mem_debug4_cn30xx cn38xxp2; struct cvmx_pko_mem_debug4_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t cmnd_segs:3; uint64_t cmnd_siz:16; uint64_t cmnd_off:6; @@ -412,8 +621,29 @@ union cvmx_pko_mem_debug4 { uint64_t wait:1; uint64_t minor:2; uint64_t major:3; +#else + uint64_t major:3; + uint64_t minor:2; + uint64_t wait:1; + uint64_t qid_base:8; + uint64_t qid_off:4; + uint64_t qid_off_max:4; + uint64_t qcb_ridx:5; + uint64_t qos:3; + uint64_t static_p:1; + uint64_t active:1; + uint64_t chk_mode:1; + uint64_t chk_once:1; + uint64_t init_dwrite:1; + uint64_t dread_sop:1; + uint64_t uid:3; + uint64_t cmnd_off:6; + uint64_t cmnd_siz:16; + uint64_t cmnd_segs:3; +#endif } cn50xx; struct cvmx_pko_mem_debug4_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t curr_siz:8; uint64_t curr_off:16; uint64_t cmnd_segs:6; @@ -427,20 +657,47 @@ union cvmx_pko_mem_debug4 { uint64_t wait:1; uint64_t minor:2; uint64_t major:3; +#else + uint64_t major:3; + uint64_t minor:2; + uint64_t wait:1; + uint64_t chk_mode:1; + uint64_t chk_once:1; + uint64_t init_dwrite:1; + uint64_t dread_sop:1; + uint64_t uid:2; + uint64_t cmnd_off:6; + uint64_t cmnd_siz:16; + uint64_t cmnd_segs:6; + uint64_t curr_off:16; + uint64_t curr_siz:8; +#endif } cn52xx; struct cvmx_pko_mem_debug4_cn52xx cn52xxp1; struct cvmx_pko_mem_debug4_cn52xx cn56xx; struct cvmx_pko_mem_debug4_cn52xx cn56xxp1; struct cvmx_pko_mem_debug4_cn50xx cn58xx; struct cvmx_pko_mem_debug4_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug4_cn52xx cn61xx; + struct cvmx_pko_mem_debug4_cn52xx cn63xx; + struct cvmx_pko_mem_debug4_cn52xx cn63xxp1; + struct cvmx_pko_mem_debug4_cn52xx cn66xx; + struct cvmx_pko_mem_debug4_cn52xx cn68xx; + struct cvmx_pko_mem_debug4_cn52xx cn68xxp1; + struct cvmx_pko_mem_debug4_cn52xx cnf71xx; }; union cvmx_pko_mem_debug5 { uint64_t u64; struct cvmx_pko_mem_debug5_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug5_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dwri_mod:1; uint64_t dwri_sop:1; uint64_t dwri_len:1; @@ -460,32 +717,109 @@ union cvmx_pko_mem_debug5 { uint64_t wait:1; uint64_t minor:2; uint64_t major:4; +#else + uint64_t major:4; + uint64_t minor:2; + uint64_t wait:1; + uint64_t qid_base:7; + uint64_t qid_off:3; + uint64_t qcb_ridx:5; + uint64_t qos:3; + uint64_t active:1; + uint64_t chk_mode:1; + uint64_t reserved_27_27:1; + uint64_t cbuf_fre:1; + uint64_t xfer_dwr:1; + uint64_t xfer_wor:1; + uint64_t uid:1; + uint64_t cmnd_siz:16; + uint64_t dwri_cnt:13; + uint64_t dwri_len:1; + uint64_t dwri_sop:1; + uint64_t dwri_mod:1; +#endif } cn30xx; struct cvmx_pko_mem_debug5_cn30xx cn31xx; struct cvmx_pko_mem_debug5_cn30xx cn38xx; struct cvmx_pko_mem_debug5_cn30xx cn38xxp2; struct cvmx_pko_mem_debug5_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t curr_ptr:29; uint64_t curr_siz:16; uint64_t curr_off:16; uint64_t cmnd_segs:3; +#else + uint64_t cmnd_segs:3; + uint64_t curr_off:16; + uint64_t curr_siz:16; + uint64_t curr_ptr:29; +#endif } cn50xx; struct cvmx_pko_mem_debug5_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t nxt_inflt:6; uint64_t curr_ptr:40; uint64_t curr_siz:8; +#else + uint64_t curr_siz:8; + uint64_t curr_ptr:40; + uint64_t nxt_inflt:6; + uint64_t reserved_54_63:10; +#endif } cn52xx; struct cvmx_pko_mem_debug5_cn52xx cn52xxp1; struct cvmx_pko_mem_debug5_cn52xx cn56xx; struct cvmx_pko_mem_debug5_cn52xx cn56xxp1; struct cvmx_pko_mem_debug5_cn50xx cn58xx; struct cvmx_pko_mem_debug5_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug5_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t ptp:1; + uint64_t major_3:1; + uint64_t nxt_inflt:6; + uint64_t curr_ptr:40; + uint64_t curr_siz:8; +#else + uint64_t curr_siz:8; + uint64_t curr_ptr:40; + uint64_t nxt_inflt:6; + uint64_t major_3:1; + uint64_t ptp:1; + uint64_t reserved_56_63:8; +#endif + } cn61xx; + struct cvmx_pko_mem_debug5_cn61xx cn63xx; + struct cvmx_pko_mem_debug5_cn61xx cn63xxp1; + struct cvmx_pko_mem_debug5_cn61xx cn66xx; + struct cvmx_pko_mem_debug5_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_57_63:7; + uint64_t uid_2:1; + uint64_t ptp:1; + uint64_t major_3:1; + uint64_t nxt_inflt:6; + uint64_t curr_ptr:40; + uint64_t curr_siz:8; +#else + uint64_t curr_siz:8; + uint64_t curr_ptr:40; + uint64_t nxt_inflt:6; + uint64_t major_3:1; + uint64_t ptp:1; + uint64_t uid_2:1; + uint64_t reserved_57_63:7; +#endif + } cn68xx; + struct cvmx_pko_mem_debug5_cn68xx cn68xxp1; + struct cvmx_pko_mem_debug5_cn61xx cnf71xx; }; union cvmx_pko_mem_debug6 { uint64_t u64; struct cvmx_pko_mem_debug6_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t qid_offres:4; uint64_t qid_offths:4; @@ -498,8 +832,23 @@ union cvmx_pko_mem_debug6 { uint64_t qcb_ridx:5; uint64_t qid_offmax:4; uint64_t reserved_0_11:12; +#else + uint64_t reserved_0_11:12; + uint64_t qid_offmax:4; + uint64_t qcb_ridx:5; + uint64_t qos:3; + uint64_t statc:1; + uint64_t active:1; + uint64_t preempted:1; + uint64_t preemptee:1; + uint64_t preempter:1; + uint64_t qid_offths:4; + uint64_t qid_offres:4; + uint64_t reserved_37_63:27; +#endif } s; struct cvmx_pko_mem_debug6_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t qid_offm:3; uint64_t static_p:1; @@ -507,15 +856,30 @@ union cvmx_pko_mem_debug6 { uint64_t dwri_chk:1; uint64_t dwri_uid:1; uint64_t dwri_mod:2; +#else + uint64_t dwri_mod:2; + uint64_t dwri_uid:1; + uint64_t dwri_chk:1; + uint64_t work_min:3; + uint64_t static_p:1; + uint64_t qid_offm:3; + uint64_t reserved_11_63:53; +#endif } cn30xx; struct cvmx_pko_mem_debug6_cn30xx cn31xx; struct cvmx_pko_mem_debug6_cn30xx cn38xx; struct cvmx_pko_mem_debug6_cn30xx cn38xxp2; struct cvmx_pko_mem_debug6_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t curr_ptr:11; +#else + uint64_t curr_ptr:11; + uint64_t reserved_11_63:53; +#endif } cn50xx; struct cvmx_pko_mem_debug6_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t qid_offres:4; uint64_t qid_offths:4; @@ -529,37 +893,77 @@ union cvmx_pko_mem_debug6 { uint64_t qid_offmax:4; uint64_t qid_off:4; uint64_t qid_base:8; +#else + uint64_t qid_base:8; + uint64_t qid_off:4; + uint64_t qid_offmax:4; + uint64_t qcb_ridx:5; + uint64_t qos:3; + uint64_t statc:1; + uint64_t active:1; + uint64_t preempted:1; + uint64_t preemptee:1; + uint64_t preempter:1; + uint64_t qid_offths:4; + uint64_t qid_offres:4; + uint64_t reserved_37_63:27; +#endif } cn52xx; struct cvmx_pko_mem_debug6_cn52xx cn52xxp1; struct cvmx_pko_mem_debug6_cn52xx cn56xx; struct cvmx_pko_mem_debug6_cn52xx cn56xxp1; struct cvmx_pko_mem_debug6_cn50xx cn58xx; struct cvmx_pko_mem_debug6_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug6_cn52xx cn61xx; + struct cvmx_pko_mem_debug6_cn52xx cn63xx; + struct cvmx_pko_mem_debug6_cn52xx cn63xxp1; + struct cvmx_pko_mem_debug6_cn52xx cn66xx; + struct cvmx_pko_mem_debug6_cn52xx cn68xx; + struct cvmx_pko_mem_debug6_cn52xx cn68xxp1; + struct cvmx_pko_mem_debug6_cn52xx cnf71xx; }; union cvmx_pko_mem_debug7 { uint64_t u64; struct cvmx_pko_mem_debug7_s { - uint64_t qos:5; - uint64_t tail:1; - uint64_t reserved_0_57:58; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug7_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t dwb:9; uint64_t start:33; uint64_t size:16; +#else + uint64_t size:16; + uint64_t start:33; + uint64_t dwb:9; + uint64_t reserved_58_63:6; +#endif } cn30xx; struct cvmx_pko_mem_debug7_cn30xx cn31xx; struct cvmx_pko_mem_debug7_cn30xx cn38xx; struct cvmx_pko_mem_debug7_cn30xx cn38xxp2; struct cvmx_pko_mem_debug7_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t qos:5; uint64_t tail:1; uint64_t buf_siz:13; uint64_t buf_ptr:33; uint64_t qcb_widx:6; uint64_t qcb_ridx:6; +#else + uint64_t qcb_ridx:6; + uint64_t qcb_widx:6; + uint64_t buf_ptr:33; + uint64_t buf_siz:13; + uint64_t tail:1; + uint64_t qos:5; +#endif } cn50xx; struct cvmx_pko_mem_debug7_cn50xx cn52xx; struct cvmx_pko_mem_debug7_cn50xx cn52xxp1; @@ -567,28 +971,68 @@ union cvmx_pko_mem_debug7 { struct cvmx_pko_mem_debug7_cn50xx cn56xxp1; struct cvmx_pko_mem_debug7_cn50xx cn58xx; struct cvmx_pko_mem_debug7_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug7_cn50xx cn61xx; + struct cvmx_pko_mem_debug7_cn50xx cn63xx; + struct cvmx_pko_mem_debug7_cn50xx cn63xxp1; + struct cvmx_pko_mem_debug7_cn50xx cn66xx; + struct cvmx_pko_mem_debug7_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t qos:3; + uint64_t tail:1; + uint64_t buf_siz:13; + uint64_t buf_ptr:33; + uint64_t qcb_widx:7; + uint64_t qcb_ridx:7; +#else + uint64_t qcb_ridx:7; + uint64_t qcb_widx:7; + uint64_t buf_ptr:33; + uint64_t buf_siz:13; + uint64_t tail:1; + uint64_t qos:3; +#endif + } cn68xx; + struct cvmx_pko_mem_debug7_cn68xx cn68xxp1; + struct cvmx_pko_mem_debug7_cn50xx cnf71xx; }; union cvmx_pko_mem_debug8 { uint64_t u64; struct cvmx_pko_mem_debug8_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t tail:1; uint64_t buf_siz:13; uint64_t reserved_0_44:45; +#else + uint64_t reserved_0_44:45; + uint64_t buf_siz:13; + uint64_t tail:1; + uint64_t reserved_59_63:5; +#endif } s; struct cvmx_pko_mem_debug8_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t qos:5; uint64_t tail:1; uint64_t buf_siz:13; uint64_t buf_ptr:33; uint64_t qcb_widx:6; uint64_t qcb_ridx:6; +#else + uint64_t qcb_ridx:6; + uint64_t qcb_widx:6; + uint64_t buf_ptr:33; + uint64_t buf_siz:13; + uint64_t tail:1; + uint64_t qos:5; +#endif } cn30xx; struct cvmx_pko_mem_debug8_cn30xx cn31xx; struct cvmx_pko_mem_debug8_cn30xx cn38xx; struct cvmx_pko_mem_debug8_cn30xx cn38xxp2; struct cvmx_pko_mem_debug8_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t doorbell:20; uint64_t reserved_6_7:2; @@ -596,8 +1040,18 @@ union cvmx_pko_mem_debug8 { uint64_t s_tail:1; uint64_t static_q:1; uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t static_q:1; + uint64_t s_tail:1; + uint64_t static_p:1; + uint64_t reserved_6_7:2; + uint64_t doorbell:20; + uint64_t reserved_28_63:36; +#endif } cn50xx; struct cvmx_pko_mem_debug8_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t preempter:1; uint64_t doorbell:20; @@ -607,31 +1061,115 @@ union cvmx_pko_mem_debug8 { uint64_t s_tail:1; uint64_t static_q:1; uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t static_q:1; + uint64_t s_tail:1; + uint64_t static_p:1; + uint64_t preemptee:1; + uint64_t reserved_7_7:1; + uint64_t doorbell:20; + uint64_t preempter:1; + uint64_t reserved_29_63:35; +#endif } cn52xx; struct cvmx_pko_mem_debug8_cn52xx cn52xxp1; struct cvmx_pko_mem_debug8_cn52xx cn56xx; struct cvmx_pko_mem_debug8_cn52xx cn56xxp1; struct cvmx_pko_mem_debug8_cn50xx cn58xx; struct cvmx_pko_mem_debug8_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug8_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_42_63:22; + uint64_t qid_qqos:8; + uint64_t reserved_33_33:1; + uint64_t qid_idx:4; + uint64_t preempter:1; + uint64_t doorbell:20; + uint64_t reserved_7_7:1; + uint64_t preemptee:1; + uint64_t static_p:1; + uint64_t s_tail:1; + uint64_t static_q:1; + uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t static_q:1; + uint64_t s_tail:1; + uint64_t static_p:1; + uint64_t preemptee:1; + uint64_t reserved_7_7:1; + uint64_t doorbell:20; + uint64_t preempter:1; + uint64_t qid_idx:4; + uint64_t reserved_33_33:1; + uint64_t qid_qqos:8; + uint64_t reserved_42_63:22; +#endif + } cn61xx; + struct cvmx_pko_mem_debug8_cn52xx cn63xx; + struct cvmx_pko_mem_debug8_cn52xx cn63xxp1; + struct cvmx_pko_mem_debug8_cn61xx cn66xx; + struct cvmx_pko_mem_debug8_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_37_63:27; + uint64_t preempter:1; + uint64_t doorbell:20; + uint64_t reserved_9_15:7; + uint64_t preemptee:1; + uint64_t static_p:1; + uint64_t s_tail:1; + uint64_t static_q:1; + uint64_t qos:5; +#else + uint64_t qos:5; + uint64_t static_q:1; + uint64_t s_tail:1; + uint64_t static_p:1; + uint64_t preemptee:1; + uint64_t reserved_9_15:7; + uint64_t doorbell:20; + uint64_t preempter:1; + uint64_t reserved_37_63:27; +#endif + } cn68xx; + struct cvmx_pko_mem_debug8_cn68xx cn68xxp1; + struct cvmx_pko_mem_debug8_cn61xx cnf71xx; }; union cvmx_pko_mem_debug9 { uint64_t u64; struct cvmx_pko_mem_debug9_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t ptrs0:17; uint64_t reserved_0_31:32; +#else + uint64_t reserved_0_31:32; + uint64_t ptrs0:17; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_pko_mem_debug9_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t doorbell:20; uint64_t reserved_5_7:3; uint64_t s_tail:1; uint64_t static_q:1; uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t static_q:1; + uint64_t s_tail:1; + uint64_t reserved_5_7:3; + uint64_t doorbell:20; + uint64_t reserved_28_63:36; +#endif } cn30xx; struct cvmx_pko_mem_debug9_cn30xx cn31xx; struct cvmx_pko_mem_debug9_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t doorbell:20; uint64_t reserved_6_7:2; @@ -639,13 +1177,29 @@ union cvmx_pko_mem_debug9 { uint64_t s_tail:1; uint64_t static_q:1; uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t static_q:1; + uint64_t s_tail:1; + uint64_t static_p:1; + uint64_t reserved_6_7:2; + uint64_t doorbell:20; + uint64_t reserved_28_63:36; +#endif } cn38xx; struct cvmx_pko_mem_debug9_cn38xx cn38xxp2; struct cvmx_pko_mem_debug9_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t ptrs0:17; uint64_t reserved_17_31:15; uint64_t ptrs3:17; +#else + uint64_t ptrs3:17; + uint64_t reserved_17_31:15; + uint64_t ptrs0:17; + uint64_t reserved_49_63:15; +#endif } cn50xx; struct cvmx_pko_mem_debug9_cn50xx cn52xx; struct cvmx_pko_mem_debug9_cn50xx cn52xxp1; @@ -653,11 +1207,131 @@ union cvmx_pko_mem_debug9 { struct cvmx_pko_mem_debug9_cn50xx cn56xxp1; struct cvmx_pko_mem_debug9_cn50xx cn58xx; struct cvmx_pko_mem_debug9_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug9_cn50xx cn61xx; + struct cvmx_pko_mem_debug9_cn50xx cn63xx; + struct cvmx_pko_mem_debug9_cn50xx cn63xxp1; + struct cvmx_pko_mem_debug9_cn50xx cn66xx; + struct cvmx_pko_mem_debug9_cn50xx cn68xx; + struct cvmx_pko_mem_debug9_cn50xx cn68xxp1; + struct cvmx_pko_mem_debug9_cn50xx cnf71xx; +}; + +union cvmx_pko_mem_iport_ptrs { + uint64_t u64; + struct cvmx_pko_mem_iport_ptrs_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_63_63:1; + uint64_t crc:1; + uint64_t static_p:1; + uint64_t qos_mask:8; + uint64_t min_pkt:3; + uint64_t reserved_31_49:19; + uint64_t pipe:7; + uint64_t reserved_21_23:3; + uint64_t intr:5; + uint64_t reserved_13_15:3; + uint64_t eid:5; + uint64_t reserved_7_7:1; + uint64_t ipid:7; +#else + uint64_t ipid:7; + uint64_t reserved_7_7:1; + uint64_t eid:5; + uint64_t reserved_13_15:3; + uint64_t intr:5; + uint64_t reserved_21_23:3; + uint64_t pipe:7; + uint64_t reserved_31_49:19; + uint64_t min_pkt:3; + uint64_t qos_mask:8; + uint64_t static_p:1; + uint64_t crc:1; + uint64_t reserved_63_63:1; +#endif + } s; + struct cvmx_pko_mem_iport_ptrs_s cn68xx; + struct cvmx_pko_mem_iport_ptrs_s cn68xxp1; +}; + +union cvmx_pko_mem_iport_qos { + uint64_t u64; + struct cvmx_pko_mem_iport_qos_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_61_63:3; + uint64_t qos_mask:8; + uint64_t reserved_13_52:40; + uint64_t eid:5; + uint64_t reserved_7_7:1; + uint64_t ipid:7; +#else + uint64_t ipid:7; + uint64_t reserved_7_7:1; + uint64_t eid:5; + uint64_t reserved_13_52:40; + uint64_t qos_mask:8; + uint64_t reserved_61_63:3; +#endif + } s; + struct cvmx_pko_mem_iport_qos_s cn68xx; + struct cvmx_pko_mem_iport_qos_s cn68xxp1; +}; + +union cvmx_pko_mem_iqueue_ptrs { + uint64_t u64; + struct cvmx_pko_mem_iqueue_ptrs_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t s_tail:1; + uint64_t static_p:1; + uint64_t static_q:1; + uint64_t qos_mask:8; + uint64_t buf_ptr:31; + uint64_t tail:1; + uint64_t index:5; + uint64_t reserved_15_15:1; + uint64_t ipid:7; + uint64_t qid:8; +#else + uint64_t qid:8; + uint64_t ipid:7; + uint64_t reserved_15_15:1; + uint64_t index:5; + uint64_t tail:1; + uint64_t buf_ptr:31; + uint64_t qos_mask:8; + uint64_t static_q:1; + uint64_t static_p:1; + uint64_t s_tail:1; +#endif + } s; + struct cvmx_pko_mem_iqueue_ptrs_s cn68xx; + struct cvmx_pko_mem_iqueue_ptrs_s cn68xxp1; +}; + +union cvmx_pko_mem_iqueue_qos { + uint64_t u64; + struct cvmx_pko_mem_iqueue_qos_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_61_63:3; + uint64_t qos_mask:8; + uint64_t reserved_15_52:38; + uint64_t ipid:7; + uint64_t qid:8; +#else + uint64_t qid:8; + uint64_t ipid:7; + uint64_t reserved_15_52:38; + uint64_t qos_mask:8; + uint64_t reserved_61_63:3; +#endif + } s; + struct cvmx_pko_mem_iqueue_qos_s cn68xx; + struct cvmx_pko_mem_iqueue_qos_s cn68xxp1; }; union cvmx_pko_mem_port_ptrs { uint64_t u64; struct cvmx_pko_mem_port_ptrs_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t static_p:1; uint64_t qos_mask:8; @@ -665,60 +1339,143 @@ union cvmx_pko_mem_port_ptrs { uint64_t bp_port:6; uint64_t eid:4; uint64_t pid:6; +#else + uint64_t pid:6; + uint64_t eid:4; + uint64_t bp_port:6; + uint64_t reserved_16_52:37; + uint64_t qos_mask:8; + uint64_t static_p:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_pko_mem_port_ptrs_s cn52xx; struct cvmx_pko_mem_port_ptrs_s cn52xxp1; struct cvmx_pko_mem_port_ptrs_s cn56xx; struct cvmx_pko_mem_port_ptrs_s cn56xxp1; + struct cvmx_pko_mem_port_ptrs_s cn61xx; + struct cvmx_pko_mem_port_ptrs_s cn63xx; + struct cvmx_pko_mem_port_ptrs_s cn63xxp1; + struct cvmx_pko_mem_port_ptrs_s cn66xx; + struct cvmx_pko_mem_port_ptrs_s cnf71xx; }; union cvmx_pko_mem_port_qos { uint64_t u64; struct cvmx_pko_mem_port_qos_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t qos_mask:8; uint64_t reserved_10_52:43; uint64_t eid:4; uint64_t pid:6; +#else + uint64_t pid:6; + uint64_t eid:4; + uint64_t reserved_10_52:43; + uint64_t qos_mask:8; + uint64_t reserved_61_63:3; +#endif } s; struct cvmx_pko_mem_port_qos_s cn52xx; struct cvmx_pko_mem_port_qos_s cn52xxp1; struct cvmx_pko_mem_port_qos_s cn56xx; struct cvmx_pko_mem_port_qos_s cn56xxp1; + struct cvmx_pko_mem_port_qos_s cn61xx; + struct cvmx_pko_mem_port_qos_s cn63xx; + struct cvmx_pko_mem_port_qos_s cn63xxp1; + struct cvmx_pko_mem_port_qos_s cn66xx; + struct cvmx_pko_mem_port_qos_s cnf71xx; }; union cvmx_pko_mem_port_rate0 { uint64_t u64; struct cvmx_pko_mem_port_rate0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_51_63:13; + uint64_t rate_word:19; + uint64_t rate_pkt:24; + uint64_t reserved_7_7:1; + uint64_t pid:7; +#else + uint64_t pid:7; + uint64_t reserved_7_7:1; + uint64_t rate_pkt:24; + uint64_t rate_word:19; + uint64_t reserved_51_63:13; +#endif + } s; + struct cvmx_pko_mem_port_rate0_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_51_63:13; uint64_t rate_word:19; uint64_t rate_pkt:24; uint64_t reserved_6_7:2; uint64_t pid:6; - } s; - struct cvmx_pko_mem_port_rate0_s cn52xx; - struct cvmx_pko_mem_port_rate0_s cn52xxp1; - struct cvmx_pko_mem_port_rate0_s cn56xx; - struct cvmx_pko_mem_port_rate0_s cn56xxp1; +#else + uint64_t pid:6; + uint64_t reserved_6_7:2; + uint64_t rate_pkt:24; + uint64_t rate_word:19; + uint64_t reserved_51_63:13; +#endif + } cn52xx; + struct cvmx_pko_mem_port_rate0_cn52xx cn52xxp1; + struct cvmx_pko_mem_port_rate0_cn52xx cn56xx; + struct cvmx_pko_mem_port_rate0_cn52xx cn56xxp1; + struct cvmx_pko_mem_port_rate0_cn52xx cn61xx; + struct cvmx_pko_mem_port_rate0_cn52xx cn63xx; + struct cvmx_pko_mem_port_rate0_cn52xx cn63xxp1; + struct cvmx_pko_mem_port_rate0_cn52xx cn66xx; + struct cvmx_pko_mem_port_rate0_s cn68xx; + struct cvmx_pko_mem_port_rate0_s cn68xxp1; + struct cvmx_pko_mem_port_rate0_cn52xx cnf71xx; }; union cvmx_pko_mem_port_rate1 { uint64_t u64; struct cvmx_pko_mem_port_rate1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t rate_lim:24; + uint64_t reserved_7_7:1; + uint64_t pid:7; +#else + uint64_t pid:7; + uint64_t reserved_7_7:1; + uint64_t rate_lim:24; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_pko_mem_port_rate1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rate_lim:24; uint64_t reserved_6_7:2; uint64_t pid:6; - } s; - struct cvmx_pko_mem_port_rate1_s cn52xx; - struct cvmx_pko_mem_port_rate1_s cn52xxp1; - struct cvmx_pko_mem_port_rate1_s cn56xx; - struct cvmx_pko_mem_port_rate1_s cn56xxp1; +#else + uint64_t pid:6; + uint64_t reserved_6_7:2; + uint64_t rate_lim:24; + uint64_t reserved_32_63:32; +#endif + } cn52xx; + struct cvmx_pko_mem_port_rate1_cn52xx cn52xxp1; + struct cvmx_pko_mem_port_rate1_cn52xx cn56xx; + struct cvmx_pko_mem_port_rate1_cn52xx cn56xxp1; + struct cvmx_pko_mem_port_rate1_cn52xx cn61xx; + struct cvmx_pko_mem_port_rate1_cn52xx cn63xx; + struct cvmx_pko_mem_port_rate1_cn52xx cn63xxp1; + struct cvmx_pko_mem_port_rate1_cn52xx cn66xx; + struct cvmx_pko_mem_port_rate1_s cn68xx; + struct cvmx_pko_mem_port_rate1_s cn68xxp1; + struct cvmx_pko_mem_port_rate1_cn52xx cnf71xx; }; union cvmx_pko_mem_queue_ptrs { uint64_t u64; struct cvmx_pko_mem_queue_ptrs_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t s_tail:1; uint64_t static_p:1; uint64_t static_q:1; @@ -728,6 +1485,17 @@ union cvmx_pko_mem_queue_ptrs { uint64_t index:3; uint64_t port:6; uint64_t queue:7; +#else + uint64_t queue:7; + uint64_t port:6; + uint64_t index:3; + uint64_t tail:1; + uint64_t buf_ptr:36; + uint64_t qos_mask:8; + uint64_t static_q:1; + uint64_t static_p:1; + uint64_t s_tail:1; +#endif } s; struct cvmx_pko_mem_queue_ptrs_s cn30xx; struct cvmx_pko_mem_queue_ptrs_s cn31xx; @@ -740,16 +1508,29 @@ union cvmx_pko_mem_queue_ptrs { struct cvmx_pko_mem_queue_ptrs_s cn56xxp1; struct cvmx_pko_mem_queue_ptrs_s cn58xx; struct cvmx_pko_mem_queue_ptrs_s cn58xxp1; + struct cvmx_pko_mem_queue_ptrs_s cn61xx; + struct cvmx_pko_mem_queue_ptrs_s cn63xx; + struct cvmx_pko_mem_queue_ptrs_s cn63xxp1; + struct cvmx_pko_mem_queue_ptrs_s cn66xx; + struct cvmx_pko_mem_queue_ptrs_s cnf71xx; }; union cvmx_pko_mem_queue_qos { uint64_t u64; struct cvmx_pko_mem_queue_qos_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t qos_mask:8; uint64_t reserved_13_52:40; uint64_t pid:6; uint64_t qid:7; +#else + uint64_t qid:7; + uint64_t pid:6; + uint64_t reserved_13_52:40; + uint64_t qos_mask:8; + uint64_t reserved_61_63:3; +#endif } s; struct cvmx_pko_mem_queue_qos_s cn30xx; struct cvmx_pko_mem_queue_qos_s cn31xx; @@ -762,14 +1543,70 @@ union cvmx_pko_mem_queue_qos { struct cvmx_pko_mem_queue_qos_s cn56xxp1; struct cvmx_pko_mem_queue_qos_s cn58xx; struct cvmx_pko_mem_queue_qos_s cn58xxp1; + struct cvmx_pko_mem_queue_qos_s cn61xx; + struct cvmx_pko_mem_queue_qos_s cn63xx; + struct cvmx_pko_mem_queue_qos_s cn63xxp1; + struct cvmx_pko_mem_queue_qos_s cn66xx; + struct cvmx_pko_mem_queue_qos_s cnf71xx; +}; + +union cvmx_pko_mem_throttle_int { + uint64_t u64; + struct cvmx_pko_mem_throttle_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_47_63:17; + uint64_t word:15; + uint64_t reserved_14_31:18; + uint64_t packet:6; + uint64_t reserved_5_7:3; + uint64_t intr:5; +#else + uint64_t intr:5; + uint64_t reserved_5_7:3; + uint64_t packet:6; + uint64_t reserved_14_31:18; + uint64_t word:15; + uint64_t reserved_47_63:17; +#endif + } s; + struct cvmx_pko_mem_throttle_int_s cn68xx; + struct cvmx_pko_mem_throttle_int_s cn68xxp1; +}; + +union cvmx_pko_mem_throttle_pipe { + uint64_t u64; + struct cvmx_pko_mem_throttle_pipe_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_47_63:17; + uint64_t word:15; + uint64_t reserved_14_31:18; + uint64_t packet:6; + uint64_t reserved_7_7:1; + uint64_t pipe:7; +#else + uint64_t pipe:7; + uint64_t reserved_7_7:1; + uint64_t packet:6; + uint64_t reserved_14_31:18; + uint64_t word:15; + uint64_t reserved_47_63:17; +#endif + } s; + struct cvmx_pko_mem_throttle_pipe_s cn68xx; + struct cvmx_pko_mem_throttle_pipe_s cn68xxp1; }; union cvmx_pko_reg_bist_result { uint64_t u64; struct cvmx_pko_reg_bist_result_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_reg_bist_result_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t psb2:5; uint64_t count:1; @@ -783,11 +1620,27 @@ union cvmx_pko_reg_bist_result { uint64_t qcb:2; uint64_t pdb:4; uint64_t psb:7; +#else + uint64_t psb:7; + uint64_t pdb:4; + uint64_t qcb:2; + uint64_t qsb:2; + uint64_t chk:1; + uint64_t crc:1; + uint64_t out:1; + uint64_t ncb:1; + uint64_t wif:1; + uint64_t rif:1; + uint64_t count:1; + uint64_t psb2:5; + uint64_t reserved_27_63:37; +#endif } cn30xx; struct cvmx_pko_reg_bist_result_cn30xx cn31xx; struct cvmx_pko_reg_bist_result_cn30xx cn38xx; struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2; struct cvmx_pko_reg_bist_result_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_33_63:31; uint64_t csr:1; uint64_t iob:1; @@ -803,8 +1656,26 @@ union cvmx_pko_reg_bist_result { uint64_t prt_qsb:3; uint64_t dat_dat:4; uint64_t dat_ptr:4; +#else + uint64_t dat_ptr:4; + uint64_t dat_dat:4; + uint64_t prt_qsb:3; + uint64_t prt_qcb:2; + uint64_t ncb_inb:2; + uint64_t prt_psb:6; + uint64_t prt_nxt:1; + uint64_t prt_chk:3; + uint64_t out_wif:1; + uint64_t out_sta:1; + uint64_t out_ctl:3; + uint64_t out_crc:1; + uint64_t iob:1; + uint64_t csr:1; + uint64_t reserved_33_63:31; +#endif } cn50xx; struct cvmx_pko_reg_bist_result_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t csr:1; uint64_t iob:1; @@ -821,21 +1692,139 @@ union cvmx_pko_reg_bist_result { uint64_t prt_ctl:2; uint64_t dat_dat:2; uint64_t dat_ptr:4; +#else + uint64_t dat_ptr:4; + uint64_t dat_dat:2; + uint64_t prt_ctl:2; + uint64_t prt_qsb:3; + uint64_t prt_qcb:2; + uint64_t ncb_inb:2; + uint64_t prt_psb:8; + uint64_t prt_nxt:1; + uint64_t prt_chk:3; + uint64_t out_wif:1; + uint64_t out_sta:1; + uint64_t out_ctl:3; + uint64_t out_dat:1; + uint64_t iob:1; + uint64_t csr:1; + uint64_t reserved_35_63:29; +#endif } cn52xx; struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1; struct cvmx_pko_reg_bist_result_cn52xx cn56xx; struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1; struct cvmx_pko_reg_bist_result_cn50xx cn58xx; struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1; + struct cvmx_pko_reg_bist_result_cn52xx cn61xx; + struct cvmx_pko_reg_bist_result_cn52xx cn63xx; + struct cvmx_pko_reg_bist_result_cn52xx cn63xxp1; + struct cvmx_pko_reg_bist_result_cn52xx cn66xx; + struct cvmx_pko_reg_bist_result_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_36_63:28; + uint64_t crc:1; + uint64_t csr:1; + uint64_t iob:1; + uint64_t out_dat:1; + uint64_t reserved_31_31:1; + uint64_t out_ctl:2; + uint64_t out_sta:1; + uint64_t out_wif:1; + uint64_t prt_chk:3; + uint64_t prt_nxt:1; + uint64_t prt_psb7:1; + uint64_t reserved_21_21:1; + uint64_t prt_psb:6; + uint64_t ncb_inb:2; + uint64_t prt_qcb:2; + uint64_t prt_qsb:3; + uint64_t prt_ctl:2; + uint64_t dat_dat:2; + uint64_t dat_ptr:4; +#else + uint64_t dat_ptr:4; + uint64_t dat_dat:2; + uint64_t prt_ctl:2; + uint64_t prt_qsb:3; + uint64_t prt_qcb:2; + uint64_t ncb_inb:2; + uint64_t prt_psb:6; + uint64_t reserved_21_21:1; + uint64_t prt_psb7:1; + uint64_t prt_nxt:1; + uint64_t prt_chk:3; + uint64_t out_wif:1; + uint64_t out_sta:1; + uint64_t out_ctl:2; + uint64_t reserved_31_31:1; + uint64_t out_dat:1; + uint64_t iob:1; + uint64_t csr:1; + uint64_t crc:1; + uint64_t reserved_36_63:28; +#endif + } cn68xx; + struct cvmx_pko_reg_bist_result_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_35_63:29; + uint64_t csr:1; + uint64_t iob:1; + uint64_t out_dat:1; + uint64_t reserved_31_31:1; + uint64_t out_ctl:2; + uint64_t out_sta:1; + uint64_t out_wif:1; + uint64_t prt_chk:3; + uint64_t prt_nxt:1; + uint64_t prt_psb7:1; + uint64_t reserved_21_21:1; + uint64_t prt_psb:6; + uint64_t ncb_inb:2; + uint64_t prt_qcb:2; + uint64_t prt_qsb:3; + uint64_t prt_ctl:2; + uint64_t dat_dat:2; + uint64_t dat_ptr:4; +#else + uint64_t dat_ptr:4; + uint64_t dat_dat:2; + uint64_t prt_ctl:2; + uint64_t prt_qsb:3; + uint64_t prt_qcb:2; + uint64_t ncb_inb:2; + uint64_t prt_psb:6; + uint64_t reserved_21_21:1; + uint64_t prt_psb7:1; + uint64_t prt_nxt:1; + uint64_t prt_chk:3; + uint64_t out_wif:1; + uint64_t out_sta:1; + uint64_t out_ctl:2; + uint64_t reserved_31_31:1; + uint64_t out_dat:1; + uint64_t iob:1; + uint64_t csr:1; + uint64_t reserved_35_63:29; +#endif + } cn68xxp1; + struct cvmx_pko_reg_bist_result_cn52xx cnf71xx; }; union cvmx_pko_reg_cmd_buf { uint64_t u64; struct cvmx_pko_reg_cmd_buf_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t pool:3; uint64_t reserved_13_19:7; uint64_t size:13; +#else + uint64_t size:13; + uint64_t reserved_13_19:7; + uint64_t pool:3; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_pko_reg_cmd_buf_s cn30xx; struct cvmx_pko_reg_cmd_buf_s cn31xx; @@ -848,14 +1837,27 @@ union cvmx_pko_reg_cmd_buf { struct cvmx_pko_reg_cmd_buf_s cn56xxp1; struct cvmx_pko_reg_cmd_buf_s cn58xx; struct cvmx_pko_reg_cmd_buf_s cn58xxp1; + struct cvmx_pko_reg_cmd_buf_s cn61xx; + struct cvmx_pko_reg_cmd_buf_s cn63xx; + struct cvmx_pko_reg_cmd_buf_s cn63xxp1; + struct cvmx_pko_reg_cmd_buf_s cn66xx; + struct cvmx_pko_reg_cmd_buf_s cn68xx; + struct cvmx_pko_reg_cmd_buf_s cn68xxp1; + struct cvmx_pko_reg_cmd_buf_s cnf71xx; }; union cvmx_pko_reg_crc_ctlx { uint64_t u64; struct cvmx_pko_reg_crc_ctlx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t invres:1; uint64_t refin:1; +#else + uint64_t refin:1; + uint64_t invres:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pko_reg_crc_ctlx_s cn38xx; struct cvmx_pko_reg_crc_ctlx_s cn38xxp2; @@ -866,8 +1868,13 @@ union cvmx_pko_reg_crc_ctlx { union cvmx_pko_reg_crc_enable { uint64_t u64; struct cvmx_pko_reg_crc_enable_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enable:32; +#else + uint64_t enable:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pko_reg_crc_enable_s cn38xx; struct cvmx_pko_reg_crc_enable_s cn38xxp2; @@ -878,8 +1885,13 @@ union cvmx_pko_reg_crc_enable { union cvmx_pko_reg_crc_ivx { uint64_t u64; struct cvmx_pko_reg_crc_ivx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iv:32; +#else + uint64_t iv:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pko_reg_crc_ivx_s cn38xx; struct cvmx_pko_reg_crc_ivx_s cn38xxp2; @@ -890,11 +1902,20 @@ union cvmx_pko_reg_crc_ivx { union cvmx_pko_reg_debug0 { uint64_t u64; struct cvmx_pko_reg_debug0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t asserts:64; +#else uint64_t asserts:64; +#endif } s; struct cvmx_pko_reg_debug0_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t asserts:17; +#else + uint64_t asserts:17; + uint64_t reserved_17_63:47; +#endif } cn30xx; struct cvmx_pko_reg_debug0_cn30xx cn31xx; struct cvmx_pko_reg_debug0_cn30xx cn38xx; @@ -906,12 +1927,23 @@ union cvmx_pko_reg_debug0 { struct cvmx_pko_reg_debug0_s cn56xxp1; struct cvmx_pko_reg_debug0_s cn58xx; struct cvmx_pko_reg_debug0_s cn58xxp1; + struct cvmx_pko_reg_debug0_s cn61xx; + struct cvmx_pko_reg_debug0_s cn63xx; + struct cvmx_pko_reg_debug0_s cn63xxp1; + struct cvmx_pko_reg_debug0_s cn66xx; + struct cvmx_pko_reg_debug0_s cn68xx; + struct cvmx_pko_reg_debug0_s cn68xxp1; + struct cvmx_pko_reg_debug0_s cnf71xx; }; union cvmx_pko_reg_debug1 { uint64_t u64; struct cvmx_pko_reg_debug1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t asserts:64; +#else uint64_t asserts:64; +#endif } s; struct cvmx_pko_reg_debug1_s cn50xx; struct cvmx_pko_reg_debug1_s cn52xx; @@ -920,12 +1952,23 @@ union cvmx_pko_reg_debug1 { struct cvmx_pko_reg_debug1_s cn56xxp1; struct cvmx_pko_reg_debug1_s cn58xx; struct cvmx_pko_reg_debug1_s cn58xxp1; + struct cvmx_pko_reg_debug1_s cn61xx; + struct cvmx_pko_reg_debug1_s cn63xx; + struct cvmx_pko_reg_debug1_s cn63xxp1; + struct cvmx_pko_reg_debug1_s cn66xx; + struct cvmx_pko_reg_debug1_s cn68xx; + struct cvmx_pko_reg_debug1_s cn68xxp1; + struct cvmx_pko_reg_debug1_s cnf71xx; }; union cvmx_pko_reg_debug2 { uint64_t u64; struct cvmx_pko_reg_debug2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t asserts:64; +#else + uint64_t asserts:64; +#endif } s; struct cvmx_pko_reg_debug2_s cn50xx; struct cvmx_pko_reg_debug2_s cn52xx; @@ -934,12 +1977,23 @@ union cvmx_pko_reg_debug2 { struct cvmx_pko_reg_debug2_s cn56xxp1; struct cvmx_pko_reg_debug2_s cn58xx; struct cvmx_pko_reg_debug2_s cn58xxp1; + struct cvmx_pko_reg_debug2_s cn61xx; + struct cvmx_pko_reg_debug2_s cn63xx; + struct cvmx_pko_reg_debug2_s cn63xxp1; + struct cvmx_pko_reg_debug2_s cn66xx; + struct cvmx_pko_reg_debug2_s cn68xx; + struct cvmx_pko_reg_debug2_s cn68xxp1; + struct cvmx_pko_reg_debug2_s cnf71xx; }; union cvmx_pko_reg_debug3 { uint64_t u64; struct cvmx_pko_reg_debug3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t asserts:64; +#else uint64_t asserts:64; +#endif } s; struct cvmx_pko_reg_debug3_s cn50xx; struct cvmx_pko_reg_debug3_s cn52xx; @@ -948,11 +2002,69 @@ union cvmx_pko_reg_debug3 { struct cvmx_pko_reg_debug3_s cn56xxp1; struct cvmx_pko_reg_debug3_s cn58xx; struct cvmx_pko_reg_debug3_s cn58xxp1; + struct cvmx_pko_reg_debug3_s cn61xx; + struct cvmx_pko_reg_debug3_s cn63xx; + struct cvmx_pko_reg_debug3_s cn63xxp1; + struct cvmx_pko_reg_debug3_s cn66xx; + struct cvmx_pko_reg_debug3_s cn68xx; + struct cvmx_pko_reg_debug3_s cn68xxp1; + struct cvmx_pko_reg_debug3_s cnf71xx; +}; + +union cvmx_pko_reg_debug4 { + uint64_t u64; + struct cvmx_pko_reg_debug4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t asserts:64; +#else + uint64_t asserts:64; +#endif + } s; + struct cvmx_pko_reg_debug4_s cn68xx; + struct cvmx_pko_reg_debug4_s cn68xxp1; }; union cvmx_pko_reg_engine_inflight { uint64_t u64; struct cvmx_pko_reg_engine_inflight_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t engine15:4; + uint64_t engine14:4; + uint64_t engine13:4; + uint64_t engine12:4; + uint64_t engine11:4; + uint64_t engine10:4; + uint64_t engine9:4; + uint64_t engine8:4; + uint64_t engine7:4; + uint64_t engine6:4; + uint64_t engine5:4; + uint64_t engine4:4; + uint64_t engine3:4; + uint64_t engine2:4; + uint64_t engine1:4; + uint64_t engine0:4; +#else + uint64_t engine0:4; + uint64_t engine1:4; + uint64_t engine2:4; + uint64_t engine3:4; + uint64_t engine4:4; + uint64_t engine5:4; + uint64_t engine6:4; + uint64_t engine7:4; + uint64_t engine8:4; + uint64_t engine9:4; + uint64_t engine10:4; + uint64_t engine11:4; + uint64_t engine12:4; + uint64_t engine13:4; + uint64_t engine14:4; + uint64_t engine15:4; +#endif + } s; + struct cvmx_pko_reg_engine_inflight_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t engine9:4; uint64_t engine8:4; @@ -964,78 +2076,380 @@ union cvmx_pko_reg_engine_inflight { uint64_t engine2:4; uint64_t engine1:4; uint64_t engine0:4; +#else + uint64_t engine0:4; + uint64_t engine1:4; + uint64_t engine2:4; + uint64_t engine3:4; + uint64_t engine4:4; + uint64_t engine5:4; + uint64_t engine6:4; + uint64_t engine7:4; + uint64_t engine8:4; + uint64_t engine9:4; + uint64_t reserved_40_63:24; +#endif + } cn52xx; + struct cvmx_pko_reg_engine_inflight_cn52xx cn52xxp1; + struct cvmx_pko_reg_engine_inflight_cn52xx cn56xx; + struct cvmx_pko_reg_engine_inflight_cn52xx cn56xxp1; + struct cvmx_pko_reg_engine_inflight_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t engine13:4; + uint64_t engine12:4; + uint64_t engine11:4; + uint64_t engine10:4; + uint64_t engine9:4; + uint64_t engine8:4; + uint64_t engine7:4; + uint64_t engine6:4; + uint64_t engine5:4; + uint64_t engine4:4; + uint64_t engine3:4; + uint64_t engine2:4; + uint64_t engine1:4; + uint64_t engine0:4; +#else + uint64_t engine0:4; + uint64_t engine1:4; + uint64_t engine2:4; + uint64_t engine3:4; + uint64_t engine4:4; + uint64_t engine5:4; + uint64_t engine6:4; + uint64_t engine7:4; + uint64_t engine8:4; + uint64_t engine9:4; + uint64_t engine10:4; + uint64_t engine11:4; + uint64_t engine12:4; + uint64_t engine13:4; + uint64_t reserved_56_63:8; +#endif + } cn61xx; + struct cvmx_pko_reg_engine_inflight_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t engine11:4; + uint64_t engine10:4; + uint64_t engine9:4; + uint64_t engine8:4; + uint64_t engine7:4; + uint64_t engine6:4; + uint64_t engine5:4; + uint64_t engine4:4; + uint64_t engine3:4; + uint64_t engine2:4; + uint64_t engine1:4; + uint64_t engine0:4; +#else + uint64_t engine0:4; + uint64_t engine1:4; + uint64_t engine2:4; + uint64_t engine3:4; + uint64_t engine4:4; + uint64_t engine5:4; + uint64_t engine6:4; + uint64_t engine7:4; + uint64_t engine8:4; + uint64_t engine9:4; + uint64_t engine10:4; + uint64_t engine11:4; + uint64_t reserved_48_63:16; +#endif + } cn63xx; + struct cvmx_pko_reg_engine_inflight_cn63xx cn63xxp1; + struct cvmx_pko_reg_engine_inflight_cn61xx cn66xx; + struct cvmx_pko_reg_engine_inflight_s cn68xx; + struct cvmx_pko_reg_engine_inflight_s cn68xxp1; + struct cvmx_pko_reg_engine_inflight_cn61xx cnf71xx; +}; + +union cvmx_pko_reg_engine_inflight1 { + uint64_t u64; + struct cvmx_pko_reg_engine_inflight1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t engine19:4; + uint64_t engine18:4; + uint64_t engine17:4; + uint64_t engine16:4; +#else + uint64_t engine16:4; + uint64_t engine17:4; + uint64_t engine18:4; + uint64_t engine19:4; + uint64_t reserved_16_63:48; +#endif } s; - struct cvmx_pko_reg_engine_inflight_s cn52xx; - struct cvmx_pko_reg_engine_inflight_s cn52xxp1; - struct cvmx_pko_reg_engine_inflight_s cn56xx; - struct cvmx_pko_reg_engine_inflight_s cn56xxp1; + struct cvmx_pko_reg_engine_inflight1_s cn68xx; + struct cvmx_pko_reg_engine_inflight1_s cn68xxp1; +}; + +union cvmx_pko_reg_engine_storagex { + uint64_t u64; + struct cvmx_pko_reg_engine_storagex_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t engine15:4; + uint64_t engine14:4; + uint64_t engine13:4; + uint64_t engine12:4; + uint64_t engine11:4; + uint64_t engine10:4; + uint64_t engine9:4; + uint64_t engine8:4; + uint64_t engine7:4; + uint64_t engine6:4; + uint64_t engine5:4; + uint64_t engine4:4; + uint64_t engine3:4; + uint64_t engine2:4; + uint64_t engine1:4; + uint64_t engine0:4; +#else + uint64_t engine0:4; + uint64_t engine1:4; + uint64_t engine2:4; + uint64_t engine3:4; + uint64_t engine4:4; + uint64_t engine5:4; + uint64_t engine6:4; + uint64_t engine7:4; + uint64_t engine8:4; + uint64_t engine9:4; + uint64_t engine10:4; + uint64_t engine11:4; + uint64_t engine12:4; + uint64_t engine13:4; + uint64_t engine14:4; + uint64_t engine15:4; +#endif + } s; + struct cvmx_pko_reg_engine_storagex_s cn68xx; + struct cvmx_pko_reg_engine_storagex_s cn68xxp1; }; union cvmx_pko_reg_engine_thresh { uint64_t u64; struct cvmx_pko_reg_engine_thresh_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t mask:20; +#else + uint64_t mask:20; + uint64_t reserved_20_63:44; +#endif + } s; + struct cvmx_pko_reg_engine_thresh_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t mask:10; - } s; - struct cvmx_pko_reg_engine_thresh_s cn52xx; - struct cvmx_pko_reg_engine_thresh_s cn52xxp1; - struct cvmx_pko_reg_engine_thresh_s cn56xx; - struct cvmx_pko_reg_engine_thresh_s cn56xxp1; +#else + uint64_t mask:10; + uint64_t reserved_10_63:54; +#endif + } cn52xx; + struct cvmx_pko_reg_engine_thresh_cn52xx cn52xxp1; + struct cvmx_pko_reg_engine_thresh_cn52xx cn56xx; + struct cvmx_pko_reg_engine_thresh_cn52xx cn56xxp1; + struct cvmx_pko_reg_engine_thresh_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_14_63:50; + uint64_t mask:14; +#else + uint64_t mask:14; + uint64_t reserved_14_63:50; +#endif + } cn61xx; + struct cvmx_pko_reg_engine_thresh_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t mask:12; +#else + uint64_t mask:12; + uint64_t reserved_12_63:52; +#endif + } cn63xx; + struct cvmx_pko_reg_engine_thresh_cn63xx cn63xxp1; + struct cvmx_pko_reg_engine_thresh_cn61xx cn66xx; + struct cvmx_pko_reg_engine_thresh_s cn68xx; + struct cvmx_pko_reg_engine_thresh_s cn68xxp1; + struct cvmx_pko_reg_engine_thresh_cn61xx cnf71xx; }; union cvmx_pko_reg_error { uint64_t u64; struct cvmx_pko_reg_error_s { - uint64_t reserved_3_63:61; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t loopback:1; uint64_t currzero:1; uint64_t doorbell:1; uint64_t parity:1; +#else + uint64_t parity:1; + uint64_t doorbell:1; + uint64_t currzero:1; + uint64_t loopback:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pko_reg_error_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t doorbell:1; uint64_t parity:1; +#else + uint64_t parity:1; + uint64_t doorbell:1; + uint64_t reserved_2_63:62; +#endif } cn30xx; struct cvmx_pko_reg_error_cn30xx cn31xx; struct cvmx_pko_reg_error_cn30xx cn38xx; struct cvmx_pko_reg_error_cn30xx cn38xxp2; - struct cvmx_pko_reg_error_s cn50xx; - struct cvmx_pko_reg_error_s cn52xx; - struct cvmx_pko_reg_error_s cn52xxp1; - struct cvmx_pko_reg_error_s cn56xx; - struct cvmx_pko_reg_error_s cn56xxp1; - struct cvmx_pko_reg_error_s cn58xx; - struct cvmx_pko_reg_error_s cn58xxp1; + struct cvmx_pko_reg_error_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t currzero:1; + uint64_t doorbell:1; + uint64_t parity:1; +#else + uint64_t parity:1; + uint64_t doorbell:1; + uint64_t currzero:1; + uint64_t reserved_3_63:61; +#endif + } cn50xx; + struct cvmx_pko_reg_error_cn50xx cn52xx; + struct cvmx_pko_reg_error_cn50xx cn52xxp1; + struct cvmx_pko_reg_error_cn50xx cn56xx; + struct cvmx_pko_reg_error_cn50xx cn56xxp1; + struct cvmx_pko_reg_error_cn50xx cn58xx; + struct cvmx_pko_reg_error_cn50xx cn58xxp1; + struct cvmx_pko_reg_error_cn50xx cn61xx; + struct cvmx_pko_reg_error_cn50xx cn63xx; + struct cvmx_pko_reg_error_cn50xx cn63xxp1; + struct cvmx_pko_reg_error_cn50xx cn66xx; + struct cvmx_pko_reg_error_s cn68xx; + struct cvmx_pko_reg_error_s cn68xxp1; + struct cvmx_pko_reg_error_cn50xx cnf71xx; }; union cvmx_pko_reg_flags { uint64_t u64; struct cvmx_pko_reg_flags_s { - uint64_t reserved_4_63:60; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t dis_perf3:1; + uint64_t dis_perf2:1; + uint64_t dis_perf1:1; + uint64_t dis_perf0:1; + uint64_t ena_throttle:1; uint64_t reset:1; uint64_t store_be:1; uint64_t ena_dwb:1; uint64_t ena_pko:1; +#else + uint64_t ena_pko:1; + uint64_t ena_dwb:1; + uint64_t store_be:1; + uint64_t reset:1; + uint64_t ena_throttle:1; + uint64_t dis_perf0:1; + uint64_t dis_perf1:1; + uint64_t dis_perf2:1; + uint64_t dis_perf3:1; + uint64_t reserved_9_63:55; +#endif } s; - struct cvmx_pko_reg_flags_s cn30xx; - struct cvmx_pko_reg_flags_s cn31xx; - struct cvmx_pko_reg_flags_s cn38xx; - struct cvmx_pko_reg_flags_s cn38xxp2; - struct cvmx_pko_reg_flags_s cn50xx; - struct cvmx_pko_reg_flags_s cn52xx; - struct cvmx_pko_reg_flags_s cn52xxp1; - struct cvmx_pko_reg_flags_s cn56xx; - struct cvmx_pko_reg_flags_s cn56xxp1; - struct cvmx_pko_reg_flags_s cn58xx; - struct cvmx_pko_reg_flags_s cn58xxp1; + struct cvmx_pko_reg_flags_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t reset:1; + uint64_t store_be:1; + uint64_t ena_dwb:1; + uint64_t ena_pko:1; +#else + uint64_t ena_pko:1; + uint64_t ena_dwb:1; + uint64_t store_be:1; + uint64_t reset:1; + uint64_t reserved_4_63:60; +#endif + } cn30xx; + struct cvmx_pko_reg_flags_cn30xx cn31xx; + struct cvmx_pko_reg_flags_cn30xx cn38xx; + struct cvmx_pko_reg_flags_cn30xx cn38xxp2; + struct cvmx_pko_reg_flags_cn30xx cn50xx; + struct cvmx_pko_reg_flags_cn30xx cn52xx; + struct cvmx_pko_reg_flags_cn30xx cn52xxp1; + struct cvmx_pko_reg_flags_cn30xx cn56xx; + struct cvmx_pko_reg_flags_cn30xx cn56xxp1; + struct cvmx_pko_reg_flags_cn30xx cn58xx; + struct cvmx_pko_reg_flags_cn30xx cn58xxp1; + struct cvmx_pko_reg_flags_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t dis_perf3:1; + uint64_t dis_perf2:1; + uint64_t reserved_4_6:3; + uint64_t reset:1; + uint64_t store_be:1; + uint64_t ena_dwb:1; + uint64_t ena_pko:1; +#else + uint64_t ena_pko:1; + uint64_t ena_dwb:1; + uint64_t store_be:1; + uint64_t reset:1; + uint64_t reserved_4_6:3; + uint64_t dis_perf2:1; + uint64_t dis_perf3:1; + uint64_t reserved_9_63:55; +#endif + } cn61xx; + struct cvmx_pko_reg_flags_cn30xx cn63xx; + struct cvmx_pko_reg_flags_cn30xx cn63xxp1; + struct cvmx_pko_reg_flags_cn61xx cn66xx; + struct cvmx_pko_reg_flags_s cn68xx; + struct cvmx_pko_reg_flags_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t dis_perf1:1; + uint64_t dis_perf0:1; + uint64_t ena_throttle:1; + uint64_t reset:1; + uint64_t store_be:1; + uint64_t ena_dwb:1; + uint64_t ena_pko:1; +#else + uint64_t ena_pko:1; + uint64_t ena_dwb:1; + uint64_t store_be:1; + uint64_t reset:1; + uint64_t ena_throttle:1; + uint64_t dis_perf0:1; + uint64_t dis_perf1:1; + uint64_t reserved_7_63:57; +#endif + } cn68xxp1; + struct cvmx_pko_reg_flags_cn61xx cnf71xx; }; union cvmx_pko_reg_gmx_port_mode { uint64_t u64; struct cvmx_pko_reg_gmx_port_mode_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mode1:3; uint64_t mode0:3; +#else + uint64_t mode0:3; + uint64_t mode1:3; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_pko_reg_gmx_port_mode_s cn30xx; struct cvmx_pko_reg_gmx_port_mode_s cn31xx; @@ -1048,38 +2462,223 @@ union cvmx_pko_reg_gmx_port_mode { struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1; struct cvmx_pko_reg_gmx_port_mode_s cn58xx; struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1; + struct cvmx_pko_reg_gmx_port_mode_s cn61xx; + struct cvmx_pko_reg_gmx_port_mode_s cn63xx; + struct cvmx_pko_reg_gmx_port_mode_s cn63xxp1; + struct cvmx_pko_reg_gmx_port_mode_s cn66xx; + struct cvmx_pko_reg_gmx_port_mode_s cnf71xx; }; union cvmx_pko_reg_int_mask { uint64_t u64; struct cvmx_pko_reg_int_mask_s { - uint64_t reserved_3_63:61; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t loopback:1; uint64_t currzero:1; uint64_t doorbell:1; uint64_t parity:1; +#else + uint64_t parity:1; + uint64_t doorbell:1; + uint64_t currzero:1; + uint64_t loopback:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pko_reg_int_mask_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t doorbell:1; uint64_t parity:1; +#else + uint64_t parity:1; + uint64_t doorbell:1; + uint64_t reserved_2_63:62; +#endif } cn30xx; struct cvmx_pko_reg_int_mask_cn30xx cn31xx; struct cvmx_pko_reg_int_mask_cn30xx cn38xx; struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2; - struct cvmx_pko_reg_int_mask_s cn50xx; - struct cvmx_pko_reg_int_mask_s cn52xx; - struct cvmx_pko_reg_int_mask_s cn52xxp1; - struct cvmx_pko_reg_int_mask_s cn56xx; - struct cvmx_pko_reg_int_mask_s cn56xxp1; - struct cvmx_pko_reg_int_mask_s cn58xx; - struct cvmx_pko_reg_int_mask_s cn58xxp1; + struct cvmx_pko_reg_int_mask_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t currzero:1; + uint64_t doorbell:1; + uint64_t parity:1; +#else + uint64_t parity:1; + uint64_t doorbell:1; + uint64_t currzero:1; + uint64_t reserved_3_63:61; +#endif + } cn50xx; + struct cvmx_pko_reg_int_mask_cn50xx cn52xx; + struct cvmx_pko_reg_int_mask_cn50xx cn52xxp1; + struct cvmx_pko_reg_int_mask_cn50xx cn56xx; + struct cvmx_pko_reg_int_mask_cn50xx cn56xxp1; + struct cvmx_pko_reg_int_mask_cn50xx cn58xx; + struct cvmx_pko_reg_int_mask_cn50xx cn58xxp1; + struct cvmx_pko_reg_int_mask_cn50xx cn61xx; + struct cvmx_pko_reg_int_mask_cn50xx cn63xx; + struct cvmx_pko_reg_int_mask_cn50xx cn63xxp1; + struct cvmx_pko_reg_int_mask_cn50xx cn66xx; + struct cvmx_pko_reg_int_mask_s cn68xx; + struct cvmx_pko_reg_int_mask_s cn68xxp1; + struct cvmx_pko_reg_int_mask_cn50xx cnf71xx; +}; + +union cvmx_pko_reg_loopback_bpid { + uint64_t u64; + struct cvmx_pko_reg_loopback_bpid_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_59_63:5; + uint64_t bpid7:6; + uint64_t reserved_52_52:1; + uint64_t bpid6:6; + uint64_t reserved_45_45:1; + uint64_t bpid5:6; + uint64_t reserved_38_38:1; + uint64_t bpid4:6; + uint64_t reserved_31_31:1; + uint64_t bpid3:6; + uint64_t reserved_24_24:1; + uint64_t bpid2:6; + uint64_t reserved_17_17:1; + uint64_t bpid1:6; + uint64_t reserved_10_10:1; + uint64_t bpid0:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t bpid0:6; + uint64_t reserved_10_10:1; + uint64_t bpid1:6; + uint64_t reserved_17_17:1; + uint64_t bpid2:6; + uint64_t reserved_24_24:1; + uint64_t bpid3:6; + uint64_t reserved_31_31:1; + uint64_t bpid4:6; + uint64_t reserved_38_38:1; + uint64_t bpid5:6; + uint64_t reserved_45_45:1; + uint64_t bpid6:6; + uint64_t reserved_52_52:1; + uint64_t bpid7:6; + uint64_t reserved_59_63:5; +#endif + } s; + struct cvmx_pko_reg_loopback_bpid_s cn68xx; + struct cvmx_pko_reg_loopback_bpid_s cn68xxp1; +}; + +union cvmx_pko_reg_loopback_pkind { + uint64_t u64; + struct cvmx_pko_reg_loopback_pkind_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_59_63:5; + uint64_t pkind7:6; + uint64_t reserved_52_52:1; + uint64_t pkind6:6; + uint64_t reserved_45_45:1; + uint64_t pkind5:6; + uint64_t reserved_38_38:1; + uint64_t pkind4:6; + uint64_t reserved_31_31:1; + uint64_t pkind3:6; + uint64_t reserved_24_24:1; + uint64_t pkind2:6; + uint64_t reserved_17_17:1; + uint64_t pkind1:6; + uint64_t reserved_10_10:1; + uint64_t pkind0:6; + uint64_t num_ports:4; +#else + uint64_t num_ports:4; + uint64_t pkind0:6; + uint64_t reserved_10_10:1; + uint64_t pkind1:6; + uint64_t reserved_17_17:1; + uint64_t pkind2:6; + uint64_t reserved_24_24:1; + uint64_t pkind3:6; + uint64_t reserved_31_31:1; + uint64_t pkind4:6; + uint64_t reserved_38_38:1; + uint64_t pkind5:6; + uint64_t reserved_45_45:1; + uint64_t pkind6:6; + uint64_t reserved_52_52:1; + uint64_t pkind7:6; + uint64_t reserved_59_63:5; +#endif + } s; + struct cvmx_pko_reg_loopback_pkind_s cn68xx; + struct cvmx_pko_reg_loopback_pkind_s cn68xxp1; +}; + +union cvmx_pko_reg_min_pkt { + uint64_t u64; + struct cvmx_pko_reg_min_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t size7:8; + uint64_t size6:8; + uint64_t size5:8; + uint64_t size4:8; + uint64_t size3:8; + uint64_t size2:8; + uint64_t size1:8; + uint64_t size0:8; +#else + uint64_t size0:8; + uint64_t size1:8; + uint64_t size2:8; + uint64_t size3:8; + uint64_t size4:8; + uint64_t size5:8; + uint64_t size6:8; + uint64_t size7:8; +#endif + } s; + struct cvmx_pko_reg_min_pkt_s cn68xx; + struct cvmx_pko_reg_min_pkt_s cn68xxp1; +}; + +union cvmx_pko_reg_preempt { + uint64_t u64; + struct cvmx_pko_reg_preempt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t min_size:16; +#else + uint64_t min_size:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_pko_reg_preempt_s cn52xx; + struct cvmx_pko_reg_preempt_s cn52xxp1; + struct cvmx_pko_reg_preempt_s cn56xx; + struct cvmx_pko_reg_preempt_s cn56xxp1; + struct cvmx_pko_reg_preempt_s cn61xx; + struct cvmx_pko_reg_preempt_s cn63xx; + struct cvmx_pko_reg_preempt_s cn63xxp1; + struct cvmx_pko_reg_preempt_s cn66xx; + struct cvmx_pko_reg_preempt_s cn68xx; + struct cvmx_pko_reg_preempt_s cn68xxp1; + struct cvmx_pko_reg_preempt_s cnf71xx; }; union cvmx_pko_reg_queue_mode { uint64_t u64; struct cvmx_pko_reg_queue_mode_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t mode:2; +#else + uint64_t mode:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pko_reg_queue_mode_s cn30xx; struct cvmx_pko_reg_queue_mode_s cn31xx; @@ -1092,14 +2691,53 @@ union cvmx_pko_reg_queue_mode { struct cvmx_pko_reg_queue_mode_s cn56xxp1; struct cvmx_pko_reg_queue_mode_s cn58xx; struct cvmx_pko_reg_queue_mode_s cn58xxp1; + struct cvmx_pko_reg_queue_mode_s cn61xx; + struct cvmx_pko_reg_queue_mode_s cn63xx; + struct cvmx_pko_reg_queue_mode_s cn63xxp1; + struct cvmx_pko_reg_queue_mode_s cn66xx; + struct cvmx_pko_reg_queue_mode_s cn68xx; + struct cvmx_pko_reg_queue_mode_s cn68xxp1; + struct cvmx_pko_reg_queue_mode_s cnf71xx; +}; + +union cvmx_pko_reg_queue_preempt { + uint64_t u64; + struct cvmx_pko_reg_queue_preempt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_2_63:62; + uint64_t preemptee:1; + uint64_t preempter:1; +#else + uint64_t preempter:1; + uint64_t preemptee:1; + uint64_t reserved_2_63:62; +#endif + } s; + struct cvmx_pko_reg_queue_preempt_s cn52xx; + struct cvmx_pko_reg_queue_preempt_s cn52xxp1; + struct cvmx_pko_reg_queue_preempt_s cn56xx; + struct cvmx_pko_reg_queue_preempt_s cn56xxp1; + struct cvmx_pko_reg_queue_preempt_s cn61xx; + struct cvmx_pko_reg_queue_preempt_s cn63xx; + struct cvmx_pko_reg_queue_preempt_s cn63xxp1; + struct cvmx_pko_reg_queue_preempt_s cn66xx; + struct cvmx_pko_reg_queue_preempt_s cn68xx; + struct cvmx_pko_reg_queue_preempt_s cn68xxp1; + struct cvmx_pko_reg_queue_preempt_s cnf71xx; }; union cvmx_pko_reg_queue_ptrs1 { uint64_t u64; struct cvmx_pko_reg_queue_ptrs1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t idx3:1; uint64_t qid7:1; +#else + uint64_t qid7:1; + uint64_t idx3:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pko_reg_queue_ptrs1_s cn50xx; struct cvmx_pko_reg_queue_ptrs1_s cn52xx; @@ -1108,14 +2746,25 @@ union cvmx_pko_reg_queue_ptrs1 { struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1; struct cvmx_pko_reg_queue_ptrs1_s cn58xx; struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1; + struct cvmx_pko_reg_queue_ptrs1_s cn61xx; + struct cvmx_pko_reg_queue_ptrs1_s cn63xx; + struct cvmx_pko_reg_queue_ptrs1_s cn63xxp1; + struct cvmx_pko_reg_queue_ptrs1_s cn66xx; + struct cvmx_pko_reg_queue_ptrs1_s cnf71xx; }; union cvmx_pko_reg_read_idx { uint64_t u64; struct cvmx_pko_reg_read_idx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t inc:8; uint64_t index:8; +#else + uint64_t index:8; + uint64_t inc:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pko_reg_read_idx_s cn30xx; struct cvmx_pko_reg_read_idx_s cn31xx; @@ -1128,6 +2777,48 @@ union cvmx_pko_reg_read_idx { struct cvmx_pko_reg_read_idx_s cn56xxp1; struct cvmx_pko_reg_read_idx_s cn58xx; struct cvmx_pko_reg_read_idx_s cn58xxp1; + struct cvmx_pko_reg_read_idx_s cn61xx; + struct cvmx_pko_reg_read_idx_s cn63xx; + struct cvmx_pko_reg_read_idx_s cn63xxp1; + struct cvmx_pko_reg_read_idx_s cn66xx; + struct cvmx_pko_reg_read_idx_s cn68xx; + struct cvmx_pko_reg_read_idx_s cn68xxp1; + struct cvmx_pko_reg_read_idx_s cnf71xx; +}; + +union cvmx_pko_reg_throttle { + uint64_t u64; + struct cvmx_pko_reg_throttle_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t int_mask:32; +#else + uint64_t int_mask:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_pko_reg_throttle_s cn68xx; + struct cvmx_pko_reg_throttle_s cn68xxp1; +}; + +union cvmx_pko_reg_timestamp { + uint64_t u64; + struct cvmx_pko_reg_timestamp_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t wqe_word:4; +#else + uint64_t wqe_word:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_pko_reg_timestamp_s cn61xx; + struct cvmx_pko_reg_timestamp_s cn63xx; + struct cvmx_pko_reg_timestamp_s cn63xxp1; + struct cvmx_pko_reg_timestamp_s cn66xx; + struct cvmx_pko_reg_timestamp_s cn68xx; + struct cvmx_pko_reg_timestamp_s cn68xxp1; + struct cvmx_pko_reg_timestamp_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-pow-defs.h b/arch/mips/include/asm/octeon/cvmx-pow-defs.h index 39fd75b03f77..9020ef443736 100644 --- a/arch/mips/include/asm/octeon/cvmx-pow-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pow-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -55,11 +55,18 @@ union cvmx_pow_bist_stat { uint64_t u64; struct cvmx_pow_bist_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pp:16; uint64_t reserved_0_15:16; +#else + uint64_t reserved_0_15:16; + uint64_t pp:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_bist_stat_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t pp:1; uint64_t reserved_9_15:7; @@ -72,8 +79,23 @@ union cvmx_pow_bist_stat { uint64_t nbr0:1; uint64_t pend:1; uint64_t adr:1; +#else + uint64_t adr:1; + uint64_t pend:1; + uint64_t nbr0:1; + uint64_t nbr1:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt0:1; + uint64_t nbt1:1; + uint64_t cam:1; + uint64_t reserved_9_15:7; + uint64_t pp:1; + uint64_t reserved_17_63:47; +#endif } cn30xx; struct cvmx_pow_bist_stat_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t pp:2; uint64_t reserved_9_15:7; @@ -86,8 +108,23 @@ union cvmx_pow_bist_stat { uint64_t nbr0:1; uint64_t pend:1; uint64_t adr:1; +#else + uint64_t adr:1; + uint64_t pend:1; + uint64_t nbr0:1; + uint64_t nbr1:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt0:1; + uint64_t nbt1:1; + uint64_t cam:1; + uint64_t reserved_9_15:7; + uint64_t pp:2; + uint64_t reserved_18_63:46; +#endif } cn31xx; struct cvmx_pow_bist_stat_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pp:16; uint64_t reserved_10_15:6; @@ -101,10 +138,26 @@ union cvmx_pow_bist_stat { uint64_t pend0:1; uint64_t adr1:1; uint64_t adr0:1; +#else + uint64_t adr0:1; + uint64_t adr1:1; + uint64_t pend0:1; + uint64_t pend1:1; + uint64_t nbr0:1; + uint64_t nbr1:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt:1; + uint64_t cam:1; + uint64_t reserved_10_15:6; + uint64_t pp:16; + uint64_t reserved_32_63:32; +#endif } cn38xx; struct cvmx_pow_bist_stat_cn38xx cn38xxp2; struct cvmx_pow_bist_stat_cn31xx cn50xx; struct cvmx_pow_bist_stat_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pp:4; uint64_t reserved_9_15:7; @@ -117,9 +170,24 @@ union cvmx_pow_bist_stat { uint64_t nbr0:1; uint64_t pend:1; uint64_t adr:1; +#else + uint64_t adr:1; + uint64_t pend:1; + uint64_t nbr0:1; + uint64_t nbr1:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt0:1; + uint64_t nbt1:1; + uint64_t cam:1; + uint64_t reserved_9_15:7; + uint64_t pp:4; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_pow_bist_stat_cn52xx cn52xxp1; struct cvmx_pow_bist_stat_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t pp:12; uint64_t reserved_10_15:6; @@ -133,11 +201,52 @@ union cvmx_pow_bist_stat { uint64_t pend0:1; uint64_t adr1:1; uint64_t adr0:1; +#else + uint64_t adr0:1; + uint64_t adr1:1; + uint64_t pend0:1; + uint64_t pend1:1; + uint64_t nbr0:1; + uint64_t nbr1:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt:1; + uint64_t cam:1; + uint64_t reserved_10_15:6; + uint64_t pp:12; + uint64_t reserved_28_63:36; +#endif } cn56xx; struct cvmx_pow_bist_stat_cn56xx cn56xxp1; struct cvmx_pow_bist_stat_cn38xx cn58xx; struct cvmx_pow_bist_stat_cn38xx cn58xxp1; + struct cvmx_pow_bist_stat_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t pp:4; + uint64_t reserved_12_15:4; + uint64_t cam:1; + uint64_t nbr:3; + uint64_t nbt:4; + uint64_t index:1; + uint64_t fidx:1; + uint64_t pend:1; + uint64_t adr:1; +#else + uint64_t adr:1; + uint64_t pend:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt:4; + uint64_t nbr:3; + uint64_t cam:1; + uint64_t reserved_12_15:4; + uint64_t pp:4; + uint64_t reserved_20_63:44; +#endif + } cn61xx; struct cvmx_pow_bist_stat_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t pp:6; uint64_t reserved_12_15:4; @@ -148,15 +257,58 @@ union cvmx_pow_bist_stat { uint64_t fidx:1; uint64_t pend:1; uint64_t adr:1; +#else + uint64_t adr:1; + uint64_t pend:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt:4; + uint64_t nbr:3; + uint64_t cam:1; + uint64_t reserved_12_15:4; + uint64_t pp:6; + uint64_t reserved_22_63:42; +#endif } cn63xx; struct cvmx_pow_bist_stat_cn63xx cn63xxp1; + struct cvmx_pow_bist_stat_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_26_63:38; + uint64_t pp:10; + uint64_t reserved_12_15:4; + uint64_t cam:1; + uint64_t nbr:3; + uint64_t nbt:4; + uint64_t index:1; + uint64_t fidx:1; + uint64_t pend:1; + uint64_t adr:1; +#else + uint64_t adr:1; + uint64_t pend:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt:4; + uint64_t nbr:3; + uint64_t cam:1; + uint64_t reserved_12_15:4; + uint64_t pp:10; + uint64_t reserved_26_63:38; +#endif + } cn66xx; + struct cvmx_pow_bist_stat_cn61xx cnf71xx; }; union cvmx_pow_ds_pc { uint64_t u64; struct cvmx_pow_ds_pc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ds_pc:32; +#else + uint64_t ds_pc:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_ds_pc_s cn30xx; struct cvmx_pow_ds_pc_s cn31xx; @@ -169,13 +321,17 @@ union cvmx_pow_ds_pc { struct cvmx_pow_ds_pc_s cn56xxp1; struct cvmx_pow_ds_pc_s cn58xx; struct cvmx_pow_ds_pc_s cn58xxp1; + struct cvmx_pow_ds_pc_s cn61xx; struct cvmx_pow_ds_pc_s cn63xx; struct cvmx_pow_ds_pc_s cn63xxp1; + struct cvmx_pow_ds_pc_s cn66xx; + struct cvmx_pow_ds_pc_s cnf71xx; }; union cvmx_pow_ecc_err { uint64_t u64; struct cvmx_pow_ecc_err_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t iop_ie:13; uint64_t reserved_29_31:3; @@ -189,9 +345,25 @@ union cvmx_pow_ecc_err { uint64_t sbe_ie:1; uint64_t dbe:1; uint64_t sbe:1; +#else + uint64_t sbe:1; + uint64_t dbe:1; + uint64_t sbe_ie:1; + uint64_t dbe_ie:1; + uint64_t syn:5; + uint64_t reserved_9_11:3; + uint64_t rpe:1; + uint64_t rpe_ie:1; + uint64_t reserved_14_15:2; + uint64_t iop:13; + uint64_t reserved_29_31:3; + uint64_t iop_ie:13; + uint64_t reserved_45_63:19; +#endif } s; struct cvmx_pow_ecc_err_s cn30xx; struct cvmx_pow_ecc_err_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t rpe_ie:1; uint64_t rpe:1; @@ -201,6 +373,17 @@ union cvmx_pow_ecc_err { uint64_t sbe_ie:1; uint64_t dbe:1; uint64_t sbe:1; +#else + uint64_t sbe:1; + uint64_t dbe:1; + uint64_t sbe_ie:1; + uint64_t dbe_ie:1; + uint64_t syn:5; + uint64_t reserved_9_11:3; + uint64_t rpe:1; + uint64_t rpe_ie:1; + uint64_t reserved_14_63:50; +#endif } cn31xx; struct cvmx_pow_ecc_err_s cn38xx; struct cvmx_pow_ecc_err_cn31xx cn38xxp2; @@ -211,16 +394,25 @@ union cvmx_pow_ecc_err { struct cvmx_pow_ecc_err_s cn56xxp1; struct cvmx_pow_ecc_err_s cn58xx; struct cvmx_pow_ecc_err_s cn58xxp1; + struct cvmx_pow_ecc_err_s cn61xx; struct cvmx_pow_ecc_err_s cn63xx; struct cvmx_pow_ecc_err_s cn63xxp1; + struct cvmx_pow_ecc_err_s cn66xx; + struct cvmx_pow_ecc_err_s cnf71xx; }; union cvmx_pow_int_ctl { uint64_t u64; struct cvmx_pow_int_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t pfr_dis:1; uint64_t nbr_thr:5; +#else + uint64_t nbr_thr:5; + uint64_t pfr_dis:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_pow_int_ctl_s cn30xx; struct cvmx_pow_int_ctl_s cn31xx; @@ -233,15 +425,23 @@ union cvmx_pow_int_ctl { struct cvmx_pow_int_ctl_s cn56xxp1; struct cvmx_pow_int_ctl_s cn58xx; struct cvmx_pow_int_ctl_s cn58xxp1; + struct cvmx_pow_int_ctl_s cn61xx; struct cvmx_pow_int_ctl_s cn63xx; struct cvmx_pow_int_ctl_s cn63xxp1; + struct cvmx_pow_int_ctl_s cn66xx; + struct cvmx_pow_int_ctl_s cnf71xx; }; union cvmx_pow_iq_cntx { uint64_t u64; struct cvmx_pow_iq_cntx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iq_cnt:32; +#else + uint64_t iq_cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_iq_cntx_s cn30xx; struct cvmx_pow_iq_cntx_s cn31xx; @@ -254,15 +454,23 @@ union cvmx_pow_iq_cntx { struct cvmx_pow_iq_cntx_s cn56xxp1; struct cvmx_pow_iq_cntx_s cn58xx; struct cvmx_pow_iq_cntx_s cn58xxp1; + struct cvmx_pow_iq_cntx_s cn61xx; struct cvmx_pow_iq_cntx_s cn63xx; struct cvmx_pow_iq_cntx_s cn63xxp1; + struct cvmx_pow_iq_cntx_s cn66xx; + struct cvmx_pow_iq_cntx_s cnf71xx; }; union cvmx_pow_iq_com_cnt { uint64_t u64; struct cvmx_pow_iq_com_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iq_cnt:32; +#else + uint64_t iq_cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_iq_com_cnt_s cn30xx; struct cvmx_pow_iq_com_cnt_s cn31xx; @@ -275,90 +483,150 @@ union cvmx_pow_iq_com_cnt { struct cvmx_pow_iq_com_cnt_s cn56xxp1; struct cvmx_pow_iq_com_cnt_s cn58xx; struct cvmx_pow_iq_com_cnt_s cn58xxp1; + struct cvmx_pow_iq_com_cnt_s cn61xx; struct cvmx_pow_iq_com_cnt_s cn63xx; struct cvmx_pow_iq_com_cnt_s cn63xxp1; + struct cvmx_pow_iq_com_cnt_s cn66xx; + struct cvmx_pow_iq_com_cnt_s cnf71xx; }; union cvmx_pow_iq_int { uint64_t u64; struct cvmx_pow_iq_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t iq_int:8; +#else + uint64_t iq_int:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_pow_iq_int_s cn52xx; struct cvmx_pow_iq_int_s cn52xxp1; struct cvmx_pow_iq_int_s cn56xx; struct cvmx_pow_iq_int_s cn56xxp1; + struct cvmx_pow_iq_int_s cn61xx; struct cvmx_pow_iq_int_s cn63xx; struct cvmx_pow_iq_int_s cn63xxp1; + struct cvmx_pow_iq_int_s cn66xx; + struct cvmx_pow_iq_int_s cnf71xx; }; union cvmx_pow_iq_int_en { uint64_t u64; struct cvmx_pow_iq_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t int_en:8; +#else + uint64_t int_en:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_pow_iq_int_en_s cn52xx; struct cvmx_pow_iq_int_en_s cn52xxp1; struct cvmx_pow_iq_int_en_s cn56xx; struct cvmx_pow_iq_int_en_s cn56xxp1; + struct cvmx_pow_iq_int_en_s cn61xx; struct cvmx_pow_iq_int_en_s cn63xx; struct cvmx_pow_iq_int_en_s cn63xxp1; + struct cvmx_pow_iq_int_en_s cn66xx; + struct cvmx_pow_iq_int_en_s cnf71xx; }; union cvmx_pow_iq_thrx { uint64_t u64; struct cvmx_pow_iq_thrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iq_thr:32; +#else + uint64_t iq_thr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_iq_thrx_s cn52xx; struct cvmx_pow_iq_thrx_s cn52xxp1; struct cvmx_pow_iq_thrx_s cn56xx; struct cvmx_pow_iq_thrx_s cn56xxp1; + struct cvmx_pow_iq_thrx_s cn61xx; struct cvmx_pow_iq_thrx_s cn63xx; struct cvmx_pow_iq_thrx_s cn63xxp1; + struct cvmx_pow_iq_thrx_s cn66xx; + struct cvmx_pow_iq_thrx_s cnf71xx; }; union cvmx_pow_nos_cnt { uint64_t u64; struct cvmx_pow_nos_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t nos_cnt:12; +#else + uint64_t nos_cnt:12; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_pow_nos_cnt_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t nos_cnt:7; +#else + uint64_t nos_cnt:7; + uint64_t reserved_7_63:57; +#endif } cn30xx; struct cvmx_pow_nos_cnt_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t nos_cnt:9; +#else + uint64_t nos_cnt:9; + uint64_t reserved_9_63:55; +#endif } cn31xx; struct cvmx_pow_nos_cnt_s cn38xx; struct cvmx_pow_nos_cnt_s cn38xxp2; struct cvmx_pow_nos_cnt_cn31xx cn50xx; struct cvmx_pow_nos_cnt_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t nos_cnt:10; +#else + uint64_t nos_cnt:10; + uint64_t reserved_10_63:54; +#endif } cn52xx; struct cvmx_pow_nos_cnt_cn52xx cn52xxp1; struct cvmx_pow_nos_cnt_s cn56xx; struct cvmx_pow_nos_cnt_s cn56xxp1; struct cvmx_pow_nos_cnt_s cn58xx; struct cvmx_pow_nos_cnt_s cn58xxp1; + struct cvmx_pow_nos_cnt_cn52xx cn61xx; struct cvmx_pow_nos_cnt_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t nos_cnt:11; +#else + uint64_t nos_cnt:11; + uint64_t reserved_11_63:53; +#endif } cn63xx; struct cvmx_pow_nos_cnt_cn63xx cn63xxp1; + struct cvmx_pow_nos_cnt_cn63xx cn66xx; + struct cvmx_pow_nos_cnt_cn52xx cnf71xx; }; union cvmx_pow_nw_tim { uint64_t u64; struct cvmx_pow_nw_tim_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t nw_tim:10; +#else + uint64_t nw_tim:10; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_pow_nw_tim_s cn30xx; struct cvmx_pow_nw_tim_s cn31xx; @@ -371,15 +639,23 @@ union cvmx_pow_nw_tim { struct cvmx_pow_nw_tim_s cn56xxp1; struct cvmx_pow_nw_tim_s cn58xx; struct cvmx_pow_nw_tim_s cn58xxp1; + struct cvmx_pow_nw_tim_s cn61xx; struct cvmx_pow_nw_tim_s cn63xx; struct cvmx_pow_nw_tim_s cn63xxp1; + struct cvmx_pow_nw_tim_s cn66xx; + struct cvmx_pow_nw_tim_s cnf71xx; }; union cvmx_pow_pf_rst_msk { uint64_t u64; struct cvmx_pow_pf_rst_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rst_msk:8; +#else + uint64_t rst_msk:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_pow_pf_rst_msk_s cn50xx; struct cvmx_pow_pf_rst_msk_s cn52xx; @@ -388,13 +664,17 @@ union cvmx_pow_pf_rst_msk { struct cvmx_pow_pf_rst_msk_s cn56xxp1; struct cvmx_pow_pf_rst_msk_s cn58xx; struct cvmx_pow_pf_rst_msk_s cn58xxp1; + struct cvmx_pow_pf_rst_msk_s cn61xx; struct cvmx_pow_pf_rst_msk_s cn63xx; struct cvmx_pow_pf_rst_msk_s cn63xxp1; + struct cvmx_pow_pf_rst_msk_s cn66xx; + struct cvmx_pow_pf_rst_msk_s cnf71xx; }; union cvmx_pow_pp_grp_mskx { uint64_t u64; struct cvmx_pow_pp_grp_mskx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t qos7_pri:4; uint64_t qos6_pri:4; @@ -405,10 +685,27 @@ union cvmx_pow_pp_grp_mskx { uint64_t qos1_pri:4; uint64_t qos0_pri:4; uint64_t grp_msk:16; +#else + uint64_t grp_msk:16; + uint64_t qos0_pri:4; + uint64_t qos1_pri:4; + uint64_t qos2_pri:4; + uint64_t qos3_pri:4; + uint64_t qos4_pri:4; + uint64_t qos5_pri:4; + uint64_t qos6_pri:4; + uint64_t qos7_pri:4; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_pow_pp_grp_mskx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t grp_msk:16; +#else + uint64_t grp_msk:16; + uint64_t reserved_16_63:48; +#endif } cn30xx; struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx; struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx; @@ -420,18 +717,29 @@ union cvmx_pow_pp_grp_mskx { struct cvmx_pow_pp_grp_mskx_s cn56xxp1; struct cvmx_pow_pp_grp_mskx_s cn58xx; struct cvmx_pow_pp_grp_mskx_s cn58xxp1; + struct cvmx_pow_pp_grp_mskx_s cn61xx; struct cvmx_pow_pp_grp_mskx_s cn63xx; struct cvmx_pow_pp_grp_mskx_s cn63xxp1; + struct cvmx_pow_pp_grp_mskx_s cn66xx; + struct cvmx_pow_pp_grp_mskx_s cnf71xx; }; union cvmx_pow_qos_rndx { uint64_t u64; struct cvmx_pow_qos_rndx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rnd_p3:8; uint64_t rnd_p2:8; uint64_t rnd_p1:8; uint64_t rnd:8; +#else + uint64_t rnd:8; + uint64_t rnd_p1:8; + uint64_t rnd_p2:8; + uint64_t rnd_p3:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_qos_rndx_s cn30xx; struct cvmx_pow_qos_rndx_s cn31xx; @@ -444,13 +752,17 @@ union cvmx_pow_qos_rndx { struct cvmx_pow_qos_rndx_s cn56xxp1; struct cvmx_pow_qos_rndx_s cn58xx; struct cvmx_pow_qos_rndx_s cn58xxp1; + struct cvmx_pow_qos_rndx_s cn61xx; struct cvmx_pow_qos_rndx_s cn63xx; struct cvmx_pow_qos_rndx_s cn63xxp1; + struct cvmx_pow_qos_rndx_s cn66xx; + struct cvmx_pow_qos_rndx_s cnf71xx; }; union cvmx_pow_qos_thrx { uint64_t u64; struct cvmx_pow_qos_thrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t des_cnt:12; uint64_t buf_cnt:12; @@ -459,8 +771,19 @@ union cvmx_pow_qos_thrx { uint64_t max_thr:11; uint64_t reserved_11_11:1; uint64_t min_thr:11; +#else + uint64_t min_thr:11; + uint64_t reserved_11_11:1; + uint64_t max_thr:11; + uint64_t reserved_23_23:1; + uint64_t free_cnt:12; + uint64_t buf_cnt:12; + uint64_t des_cnt:12; + uint64_t reserved_60_63:4; +#endif } s; struct cvmx_pow_qos_thrx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_55_63:9; uint64_t des_cnt:7; uint64_t reserved_43_47:5; @@ -471,8 +794,21 @@ union cvmx_pow_qos_thrx { uint64_t max_thr:6; uint64_t reserved_6_11:6; uint64_t min_thr:6; +#else + uint64_t min_thr:6; + uint64_t reserved_6_11:6; + uint64_t max_thr:6; + uint64_t reserved_18_23:6; + uint64_t free_cnt:7; + uint64_t reserved_31_35:5; + uint64_t buf_cnt:7; + uint64_t reserved_43_47:5; + uint64_t des_cnt:7; + uint64_t reserved_55_63:9; +#endif } cn30xx; struct cvmx_pow_qos_thrx_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_57_63:7; uint64_t des_cnt:9; uint64_t reserved_45_47:3; @@ -483,11 +819,24 @@ union cvmx_pow_qos_thrx { uint64_t max_thr:8; uint64_t reserved_8_11:4; uint64_t min_thr:8; +#else + uint64_t min_thr:8; + uint64_t reserved_8_11:4; + uint64_t max_thr:8; + uint64_t reserved_20_23:4; + uint64_t free_cnt:9; + uint64_t reserved_33_35:3; + uint64_t buf_cnt:9; + uint64_t reserved_45_47:3; + uint64_t des_cnt:9; + uint64_t reserved_57_63:7; +#endif } cn31xx; struct cvmx_pow_qos_thrx_s cn38xx; struct cvmx_pow_qos_thrx_s cn38xxp2; struct cvmx_pow_qos_thrx_cn31xx cn50xx; struct cvmx_pow_qos_thrx_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t des_cnt:10; uint64_t reserved_46_47:2; @@ -498,13 +847,27 @@ union cvmx_pow_qos_thrx { uint64_t max_thr:9; uint64_t reserved_9_11:3; uint64_t min_thr:9; +#else + uint64_t min_thr:9; + uint64_t reserved_9_11:3; + uint64_t max_thr:9; + uint64_t reserved_21_23:3; + uint64_t free_cnt:10; + uint64_t reserved_34_35:2; + uint64_t buf_cnt:10; + uint64_t reserved_46_47:2; + uint64_t des_cnt:10; + uint64_t reserved_58_63:6; +#endif } cn52xx; struct cvmx_pow_qos_thrx_cn52xx cn52xxp1; struct cvmx_pow_qos_thrx_s cn56xx; struct cvmx_pow_qos_thrx_s cn56xxp1; struct cvmx_pow_qos_thrx_s cn58xx; struct cvmx_pow_qos_thrx_s cn58xxp1; + struct cvmx_pow_qos_thrx_cn52xx cn61xx; struct cvmx_pow_qos_thrx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t des_cnt:11; uint64_t reserved_47_47:1; @@ -515,15 +878,34 @@ union cvmx_pow_qos_thrx { uint64_t max_thr:10; uint64_t reserved_10_11:2; uint64_t min_thr:10; +#else + uint64_t min_thr:10; + uint64_t reserved_10_11:2; + uint64_t max_thr:10; + uint64_t reserved_22_23:2; + uint64_t free_cnt:11; + uint64_t reserved_35_35:1; + uint64_t buf_cnt:11; + uint64_t reserved_47_47:1; + uint64_t des_cnt:11; + uint64_t reserved_59_63:5; +#endif } cn63xx; struct cvmx_pow_qos_thrx_cn63xx cn63xxp1; + struct cvmx_pow_qos_thrx_cn63xx cn66xx; + struct cvmx_pow_qos_thrx_cn52xx cnf71xx; }; union cvmx_pow_ts_pc { uint64_t u64; struct cvmx_pow_ts_pc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ts_pc:32; +#else + uint64_t ts_pc:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_ts_pc_s cn30xx; struct cvmx_pow_ts_pc_s cn31xx; @@ -536,15 +918,23 @@ union cvmx_pow_ts_pc { struct cvmx_pow_ts_pc_s cn56xxp1; struct cvmx_pow_ts_pc_s cn58xx; struct cvmx_pow_ts_pc_s cn58xxp1; + struct cvmx_pow_ts_pc_s cn61xx; struct cvmx_pow_ts_pc_s cn63xx; struct cvmx_pow_ts_pc_s cn63xxp1; + struct cvmx_pow_ts_pc_s cn66xx; + struct cvmx_pow_ts_pc_s cnf71xx; }; union cvmx_pow_wa_com_pc { uint64_t u64; struct cvmx_pow_wa_com_pc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t wa_pc:32; +#else + uint64_t wa_pc:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_wa_com_pc_s cn30xx; struct cvmx_pow_wa_com_pc_s cn31xx; @@ -557,15 +947,23 @@ union cvmx_pow_wa_com_pc { struct cvmx_pow_wa_com_pc_s cn56xxp1; struct cvmx_pow_wa_com_pc_s cn58xx; struct cvmx_pow_wa_com_pc_s cn58xxp1; + struct cvmx_pow_wa_com_pc_s cn61xx; struct cvmx_pow_wa_com_pc_s cn63xx; struct cvmx_pow_wa_com_pc_s cn63xxp1; + struct cvmx_pow_wa_com_pc_s cn66xx; + struct cvmx_pow_wa_com_pc_s cnf71xx; }; union cvmx_pow_wa_pcx { uint64_t u64; struct cvmx_pow_wa_pcx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t wa_pc:32; +#else + uint64_t wa_pc:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_wa_pcx_s cn30xx; struct cvmx_pow_wa_pcx_s cn31xx; @@ -578,16 +976,25 @@ union cvmx_pow_wa_pcx { struct cvmx_pow_wa_pcx_s cn56xxp1; struct cvmx_pow_wa_pcx_s cn58xx; struct cvmx_pow_wa_pcx_s cn58xxp1; + struct cvmx_pow_wa_pcx_s cn61xx; struct cvmx_pow_wa_pcx_s cn63xx; struct cvmx_pow_wa_pcx_s cn63xxp1; + struct cvmx_pow_wa_pcx_s cn66xx; + struct cvmx_pow_wa_pcx_s cnf71xx; }; union cvmx_pow_wq_int { uint64_t u64; struct cvmx_pow_wq_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iq_dis:16; uint64_t wq_int:16; +#else + uint64_t wq_int:16; + uint64_t iq_dis:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_wq_int_s cn30xx; struct cvmx_pow_wq_int_s cn31xx; @@ -600,69 +1007,126 @@ union cvmx_pow_wq_int { struct cvmx_pow_wq_int_s cn56xxp1; struct cvmx_pow_wq_int_s cn58xx; struct cvmx_pow_wq_int_s cn58xxp1; + struct cvmx_pow_wq_int_s cn61xx; struct cvmx_pow_wq_int_s cn63xx; struct cvmx_pow_wq_int_s cn63xxp1; + struct cvmx_pow_wq_int_s cn66xx; + struct cvmx_pow_wq_int_s cnf71xx; }; union cvmx_pow_wq_int_cntx { uint64_t u64; struct cvmx_pow_wq_int_cntx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t tc_cnt:4; uint64_t ds_cnt:12; uint64_t iq_cnt:12; +#else + uint64_t iq_cnt:12; + uint64_t ds_cnt:12; + uint64_t tc_cnt:4; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_pow_wq_int_cntx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t tc_cnt:4; uint64_t reserved_19_23:5; uint64_t ds_cnt:7; uint64_t reserved_7_11:5; uint64_t iq_cnt:7; +#else + uint64_t iq_cnt:7; + uint64_t reserved_7_11:5; + uint64_t ds_cnt:7; + uint64_t reserved_19_23:5; + uint64_t tc_cnt:4; + uint64_t reserved_28_63:36; +#endif } cn30xx; struct cvmx_pow_wq_int_cntx_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t tc_cnt:4; uint64_t reserved_21_23:3; uint64_t ds_cnt:9; uint64_t reserved_9_11:3; uint64_t iq_cnt:9; +#else + uint64_t iq_cnt:9; + uint64_t reserved_9_11:3; + uint64_t ds_cnt:9; + uint64_t reserved_21_23:3; + uint64_t tc_cnt:4; + uint64_t reserved_28_63:36; +#endif } cn31xx; struct cvmx_pow_wq_int_cntx_s cn38xx; struct cvmx_pow_wq_int_cntx_s cn38xxp2; struct cvmx_pow_wq_int_cntx_cn31xx cn50xx; struct cvmx_pow_wq_int_cntx_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t tc_cnt:4; uint64_t reserved_22_23:2; uint64_t ds_cnt:10; uint64_t reserved_10_11:2; uint64_t iq_cnt:10; +#else + uint64_t iq_cnt:10; + uint64_t reserved_10_11:2; + uint64_t ds_cnt:10; + uint64_t reserved_22_23:2; + uint64_t tc_cnt:4; + uint64_t reserved_28_63:36; +#endif } cn52xx; struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1; struct cvmx_pow_wq_int_cntx_s cn56xx; struct cvmx_pow_wq_int_cntx_s cn56xxp1; struct cvmx_pow_wq_int_cntx_s cn58xx; struct cvmx_pow_wq_int_cntx_s cn58xxp1; + struct cvmx_pow_wq_int_cntx_cn52xx cn61xx; struct cvmx_pow_wq_int_cntx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t tc_cnt:4; uint64_t reserved_23_23:1; uint64_t ds_cnt:11; uint64_t reserved_11_11:1; uint64_t iq_cnt:11; +#else + uint64_t iq_cnt:11; + uint64_t reserved_11_11:1; + uint64_t ds_cnt:11; + uint64_t reserved_23_23:1; + uint64_t tc_cnt:4; + uint64_t reserved_28_63:36; +#endif } cn63xx; struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1; + struct cvmx_pow_wq_int_cntx_cn63xx cn66xx; + struct cvmx_pow_wq_int_cntx_cn52xx cnf71xx; }; union cvmx_pow_wq_int_pc { uint64_t u64; struct cvmx_pow_wq_int_pc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t pc:28; uint64_t reserved_28_31:4; uint64_t pc_thr:20; uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t pc_thr:20; + uint64_t reserved_28_31:4; + uint64_t pc:28; + uint64_t reserved_60_63:4; +#endif } s; struct cvmx_pow_wq_int_pc_s cn30xx; struct cvmx_pow_wq_int_pc_s cn31xx; @@ -675,13 +1139,17 @@ union cvmx_pow_wq_int_pc { struct cvmx_pow_wq_int_pc_s cn56xxp1; struct cvmx_pow_wq_int_pc_s cn58xx; struct cvmx_pow_wq_int_pc_s cn58xxp1; + struct cvmx_pow_wq_int_pc_s cn61xx; struct cvmx_pow_wq_int_pc_s cn63xx; struct cvmx_pow_wq_int_pc_s cn63xxp1; + struct cvmx_pow_wq_int_pc_s cn66xx; + struct cvmx_pow_wq_int_pc_s cnf71xx; }; union cvmx_pow_wq_int_thrx { uint64_t u64; struct cvmx_pow_wq_int_thrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t tc_en:1; uint64_t tc_thr:4; @@ -689,8 +1157,18 @@ union cvmx_pow_wq_int_thrx { uint64_t ds_thr:11; uint64_t reserved_11_11:1; uint64_t iq_thr:11; +#else + uint64_t iq_thr:11; + uint64_t reserved_11_11:1; + uint64_t ds_thr:11; + uint64_t reserved_23_23:1; + uint64_t tc_thr:4; + uint64_t tc_en:1; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_pow_wq_int_thrx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t tc_en:1; uint64_t tc_thr:4; @@ -698,8 +1176,18 @@ union cvmx_pow_wq_int_thrx { uint64_t ds_thr:6; uint64_t reserved_6_11:6; uint64_t iq_thr:6; +#else + uint64_t iq_thr:6; + uint64_t reserved_6_11:6; + uint64_t ds_thr:6; + uint64_t reserved_18_23:6; + uint64_t tc_thr:4; + uint64_t tc_en:1; + uint64_t reserved_29_63:35; +#endif } cn30xx; struct cvmx_pow_wq_int_thrx_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t tc_en:1; uint64_t tc_thr:4; @@ -707,11 +1195,21 @@ union cvmx_pow_wq_int_thrx { uint64_t ds_thr:8; uint64_t reserved_8_11:4; uint64_t iq_thr:8; +#else + uint64_t iq_thr:8; + uint64_t reserved_8_11:4; + uint64_t ds_thr:8; + uint64_t reserved_20_23:4; + uint64_t tc_thr:4; + uint64_t tc_en:1; + uint64_t reserved_29_63:35; +#endif } cn31xx; struct cvmx_pow_wq_int_thrx_s cn38xx; struct cvmx_pow_wq_int_thrx_s cn38xxp2; struct cvmx_pow_wq_int_thrx_cn31xx cn50xx; struct cvmx_pow_wq_int_thrx_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t tc_en:1; uint64_t tc_thr:4; @@ -719,13 +1217,24 @@ union cvmx_pow_wq_int_thrx { uint64_t ds_thr:9; uint64_t reserved_9_11:3; uint64_t iq_thr:9; +#else + uint64_t iq_thr:9; + uint64_t reserved_9_11:3; + uint64_t ds_thr:9; + uint64_t reserved_21_23:3; + uint64_t tc_thr:4; + uint64_t tc_en:1; + uint64_t reserved_29_63:35; +#endif } cn52xx; struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1; struct cvmx_pow_wq_int_thrx_s cn56xx; struct cvmx_pow_wq_int_thrx_s cn56xxp1; struct cvmx_pow_wq_int_thrx_s cn58xx; struct cvmx_pow_wq_int_thrx_s cn58xxp1; + struct cvmx_pow_wq_int_thrx_cn52xx cn61xx; struct cvmx_pow_wq_int_thrx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t tc_en:1; uint64_t tc_thr:4; @@ -733,15 +1242,31 @@ union cvmx_pow_wq_int_thrx { uint64_t ds_thr:10; uint64_t reserved_10_11:2; uint64_t iq_thr:10; +#else + uint64_t iq_thr:10; + uint64_t reserved_10_11:2; + uint64_t ds_thr:10; + uint64_t reserved_22_23:2; + uint64_t tc_thr:4; + uint64_t tc_en:1; + uint64_t reserved_29_63:35; +#endif } cn63xx; struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1; + struct cvmx_pow_wq_int_thrx_cn63xx cn66xx; + struct cvmx_pow_wq_int_thrx_cn52xx cnf71xx; }; union cvmx_pow_ws_pcx { uint64_t u64; struct cvmx_pow_ws_pcx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ws_pc:32; +#else + uint64_t ws_pc:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_ws_pcx_s cn30xx; struct cvmx_pow_ws_pcx_s cn31xx; @@ -754,8 +1279,11 @@ union cvmx_pow_ws_pcx { struct cvmx_pow_ws_pcx_s cn56xxp1; struct cvmx_pow_ws_pcx_s cn58xx; struct cvmx_pow_ws_pcx_s cn58xxp1; + struct cvmx_pow_ws_pcx_s cn61xx; struct cvmx_pow_ws_pcx_s cn63xx; struct cvmx_pow_ws_pcx_s cn63xxp1; + struct cvmx_pow_ws_pcx_s cn66xx; + struct cvmx_pow_ws_pcx_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h index c45da1f35ea7..87d6f92a548a 100644 --- a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,8 +28,6 @@ #ifndef __CVMX_RNM_DEFS_H__ #define __CVMX_RNM_DEFS_H__ -#include <linux/types.h> - #define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull)) #define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull)) #define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull)) @@ -39,9 +37,15 @@ union cvmx_rnm_bist_status { uint64_t u64; struct cvmx_rnm_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t rrc:1; uint64_t mem:1; +#else + uint64_t mem:1; + uint64_t rrc:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_rnm_bist_status_s cn30xx; struct cvmx_rnm_bist_status_s cn31xx; @@ -54,14 +58,21 @@ union cvmx_rnm_bist_status { struct cvmx_rnm_bist_status_s cn56xxp1; struct cvmx_rnm_bist_status_s cn58xx; struct cvmx_rnm_bist_status_s cn58xxp1; + struct cvmx_rnm_bist_status_s cn61xx; struct cvmx_rnm_bist_status_s cn63xx; struct cvmx_rnm_bist_status_s cn63xxp1; + struct cvmx_rnm_bist_status_s cn66xx; + struct cvmx_rnm_bist_status_s cn68xx; + struct cvmx_rnm_bist_status_s cn68xxp1; + struct cvmx_rnm_bist_status_s cnf71xx; }; union cvmx_rnm_ctl_status { uint64_t u64; struct cvmx_rnm_ctl_status_s { - uint64_t reserved_11_63:53; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t dis_mak:1; uint64_t eer_lck:1; uint64_t eer_val:1; uint64_t ent_sel:4; @@ -70,18 +81,39 @@ union cvmx_rnm_ctl_status { uint64_t rnm_rst:1; uint64_t rng_en:1; uint64_t ent_en:1; +#else + uint64_t ent_en:1; + uint64_t rng_en:1; + uint64_t rnm_rst:1; + uint64_t rng_rst:1; + uint64_t exp_ent:1; + uint64_t ent_sel:4; + uint64_t eer_val:1; + uint64_t eer_lck:1; + uint64_t dis_mak:1; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_rnm_ctl_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t rng_rst:1; uint64_t rnm_rst:1; uint64_t rng_en:1; uint64_t ent_en:1; +#else + uint64_t ent_en:1; + uint64_t rng_en:1; + uint64_t rnm_rst:1; + uint64_t rng_rst:1; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_rnm_ctl_status_cn30xx cn31xx; struct cvmx_rnm_ctl_status_cn30xx cn38xx; struct cvmx_rnm_ctl_status_cn30xx cn38xxp2; struct cvmx_rnm_ctl_status_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t ent_sel:4; uint64_t exp_ent:1; @@ -89,6 +121,15 @@ union cvmx_rnm_ctl_status { uint64_t rnm_rst:1; uint64_t rng_en:1; uint64_t ent_en:1; +#else + uint64_t ent_en:1; + uint64_t rng_en:1; + uint64_t rnm_rst:1; + uint64_t rng_rst:1; + uint64_t exp_ent:1; + uint64_t ent_sel:4; + uint64_t reserved_9_63:55; +#endif } cn50xx; struct cvmx_rnm_ctl_status_cn50xx cn52xx; struct cvmx_rnm_ctl_status_cn50xx cn52xxp1; @@ -96,34 +137,88 @@ union cvmx_rnm_ctl_status { struct cvmx_rnm_ctl_status_cn50xx cn56xxp1; struct cvmx_rnm_ctl_status_cn50xx cn58xx; struct cvmx_rnm_ctl_status_cn50xx cn58xxp1; - struct cvmx_rnm_ctl_status_s cn63xx; - struct cvmx_rnm_ctl_status_s cn63xxp1; + struct cvmx_rnm_ctl_status_s cn61xx; + struct cvmx_rnm_ctl_status_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t eer_lck:1; + uint64_t eer_val:1; + uint64_t ent_sel:4; + uint64_t exp_ent:1; + uint64_t rng_rst:1; + uint64_t rnm_rst:1; + uint64_t rng_en:1; + uint64_t ent_en:1; +#else + uint64_t ent_en:1; + uint64_t rng_en:1; + uint64_t rnm_rst:1; + uint64_t rng_rst:1; + uint64_t exp_ent:1; + uint64_t ent_sel:4; + uint64_t eer_val:1; + uint64_t eer_lck:1; + uint64_t reserved_11_63:53; +#endif + } cn63xx; + struct cvmx_rnm_ctl_status_cn63xx cn63xxp1; + struct cvmx_rnm_ctl_status_s cn66xx; + struct cvmx_rnm_ctl_status_cn63xx cn68xx; + struct cvmx_rnm_ctl_status_cn63xx cn68xxp1; + struct cvmx_rnm_ctl_status_s cnf71xx; }; union cvmx_rnm_eer_dbg { uint64_t u64; struct cvmx_rnm_eer_dbg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dat:64; +#else + uint64_t dat:64; +#endif } s; + struct cvmx_rnm_eer_dbg_s cn61xx; struct cvmx_rnm_eer_dbg_s cn63xx; struct cvmx_rnm_eer_dbg_s cn63xxp1; + struct cvmx_rnm_eer_dbg_s cn66xx; + struct cvmx_rnm_eer_dbg_s cn68xx; + struct cvmx_rnm_eer_dbg_s cn68xxp1; + struct cvmx_rnm_eer_dbg_s cnf71xx; }; union cvmx_rnm_eer_key { uint64_t u64; struct cvmx_rnm_eer_key_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t key:64; +#else uint64_t key:64; +#endif } s; + struct cvmx_rnm_eer_key_s cn61xx; struct cvmx_rnm_eer_key_s cn63xx; struct cvmx_rnm_eer_key_s cn63xxp1; + struct cvmx_rnm_eer_key_s cn66xx; + struct cvmx_rnm_eer_key_s cn68xx; + struct cvmx_rnm_eer_key_s cn68xxp1; + struct cvmx_rnm_eer_key_s cnf71xx; }; union cvmx_rnm_serial_num { uint64_t u64; struct cvmx_rnm_serial_num_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dat:64; +#else uint64_t dat:64; +#endif } s; + struct cvmx_rnm_serial_num_s cn61xx; struct cvmx_rnm_serial_num_s cn63xx; + struct cvmx_rnm_serial_num_s cn66xx; + struct cvmx_rnm_serial_num_s cn68xx; + struct cvmx_rnm_serial_num_s cn68xxp1; + struct cvmx_rnm_serial_num_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/arch/mips/include/asm/octeon/cvmx-sli-defs.h index 7c6c901d3d28..e697c2f52a62 100644 --- a/arch/mips/include/asm/octeon/cvmx-sli-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-sli-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2011 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -127,6 +127,7 @@ union cvmx_sli_bist_status { uint64_t u64; struct cvmx_sli_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ncb_req:1; uint64_t n2p0_c:1; @@ -153,8 +154,37 @@ union cvmx_sli_bist_status { uint64_t dsi0_0:1; uint64_t msi:1; uint64_t ncb_cmd:1; +#else + uint64_t ncb_cmd:1; + uint64_t msi:1; + uint64_t dsi0_0:1; + uint64_t dsi0_1:1; + uint64_t dsi1_0:1; + uint64_t dsi1_1:1; + uint64_t reserved_6_8:3; + uint64_t p2n1_p1:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_n:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_c0:1; + uint64_t p2n0_p1:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_n:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_c0:1; + uint64_t reserved_19_24:6; + uint64_t cpl_p1:1; + uint64_t cpl_p0:1; + uint64_t n2p1_o:1; + uint64_t n2p1_c:1; + uint64_t n2p0_o:1; + uint64_t n2p0_c:1; + uint64_t ncb_req:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_bist_status_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t n2p0_c:1; uint64_t n2p0_o:1; @@ -179,8 +209,35 @@ union cvmx_sli_bist_status { uint64_t dsi0_0:1; uint64_t msi:1; uint64_t ncb_cmd:1; +#else + uint64_t ncb_cmd:1; + uint64_t msi:1; + uint64_t dsi0_0:1; + uint64_t dsi0_1:1; + uint64_t dsi1_0:1; + uint64_t dsi1_1:1; + uint64_t reserved_6_8:3; + uint64_t p2n1_p1:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_n:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_c0:1; + uint64_t p2n0_p1:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_n:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_c0:1; + uint64_t reserved_19_24:6; + uint64_t cpl_p1:1; + uint64_t cpl_p0:1; + uint64_t reserved_27_28:2; + uint64_t n2p0_o:1; + uint64_t n2p0_c:1; + uint64_t reserved_31_63:33; +#endif } cn61xx; struct cvmx_sli_bist_status_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t n2p0_c:1; uint64_t n2p0_o:1; @@ -206,16 +263,45 @@ union cvmx_sli_bist_status { uint64_t dsi0_0:1; uint64_t msi:1; uint64_t ncb_cmd:1; +#else + uint64_t ncb_cmd:1; + uint64_t msi:1; + uint64_t dsi0_0:1; + uint64_t dsi0_1:1; + uint64_t dsi1_0:1; + uint64_t dsi1_1:1; + uint64_t reserved_6_8:3; + uint64_t p2n1_p1:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_n:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_c0:1; + uint64_t p2n0_p1:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_n:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_c0:1; + uint64_t reserved_19_24:6; + uint64_t cpl_p1:1; + uint64_t cpl_p0:1; + uint64_t n2p1_o:1; + uint64_t n2p1_c:1; + uint64_t n2p0_o:1; + uint64_t n2p0_c:1; + uint64_t reserved_31_63:33; +#endif } cn63xx; struct cvmx_sli_bist_status_cn63xx cn63xxp1; struct cvmx_sli_bist_status_cn61xx cn66xx; struct cvmx_sli_bist_status_s cn68xx; struct cvmx_sli_bist_status_s cn68xxp1; + struct cvmx_sli_bist_status_cn61xx cnf71xx; }; union cvmx_sli_ctl_portx { uint64_t u64; struct cvmx_sli_ctl_portx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t intd:1; uint64_t intc:1; @@ -232,6 +318,24 @@ union cvmx_sli_ctl_portx { uint64_t ptlp_ro:1; uint64_t reserved_1_4:4; uint64_t wait_com:1; +#else + uint64_t wait_com:1; + uint64_t reserved_1_4:4; + uint64_t ptlp_ro:1; + uint64_t reserved_6_6:1; + uint64_t ctlp_ro:1; + uint64_t inta_map:2; + uint64_t intb_map:2; + uint64_t intc_map:2; + uint64_t intd_map:2; + uint64_t waitl_com:1; + uint64_t dis_port:1; + uint64_t inta:1; + uint64_t intb:1; + uint64_t intc:1; + uint64_t intd:1; + uint64_t reserved_22_63:42; +#endif } s; struct cvmx_sli_ctl_portx_s cn61xx; struct cvmx_sli_ctl_portx_s cn63xx; @@ -239,36 +343,59 @@ union cvmx_sli_ctl_portx { struct cvmx_sli_ctl_portx_s cn66xx; struct cvmx_sli_ctl_portx_s cn68xx; struct cvmx_sli_ctl_portx_s cn68xxp1; + struct cvmx_sli_ctl_portx_s cnf71xx; }; union cvmx_sli_ctl_status { uint64_t u64; struct cvmx_sli_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t p1_ntags:6; uint64_t p0_ntags:6; uint64_t chip_rev:8; +#else + uint64_t chip_rev:8; + uint64_t p0_ntags:6; + uint64_t p1_ntags:6; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_sli_ctl_status_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t p0_ntags:6; uint64_t chip_rev:8; +#else + uint64_t chip_rev:8; + uint64_t p0_ntags:6; + uint64_t reserved_14_63:50; +#endif } cn61xx; struct cvmx_sli_ctl_status_s cn63xx; struct cvmx_sli_ctl_status_s cn63xxp1; struct cvmx_sli_ctl_status_cn61xx cn66xx; struct cvmx_sli_ctl_status_s cn68xx; struct cvmx_sli_ctl_status_s cn68xxp1; + struct cvmx_sli_ctl_status_cn61xx cnf71xx; }; union cvmx_sli_data_out_cnt { uint64_t u64; struct cvmx_sli_data_out_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t p1_ucnt:16; uint64_t p1_fcnt:6; uint64_t p0_ucnt:16; uint64_t p0_fcnt:6; +#else + uint64_t p0_fcnt:6; + uint64_t p0_ucnt:16; + uint64_t p1_fcnt:6; + uint64_t p1_ucnt:16; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_sli_data_out_cnt_s cn61xx; struct cvmx_sli_data_out_cnt_s cn63xx; @@ -276,14 +403,21 @@ union cvmx_sli_data_out_cnt { struct cvmx_sli_data_out_cnt_s cn66xx; struct cvmx_sli_data_out_cnt_s cn68xx; struct cvmx_sli_data_out_cnt_s cn68xxp1; + struct cvmx_sli_data_out_cnt_s cnf71xx; }; union cvmx_sli_dbg_data { uint64_t u64; struct cvmx_sli_dbg_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_sli_dbg_data_s cn61xx; struct cvmx_sli_dbg_data_s cn63xx; @@ -291,14 +425,21 @@ union cvmx_sli_dbg_data { struct cvmx_sli_dbg_data_s cn66xx; struct cvmx_sli_dbg_data_s cn68xx; struct cvmx_sli_dbg_data_s cn68xxp1; + struct cvmx_sli_dbg_data_s cnf71xx; }; union cvmx_sli_dbg_select { uint64_t u64; struct cvmx_sli_dbg_select_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_33_63:31; uint64_t adbg_sel:1; uint64_t dbg_sel:32; +#else + uint64_t dbg_sel:32; + uint64_t adbg_sel:1; + uint64_t reserved_33_63:31; +#endif } s; struct cvmx_sli_dbg_select_s cn61xx; struct cvmx_sli_dbg_select_s cn63xx; @@ -306,13 +447,19 @@ union cvmx_sli_dbg_select { struct cvmx_sli_dbg_select_s cn66xx; struct cvmx_sli_dbg_select_s cn68xx; struct cvmx_sli_dbg_select_s cn68xxp1; + struct cvmx_sli_dbg_select_s cnf71xx; }; union cvmx_sli_dmax_cnt { uint64_t u64; struct cvmx_sli_dmax_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_dmax_cnt_s cn61xx; struct cvmx_sli_dmax_cnt_s cn63xx; @@ -320,13 +467,19 @@ union cvmx_sli_dmax_cnt { struct cvmx_sli_dmax_cnt_s cn66xx; struct cvmx_sli_dmax_cnt_s cn68xx; struct cvmx_sli_dmax_cnt_s cn68xxp1; + struct cvmx_sli_dmax_cnt_s cnf71xx; }; union cvmx_sli_dmax_int_level { uint64_t u64; struct cvmx_sli_dmax_int_level_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t time:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t time:32; +#endif } s; struct cvmx_sli_dmax_int_level_s cn61xx; struct cvmx_sli_dmax_int_level_s cn63xx; @@ -334,13 +487,19 @@ union cvmx_sli_dmax_int_level { struct cvmx_sli_dmax_int_level_s cn66xx; struct cvmx_sli_dmax_int_level_s cn68xx; struct cvmx_sli_dmax_int_level_s cn68xxp1; + struct cvmx_sli_dmax_int_level_s cnf71xx; }; union cvmx_sli_dmax_tim { uint64_t u64; struct cvmx_sli_dmax_tim_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t tim:32; +#else + uint64_t tim:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_dmax_tim_s cn61xx; struct cvmx_sli_dmax_tim_s cn63xx; @@ -348,11 +507,13 @@ union cvmx_sli_dmax_tim { struct cvmx_sli_dmax_tim_s cn66xx; struct cvmx_sli_dmax_tim_s cn68xx; struct cvmx_sli_dmax_tim_s cn68xxp1; + struct cvmx_sli_dmax_tim_s cnf71xx; }; union cvmx_sli_int_enb_ciu { uint64_t u64; struct cvmx_sli_int_enb_ciu_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -399,8 +560,57 @@ union cvmx_sli_int_enb_ciu { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t reserved_18_19:2; + uint64_t m2_up_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_un_wi:1; + uint64_t m3_up_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_un_wi:1; + uint64_t reserved_28_31:4; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t sprt2_err:1; + uint64_t sprt3_err:1; + uint64_t ill_pad:1; + uint64_t pipe_err:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_sli_int_enb_ciu_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t sprt3_err:1; @@ -446,8 +656,56 @@ union cvmx_sli_int_enb_ciu { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t reserved_18_19:2; + uint64_t m2_up_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_un_wi:1; + uint64_t m3_up_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_un_wi:1; + uint64_t reserved_28_31:4; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t sprt2_err:1; + uint64_t sprt3_err:1; + uint64_t ill_pad:1; + uint64_t reserved_61_63:3; +#endif } cn61xx; struct cvmx_sli_int_enb_ciu_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t reserved_58_59:2; @@ -483,10 +741,48 @@ union cvmx_sli_int_enb_ciu { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t reserved_18_31:14; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t reserved_58_59:2; + uint64_t ill_pad:1; + uint64_t reserved_61_63:3; +#endif } cn63xx; struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1; struct cvmx_sli_int_enb_ciu_cn61xx cn66xx; struct cvmx_sli_int_enb_ciu_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -523,13 +819,53 @@ union cvmx_sli_int_enb_ciu { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t reserved_18_31:14; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t reserved_51_51:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t reserved_58_59:2; + uint64_t ill_pad:1; + uint64_t pipe_err:1; + uint64_t reserved_62_63:2; +#endif } cn68xx; struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1; + struct cvmx_sli_int_enb_ciu_cn61xx cnf71xx; }; union cvmx_sli_int_enb_portx { uint64_t u64; struct cvmx_sli_int_enb_portx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -577,8 +913,58 @@ union cvmx_sli_int_enb_portx { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t m2_up_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_un_wi:1; + uint64_t m3_up_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_un_wi:1; + uint64_t reserved_28_31:4; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t sprt2_err:1; + uint64_t sprt3_err:1; + uint64_t ill_pad:1; + uint64_t pipe_err:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_sli_int_enb_portx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t sprt3_err:1; @@ -625,8 +1011,57 @@ union cvmx_sli_int_enb_portx { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t m2_up_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_un_wi:1; + uint64_t m3_up_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_un_wi:1; + uint64_t reserved_28_31:4; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t sprt2_err:1; + uint64_t sprt3_err:1; + uint64_t ill_pad:1; + uint64_t reserved_61_63:3; +#endif } cn61xx; struct cvmx_sli_int_enb_portx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t reserved_58_59:2; @@ -664,10 +1099,50 @@ union cvmx_sli_int_enb_portx { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t reserved_20_31:12; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t reserved_58_59:2; + uint64_t ill_pad:1; + uint64_t reserved_61_63:3; +#endif } cn63xx; struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1; struct cvmx_sli_int_enb_portx_cn61xx cn66xx; struct cvmx_sli_int_enb_portx_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -706,13 +1181,55 @@ union cvmx_sli_int_enb_portx { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t reserved_20_31:12; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t reserved_51_51:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t reserved_58_59:2; + uint64_t ill_pad:1; + uint64_t pipe_err:1; + uint64_t reserved_62_63:2; +#endif } cn68xx; struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1; + struct cvmx_sli_int_enb_portx_cn61xx cnf71xx; }; union cvmx_sli_int_sum { uint64_t u64; struct cvmx_sli_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -760,8 +1277,58 @@ union cvmx_sli_int_sum { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t m2_up_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_un_wi:1; + uint64_t m3_up_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_un_wi:1; + uint64_t reserved_28_31:4; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t sprt2_err:1; + uint64_t sprt3_err:1; + uint64_t ill_pad:1; + uint64_t pipe_err:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_sli_int_sum_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t sprt3_err:1; @@ -808,8 +1375,57 @@ union cvmx_sli_int_sum { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t m2_up_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_un_wi:1; + uint64_t m3_up_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_un_wi:1; + uint64_t reserved_28_31:4; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t sprt2_err:1; + uint64_t sprt3_err:1; + uint64_t ill_pad:1; + uint64_t reserved_61_63:3; +#endif } cn61xx; struct cvmx_sli_int_sum_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t reserved_58_59:2; @@ -847,10 +1463,50 @@ union cvmx_sli_int_sum { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t reserved_20_31:12; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t reserved_58_59:2; + uint64_t ill_pad:1; + uint64_t reserved_61_63:3; +#endif } cn63xx; struct cvmx_sli_int_sum_cn63xx cn63xxp1; struct cvmx_sli_int_sum_cn61xx cn66xx; struct cvmx_sli_int_sum_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -889,14 +1545,59 @@ union cvmx_sli_int_sum { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t reserved_20_31:12; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t reserved_51_51:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t reserved_58_59:2; + uint64_t ill_pad:1; + uint64_t pipe_err:1; + uint64_t reserved_62_63:2; +#endif } cn68xx; struct cvmx_sli_int_sum_cn68xx cn68xxp1; + struct cvmx_sli_int_sum_cn61xx cnf71xx; }; union cvmx_sli_last_win_rdata0 { uint64_t u64; struct cvmx_sli_last_win_rdata0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_sli_last_win_rdata0_s cn61xx; struct cvmx_sli_last_win_rdata0_s cn63xx; @@ -904,12 +1605,17 @@ union cvmx_sli_last_win_rdata0 { struct cvmx_sli_last_win_rdata0_s cn66xx; struct cvmx_sli_last_win_rdata0_s cn68xx; struct cvmx_sli_last_win_rdata0_s cn68xxp1; + struct cvmx_sli_last_win_rdata0_s cnf71xx; }; union cvmx_sli_last_win_rdata1 { uint64_t u64; struct cvmx_sli_last_win_rdata1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_sli_last_win_rdata1_s cn61xx; struct cvmx_sli_last_win_rdata1_s cn63xx; @@ -917,29 +1623,41 @@ union cvmx_sli_last_win_rdata1 { struct cvmx_sli_last_win_rdata1_s cn66xx; struct cvmx_sli_last_win_rdata1_s cn68xx; struct cvmx_sli_last_win_rdata1_s cn68xxp1; + struct cvmx_sli_last_win_rdata1_s cnf71xx; }; union cvmx_sli_last_win_rdata2 { uint64_t u64; struct cvmx_sli_last_win_rdata2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_sli_last_win_rdata2_s cn61xx; struct cvmx_sli_last_win_rdata2_s cn66xx; + struct cvmx_sli_last_win_rdata2_s cnf71xx; }; union cvmx_sli_last_win_rdata3 { uint64_t u64; struct cvmx_sli_last_win_rdata3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_sli_last_win_rdata3_s cn61xx; struct cvmx_sli_last_win_rdata3_s cn66xx; + struct cvmx_sli_last_win_rdata3_s cnf71xx; }; union cvmx_sli_mac_credit_cnt { uint64_t u64; struct cvmx_sli_mac_credit_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t p1_c_d:1; uint64_t p1_n_d:1; @@ -953,10 +1671,26 @@ union cvmx_sli_mac_credit_cnt { uint64_t p0_ccnt:8; uint64_t p0_ncnt:8; uint64_t p0_pcnt:8; +#else + uint64_t p0_pcnt:8; + uint64_t p0_ncnt:8; + uint64_t p0_ccnt:8; + uint64_t p1_pcnt:8; + uint64_t p1_ncnt:8; + uint64_t p1_ccnt:8; + uint64_t p0_p_d:1; + uint64_t p0_n_d:1; + uint64_t p0_c_d:1; + uint64_t p1_p_d:1; + uint64_t p1_n_d:1; + uint64_t p1_c_d:1; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_sli_mac_credit_cnt_s cn61xx; struct cvmx_sli_mac_credit_cnt_s cn63xx; struct cvmx_sli_mac_credit_cnt_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t p1_ccnt:8; uint64_t p1_ncnt:8; @@ -964,15 +1698,26 @@ union cvmx_sli_mac_credit_cnt { uint64_t p0_ccnt:8; uint64_t p0_ncnt:8; uint64_t p0_pcnt:8; +#else + uint64_t p0_pcnt:8; + uint64_t p0_ncnt:8; + uint64_t p0_ccnt:8; + uint64_t p1_pcnt:8; + uint64_t p1_ncnt:8; + uint64_t p1_ccnt:8; + uint64_t reserved_48_63:16; +#endif } cn63xxp1; struct cvmx_sli_mac_credit_cnt_s cn66xx; struct cvmx_sli_mac_credit_cnt_s cn68xx; struct cvmx_sli_mac_credit_cnt_s cn68xxp1; + struct cvmx_sli_mac_credit_cnt_s cnf71xx; }; union cvmx_sli_mac_credit_cnt2 { uint64_t u64; struct cvmx_sli_mac_credit_cnt2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t p3_c_d:1; uint64_t p3_n_d:1; @@ -986,34 +1731,68 @@ union cvmx_sli_mac_credit_cnt2 { uint64_t p2_ccnt:8; uint64_t p2_ncnt:8; uint64_t p2_pcnt:8; +#else + uint64_t p2_pcnt:8; + uint64_t p2_ncnt:8; + uint64_t p2_ccnt:8; + uint64_t p3_pcnt:8; + uint64_t p3_ncnt:8; + uint64_t p3_ccnt:8; + uint64_t p2_p_d:1; + uint64_t p2_n_d:1; + uint64_t p2_c_d:1; + uint64_t p3_p_d:1; + uint64_t p3_n_d:1; + uint64_t p3_c_d:1; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_sli_mac_credit_cnt2_s cn61xx; struct cvmx_sli_mac_credit_cnt2_s cn66xx; + struct cvmx_sli_mac_credit_cnt2_s cnf71xx; }; union cvmx_sli_mac_number { uint64_t u64; struct cvmx_sli_mac_number_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t a_mode:1; uint64_t num:8; +#else + uint64_t num:8; + uint64_t a_mode:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_sli_mac_number_s cn61xx; struct cvmx_sli_mac_number_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t num:8; +#else + uint64_t num:8; + uint64_t reserved_8_63:56; +#endif } cn63xx; struct cvmx_sli_mac_number_s cn66xx; struct cvmx_sli_mac_number_cn63xx cn68xx; struct cvmx_sli_mac_number_cn63xx cn68xxp1; + struct cvmx_sli_mac_number_s cnf71xx; }; union cvmx_sli_mem_access_ctl { uint64_t u64; struct cvmx_sli_mem_access_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t max_word:4; uint64_t timer:10; +#else + uint64_t timer:10; + uint64_t max_word:4; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_sli_mem_access_ctl_s cn61xx; struct cvmx_sli_mem_access_ctl_s cn63xx; @@ -1021,11 +1800,13 @@ union cvmx_sli_mem_access_ctl { struct cvmx_sli_mem_access_ctl_s cn66xx; struct cvmx_sli_mem_access_ctl_s cn68xx; struct cvmx_sli_mem_access_ctl_s cn68xxp1; + struct cvmx_sli_mem_access_ctl_s cnf71xx; }; union cvmx_sli_mem_access_subidx { uint64_t u64; struct cvmx_sli_mem_access_subidx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_43_63:21; uint64_t zero:1; uint64_t port:3; @@ -1035,8 +1816,20 @@ union cvmx_sli_mem_access_subidx { uint64_t wtype:2; uint64_t rtype:2; uint64_t reserved_0_29:30; +#else + uint64_t reserved_0_29:30; + uint64_t rtype:2; + uint64_t wtype:2; + uint64_t esw:2; + uint64_t esr:2; + uint64_t nmerge:1; + uint64_t port:3; + uint64_t zero:1; + uint64_t reserved_43_63:21; +#endif } s; struct cvmx_sli_mem_access_subidx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_43_63:21; uint64_t zero:1; uint64_t port:3; @@ -1046,11 +1839,23 @@ union cvmx_sli_mem_access_subidx { uint64_t wtype:2; uint64_t rtype:2; uint64_t ba:30; +#else + uint64_t ba:30; + uint64_t rtype:2; + uint64_t wtype:2; + uint64_t esw:2; + uint64_t esr:2; + uint64_t nmerge:1; + uint64_t port:3; + uint64_t zero:1; + uint64_t reserved_43_63:21; +#endif } cn61xx; struct cvmx_sli_mem_access_subidx_cn61xx cn63xx; struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1; struct cvmx_sli_mem_access_subidx_cn61xx cn66xx; struct cvmx_sli_mem_access_subidx_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_43_63:21; uint64_t zero:1; uint64_t port:3; @@ -1061,14 +1866,31 @@ union cvmx_sli_mem_access_subidx { uint64_t rtype:2; uint64_t ba:28; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t ba:28; + uint64_t rtype:2; + uint64_t wtype:2; + uint64_t esw:2; + uint64_t esr:2; + uint64_t nmerge:1; + uint64_t port:3; + uint64_t zero:1; + uint64_t reserved_43_63:21; +#endif } cn68xx; struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1; + struct cvmx_sli_mem_access_subidx_cn61xx cnf71xx; }; union cvmx_sli_msi_enb0 { uint64_t u64; struct cvmx_sli_msi_enb0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t enb:64; +#else uint64_t enb:64; +#endif } s; struct cvmx_sli_msi_enb0_s cn61xx; struct cvmx_sli_msi_enb0_s cn63xx; @@ -1076,12 +1898,17 @@ union cvmx_sli_msi_enb0 { struct cvmx_sli_msi_enb0_s cn66xx; struct cvmx_sli_msi_enb0_s cn68xx; struct cvmx_sli_msi_enb0_s cn68xxp1; + struct cvmx_sli_msi_enb0_s cnf71xx; }; union cvmx_sli_msi_enb1 { uint64_t u64; struct cvmx_sli_msi_enb1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t enb:64; +#else uint64_t enb:64; +#endif } s; struct cvmx_sli_msi_enb1_s cn61xx; struct cvmx_sli_msi_enb1_s cn63xx; @@ -1089,12 +1916,17 @@ union cvmx_sli_msi_enb1 { struct cvmx_sli_msi_enb1_s cn66xx; struct cvmx_sli_msi_enb1_s cn68xx; struct cvmx_sli_msi_enb1_s cn68xxp1; + struct cvmx_sli_msi_enb1_s cnf71xx; }; union cvmx_sli_msi_enb2 { uint64_t u64; struct cvmx_sli_msi_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t enb:64; +#else uint64_t enb:64; +#endif } s; struct cvmx_sli_msi_enb2_s cn61xx; struct cvmx_sli_msi_enb2_s cn63xx; @@ -1102,12 +1934,17 @@ union cvmx_sli_msi_enb2 { struct cvmx_sli_msi_enb2_s cn66xx; struct cvmx_sli_msi_enb2_s cn68xx; struct cvmx_sli_msi_enb2_s cn68xxp1; + struct cvmx_sli_msi_enb2_s cnf71xx; }; union cvmx_sli_msi_enb3 { uint64_t u64; struct cvmx_sli_msi_enb3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t enb:64; +#else uint64_t enb:64; +#endif } s; struct cvmx_sli_msi_enb3_s cn61xx; struct cvmx_sli_msi_enb3_s cn63xx; @@ -1115,12 +1952,17 @@ union cvmx_sli_msi_enb3 { struct cvmx_sli_msi_enb3_s cn66xx; struct cvmx_sli_msi_enb3_s cn68xx; struct cvmx_sli_msi_enb3_s cn68xxp1; + struct cvmx_sli_msi_enb3_s cnf71xx; }; union cvmx_sli_msi_rcv0 { uint64_t u64; struct cvmx_sli_msi_rcv0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t intr:64; +#else uint64_t intr:64; +#endif } s; struct cvmx_sli_msi_rcv0_s cn61xx; struct cvmx_sli_msi_rcv0_s cn63xx; @@ -1128,12 +1970,17 @@ union cvmx_sli_msi_rcv0 { struct cvmx_sli_msi_rcv0_s cn66xx; struct cvmx_sli_msi_rcv0_s cn68xx; struct cvmx_sli_msi_rcv0_s cn68xxp1; + struct cvmx_sli_msi_rcv0_s cnf71xx; }; union cvmx_sli_msi_rcv1 { uint64_t u64; struct cvmx_sli_msi_rcv1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t intr:64; +#else uint64_t intr:64; +#endif } s; struct cvmx_sli_msi_rcv1_s cn61xx; struct cvmx_sli_msi_rcv1_s cn63xx; @@ -1141,12 +1988,17 @@ union cvmx_sli_msi_rcv1 { struct cvmx_sli_msi_rcv1_s cn66xx; struct cvmx_sli_msi_rcv1_s cn68xx; struct cvmx_sli_msi_rcv1_s cn68xxp1; + struct cvmx_sli_msi_rcv1_s cnf71xx; }; union cvmx_sli_msi_rcv2 { uint64_t u64; struct cvmx_sli_msi_rcv2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t intr:64; +#else uint64_t intr:64; +#endif } s; struct cvmx_sli_msi_rcv2_s cn61xx; struct cvmx_sli_msi_rcv2_s cn63xx; @@ -1154,12 +2006,17 @@ union cvmx_sli_msi_rcv2 { struct cvmx_sli_msi_rcv2_s cn66xx; struct cvmx_sli_msi_rcv2_s cn68xx; struct cvmx_sli_msi_rcv2_s cn68xxp1; + struct cvmx_sli_msi_rcv2_s cnf71xx; }; union cvmx_sli_msi_rcv3 { uint64_t u64; struct cvmx_sli_msi_rcv3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t intr:64; +#else uint64_t intr:64; +#endif } s; struct cvmx_sli_msi_rcv3_s cn61xx; struct cvmx_sli_msi_rcv3_s cn63xx; @@ -1167,14 +2024,21 @@ union cvmx_sli_msi_rcv3 { struct cvmx_sli_msi_rcv3_s cn66xx; struct cvmx_sli_msi_rcv3_s cn68xx; struct cvmx_sli_msi_rcv3_s cn68xxp1; + struct cvmx_sli_msi_rcv3_s cnf71xx; }; union cvmx_sli_msi_rd_map { uint64_t u64; struct cvmx_sli_msi_rd_map_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t rd_int:8; uint64_t msi_int:8; +#else + uint64_t msi_int:8; + uint64_t rd_int:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_sli_msi_rd_map_s cn61xx; struct cvmx_sli_msi_rd_map_s cn63xx; @@ -1182,12 +2046,17 @@ union cvmx_sli_msi_rd_map { struct cvmx_sli_msi_rd_map_s cn66xx; struct cvmx_sli_msi_rd_map_s cn68xx; struct cvmx_sli_msi_rd_map_s cn68xxp1; + struct cvmx_sli_msi_rd_map_s cnf71xx; }; union cvmx_sli_msi_w1c_enb0 { uint64_t u64; struct cvmx_sli_msi_w1c_enb0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t clr:64; +#else uint64_t clr:64; +#endif } s; struct cvmx_sli_msi_w1c_enb0_s cn61xx; struct cvmx_sli_msi_w1c_enb0_s cn63xx; @@ -1195,12 +2064,17 @@ union cvmx_sli_msi_w1c_enb0 { struct cvmx_sli_msi_w1c_enb0_s cn66xx; struct cvmx_sli_msi_w1c_enb0_s cn68xx; struct cvmx_sli_msi_w1c_enb0_s cn68xxp1; + struct cvmx_sli_msi_w1c_enb0_s cnf71xx; }; union cvmx_sli_msi_w1c_enb1 { uint64_t u64; struct cvmx_sli_msi_w1c_enb1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t clr:64; +#else uint64_t clr:64; +#endif } s; struct cvmx_sli_msi_w1c_enb1_s cn61xx; struct cvmx_sli_msi_w1c_enb1_s cn63xx; @@ -1208,12 +2082,17 @@ union cvmx_sli_msi_w1c_enb1 { struct cvmx_sli_msi_w1c_enb1_s cn66xx; struct cvmx_sli_msi_w1c_enb1_s cn68xx; struct cvmx_sli_msi_w1c_enb1_s cn68xxp1; + struct cvmx_sli_msi_w1c_enb1_s cnf71xx; }; union cvmx_sli_msi_w1c_enb2 { uint64_t u64; struct cvmx_sli_msi_w1c_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t clr:64; +#else uint64_t clr:64; +#endif } s; struct cvmx_sli_msi_w1c_enb2_s cn61xx; struct cvmx_sli_msi_w1c_enb2_s cn63xx; @@ -1221,12 +2100,17 @@ union cvmx_sli_msi_w1c_enb2 { struct cvmx_sli_msi_w1c_enb2_s cn66xx; struct cvmx_sli_msi_w1c_enb2_s cn68xx; struct cvmx_sli_msi_w1c_enb2_s cn68xxp1; + struct cvmx_sli_msi_w1c_enb2_s cnf71xx; }; union cvmx_sli_msi_w1c_enb3 { uint64_t u64; struct cvmx_sli_msi_w1c_enb3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t clr:64; +#else uint64_t clr:64; +#endif } s; struct cvmx_sli_msi_w1c_enb3_s cn61xx; struct cvmx_sli_msi_w1c_enb3_s cn63xx; @@ -1234,12 +2118,17 @@ union cvmx_sli_msi_w1c_enb3 { struct cvmx_sli_msi_w1c_enb3_s cn66xx; struct cvmx_sli_msi_w1c_enb3_s cn68xx; struct cvmx_sli_msi_w1c_enb3_s cn68xxp1; + struct cvmx_sli_msi_w1c_enb3_s cnf71xx; }; union cvmx_sli_msi_w1s_enb0 { uint64_t u64; struct cvmx_sli_msi_w1s_enb0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t set:64; +#else uint64_t set:64; +#endif } s; struct cvmx_sli_msi_w1s_enb0_s cn61xx; struct cvmx_sli_msi_w1s_enb0_s cn63xx; @@ -1247,12 +2136,17 @@ union cvmx_sli_msi_w1s_enb0 { struct cvmx_sli_msi_w1s_enb0_s cn66xx; struct cvmx_sli_msi_w1s_enb0_s cn68xx; struct cvmx_sli_msi_w1s_enb0_s cn68xxp1; + struct cvmx_sli_msi_w1s_enb0_s cnf71xx; }; union cvmx_sli_msi_w1s_enb1 { uint64_t u64; struct cvmx_sli_msi_w1s_enb1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t set:64; +#else uint64_t set:64; +#endif } s; struct cvmx_sli_msi_w1s_enb1_s cn61xx; struct cvmx_sli_msi_w1s_enb1_s cn63xx; @@ -1260,12 +2154,17 @@ union cvmx_sli_msi_w1s_enb1 { struct cvmx_sli_msi_w1s_enb1_s cn66xx; struct cvmx_sli_msi_w1s_enb1_s cn68xx; struct cvmx_sli_msi_w1s_enb1_s cn68xxp1; + struct cvmx_sli_msi_w1s_enb1_s cnf71xx; }; union cvmx_sli_msi_w1s_enb2 { uint64_t u64; struct cvmx_sli_msi_w1s_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t set:64; +#else uint64_t set:64; +#endif } s; struct cvmx_sli_msi_w1s_enb2_s cn61xx; struct cvmx_sli_msi_w1s_enb2_s cn63xx; @@ -1273,12 +2172,17 @@ union cvmx_sli_msi_w1s_enb2 { struct cvmx_sli_msi_w1s_enb2_s cn66xx; struct cvmx_sli_msi_w1s_enb2_s cn68xx; struct cvmx_sli_msi_w1s_enb2_s cn68xxp1; + struct cvmx_sli_msi_w1s_enb2_s cnf71xx; }; union cvmx_sli_msi_w1s_enb3 { uint64_t u64; struct cvmx_sli_msi_w1s_enb3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t set:64; +#else uint64_t set:64; +#endif } s; struct cvmx_sli_msi_w1s_enb3_s cn61xx; struct cvmx_sli_msi_w1s_enb3_s cn63xx; @@ -1286,14 +2190,21 @@ union cvmx_sli_msi_w1s_enb3 { struct cvmx_sli_msi_w1s_enb3_s cn66xx; struct cvmx_sli_msi_w1s_enb3_s cn68xx; struct cvmx_sli_msi_w1s_enb3_s cn68xxp1; + struct cvmx_sli_msi_w1s_enb3_s cnf71xx; }; union cvmx_sli_msi_wr_map { uint64_t u64; struct cvmx_sli_msi_wr_map_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ciu_int:8; uint64_t msi_int:8; +#else + uint64_t msi_int:8; + uint64_t ciu_int:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_sli_msi_wr_map_s cn61xx; struct cvmx_sli_msi_wr_map_s cn63xx; @@ -1301,13 +2212,19 @@ union cvmx_sli_msi_wr_map { struct cvmx_sli_msi_wr_map_s cn66xx; struct cvmx_sli_msi_wr_map_s cn68xx; struct cvmx_sli_msi_wr_map_s cn68xxp1; + struct cvmx_sli_msi_wr_map_s cnf71xx; }; union cvmx_sli_pcie_msi_rcv { uint64_t u64; struct cvmx_sli_pcie_msi_rcv_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t intr:8; +#else + uint64_t intr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_sli_pcie_msi_rcv_s cn61xx; struct cvmx_sli_pcie_msi_rcv_s cn63xx; @@ -1315,14 +2232,21 @@ union cvmx_sli_pcie_msi_rcv { struct cvmx_sli_pcie_msi_rcv_s cn66xx; struct cvmx_sli_pcie_msi_rcv_s cn68xx; struct cvmx_sli_pcie_msi_rcv_s cn68xxp1; + struct cvmx_sli_pcie_msi_rcv_s cnf71xx; }; union cvmx_sli_pcie_msi_rcv_b1 { uint64_t u64; struct cvmx_sli_pcie_msi_rcv_b1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t intr:8; uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t intr:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx; struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx; @@ -1330,14 +2254,21 @@ union cvmx_sli_pcie_msi_rcv_b1 { struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx; struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx; struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1; + struct cvmx_sli_pcie_msi_rcv_b1_s cnf71xx; }; union cvmx_sli_pcie_msi_rcv_b2 { uint64_t u64; struct cvmx_sli_pcie_msi_rcv_b2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t intr:8; uint64_t reserved_0_15:16; +#else + uint64_t reserved_0_15:16; + uint64_t intr:8; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx; struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx; @@ -1345,14 +2276,21 @@ union cvmx_sli_pcie_msi_rcv_b2 { struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx; struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx; struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1; + struct cvmx_sli_pcie_msi_rcv_b2_s cnf71xx; }; union cvmx_sli_pcie_msi_rcv_b3 { uint64_t u64; struct cvmx_sli_pcie_msi_rcv_b3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t intr:8; uint64_t reserved_0_23:24; +#else + uint64_t reserved_0_23:24; + uint64_t intr:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx; struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx; @@ -1360,14 +2298,21 @@ union cvmx_sli_pcie_msi_rcv_b3 { struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx; struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx; struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1; + struct cvmx_sli_pcie_msi_rcv_b3_s cnf71xx; }; union cvmx_sli_pktx_cnts { uint64_t u64; struct cvmx_sli_pktx_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t timer:22; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t timer:22; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_sli_pktx_cnts_s cn61xx; struct cvmx_sli_pktx_cnts_s cn63xx; @@ -1375,25 +2320,37 @@ union cvmx_sli_pktx_cnts { struct cvmx_sli_pktx_cnts_s cn66xx; struct cvmx_sli_pktx_cnts_s cn68xx; struct cvmx_sli_pktx_cnts_s cn68xxp1; + struct cvmx_sli_pktx_cnts_s cnf71xx; }; union cvmx_sli_pktx_in_bp { uint64_t u64; struct cvmx_sli_pktx_in_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wmark:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t wmark:32; +#endif } s; struct cvmx_sli_pktx_in_bp_s cn61xx; struct cvmx_sli_pktx_in_bp_s cn63xx; struct cvmx_sli_pktx_in_bp_s cn63xxp1; struct cvmx_sli_pktx_in_bp_s cn66xx; + struct cvmx_sli_pktx_in_bp_s cnf71xx; }; union cvmx_sli_pktx_instr_baddr { uint64_t u64; struct cvmx_sli_pktx_instr_baddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:61; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t addr:61; +#endif } s; struct cvmx_sli_pktx_instr_baddr_s cn61xx; struct cvmx_sli_pktx_instr_baddr_s cn63xx; @@ -1401,13 +2358,19 @@ union cvmx_sli_pktx_instr_baddr { struct cvmx_sli_pktx_instr_baddr_s cn66xx; struct cvmx_sli_pktx_instr_baddr_s cn68xx; struct cvmx_sli_pktx_instr_baddr_s cn68xxp1; + struct cvmx_sli_pktx_instr_baddr_s cnf71xx; }; union cvmx_sli_pktx_instr_baoff_dbell { uint64_t u64; struct cvmx_sli_pktx_instr_baoff_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t aoff:32; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t aoff:32; +#endif } s; struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx; struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx; @@ -1415,16 +2378,25 @@ union cvmx_sli_pktx_instr_baoff_dbell { struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx; struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx; struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1; + struct cvmx_sli_pktx_instr_baoff_dbell_s cnf71xx; }; union cvmx_sli_pktx_instr_fifo_rsize { uint64_t u64; struct cvmx_sli_pktx_instr_fifo_rsize_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t max:9; uint64_t rrp:9; uint64_t wrp:9; uint64_t fcnt:5; uint64_t rsize:32; +#else + uint64_t rsize:32; + uint64_t fcnt:5; + uint64_t wrp:9; + uint64_t rrp:9; + uint64_t max:9; +#endif } s; struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx; struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx; @@ -1432,11 +2404,13 @@ union cvmx_sli_pktx_instr_fifo_rsize { struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx; struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx; struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1; + struct cvmx_sli_pktx_instr_fifo_rsize_s cnf71xx; }; union cvmx_sli_pktx_instr_header { uint64_t u64; struct cvmx_sli_pktx_instr_header_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t reserved_38_42:5; @@ -1458,8 +2432,32 @@ union cvmx_sli_pktx_instr_header { uint64_t ngrp:1; uint64_t ntt:1; uint64_t ntag:1; +#else + uint64_t ntag:1; + uint64_t ntt:1; + uint64_t ngrp:1; + uint64_t nqos:1; + uint64_t ngrpext:2; + uint64_t skp_len:7; + uint64_t reserved_13_13:1; + uint64_t par_mode:2; + uint64_t reserved_16_20:5; + uint64_t use_ihdr:1; + uint64_t rntag:1; + uint64_t rntt:1; + uint64_t rngrp:1; + uint64_t rnqos:1; + uint64_t rngrpext:2; + uint64_t rskp_len:7; + uint64_t reserved_35_35:1; + uint64_t rparmode:2; + uint64_t reserved_38_42:5; + uint64_t pbp:1; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_sli_pktx_instr_header_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t reserved_38_42:5; @@ -1481,20 +2479,50 @@ union cvmx_sli_pktx_instr_header { uint64_t ngrp:1; uint64_t ntt:1; uint64_t ntag:1; +#else + uint64_t ntag:1; + uint64_t ntt:1; + uint64_t ngrp:1; + uint64_t nqos:1; + uint64_t reserved_4_5:2; + uint64_t skp_len:7; + uint64_t reserved_13_13:1; + uint64_t par_mode:2; + uint64_t reserved_16_20:5; + uint64_t use_ihdr:1; + uint64_t rntag:1; + uint64_t rntt:1; + uint64_t rngrp:1; + uint64_t rnqos:1; + uint64_t reserved_26_27:2; + uint64_t rskp_len:7; + uint64_t reserved_35_35:1; + uint64_t rparmode:2; + uint64_t reserved_38_42:5; + uint64_t pbp:1; + uint64_t reserved_44_63:20; +#endif } cn61xx; struct cvmx_sli_pktx_instr_header_cn61xx cn63xx; struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1; struct cvmx_sli_pktx_instr_header_cn61xx cn66xx; struct cvmx_sli_pktx_instr_header_s cn68xx; struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1; + struct cvmx_sli_pktx_instr_header_cn61xx cnf71xx; }; union cvmx_sli_pktx_out_size { uint64_t u64; struct cvmx_sli_pktx_out_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t isize:7; uint64_t bsize:16; +#else + uint64_t bsize:16; + uint64_t isize:7; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_sli_pktx_out_size_s cn61xx; struct cvmx_sli_pktx_out_size_s cn63xx; @@ -1502,13 +2530,19 @@ union cvmx_sli_pktx_out_size { struct cvmx_sli_pktx_out_size_s cn66xx; struct cvmx_sli_pktx_out_size_s cn68xx; struct cvmx_sli_pktx_out_size_s cn68xxp1; + struct cvmx_sli_pktx_out_size_s cnf71xx; }; union cvmx_sli_pktx_slist_baddr { uint64_t u64; struct cvmx_sli_pktx_slist_baddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:60; uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t addr:60; +#endif } s; struct cvmx_sli_pktx_slist_baddr_s cn61xx; struct cvmx_sli_pktx_slist_baddr_s cn63xx; @@ -1516,13 +2550,19 @@ union cvmx_sli_pktx_slist_baddr { struct cvmx_sli_pktx_slist_baddr_s cn66xx; struct cvmx_sli_pktx_slist_baddr_s cn68xx; struct cvmx_sli_pktx_slist_baddr_s cn68xxp1; + struct cvmx_sli_pktx_slist_baddr_s cnf71xx; }; union cvmx_sli_pktx_slist_baoff_dbell { uint64_t u64; struct cvmx_sli_pktx_slist_baoff_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t aoff:32; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t aoff:32; +#endif } s; struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx; struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx; @@ -1530,13 +2570,19 @@ union cvmx_sli_pktx_slist_baoff_dbell { struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx; struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx; struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1; + struct cvmx_sli_pktx_slist_baoff_dbell_s cnf71xx; }; union cvmx_sli_pktx_slist_fifo_rsize { uint64_t u64; struct cvmx_sli_pktx_slist_fifo_rsize_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rsize:32; +#else + uint64_t rsize:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx; struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx; @@ -1544,13 +2590,19 @@ union cvmx_sli_pktx_slist_fifo_rsize { struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx; struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx; struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1; + struct cvmx_sli_pktx_slist_fifo_rsize_s cnf71xx; }; union cvmx_sli_pkt_cnt_int { uint64_t u64; struct cvmx_sli_pkt_cnt_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_cnt_int_s cn61xx; struct cvmx_sli_pkt_cnt_int_s cn63xx; @@ -1558,13 +2610,19 @@ union cvmx_sli_pkt_cnt_int { struct cvmx_sli_pkt_cnt_int_s cn66xx; struct cvmx_sli_pkt_cnt_int_s cn68xx; struct cvmx_sli_pkt_cnt_int_s cn68xxp1; + struct cvmx_sli_pkt_cnt_int_s cnf71xx; }; union cvmx_sli_pkt_cnt_int_enb { uint64_t u64; struct cvmx_sli_pkt_cnt_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_cnt_int_enb_s cn61xx; struct cvmx_sli_pkt_cnt_int_enb_s cn63xx; @@ -1572,14 +2630,21 @@ union cvmx_sli_pkt_cnt_int_enb { struct cvmx_sli_pkt_cnt_int_enb_s cn66xx; struct cvmx_sli_pkt_cnt_int_enb_s cn68xx; struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1; + struct cvmx_sli_pkt_cnt_int_enb_s cnf71xx; }; union cvmx_sli_pkt_ctl { uint64_t u64; struct cvmx_sli_pkt_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t ring_en:1; uint64_t pkt_bp:4; +#else + uint64_t pkt_bp:4; + uint64_t ring_en:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_sli_pkt_ctl_s cn61xx; struct cvmx_sli_pkt_ctl_s cn63xx; @@ -1587,12 +2652,17 @@ union cvmx_sli_pkt_ctl { struct cvmx_sli_pkt_ctl_s cn66xx; struct cvmx_sli_pkt_ctl_s cn68xx; struct cvmx_sli_pkt_ctl_s cn68xxp1; + struct cvmx_sli_pkt_ctl_s cnf71xx; }; union cvmx_sli_pkt_data_out_es { uint64_t u64; struct cvmx_sli_pkt_data_out_es_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t es:64; +#else uint64_t es:64; +#endif } s; struct cvmx_sli_pkt_data_out_es_s cn61xx; struct cvmx_sli_pkt_data_out_es_s cn63xx; @@ -1600,13 +2670,19 @@ union cvmx_sli_pkt_data_out_es { struct cvmx_sli_pkt_data_out_es_s cn66xx; struct cvmx_sli_pkt_data_out_es_s cn68xx; struct cvmx_sli_pkt_data_out_es_s cn68xxp1; + struct cvmx_sli_pkt_data_out_es_s cnf71xx; }; union cvmx_sli_pkt_data_out_ns { uint64_t u64; struct cvmx_sli_pkt_data_out_ns_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t nsr:32; +#else + uint64_t nsr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_data_out_ns_s cn61xx; struct cvmx_sli_pkt_data_out_ns_s cn63xx; @@ -1614,13 +2690,19 @@ union cvmx_sli_pkt_data_out_ns { struct cvmx_sli_pkt_data_out_ns_s cn66xx; struct cvmx_sli_pkt_data_out_ns_s cn68xx; struct cvmx_sli_pkt_data_out_ns_s cn68xxp1; + struct cvmx_sli_pkt_data_out_ns_s cnf71xx; }; union cvmx_sli_pkt_data_out_ror { uint64_t u64; struct cvmx_sli_pkt_data_out_ror_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ror:32; +#else + uint64_t ror:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_data_out_ror_s cn61xx; struct cvmx_sli_pkt_data_out_ror_s cn63xx; @@ -1628,13 +2710,19 @@ union cvmx_sli_pkt_data_out_ror { struct cvmx_sli_pkt_data_out_ror_s cn66xx; struct cvmx_sli_pkt_data_out_ror_s cn68xx; struct cvmx_sli_pkt_data_out_ror_s cn68xxp1; + struct cvmx_sli_pkt_data_out_ror_s cnf71xx; }; union cvmx_sli_pkt_dpaddr { uint64_t u64; struct cvmx_sli_pkt_dpaddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t dptr:32; +#else + uint64_t dptr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_dpaddr_s cn61xx; struct cvmx_sli_pkt_dpaddr_s cn63xx; @@ -1642,25 +2730,37 @@ union cvmx_sli_pkt_dpaddr { struct cvmx_sli_pkt_dpaddr_s cn66xx; struct cvmx_sli_pkt_dpaddr_s cn68xx; struct cvmx_sli_pkt_dpaddr_s cn68xxp1; + struct cvmx_sli_pkt_dpaddr_s cnf71xx; }; union cvmx_sli_pkt_in_bp { uint64_t u64; struct cvmx_sli_pkt_in_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bp:32; +#else + uint64_t bp:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_in_bp_s cn61xx; struct cvmx_sli_pkt_in_bp_s cn63xx; struct cvmx_sli_pkt_in_bp_s cn63xxp1; struct cvmx_sli_pkt_in_bp_s cn66xx; + struct cvmx_sli_pkt_in_bp_s cnf71xx; }; union cvmx_sli_pkt_in_donex_cnts { uint64_t u64; struct cvmx_sli_pkt_in_donex_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_in_donex_cnts_s cn61xx; struct cvmx_sli_pkt_in_donex_cnts_s cn63xx; @@ -1668,13 +2768,19 @@ union cvmx_sli_pkt_in_donex_cnts { struct cvmx_sli_pkt_in_donex_cnts_s cn66xx; struct cvmx_sli_pkt_in_donex_cnts_s cn68xx; struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1; + struct cvmx_sli_pkt_in_donex_cnts_s cnf71xx; }; union cvmx_sli_pkt_in_instr_counts { uint64_t u64; struct cvmx_sli_pkt_in_instr_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_cnt:32; uint64_t rd_cnt:32; +#else + uint64_t rd_cnt:32; + uint64_t wr_cnt:32; +#endif } s; struct cvmx_sli_pkt_in_instr_counts_s cn61xx; struct cvmx_sli_pkt_in_instr_counts_s cn63xx; @@ -1682,12 +2788,17 @@ union cvmx_sli_pkt_in_instr_counts { struct cvmx_sli_pkt_in_instr_counts_s cn66xx; struct cvmx_sli_pkt_in_instr_counts_s cn68xx; struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1; + struct cvmx_sli_pkt_in_instr_counts_s cnf71xx; }; union cvmx_sli_pkt_in_pcie_port { uint64_t u64; struct cvmx_sli_pkt_in_pcie_port_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t pp:64; +#else uint64_t pp:64; +#endif } s; struct cvmx_sli_pkt_in_pcie_port_s cn61xx; struct cvmx_sli_pkt_in_pcie_port_s cn63xx; @@ -1695,11 +2806,13 @@ union cvmx_sli_pkt_in_pcie_port { struct cvmx_sli_pkt_in_pcie_port_s cn66xx; struct cvmx_sli_pkt_in_pcie_port_s cn68xx; struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1; + struct cvmx_sli_pkt_in_pcie_port_s cnf71xx; }; union cvmx_sli_pkt_input_control { uint64_t u64; struct cvmx_sli_pkt_input_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t prd_erst:1; uint64_t prd_rds:7; uint64_t gii_erst:1; @@ -1717,9 +2830,29 @@ union cvmx_sli_pkt_input_control { uint64_t nsr:1; uint64_t esr:2; uint64_t ror:1; +#else + uint64_t ror:1; + uint64_t esr:2; + uint64_t nsr:1; + uint64_t use_csr:1; + uint64_t d_ror:1; + uint64_t d_esr:2; + uint64_t d_nsr:1; + uint64_t pbp_dhi:13; + uint64_t pkt_rr:1; + uint64_t pin_rst:1; + uint64_t reserved_24_39:16; + uint64_t prc_idle:1; + uint64_t reserved_41_47:7; + uint64_t gii_rds:7; + uint64_t gii_erst:1; + uint64_t prd_rds:7; + uint64_t prd_erst:1; +#endif } s; struct cvmx_sli_pkt_input_control_s cn61xx; struct cvmx_sli_pkt_input_control_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t pkt_rr:1; uint64_t pbp_dhi:13; @@ -1730,18 +2863,36 @@ union cvmx_sli_pkt_input_control { uint64_t nsr:1; uint64_t esr:2; uint64_t ror:1; +#else + uint64_t ror:1; + uint64_t esr:2; + uint64_t nsr:1; + uint64_t use_csr:1; + uint64_t d_ror:1; + uint64_t d_esr:2; + uint64_t d_nsr:1; + uint64_t pbp_dhi:13; + uint64_t pkt_rr:1; + uint64_t reserved_23_63:41; +#endif } cn63xx; struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1; struct cvmx_sli_pkt_input_control_s cn66xx; struct cvmx_sli_pkt_input_control_s cn68xx; struct cvmx_sli_pkt_input_control_s cn68xxp1; + struct cvmx_sli_pkt_input_control_s cnf71xx; }; union cvmx_sli_pkt_instr_enb { uint64_t u64; struct cvmx_sli_pkt_instr_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enb:32; +#else + uint64_t enb:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_instr_enb_s cn61xx; struct cvmx_sli_pkt_instr_enb_s cn63xx; @@ -1749,12 +2900,17 @@ union cvmx_sli_pkt_instr_enb { struct cvmx_sli_pkt_instr_enb_s cn66xx; struct cvmx_sli_pkt_instr_enb_s cn68xx; struct cvmx_sli_pkt_instr_enb_s cn68xxp1; + struct cvmx_sli_pkt_instr_enb_s cnf71xx; }; union cvmx_sli_pkt_instr_rd_size { uint64_t u64; struct cvmx_sli_pkt_instr_rd_size_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rdsize:64; +#else uint64_t rdsize:64; +#endif } s; struct cvmx_sli_pkt_instr_rd_size_s cn61xx; struct cvmx_sli_pkt_instr_rd_size_s cn63xx; @@ -1762,13 +2918,19 @@ union cvmx_sli_pkt_instr_rd_size { struct cvmx_sli_pkt_instr_rd_size_s cn66xx; struct cvmx_sli_pkt_instr_rd_size_s cn68xx; struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1; + struct cvmx_sli_pkt_instr_rd_size_s cnf71xx; }; union cvmx_sli_pkt_instr_size { uint64_t u64; struct cvmx_sli_pkt_instr_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t is_64b:32; +#else + uint64_t is_64b:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_instr_size_s cn61xx; struct cvmx_sli_pkt_instr_size_s cn63xx; @@ -1776,14 +2938,21 @@ union cvmx_sli_pkt_instr_size { struct cvmx_sli_pkt_instr_size_s cn66xx; struct cvmx_sli_pkt_instr_size_s cn68xx; struct cvmx_sli_pkt_instr_size_s cn68xxp1; + struct cvmx_sli_pkt_instr_size_s cnf71xx; }; union cvmx_sli_pkt_int_levels { uint64_t u64; struct cvmx_sli_pkt_int_levels_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t time:22; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t time:22; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_sli_pkt_int_levels_s cn61xx; struct cvmx_sli_pkt_int_levels_s cn63xx; @@ -1791,13 +2960,19 @@ union cvmx_sli_pkt_int_levels { struct cvmx_sli_pkt_int_levels_s cn66xx; struct cvmx_sli_pkt_int_levels_s cn68xx; struct cvmx_sli_pkt_int_levels_s cn68xxp1; + struct cvmx_sli_pkt_int_levels_s cnf71xx; }; union cvmx_sli_pkt_iptr { uint64_t u64; struct cvmx_sli_pkt_iptr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iptr:32; +#else + uint64_t iptr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_iptr_s cn61xx; struct cvmx_sli_pkt_iptr_s cn63xx; @@ -1805,13 +2980,19 @@ union cvmx_sli_pkt_iptr { struct cvmx_sli_pkt_iptr_s cn66xx; struct cvmx_sli_pkt_iptr_s cn68xx; struct cvmx_sli_pkt_iptr_s cn68xxp1; + struct cvmx_sli_pkt_iptr_s cnf71xx; }; union cvmx_sli_pkt_out_bmode { uint64_t u64; struct cvmx_sli_pkt_out_bmode_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bmode:32; +#else + uint64_t bmode:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_out_bmode_s cn61xx; struct cvmx_sli_pkt_out_bmode_s cn63xx; @@ -1819,13 +3000,19 @@ union cvmx_sli_pkt_out_bmode { struct cvmx_sli_pkt_out_bmode_s cn66xx; struct cvmx_sli_pkt_out_bmode_s cn68xx; struct cvmx_sli_pkt_out_bmode_s cn68xxp1; + struct cvmx_sli_pkt_out_bmode_s cnf71xx; }; union cvmx_sli_pkt_out_bp_en { uint64_t u64; struct cvmx_sli_pkt_out_bp_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bp_en:32; +#else + uint64_t bp_en:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_out_bp_en_s cn68xx; struct cvmx_sli_pkt_out_bp_en_s cn68xxp1; @@ -1834,8 +3021,13 @@ union cvmx_sli_pkt_out_bp_en { union cvmx_sli_pkt_out_enb { uint64_t u64; struct cvmx_sli_pkt_out_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enb:32; +#else + uint64_t enb:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_out_enb_s cn61xx; struct cvmx_sli_pkt_out_enb_s cn63xx; @@ -1843,13 +3035,19 @@ union cvmx_sli_pkt_out_enb { struct cvmx_sli_pkt_out_enb_s cn66xx; struct cvmx_sli_pkt_out_enb_s cn68xx; struct cvmx_sli_pkt_out_enb_s cn68xxp1; + struct cvmx_sli_pkt_out_enb_s cnf71xx; }; union cvmx_sli_pkt_output_wmark { uint64_t u64; struct cvmx_sli_pkt_output_wmark_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t wmark:32; +#else + uint64_t wmark:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_output_wmark_s cn61xx; struct cvmx_sli_pkt_output_wmark_s cn63xx; @@ -1857,12 +3055,17 @@ union cvmx_sli_pkt_output_wmark { struct cvmx_sli_pkt_output_wmark_s cn66xx; struct cvmx_sli_pkt_output_wmark_s cn68xx; struct cvmx_sli_pkt_output_wmark_s cn68xxp1; + struct cvmx_sli_pkt_output_wmark_s cnf71xx; }; union cvmx_sli_pkt_pcie_port { uint64_t u64; struct cvmx_sli_pkt_pcie_port_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t pp:64; +#else uint64_t pp:64; +#endif } s; struct cvmx_sli_pkt_pcie_port_s cn61xx; struct cvmx_sli_pkt_pcie_port_s cn63xx; @@ -1870,13 +3073,19 @@ union cvmx_sli_pkt_pcie_port { struct cvmx_sli_pkt_pcie_port_s cn66xx; struct cvmx_sli_pkt_pcie_port_s cn68xx; struct cvmx_sli_pkt_pcie_port_s cn68xxp1; + struct cvmx_sli_pkt_pcie_port_s cnf71xx; }; union cvmx_sli_pkt_port_in_rst { uint64_t u64; struct cvmx_sli_pkt_port_in_rst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t in_rst:32; uint64_t out_rst:32; +#else + uint64_t out_rst:32; + uint64_t in_rst:32; +#endif } s; struct cvmx_sli_pkt_port_in_rst_s cn61xx; struct cvmx_sli_pkt_port_in_rst_s cn63xx; @@ -1884,12 +3093,17 @@ union cvmx_sli_pkt_port_in_rst { struct cvmx_sli_pkt_port_in_rst_s cn66xx; struct cvmx_sli_pkt_port_in_rst_s cn68xx; struct cvmx_sli_pkt_port_in_rst_s cn68xxp1; + struct cvmx_sli_pkt_port_in_rst_s cnf71xx; }; union cvmx_sli_pkt_slist_es { uint64_t u64; struct cvmx_sli_pkt_slist_es_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t es:64; +#else + uint64_t es:64; +#endif } s; struct cvmx_sli_pkt_slist_es_s cn61xx; struct cvmx_sli_pkt_slist_es_s cn63xx; @@ -1897,13 +3111,19 @@ union cvmx_sli_pkt_slist_es { struct cvmx_sli_pkt_slist_es_s cn66xx; struct cvmx_sli_pkt_slist_es_s cn68xx; struct cvmx_sli_pkt_slist_es_s cn68xxp1; + struct cvmx_sli_pkt_slist_es_s cnf71xx; }; union cvmx_sli_pkt_slist_ns { uint64_t u64; struct cvmx_sli_pkt_slist_ns_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t nsr:32; +#else + uint64_t nsr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_slist_ns_s cn61xx; struct cvmx_sli_pkt_slist_ns_s cn63xx; @@ -1911,13 +3131,19 @@ union cvmx_sli_pkt_slist_ns { struct cvmx_sli_pkt_slist_ns_s cn66xx; struct cvmx_sli_pkt_slist_ns_s cn68xx; struct cvmx_sli_pkt_slist_ns_s cn68xxp1; + struct cvmx_sli_pkt_slist_ns_s cnf71xx; }; union cvmx_sli_pkt_slist_ror { uint64_t u64; struct cvmx_sli_pkt_slist_ror_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ror:32; +#else + uint64_t ror:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_slist_ror_s cn61xx; struct cvmx_sli_pkt_slist_ror_s cn63xx; @@ -1925,13 +3151,19 @@ union cvmx_sli_pkt_slist_ror { struct cvmx_sli_pkt_slist_ror_s cn66xx; struct cvmx_sli_pkt_slist_ror_s cn68xx; struct cvmx_sli_pkt_slist_ror_s cn68xxp1; + struct cvmx_sli_pkt_slist_ror_s cnf71xx; }; union cvmx_sli_pkt_time_int { uint64_t u64; struct cvmx_sli_pkt_time_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_time_int_s cn61xx; struct cvmx_sli_pkt_time_int_s cn63xx; @@ -1939,13 +3171,19 @@ union cvmx_sli_pkt_time_int { struct cvmx_sli_pkt_time_int_s cn66xx; struct cvmx_sli_pkt_time_int_s cn68xx; struct cvmx_sli_pkt_time_int_s cn68xxp1; + struct cvmx_sli_pkt_time_int_s cnf71xx; }; union cvmx_sli_pkt_time_int_enb { uint64_t u64; struct cvmx_sli_pkt_time_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_time_int_enb_s cn61xx; struct cvmx_sli_pkt_time_int_enb_s cn63xx; @@ -1953,11 +3191,13 @@ union cvmx_sli_pkt_time_int_enb { struct cvmx_sli_pkt_time_int_enb_s cn66xx; struct cvmx_sli_pkt_time_int_enb_s cn68xx; struct cvmx_sli_pkt_time_int_enb_s cn68xxp1; + struct cvmx_sli_pkt_time_int_enb_s cnf71xx; }; union cvmx_sli_portx_pkind { uint64_t u64; struct cvmx_sli_portx_pkind_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t rpk_enb:1; uint64_t reserved_22_23:2; @@ -1966,23 +3206,47 @@ union cvmx_sli_portx_pkind { uint64_t bpkind:6; uint64_t reserved_6_7:2; uint64_t pkind:6; +#else + uint64_t pkind:6; + uint64_t reserved_6_7:2; + uint64_t bpkind:6; + uint64_t reserved_14_15:2; + uint64_t pkindr:6; + uint64_t reserved_22_23:2; + uint64_t rpk_enb:1; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_sli_portx_pkind_s cn68xx; struct cvmx_sli_portx_pkind_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t bpkind:6; uint64_t reserved_6_7:2; uint64_t pkind:6; +#else + uint64_t pkind:6; + uint64_t reserved_6_7:2; + uint64_t bpkind:6; + uint64_t reserved_14_63:50; +#endif } cn68xxp1; }; union cvmx_sli_s2m_portx_ctl { uint64_t u64; struct cvmx_sli_s2m_portx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t wind_d:1; uint64_t bar0_d:1; uint64_t mrrs:3; +#else + uint64_t mrrs:3; + uint64_t bar0_d:1; + uint64_t wind_d:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_sli_s2m_portx_ctl_s cn61xx; struct cvmx_sli_s2m_portx_ctl_s cn63xx; @@ -1990,12 +3254,17 @@ union cvmx_sli_s2m_portx_ctl { struct cvmx_sli_s2m_portx_ctl_s cn66xx; struct cvmx_sli_s2m_portx_ctl_s cn68xx; struct cvmx_sli_s2m_portx_ctl_s cn68xxp1; + struct cvmx_sli_s2m_portx_ctl_s cnf71xx; }; union cvmx_sli_scratch_1 { uint64_t u64; struct cvmx_sli_scratch_1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_sli_scratch_1_s cn61xx; struct cvmx_sli_scratch_1_s cn63xx; @@ -2003,12 +3272,17 @@ union cvmx_sli_scratch_1 { struct cvmx_sli_scratch_1_s cn66xx; struct cvmx_sli_scratch_1_s cn68xx; struct cvmx_sli_scratch_1_s cn68xxp1; + struct cvmx_sli_scratch_1_s cnf71xx; }; union cvmx_sli_scratch_2 { uint64_t u64; struct cvmx_sli_scratch_2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_sli_scratch_2_s cn61xx; struct cvmx_sli_scratch_2_s cn63xx; @@ -2016,15 +3290,23 @@ union cvmx_sli_scratch_2 { struct cvmx_sli_scratch_2_s cn66xx; struct cvmx_sli_scratch_2_s cn68xx; struct cvmx_sli_scratch_2_s cn68xxp1; + struct cvmx_sli_scratch_2_s cnf71xx; }; union cvmx_sli_state1 { uint64_t u64; struct cvmx_sli_state1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t cpl1:12; uint64_t cpl0:12; uint64_t arb:1; uint64_t csr:39; +#else + uint64_t csr:39; + uint64_t arb:1; + uint64_t cpl0:12; + uint64_t cpl1:12; +#endif } s; struct cvmx_sli_state1_s cn61xx; struct cvmx_sli_state1_s cn63xx; @@ -2032,11 +3314,13 @@ union cvmx_sli_state1 { struct cvmx_sli_state1_s cn66xx; struct cvmx_sli_state1_s cn68xx; struct cvmx_sli_state1_s cn68xxp1; + struct cvmx_sli_state1_s cnf71xx; }; union cvmx_sli_state2 { uint64_t u64; struct cvmx_sli_state2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t nnp1:8; uint64_t reserved_47_47:1; @@ -2045,6 +3329,16 @@ union cvmx_sli_state2 { uint64_t csm0:15; uint64_t nnp0:8; uint64_t nnd:8; +#else + uint64_t nnd:8; + uint64_t nnp0:8; + uint64_t csm0:15; + uint64_t csm1:15; + uint64_t rac:1; + uint64_t reserved_47_47:1; + uint64_t nnp1:8; + uint64_t reserved_56_63:8; +#endif } s; struct cvmx_sli_state2_s cn61xx; struct cvmx_sli_state2_s cn63xx; @@ -2052,16 +3346,25 @@ union cvmx_sli_state2 { struct cvmx_sli_state2_s cn66xx; struct cvmx_sli_state2_s cn68xx; struct cvmx_sli_state2_s cn68xxp1; + struct cvmx_sli_state2_s cnf71xx; }; union cvmx_sli_state3 { uint64_t u64; struct cvmx_sli_state3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t psm1:15; uint64_t psm0:15; uint64_t nsm1:13; uint64_t nsm0:13; +#else + uint64_t nsm0:13; + uint64_t nsm1:13; + uint64_t psm0:15; + uint64_t psm1:15; + uint64_t reserved_56_63:8; +#endif } s; struct cvmx_sli_state3_s cn61xx; struct cvmx_sli_state3_s cn63xx; @@ -2069,15 +3372,23 @@ union cvmx_sli_state3 { struct cvmx_sli_state3_s cn66xx; struct cvmx_sli_state3_s cn68xx; struct cvmx_sli_state3_s cn68xxp1; + struct cvmx_sli_state3_s cnf71xx; }; union cvmx_sli_tx_pipe { uint64_t u64; struct cvmx_sli_tx_pipe_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t nump:8; uint64_t reserved_7_15:9; uint64_t base:7; +#else + uint64_t base:7; + uint64_t reserved_7_15:9; + uint64_t nump:8; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_sli_tx_pipe_s cn68xx; struct cvmx_sli_tx_pipe_s cn68xxp1; @@ -2086,10 +3397,17 @@ union cvmx_sli_tx_pipe { union cvmx_sli_win_rd_addr { uint64_t u64; struct cvmx_sli_win_rd_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_51_63:13; uint64_t ld_cmd:2; uint64_t iobit:1; uint64_t rd_addr:48; +#else + uint64_t rd_addr:48; + uint64_t iobit:1; + uint64_t ld_cmd:2; + uint64_t reserved_51_63:13; +#endif } s; struct cvmx_sli_win_rd_addr_s cn61xx; struct cvmx_sli_win_rd_addr_s cn63xx; @@ -2097,12 +3415,17 @@ union cvmx_sli_win_rd_addr { struct cvmx_sli_win_rd_addr_s cn66xx; struct cvmx_sli_win_rd_addr_s cn68xx; struct cvmx_sli_win_rd_addr_s cn68xxp1; + struct cvmx_sli_win_rd_addr_s cnf71xx; }; union cvmx_sli_win_rd_data { uint64_t u64; struct cvmx_sli_win_rd_data_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rd_data:64; +#else uint64_t rd_data:64; +#endif } s; struct cvmx_sli_win_rd_data_s cn61xx; struct cvmx_sli_win_rd_data_s cn63xx; @@ -2110,15 +3433,23 @@ union cvmx_sli_win_rd_data { struct cvmx_sli_win_rd_data_s cn66xx; struct cvmx_sli_win_rd_data_s cn68xx; struct cvmx_sli_win_rd_data_s cn68xxp1; + struct cvmx_sli_win_rd_data_s cnf71xx; }; union cvmx_sli_win_wr_addr { uint64_t u64; struct cvmx_sli_win_wr_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t wr_addr:45; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t wr_addr:45; + uint64_t iobit:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_sli_win_wr_addr_s cn61xx; struct cvmx_sli_win_wr_addr_s cn63xx; @@ -2126,12 +3457,17 @@ union cvmx_sli_win_wr_addr { struct cvmx_sli_win_wr_addr_s cn66xx; struct cvmx_sli_win_wr_addr_s cn68xx; struct cvmx_sli_win_wr_addr_s cn68xxp1; + struct cvmx_sli_win_wr_addr_s cnf71xx; }; union cvmx_sli_win_wr_data { uint64_t u64; struct cvmx_sli_win_wr_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_data:64; +#else + uint64_t wr_data:64; +#endif } s; struct cvmx_sli_win_wr_data_s cn61xx; struct cvmx_sli_win_wr_data_s cn63xx; @@ -2139,13 +3475,19 @@ union cvmx_sli_win_wr_data { struct cvmx_sli_win_wr_data_s cn66xx; struct cvmx_sli_win_wr_data_s cn68xx; struct cvmx_sli_win_wr_data_s cn68xxp1; + struct cvmx_sli_win_wr_data_s cnf71xx; }; union cvmx_sli_win_wr_mask { uint64_t u64; struct cvmx_sli_win_wr_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t wr_mask:8; +#else + uint64_t wr_mask:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_sli_win_wr_mask_s cn61xx; struct cvmx_sli_win_wr_mask_s cn63xx; @@ -2153,13 +3495,19 @@ union cvmx_sli_win_wr_mask { struct cvmx_sli_win_wr_mask_s cn66xx; struct cvmx_sli_win_wr_mask_s cn68xx; struct cvmx_sli_win_wr_mask_s cn68xxp1; + struct cvmx_sli_win_wr_mask_s cnf71xx; }; union cvmx_sli_window_ctl { uint64_t u64; struct cvmx_sli_window_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t time:32; +#else + uint64_t time:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_window_ctl_s cn61xx; struct cvmx_sli_window_ctl_s cn63xx; @@ -2167,6 +3515,7 @@ union cvmx_sli_window_ctl { struct cvmx_sli_window_ctl_s cn66xx; struct cvmx_sli_window_ctl_s cn68xx; struct cvmx_sli_window_ctl_s cn68xxp1; + struct cvmx_sli_window_ctl_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h index 4f3c0666e94a..8a278e6ddba9 100644 --- a/arch/mips/include/asm/octeon/cvmx-smix-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,15 +28,120 @@ #ifndef __CVMX_SMIX_DEFS_H__ #define __CVMX_SMIX_DEFS_H__ -#define CVMX_SMIX_CLK(offset) (CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256) -#define CVMX_SMIX_CMD(offset) (CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256) -#define CVMX_SMIX_EN(offset) (CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256) -#define CVMX_SMIX_RD_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256) -#define CVMX_SMIX_WR_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256) +static inline uint64_t CVMX_SMIX_CLK(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000003818ull) + (offset) * 128; + } + return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256; +} + +static inline uint64_t CVMX_SMIX_CMD(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000003800ull) + (offset) * 128; + } + return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256; +} + +static inline uint64_t CVMX_SMIX_EN(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000003820ull) + (offset) * 128; + } + return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256; +} + +static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000003810ull) + (offset) * 128; + } + return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256; +} + +static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000003808ull) + (offset) * 128; + } + return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256; +} union cvmx_smix_clk { uint64_t u64; struct cvmx_smix_clk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t mode:1; uint64_t reserved_21_23:3; @@ -47,8 +152,21 @@ union cvmx_smix_clk { uint64_t preamble:1; uint64_t sample:4; uint64_t phase:8; +#else + uint64_t phase:8; + uint64_t sample:4; + uint64_t preamble:1; + uint64_t clk_idle:1; + uint64_t reserved_14_14:1; + uint64_t sample_mode:1; + uint64_t sample_hi:5; + uint64_t reserved_21_23:3; + uint64_t mode:1; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_smix_clk_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t sample_hi:5; uint64_t sample_mode:1; @@ -57,6 +175,16 @@ union cvmx_smix_clk { uint64_t preamble:1; uint64_t sample:4; uint64_t phase:8; +#else + uint64_t phase:8; + uint64_t sample:4; + uint64_t preamble:1; + uint64_t clk_idle:1; + uint64_t reserved_14_14:1; + uint64_t sample_mode:1; + uint64_t sample_hi:5; + uint64_t reserved_21_63:43; +#endif } cn30xx; struct cvmx_smix_clk_cn30xx cn31xx; struct cvmx_smix_clk_cn30xx cn38xx; @@ -68,27 +196,50 @@ union cvmx_smix_clk { struct cvmx_smix_clk_s cn56xxp1; struct cvmx_smix_clk_cn30xx cn58xx; struct cvmx_smix_clk_cn30xx cn58xxp1; + struct cvmx_smix_clk_s cn61xx; struct cvmx_smix_clk_s cn63xx; struct cvmx_smix_clk_s cn63xxp1; + struct cvmx_smix_clk_s cn66xx; + struct cvmx_smix_clk_s cn68xx; + struct cvmx_smix_clk_s cn68xxp1; + struct cvmx_smix_clk_s cnf71xx; }; union cvmx_smix_cmd { uint64_t u64; struct cvmx_smix_cmd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t phy_op:2; uint64_t reserved_13_15:3; uint64_t phy_adr:5; uint64_t reserved_5_7:3; uint64_t reg_adr:5; +#else + uint64_t reg_adr:5; + uint64_t reserved_5_7:3; + uint64_t phy_adr:5; + uint64_t reserved_13_15:3; + uint64_t phy_op:2; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_smix_cmd_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t phy_op:1; uint64_t reserved_13_15:3; uint64_t phy_adr:5; uint64_t reserved_5_7:3; uint64_t reg_adr:5; +#else + uint64_t reg_adr:5; + uint64_t reserved_5_7:3; + uint64_t phy_adr:5; + uint64_t reserved_13_15:3; + uint64_t phy_op:1; + uint64_t reserved_17_63:47; +#endif } cn30xx; struct cvmx_smix_cmd_cn30xx cn31xx; struct cvmx_smix_cmd_cn30xx cn38xx; @@ -100,15 +251,25 @@ union cvmx_smix_cmd { struct cvmx_smix_cmd_s cn56xxp1; struct cvmx_smix_cmd_cn30xx cn58xx; struct cvmx_smix_cmd_cn30xx cn58xxp1; + struct cvmx_smix_cmd_s cn61xx; struct cvmx_smix_cmd_s cn63xx; struct cvmx_smix_cmd_s cn63xxp1; + struct cvmx_smix_cmd_s cn66xx; + struct cvmx_smix_cmd_s cn68xx; + struct cvmx_smix_cmd_s cn68xxp1; + struct cvmx_smix_cmd_s cnf71xx; }; union cvmx_smix_en { uint64_t u64; struct cvmx_smix_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t en:1; +#else + uint64_t en:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_smix_en_s cn30xx; struct cvmx_smix_en_s cn31xx; @@ -121,17 +282,29 @@ union cvmx_smix_en { struct cvmx_smix_en_s cn56xxp1; struct cvmx_smix_en_s cn58xx; struct cvmx_smix_en_s cn58xxp1; + struct cvmx_smix_en_s cn61xx; struct cvmx_smix_en_s cn63xx; struct cvmx_smix_en_s cn63xxp1; + struct cvmx_smix_en_s cn66xx; + struct cvmx_smix_en_s cn68xx; + struct cvmx_smix_en_s cn68xxp1; + struct cvmx_smix_en_s cnf71xx; }; union cvmx_smix_rd_dat { uint64_t u64; struct cvmx_smix_rd_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t pending:1; uint64_t val:1; uint64_t dat:16; +#else + uint64_t dat:16; + uint64_t val:1; + uint64_t pending:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_smix_rd_dat_s cn30xx; struct cvmx_smix_rd_dat_s cn31xx; @@ -144,17 +317,29 @@ union cvmx_smix_rd_dat { struct cvmx_smix_rd_dat_s cn56xxp1; struct cvmx_smix_rd_dat_s cn58xx; struct cvmx_smix_rd_dat_s cn58xxp1; + struct cvmx_smix_rd_dat_s cn61xx; struct cvmx_smix_rd_dat_s cn63xx; struct cvmx_smix_rd_dat_s cn63xxp1; + struct cvmx_smix_rd_dat_s cn66xx; + struct cvmx_smix_rd_dat_s cn68xx; + struct cvmx_smix_rd_dat_s cn68xxp1; + struct cvmx_smix_rd_dat_s cnf71xx; }; union cvmx_smix_wr_dat { uint64_t u64; struct cvmx_smix_wr_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t pending:1; uint64_t val:1; uint64_t dat:16; +#else + uint64_t dat:16; + uint64_t val:1; + uint64_t pending:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_smix_wr_dat_s cn30xx; struct cvmx_smix_wr_dat_s cn31xx; @@ -167,8 +352,13 @@ union cvmx_smix_wr_dat { struct cvmx_smix_wr_dat_s cn56xxp1; struct cvmx_smix_wr_dat_s cn58xx; struct cvmx_smix_wr_dat_s cn58xxp1; + struct cvmx_smix_wr_dat_s cn61xx; struct cvmx_smix_wr_dat_s cn63xx; struct cvmx_smix_wr_dat_s cn63xxp1; + struct cvmx_smix_wr_dat_s cn66xx; + struct cvmx_smix_wr_dat_s cn68xx; + struct cvmx_smix_wr_dat_s cn68xxp1; + struct cvmx_smix_wr_dat_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-spxx-defs.h b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h index b16940e32c83..c7d601d9446e 100644 --- a/arch/mips/include/asm/octeon/cvmx-spxx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,44 +28,33 @@ #ifndef __CVMX_SPXX_DEFS_H__ #define __CVMX_SPXX_DEFS_H__ -#define CVMX_SPXX_BCKPRS_CNT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000340ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_BIST_STAT(block_id) \ - CVMX_ADD_IO_SEG(0x00011800900007F8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_CLK_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000348ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_CLK_STAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000350ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000368ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000370ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_DRV_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000358ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_ERR_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000320ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_INT_DAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000318ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_INT_MSK(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000308ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_INT_REG(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000300ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_INT_SYNC(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000310ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_TPA_ACC(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000338ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_TPA_MAX(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000330ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_TPA_SEL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000328ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_TRN4_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000360ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull) union cvmx_spxx_bckprs_cnt { uint64_t u64; struct cvmx_spxx_bckprs_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_spxx_bckprs_cnt_s cn38xx; struct cvmx_spxx_bckprs_cnt_s cn38xxp2; @@ -76,10 +65,17 @@ union cvmx_spxx_bckprs_cnt { union cvmx_spxx_bist_stat { uint64_t u64; struct cvmx_spxx_bist_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t stat2:1; uint64_t stat1:1; uint64_t stat0:1; +#else + uint64_t stat0:1; + uint64_t stat1:1; + uint64_t stat2:1; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_spxx_bist_stat_s cn38xx; struct cvmx_spxx_bist_stat_s cn38xxp2; @@ -90,6 +86,7 @@ union cvmx_spxx_bist_stat { union cvmx_spxx_clk_ctl { uint64_t u64; struct cvmx_spxx_clk_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t seetrn:1; uint64_t reserved_12_15:4; @@ -101,6 +98,19 @@ union cvmx_spxx_clk_ctl { uint64_t drptrn:1; uint64_t rcvtrn:1; uint64_t srxdlck:1; +#else + uint64_t srxdlck:1; + uint64_t rcvtrn:1; + uint64_t drptrn:1; + uint64_t sndtrn:1; + uint64_t statrcv:1; + uint64_t statdrv:1; + uint64_t runbist:1; + uint64_t clkdly:5; + uint64_t reserved_12_15:4; + uint64_t seetrn:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_spxx_clk_ctl_s cn38xx; struct cvmx_spxx_clk_ctl_s cn38xxp2; @@ -111,6 +121,7 @@ union cvmx_spxx_clk_ctl { union cvmx_spxx_clk_stat { uint64_t u64; struct cvmx_spxx_clk_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t stxcal:1; uint64_t reserved_9_9:1; @@ -120,6 +131,17 @@ union cvmx_spxx_clk_stat { uint64_t d4clk1:1; uint64_t d4clk0:1; uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t d4clk0:1; + uint64_t d4clk1:1; + uint64_t s4clk0:1; + uint64_t s4clk1:1; + uint64_t srxtrn:1; + uint64_t reserved_9_9:1; + uint64_t stxcal:1; + uint64_t reserved_11_63:53; +#endif } s; struct cvmx_spxx_clk_stat_s cn38xx; struct cvmx_spxx_clk_stat_s cn38xxp2; @@ -130,6 +152,7 @@ union cvmx_spxx_clk_stat { union cvmx_spxx_dbg_deskew_ctl { uint64_t u64; struct cvmx_spxx_dbg_deskew_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_30_63:34; uint64_t fallnop:1; uint64_t fall8:1; @@ -146,6 +169,24 @@ union cvmx_spxx_dbg_deskew_ctl { uint64_t offdly:6; uint64_t dllfrc:1; uint64_t dlldis:1; +#else + uint64_t dlldis:1; + uint64_t dllfrc:1; + uint64_t offdly:6; + uint64_t bitsel:5; + uint64_t offset:5; + uint64_t mux:1; + uint64_t inc:1; + uint64_t dec:1; + uint64_t clrdly:1; + uint64_t reserved_22_23:2; + uint64_t sstep:1; + uint64_t sstep_go:1; + uint64_t reserved_26_27:2; + uint64_t fall8:1; + uint64_t fallnop:1; + uint64_t reserved_30_63:34; +#endif } s; struct cvmx_spxx_dbg_deskew_ctl_s cn38xx; struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2; @@ -156,11 +197,19 @@ union cvmx_spxx_dbg_deskew_ctl { union cvmx_spxx_dbg_deskew_state { uint64_t u64; struct cvmx_spxx_dbg_deskew_state_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t testres:1; uint64_t unxterm:1; uint64_t muxsel:2; uint64_t offset:5; +#else + uint64_t offset:5; + uint64_t muxsel:2; + uint64_t unxterm:1; + uint64_t testres:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_spxx_dbg_deskew_state_s cn38xx; struct cvmx_spxx_dbg_deskew_state_s cn38xxp2; @@ -171,21 +220,40 @@ union cvmx_spxx_dbg_deskew_state { union cvmx_spxx_drv_ctl { uint64_t u64; struct cvmx_spxx_drv_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_spxx_drv_ctl_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t stx4ncmp:4; uint64_t stx4pcmp:4; uint64_t srx4cmp:8; +#else + uint64_t srx4cmp:8; + uint64_t stx4pcmp:4; + uint64_t stx4ncmp:4; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2; struct cvmx_spxx_drv_ctl_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t stx4ncmp:4; uint64_t stx4pcmp:4; uint64_t reserved_10_15:6; uint64_t srx4cmp:10; +#else + uint64_t srx4cmp:10; + uint64_t reserved_10_15:6; + uint64_t stx4pcmp:4; + uint64_t stx4ncmp:4; + uint64_t reserved_24_63:40; +#endif } cn58xx; struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1; }; @@ -193,12 +261,21 @@ union cvmx_spxx_drv_ctl { union cvmx_spxx_err_ctl { uint64_t u64; struct cvmx_spxx_err_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t prtnxa:1; uint64_t dipcls:1; uint64_t dippay:1; uint64_t reserved_4_5:2; uint64_t errcnt:4; +#else + uint64_t errcnt:4; + uint64_t reserved_4_5:2; + uint64_t dippay:1; + uint64_t dipcls:1; + uint64_t prtnxa:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_spxx_err_ctl_s cn38xx; struct cvmx_spxx_err_ctl_s cn38xxp2; @@ -209,12 +286,21 @@ union cvmx_spxx_err_ctl { union cvmx_spxx_int_dat { uint64_t u64; struct cvmx_spxx_int_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t mul:1; uint64_t reserved_14_30:17; uint64_t calbnk:2; uint64_t rsvop:4; uint64_t prt:8; +#else + uint64_t prt:8; + uint64_t rsvop:4; + uint64_t calbnk:2; + uint64_t reserved_14_30:17; + uint64_t mul:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_spxx_int_dat_s cn38xx; struct cvmx_spxx_int_dat_s cn38xxp2; @@ -225,6 +311,7 @@ union cvmx_spxx_int_dat { union cvmx_spxx_int_msk { uint64_t u64; struct cvmx_spxx_int_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t calerr:1; uint64_t syncerr:1; @@ -237,6 +324,20 @@ union cvmx_spxx_int_msk { uint64_t reserved_2_3:2; uint64_t abnorm:1; uint64_t prtnxa:1; +#else + uint64_t prtnxa:1; + uint64_t abnorm:1; + uint64_t reserved_2_3:2; + uint64_t spiovr:1; + uint64_t clserr:1; + uint64_t drwnng:1; + uint64_t rsverr:1; + uint64_t tpaovr:1; + uint64_t diperr:1; + uint64_t syncerr:1; + uint64_t calerr:1; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_spxx_int_msk_s cn38xx; struct cvmx_spxx_int_msk_s cn38xxp2; @@ -247,6 +348,7 @@ union cvmx_spxx_int_msk { union cvmx_spxx_int_reg { uint64_t u64; struct cvmx_spxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t spf:1; uint64_t reserved_12_30:19; @@ -261,6 +363,22 @@ union cvmx_spxx_int_reg { uint64_t reserved_2_3:2; uint64_t abnorm:1; uint64_t prtnxa:1; +#else + uint64_t prtnxa:1; + uint64_t abnorm:1; + uint64_t reserved_2_3:2; + uint64_t spiovr:1; + uint64_t clserr:1; + uint64_t drwnng:1; + uint64_t rsverr:1; + uint64_t tpaovr:1; + uint64_t diperr:1; + uint64_t syncerr:1; + uint64_t calerr:1; + uint64_t reserved_12_30:19; + uint64_t spf:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_spxx_int_reg_s cn38xx; struct cvmx_spxx_int_reg_s cn38xxp2; @@ -271,6 +389,7 @@ union cvmx_spxx_int_reg { union cvmx_spxx_int_sync { uint64_t u64; struct cvmx_spxx_int_sync_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t calerr:1; uint64_t syncerr:1; @@ -283,6 +402,20 @@ union cvmx_spxx_int_sync { uint64_t reserved_2_3:2; uint64_t abnorm:1; uint64_t prtnxa:1; +#else + uint64_t prtnxa:1; + uint64_t abnorm:1; + uint64_t reserved_2_3:2; + uint64_t spiovr:1; + uint64_t clserr:1; + uint64_t drwnng:1; + uint64_t rsverr:1; + uint64_t tpaovr:1; + uint64_t diperr:1; + uint64_t syncerr:1; + uint64_t calerr:1; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_spxx_int_sync_s cn38xx; struct cvmx_spxx_int_sync_s cn38xxp2; @@ -293,8 +426,13 @@ union cvmx_spxx_int_sync { union cvmx_spxx_tpa_acc { uint64_t u64; struct cvmx_spxx_tpa_acc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_spxx_tpa_acc_s cn38xx; struct cvmx_spxx_tpa_acc_s cn38xxp2; @@ -305,8 +443,13 @@ union cvmx_spxx_tpa_acc { union cvmx_spxx_tpa_max { uint64_t u64; struct cvmx_spxx_tpa_max_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t max:32; +#else + uint64_t max:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_spxx_tpa_max_s cn38xx; struct cvmx_spxx_tpa_max_s cn38xxp2; @@ -317,8 +460,13 @@ union cvmx_spxx_tpa_max { union cvmx_spxx_tpa_sel { uint64_t u64; struct cvmx_spxx_tpa_sel_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t prtsel:4; +#else + uint64_t prtsel:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_spxx_tpa_sel_s cn38xx; struct cvmx_spxx_tpa_sel_s cn38xxp2; @@ -329,6 +477,7 @@ union cvmx_spxx_tpa_sel { union cvmx_spxx_trn4_ctl { uint64_t u64; struct cvmx_spxx_trn4_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t trntest:1; uint64_t jitter:3; @@ -337,6 +486,16 @@ union cvmx_spxx_trn4_ctl { uint64_t maxdist:5; uint64_t macro_en:1; uint64_t mux_en:1; +#else + uint64_t mux_en:1; + uint64_t macro_en:1; + uint64_t maxdist:5; + uint64_t set_boot:1; + uint64_t clr_boot:1; + uint64_t jitter:3; + uint64_t trntest:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_spxx_trn4_ctl_s cn38xx; struct cvmx_spxx_trn4_ctl_s cn38xxp2; diff --git a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h index 7be7e9ed7465..5140f2d2ad1c 100644 --- a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2011 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -79,6 +79,7 @@ union cvmx_sriox_acc_ctrl { uint64_t u64; struct cvmx_sriox_acc_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t deny_adr2:1; uint64_t deny_adr1:1; @@ -87,12 +88,29 @@ union cvmx_sriox_acc_ctrl { uint64_t deny_bar2:1; uint64_t deny_bar1:1; uint64_t deny_bar0:1; +#else + uint64_t deny_bar0:1; + uint64_t deny_bar1:1; + uint64_t deny_bar2:1; + uint64_t reserved_3_3:1; + uint64_t deny_adr0:1; + uint64_t deny_adr1:1; + uint64_t deny_adr2:1; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_sriox_acc_ctrl_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t deny_bar2:1; uint64_t deny_bar1:1; uint64_t deny_bar0:1; +#else + uint64_t deny_bar0:1; + uint64_t deny_bar1:1; + uint64_t deny_bar2:1; + uint64_t reserved_3_63:61; +#endif } cn63xx; struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1; struct cvmx_sriox_acc_ctrl_s cn66xx; @@ -101,9 +119,15 @@ union cvmx_sriox_acc_ctrl { union cvmx_sriox_asmbly_id { uint64_t u64; struct cvmx_sriox_asmbly_id_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t assy_id:16; uint64_t assy_ven:16; +#else + uint64_t assy_ven:16; + uint64_t assy_id:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_asmbly_id_s cn63xx; struct cvmx_sriox_asmbly_id_s cn63xxp1; @@ -113,9 +137,15 @@ union cvmx_sriox_asmbly_id { union cvmx_sriox_asmbly_info { uint64_t u64; struct cvmx_sriox_asmbly_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t assy_rev:16; uint64_t reserved_0_15:16; +#else + uint64_t reserved_0_15:16; + uint64_t assy_rev:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_asmbly_info_s cn63xx; struct cvmx_sriox_asmbly_info_s cn63xxp1; @@ -125,11 +155,19 @@ union cvmx_sriox_asmbly_info { union cvmx_sriox_bell_resp_ctrl { uint64_t u64; struct cvmx_sriox_bell_resp_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t rp1_sid:1; uint64_t rp0_sid:2; uint64_t rp1_pid:1; uint64_t rp0_pid:2; +#else + uint64_t rp0_pid:2; + uint64_t rp1_pid:1; + uint64_t rp0_sid:2; + uint64_t rp1_sid:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_sriox_bell_resp_ctrl_s cn63xx; struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1; @@ -139,6 +177,7 @@ union cvmx_sriox_bell_resp_ctrl { union cvmx_sriox_bist_status { uint64_t u64; struct cvmx_sriox_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t lram:1; uint64_t mram:2; @@ -159,8 +198,31 @@ union cvmx_sriox_bist_status { uint64_t rxbuf:2; uint64_t imsg:5; uint64_t omsg:7; +#else + uint64_t omsg:7; + uint64_t imsg:5; + uint64_t rxbuf:2; + uint64_t txbuf:2; + uint64_t ospf:1; + uint64_t ispf:1; + uint64_t oarb:2; + uint64_t rxbuf2:2; + uint64_t oarb2:2; + uint64_t optrs:4; + uint64_t obulk:4; + uint64_t rtn:2; + uint64_t ofree:1; + uint64_t itag:1; + uint64_t otag:2; + uint64_t bell:2; + uint64_t cram:2; + uint64_t mram:2; + uint64_t lram:1; + uint64_t reserved_45_63:19; +#endif } s; struct cvmx_sriox_bist_status_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t mram:2; uint64_t cram:2; @@ -180,8 +242,30 @@ union cvmx_sriox_bist_status { uint64_t rxbuf:2; uint64_t imsg:5; uint64_t omsg:7; +#else + uint64_t omsg:7; + uint64_t imsg:5; + uint64_t rxbuf:2; + uint64_t txbuf:2; + uint64_t ospf:1; + uint64_t ispf:1; + uint64_t oarb:2; + uint64_t rxbuf2:2; + uint64_t oarb2:2; + uint64_t optrs:4; + uint64_t obulk:4; + uint64_t rtn:2; + uint64_t ofree:1; + uint64_t itag:1; + uint64_t otag:2; + uint64_t bell:2; + uint64_t cram:2; + uint64_t mram:2; + uint64_t reserved_44_63:20; +#endif } cn63xx; struct cvmx_sriox_bist_status_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t mram:2; uint64_t cram:2; @@ -200,6 +284,26 @@ union cvmx_sriox_bist_status { uint64_t rxbuf:2; uint64_t imsg:5; uint64_t omsg:7; +#else + uint64_t omsg:7; + uint64_t imsg:5; + uint64_t rxbuf:2; + uint64_t txbuf:2; + uint64_t ospf:1; + uint64_t ispf:1; + uint64_t oarb:2; + uint64_t reserved_20_23:4; + uint64_t optrs:4; + uint64_t obulk:4; + uint64_t rtn:2; + uint64_t ofree:1; + uint64_t itag:1; + uint64_t otag:2; + uint64_t bell:2; + uint64_t cram:2; + uint64_t mram:2; + uint64_t reserved_44_63:20; +#endif } cn63xxp1; struct cvmx_sriox_bist_status_s cn66xx; }; @@ -207,6 +311,7 @@ union cvmx_sriox_bist_status { union cvmx_sriox_imsg_ctrl { uint64_t u64; struct cvmx_sriox_imsg_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t to_mode:1; uint64_t reserved_30_30:1; @@ -221,6 +326,22 @@ union cvmx_sriox_imsg_ctrl { uint64_t lttr:4; uint64_t prio:4; uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t prio:4; + uint64_t lttr:4; + uint64_t prt_sel:3; + uint64_t reserved_15_15:1; + uint64_t rp0_pid:2; + uint64_t rp1_pid:1; + uint64_t rp0_sid:2; + uint64_t rp1_sid:1; + uint64_t reserved_22_23:2; + uint64_t rsp_thr:6; + uint64_t reserved_30_30:1; + uint64_t to_mode:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_imsg_ctrl_s cn63xx; struct cvmx_sriox_imsg_ctrl_s cn63xxp1; @@ -230,6 +351,7 @@ union cvmx_sriox_imsg_ctrl { union cvmx_sriox_imsg_inst_hdrx { uint64_t u64; struct cvmx_sriox_imsg_inst_hdrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t r:1; uint64_t reserved_58_62:5; uint64_t pm:2; @@ -244,6 +366,22 @@ union cvmx_sriox_imsg_inst_hdrx { uint64_t rs:1; uint64_t tt:2; uint64_t tag:32; +#else + uint64_t tag:32; + uint64_t tt:2; + uint64_t rs:1; + uint64_t reserved_35_41:7; + uint64_t ntag:1; + uint64_t ntt:1; + uint64_t ngrp:1; + uint64_t nqos:1; + uint64_t reserved_46_47:2; + uint64_t sl:7; + uint64_t reserved_55_55:1; + uint64_t pm:2; + uint64_t reserved_58_62:5; + uint64_t r:1; +#endif } s; struct cvmx_sriox_imsg_inst_hdrx_s cn63xx; struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1; @@ -253,6 +391,7 @@ union cvmx_sriox_imsg_inst_hdrx { union cvmx_sriox_imsg_qos_grpx { uint64_t u64; struct cvmx_sriox_imsg_qos_grpx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_63_63:1; uint64_t qos7:3; uint64_t grp7:4; @@ -277,6 +416,32 @@ union cvmx_sriox_imsg_qos_grpx { uint64_t reserved_7_7:1; uint64_t qos0:3; uint64_t grp0:4; +#else + uint64_t grp0:4; + uint64_t qos0:3; + uint64_t reserved_7_7:1; + uint64_t grp1:4; + uint64_t qos1:3; + uint64_t reserved_15_15:1; + uint64_t grp2:4; + uint64_t qos2:3; + uint64_t reserved_23_23:1; + uint64_t grp3:4; + uint64_t qos3:3; + uint64_t reserved_31_31:1; + uint64_t grp4:4; + uint64_t qos4:3; + uint64_t reserved_39_39:1; + uint64_t grp5:4; + uint64_t qos5:3; + uint64_t reserved_47_47:1; + uint64_t grp6:4; + uint64_t qos6:3; + uint64_t reserved_55_55:1; + uint64_t grp7:4; + uint64_t qos7:3; + uint64_t reserved_63_63:1; +#endif } s; struct cvmx_sriox_imsg_qos_grpx_s cn63xx; struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1; @@ -286,6 +451,7 @@ union cvmx_sriox_imsg_qos_grpx { union cvmx_sriox_imsg_statusx { uint64_t u64; struct cvmx_sriox_imsg_statusx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t val1:1; uint64_t err1:1; uint64_t toe1:1; @@ -310,6 +476,32 @@ union cvmx_sriox_imsg_statusx { uint64_t mbox0:2; uint64_t lttr0:2; uint64_t sid0:16; +#else + uint64_t sid0:16; + uint64_t lttr0:2; + uint64_t mbox0:2; + uint64_t seg0:4; + uint64_t dis0:1; + uint64_t tt0:1; + uint64_t reserved_26_26:1; + uint64_t prt0:1; + uint64_t toc0:1; + uint64_t toe0:1; + uint64_t err0:1; + uint64_t val0:1; + uint64_t sid1:16; + uint64_t lttr1:2; + uint64_t mbox1:2; + uint64_t seg1:4; + uint64_t dis1:1; + uint64_t tt1:1; + uint64_t reserved_58_58:1; + uint64_t prt1:1; + uint64_t toc1:1; + uint64_t toe1:1; + uint64_t err1:1; + uint64_t val1:1; +#endif } s; struct cvmx_sriox_imsg_statusx_s cn63xx; struct cvmx_sriox_imsg_statusx_s cn63xxp1; @@ -319,6 +511,7 @@ union cvmx_sriox_imsg_statusx { union cvmx_sriox_imsg_vport_thr { uint64_t u64; struct cvmx_sriox_imsg_vport_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t max_tot:6; uint64_t reserved_46_47:2; @@ -332,6 +525,21 @@ union cvmx_sriox_imsg_vport_thr { uint64_t max_p1:6; uint64_t reserved_6_7:2; uint64_t max_p0:6; +#else + uint64_t max_p0:6; + uint64_t reserved_6_7:2; + uint64_t max_p1:6; + uint64_t reserved_14_15:2; + uint64_t buf_thr:4; + uint64_t reserved_20_30:11; + uint64_t sp_vport:1; + uint64_t max_s0:6; + uint64_t reserved_38_39:2; + uint64_t max_s1:6; + uint64_t reserved_46_47:2; + uint64_t max_tot:6; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_sriox_imsg_vport_thr_s cn63xx; struct cvmx_sriox_imsg_vport_thr_s cn63xxp1; @@ -341,11 +549,19 @@ union cvmx_sriox_imsg_vport_thr { union cvmx_sriox_imsg_vport_thr2 { uint64_t u64; struct cvmx_sriox_imsg_vport_thr2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_46_63:18; uint64_t max_s3:6; uint64_t reserved_38_39:2; uint64_t max_s2:6; uint64_t reserved_0_31:32; +#else + uint64_t reserved_0_31:32; + uint64_t max_s2:6; + uint64_t reserved_38_39:2; + uint64_t max_s3:6; + uint64_t reserved_46_63:18; +#endif } s; struct cvmx_sriox_imsg_vport_thr2_s cn66xx; }; @@ -353,8 +569,13 @@ union cvmx_sriox_imsg_vport_thr2 { union cvmx_sriox_int2_enable { uint64_t u64; struct cvmx_sriox_int2_enable_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t pko_rst:1; +#else + uint64_t pko_rst:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_sriox_int2_enable_s cn63xx; struct cvmx_sriox_int2_enable_s cn66xx; @@ -363,10 +584,17 @@ union cvmx_sriox_int2_enable { union cvmx_sriox_int2_reg { uint64_t u64; struct cvmx_sriox_int2_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t int_sum:1; uint64_t reserved_1_30:30; uint64_t pko_rst:1; +#else + uint64_t pko_rst:1; + uint64_t reserved_1_30:30; + uint64_t int_sum:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_int2_reg_s cn63xx; struct cvmx_sriox_int2_reg_s cn66xx; @@ -375,6 +603,7 @@ union cvmx_sriox_int2_reg { union cvmx_sriox_int_enable { uint64_t u64; struct cvmx_sriox_int_enable_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t zero_pkt:1; uint64_t ttl_tout:1; @@ -403,9 +632,40 @@ union cvmx_sriox_int_enable { uint64_t rxbell:1; uint64_t bell_err:1; uint64_t txbell:1; +#else + uint64_t txbell:1; + uint64_t bell_err:1; + uint64_t rxbell:1; + uint64_t maint_op:1; + uint64_t bar_err:1; + uint64_t deny_wr:1; + uint64_t sli_err:1; + uint64_t wr_done:1; + uint64_t mce_tx:1; + uint64_t mce_rx:1; + uint64_t soft_tx:1; + uint64_t soft_rx:1; + uint64_t log_erb:1; + uint64_t phy_erb:1; + uint64_t link_dwn:1; + uint64_t link_up:1; + uint64_t omsg0:1; + uint64_t omsg1:1; + uint64_t omsg_err:1; + uint64_t pko_err:1; + uint64_t rtry_err:1; + uint64_t f_error:1; + uint64_t mac_buf:1; + uint64_t degrade:1; + uint64_t fail:1; + uint64_t ttl_tout:1; + uint64_t zero_pkt:1; + uint64_t reserved_27_63:37; +#endif } s; struct cvmx_sriox_int_enable_s cn63xx; struct cvmx_sriox_int_enable_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t f_error:1; uint64_t rtry_err:1; @@ -429,6 +689,31 @@ union cvmx_sriox_int_enable { uint64_t rxbell:1; uint64_t bell_err:1; uint64_t txbell:1; +#else + uint64_t txbell:1; + uint64_t bell_err:1; + uint64_t rxbell:1; + uint64_t maint_op:1; + uint64_t bar_err:1; + uint64_t deny_wr:1; + uint64_t sli_err:1; + uint64_t wr_done:1; + uint64_t mce_tx:1; + uint64_t mce_rx:1; + uint64_t soft_tx:1; + uint64_t soft_rx:1; + uint64_t log_erb:1; + uint64_t phy_erb:1; + uint64_t link_dwn:1; + uint64_t link_up:1; + uint64_t omsg0:1; + uint64_t omsg1:1; + uint64_t omsg_err:1; + uint64_t pko_err:1; + uint64_t rtry_err:1; + uint64_t f_error:1; + uint64_t reserved_22_63:42; +#endif } cn63xxp1; struct cvmx_sriox_int_enable_s cn66xx; }; @@ -436,6 +721,7 @@ union cvmx_sriox_int_enable { union cvmx_sriox_int_info0 { uint64_t u64; struct cvmx_sriox_int_info0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t cmd:4; uint64_t type:4; uint64_t tag:8; @@ -445,6 +731,17 @@ union cvmx_sriox_int_info0 { uint64_t reserved_16_28:13; uint64_t be0:8; uint64_t be1:8; +#else + uint64_t be1:8; + uint64_t be0:8; + uint64_t reserved_16_28:13; + uint64_t status:3; + uint64_t length:10; + uint64_t reserved_42_47:6; + uint64_t tag:8; + uint64_t type:4; + uint64_t cmd:4; +#endif } s; struct cvmx_sriox_int_info0_s cn63xx; struct cvmx_sriox_int_info0_s cn63xxp1; @@ -454,7 +751,11 @@ union cvmx_sriox_int_info0 { union cvmx_sriox_int_info1 { uint64_t u64; struct cvmx_sriox_int_info1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t info1:64; +#else + uint64_t info1:64; +#endif } s; struct cvmx_sriox_int_info1_s cn63xx; struct cvmx_sriox_int_info1_s cn63xxp1; @@ -464,6 +765,7 @@ union cvmx_sriox_int_info1 { union cvmx_sriox_int_info2 { uint64_t u64; struct cvmx_sriox_int_info2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t prio:2; uint64_t tt:1; uint64_t sis:1; @@ -475,6 +777,19 @@ union cvmx_sriox_int_info2 { uint64_t rsrvd:30; uint64_t lns:1; uint64_t intr:1; +#else + uint64_t intr:1; + uint64_t lns:1; + uint64_t rsrvd:30; + uint64_t letter:2; + uint64_t mbox:2; + uint64_t xmbox:4; + uint64_t did:16; + uint64_t ssize:4; + uint64_t sis:1; + uint64_t tt:1; + uint64_t prio:2; +#endif } s; struct cvmx_sriox_int_info2_s cn63xx; struct cvmx_sriox_int_info2_s cn63xxp1; @@ -484,11 +799,19 @@ union cvmx_sriox_int_info2 { union cvmx_sriox_int_info3 { uint64_t u64; struct cvmx_sriox_int_info3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t prio:2; uint64_t tt:2; uint64_t type:4; uint64_t other:48; uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t other:48; + uint64_t type:4; + uint64_t tt:2; + uint64_t prio:2; +#endif } s; struct cvmx_sriox_int_info3_s cn63xx; struct cvmx_sriox_int_info3_s cn63xxp1; @@ -498,6 +821,7 @@ union cvmx_sriox_int_info3 { union cvmx_sriox_int_reg { uint64_t u64; struct cvmx_sriox_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t int2_sum:1; uint64_t reserved_27_30:4; @@ -528,9 +852,42 @@ union cvmx_sriox_int_reg { uint64_t rxbell:1; uint64_t bell_err:1; uint64_t txbell:1; +#else + uint64_t txbell:1; + uint64_t bell_err:1; + uint64_t rxbell:1; + uint64_t maint_op:1; + uint64_t bar_err:1; + uint64_t deny_wr:1; + uint64_t sli_err:1; + uint64_t wr_done:1; + uint64_t mce_tx:1; + uint64_t mce_rx:1; + uint64_t soft_tx:1; + uint64_t soft_rx:1; + uint64_t log_erb:1; + uint64_t phy_erb:1; + uint64_t link_dwn:1; + uint64_t link_up:1; + uint64_t omsg0:1; + uint64_t omsg1:1; + uint64_t omsg_err:1; + uint64_t pko_err:1; + uint64_t rtry_err:1; + uint64_t f_error:1; + uint64_t mac_buf:1; + uint64_t degrad:1; + uint64_t fail:1; + uint64_t ttl_tout:1; + uint64_t zero_pkt:1; + uint64_t reserved_27_30:4; + uint64_t int2_sum:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_int_reg_s cn63xx; struct cvmx_sriox_int_reg_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t f_error:1; uint64_t rtry_err:1; @@ -554,6 +911,31 @@ union cvmx_sriox_int_reg { uint64_t rxbell:1; uint64_t bell_err:1; uint64_t txbell:1; +#else + uint64_t txbell:1; + uint64_t bell_err:1; + uint64_t rxbell:1; + uint64_t maint_op:1; + uint64_t bar_err:1; + uint64_t deny_wr:1; + uint64_t sli_err:1; + uint64_t wr_done:1; + uint64_t mce_tx:1; + uint64_t mce_rx:1; + uint64_t soft_tx:1; + uint64_t soft_rx:1; + uint64_t log_erb:1; + uint64_t phy_erb:1; + uint64_t link_dwn:1; + uint64_t link_up:1; + uint64_t omsg0:1; + uint64_t omsg1:1; + uint64_t omsg_err:1; + uint64_t pko_err:1; + uint64_t rtry_err:1; + uint64_t f_error:1; + uint64_t reserved_22_63:42; +#endif } cn63xxp1; struct cvmx_sriox_int_reg_s cn66xx; }; @@ -561,6 +943,7 @@ union cvmx_sriox_int_reg { union cvmx_sriox_ip_feature { uint64_t u64; struct cvmx_sriox_ip_feature_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t ops:32; uint64_t reserved_15_31:17; uint64_t no_vmin:1; @@ -571,8 +954,21 @@ union cvmx_sriox_ip_feature { uint64_t pt_width:2; uint64_t tx_pol:4; uint64_t rx_pol:4; +#else + uint64_t rx_pol:4; + uint64_t tx_pol:4; + uint64_t pt_width:2; + uint64_t tx_flow:1; + uint64_t reserved_11_11:1; + uint64_t a50:1; + uint64_t a66:1; + uint64_t no_vmin:1; + uint64_t reserved_15_31:17; + uint64_t ops:32; +#endif } s; struct cvmx_sriox_ip_feature_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t ops:32; uint64_t reserved_14_31:18; uint64_t a66:1; @@ -582,6 +978,17 @@ union cvmx_sriox_ip_feature { uint64_t pt_width:2; uint64_t tx_pol:4; uint64_t rx_pol:4; +#else + uint64_t rx_pol:4; + uint64_t tx_pol:4; + uint64_t pt_width:2; + uint64_t tx_flow:1; + uint64_t reserved_11_11:1; + uint64_t a50:1; + uint64_t a66:1; + uint64_t reserved_14_31:18; + uint64_t ops:32; +#endif } cn63xx; struct cvmx_sriox_ip_feature_cn63xx cn63xxp1; struct cvmx_sriox_ip_feature_s cn66xx; @@ -590,6 +997,7 @@ union cvmx_sriox_ip_feature { union cvmx_sriox_mac_buffers { uint64_t u64; struct cvmx_sriox_mac_buffers_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t tx_enb:8; uint64_t reserved_44_47:4; @@ -600,6 +1008,18 @@ union cvmx_sriox_mac_buffers { uint64_t reserved_12_15:4; uint64_t rx_inuse:4; uint64_t rx_stat:8; +#else + uint64_t rx_stat:8; + uint64_t rx_inuse:4; + uint64_t reserved_12_15:4; + uint64_t rx_enb:8; + uint64_t reserved_24_31:8; + uint64_t tx_stat:8; + uint64_t tx_inuse:4; + uint64_t reserved_44_47:4; + uint64_t tx_enb:8; + uint64_t reserved_56_63:8; +#endif } s; struct cvmx_sriox_mac_buffers_s cn63xx; struct cvmx_sriox_mac_buffers_s cn66xx; @@ -608,12 +1028,21 @@ union cvmx_sriox_mac_buffers { union cvmx_sriox_maint_op { uint64_t u64; struct cvmx_sriox_maint_op_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_data:32; uint64_t reserved_27_31:5; uint64_t fail:1; uint64_t pending:1; uint64_t op:1; uint64_t addr:24; +#else + uint64_t addr:24; + uint64_t op:1; + uint64_t pending:1; + uint64_t fail:1; + uint64_t reserved_27_31:5; + uint64_t wr_data:32; +#endif } s; struct cvmx_sriox_maint_op_s cn63xx; struct cvmx_sriox_maint_op_s cn63xxp1; @@ -623,9 +1052,15 @@ union cvmx_sriox_maint_op { union cvmx_sriox_maint_rd_data { uint64_t u64; struct cvmx_sriox_maint_rd_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_33_63:31; uint64_t valid:1; uint64_t rd_data:32; +#else + uint64_t rd_data:32; + uint64_t valid:1; + uint64_t reserved_33_63:31; +#endif } s; struct cvmx_sriox_maint_rd_data_s cn63xx; struct cvmx_sriox_maint_rd_data_s cn63xxp1; @@ -635,8 +1070,13 @@ union cvmx_sriox_maint_rd_data { union cvmx_sriox_mce_tx_ctl { uint64_t u64; struct cvmx_sriox_mce_tx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t mce:1; +#else + uint64_t mce:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_sriox_mce_tx_ctl_s cn63xx; struct cvmx_sriox_mce_tx_ctl_s cn63xxp1; @@ -646,6 +1086,7 @@ union cvmx_sriox_mce_tx_ctl { union cvmx_sriox_mem_op_ctrl { uint64_t u64; struct cvmx_sriox_mem_op_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t rr_ro:1; uint64_t w_ro:1; @@ -654,6 +1095,16 @@ union cvmx_sriox_mem_op_ctrl { uint64_t rp0_sid:2; uint64_t rp1_pid:1; uint64_t rp0_pid:2; +#else + uint64_t rp0_pid:2; + uint64_t rp1_pid:1; + uint64_t rp0_sid:2; + uint64_t rp1_sid:1; + uint64_t reserved_6_7:2; + uint64_t w_ro:1; + uint64_t rr_ro:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_sriox_mem_op_ctrl_s cn63xx; struct cvmx_sriox_mem_op_ctrl_s cn63xxp1; @@ -663,6 +1114,7 @@ union cvmx_sriox_mem_op_ctrl { union cvmx_sriox_omsg_ctrlx { uint64_t u64; struct cvmx_sriox_omsg_ctrlx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t testmode:1; uint64_t reserved_37_62:26; uint64_t silo_max:5; @@ -674,9 +1126,23 @@ union cvmx_sriox_omsg_ctrlx { uint64_t idm_did:1; uint64_t lttr_sp:4; uint64_t lttr_mp:4; +#else + uint64_t lttr_mp:4; + uint64_t lttr_sp:4; + uint64_t idm_did:1; + uint64_t idm_sis:1; + uint64_t idm_tt:1; + uint64_t reserved_11_14:4; + uint64_t rtry_en:1; + uint64_t rtry_thr:16; + uint64_t silo_max:5; + uint64_t reserved_37_62:26; + uint64_t testmode:1; +#endif } s; struct cvmx_sriox_omsg_ctrlx_s cn63xx; struct cvmx_sriox_omsg_ctrlx_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t testmode:1; uint64_t reserved_32_62:31; uint64_t rtry_thr:16; @@ -687,6 +1153,18 @@ union cvmx_sriox_omsg_ctrlx { uint64_t idm_did:1; uint64_t lttr_sp:4; uint64_t lttr_mp:4; +#else + uint64_t lttr_mp:4; + uint64_t lttr_sp:4; + uint64_t idm_did:1; + uint64_t idm_sis:1; + uint64_t idm_tt:1; + uint64_t reserved_11_14:4; + uint64_t rtry_en:1; + uint64_t rtry_thr:16; + uint64_t reserved_32_62:31; + uint64_t testmode:1; +#endif } cn63xxp1; struct cvmx_sriox_omsg_ctrlx_s cn66xx; }; @@ -694,9 +1172,15 @@ union cvmx_sriox_omsg_ctrlx { union cvmx_sriox_omsg_done_countsx { uint64_t u64; struct cvmx_sriox_omsg_done_countsx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bad:16; uint64_t good:16; +#else + uint64_t good:16; + uint64_t bad:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_omsg_done_countsx_s cn63xx; struct cvmx_sriox_omsg_done_countsx_s cn66xx; @@ -705,6 +1189,7 @@ union cvmx_sriox_omsg_done_countsx { union cvmx_sriox_omsg_fmp_mrx { uint64_t u64; struct cvmx_sriox_omsg_fmp_mrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t ctlr_sp:1; uint64_t ctlr_fmp:1; @@ -721,6 +1206,24 @@ union cvmx_sriox_omsg_fmp_mrx { uint64_t all_fmp:1; uint64_t all_nmp:1; uint64_t all_psd:1; +#else + uint64_t all_psd:1; + uint64_t all_nmp:1; + uint64_t all_fmp:1; + uint64_t all_sp:1; + uint64_t mbox_psd:1; + uint64_t mbox_nmp:1; + uint64_t mbox_fmp:1; + uint64_t mbox_sp:1; + uint64_t id_psd:1; + uint64_t id_nmp:1; + uint64_t id_fmp:1; + uint64_t id_sp:1; + uint64_t ctlr_nmp:1; + uint64_t ctlr_fmp:1; + uint64_t ctlr_sp:1; + uint64_t reserved_15_63:49; +#endif } s; struct cvmx_sriox_omsg_fmp_mrx_s cn63xx; struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1; @@ -730,6 +1233,7 @@ union cvmx_sriox_omsg_fmp_mrx { union cvmx_sriox_omsg_nmp_mrx { uint64_t u64; struct cvmx_sriox_omsg_nmp_mrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t ctlr_sp:1; uint64_t ctlr_fmp:1; @@ -746,6 +1250,24 @@ union cvmx_sriox_omsg_nmp_mrx { uint64_t all_fmp:1; uint64_t all_nmp:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t all_nmp:1; + uint64_t all_fmp:1; + uint64_t all_sp:1; + uint64_t reserved_4_4:1; + uint64_t mbox_nmp:1; + uint64_t mbox_fmp:1; + uint64_t mbox_sp:1; + uint64_t reserved_8_8:1; + uint64_t id_nmp:1; + uint64_t id_fmp:1; + uint64_t id_sp:1; + uint64_t ctlr_nmp:1; + uint64_t ctlr_fmp:1; + uint64_t ctlr_sp:1; + uint64_t reserved_15_63:49; +#endif } s; struct cvmx_sriox_omsg_nmp_mrx_s cn63xx; struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1; @@ -755,16 +1277,30 @@ union cvmx_sriox_omsg_nmp_mrx { union cvmx_sriox_omsg_portx { uint64_t u64; struct cvmx_sriox_omsg_portx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enable:1; uint64_t reserved_3_30:28; uint64_t port:3; +#else + uint64_t port:3; + uint64_t reserved_3_30:28; + uint64_t enable:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_omsg_portx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enable:1; uint64_t reserved_2_30:29; uint64_t port:2; +#else + uint64_t port:2; + uint64_t reserved_2_30:29; + uint64_t enable:1; + uint64_t reserved_32_63:32; +#endif } cn63xx; struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1; struct cvmx_sriox_omsg_portx_s cn66xx; @@ -773,8 +1309,13 @@ union cvmx_sriox_omsg_portx { union cvmx_sriox_omsg_silo_thr { uint64_t u64; struct cvmx_sriox_omsg_silo_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t tot_silo:5; +#else + uint64_t tot_silo:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_sriox_omsg_silo_thr_s cn63xx; struct cvmx_sriox_omsg_silo_thr_s cn66xx; @@ -783,6 +1324,7 @@ union cvmx_sriox_omsg_silo_thr { union cvmx_sriox_omsg_sp_mrx { uint64_t u64; struct cvmx_sriox_omsg_sp_mrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t xmbox_sp:1; uint64_t ctlr_sp:1; @@ -800,6 +1342,25 @@ union cvmx_sriox_omsg_sp_mrx { uint64_t all_fmp:1; uint64_t all_nmp:1; uint64_t all_psd:1; +#else + uint64_t all_psd:1; + uint64_t all_nmp:1; + uint64_t all_fmp:1; + uint64_t all_sp:1; + uint64_t mbox_psd:1; + uint64_t mbox_nmp:1; + uint64_t mbox_fmp:1; + uint64_t mbox_sp:1; + uint64_t id_psd:1; + uint64_t id_nmp:1; + uint64_t id_fmp:1; + uint64_t id_sp:1; + uint64_t ctlr_nmp:1; + uint64_t ctlr_fmp:1; + uint64_t ctlr_sp:1; + uint64_t xmbox_sp:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_sriox_omsg_sp_mrx_s cn63xx; struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1; @@ -809,9 +1370,15 @@ union cvmx_sriox_omsg_sp_mrx { union cvmx_sriox_priox_in_use { uint64_t u64; struct cvmx_sriox_priox_in_use_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t end_cnt:16; uint64_t start_cnt:16; +#else + uint64_t start_cnt:16; + uint64_t end_cnt:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_priox_in_use_s cn63xx; struct cvmx_sriox_priox_in_use_s cn66xx; @@ -820,6 +1387,7 @@ union cvmx_sriox_priox_in_use { union cvmx_sriox_rx_bell { uint64_t u64; struct cvmx_sriox_rx_bell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t data:16; uint64_t src_id:16; @@ -829,6 +1397,17 @@ union cvmx_sriox_rx_bell { uint64_t id16:1; uint64_t reserved_2_2:1; uint64_t priority:2; +#else + uint64_t priority:2; + uint64_t reserved_2_2:1; + uint64_t id16:1; + uint64_t dest_id:1; + uint64_t reserved_5_7:3; + uint64_t count:8; + uint64_t src_id:16; + uint64_t data:16; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_sriox_rx_bell_s cn63xx; struct cvmx_sriox_rx_bell_s cn63xxp1; @@ -838,9 +1417,15 @@ union cvmx_sriox_rx_bell { union cvmx_sriox_rx_bell_seq { uint64_t u64; struct cvmx_sriox_rx_bell_seq_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t count:8; uint64_t seq:32; +#else + uint64_t seq:32; + uint64_t count:8; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_sriox_rx_bell_seq_s cn63xx; struct cvmx_sriox_rx_bell_seq_s cn63xxp1; @@ -850,6 +1435,7 @@ union cvmx_sriox_rx_bell_seq { union cvmx_sriox_rx_status { uint64_t u64; struct cvmx_sriox_rx_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rtn_pr3:8; uint64_t rtn_pr2:8; uint64_t rtn_pr1:8; @@ -859,6 +1445,17 @@ union cvmx_sriox_rx_status { uint64_t reserved_13_15:3; uint64_t n_post:5; uint64_t post:8; +#else + uint64_t post:8; + uint64_t n_post:5; + uint64_t reserved_13_15:3; + uint64_t comp:8; + uint64_t mbox:4; + uint64_t reserved_28_39:12; + uint64_t rtn_pr1:8; + uint64_t rtn_pr2:8; + uint64_t rtn_pr3:8; +#endif } s; struct cvmx_sriox_rx_status_s cn63xx; struct cvmx_sriox_rx_status_s cn63xxp1; @@ -868,6 +1465,7 @@ union cvmx_sriox_rx_status { union cvmx_sriox_s2m_typex { uint64_t u64; struct cvmx_sriox_s2m_typex_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t wr_op:3; uint64_t reserved_15_15:1; @@ -879,6 +1477,19 @@ union cvmx_sriox_s2m_typex { uint64_t id16:1; uint64_t reserved_2_3:2; uint64_t iaow_sel:2; +#else + uint64_t iaow_sel:2; + uint64_t reserved_2_3:2; + uint64_t id16:1; + uint64_t src_id:1; + uint64_t reserved_6_7:2; + uint64_t rd_prior:2; + uint64_t wr_prior:2; + uint64_t rd_op:3; + uint64_t reserved_15_15:1; + uint64_t wr_op:3; + uint64_t reserved_19_63:45; +#endif } s; struct cvmx_sriox_s2m_typex_s cn63xx; struct cvmx_sriox_s2m_typex_s cn63xxp1; @@ -888,8 +1499,13 @@ union cvmx_sriox_s2m_typex { union cvmx_sriox_seq { uint64_t u64; struct cvmx_sriox_seq_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t seq:32; +#else + uint64_t seq:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_seq_s cn63xx; struct cvmx_sriox_seq_s cn63xxp1; @@ -899,9 +1515,15 @@ union cvmx_sriox_seq { union cvmx_sriox_status_reg { uint64_t u64; struct cvmx_sriox_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t access:1; uint64_t srio:1; +#else + uint64_t srio:1; + uint64_t access:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_sriox_status_reg_s cn63xx; struct cvmx_sriox_status_reg_s cn63xxp1; @@ -911,12 +1533,21 @@ union cvmx_sriox_status_reg { union cvmx_sriox_tag_ctrl { uint64_t u64; struct cvmx_sriox_tag_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t o_clr:1; uint64_t reserved_13_15:3; uint64_t otag:5; uint64_t reserved_5_7:3; uint64_t itag:5; +#else + uint64_t itag:5; + uint64_t reserved_5_7:3; + uint64_t otag:5; + uint64_t reserved_13_15:3; + uint64_t o_clr:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_sriox_tag_ctrl_s cn63xx; struct cvmx_sriox_tag_ctrl_s cn63xxp1; @@ -926,12 +1557,21 @@ union cvmx_sriox_tag_ctrl { union cvmx_sriox_tlp_credits { uint64_t u64; struct cvmx_sriox_tlp_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t mbox:4; uint64_t comp:8; uint64_t reserved_13_15:3; uint64_t n_post:5; uint64_t post:8; +#else + uint64_t post:8; + uint64_t n_post:5; + uint64_t reserved_13_15:3; + uint64_t comp:8; + uint64_t mbox:4; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_sriox_tlp_credits_s cn63xx; struct cvmx_sriox_tlp_credits_s cn63xxp1; @@ -941,6 +1581,7 @@ union cvmx_sriox_tlp_credits { union cvmx_sriox_tx_bell { uint64_t u64; struct cvmx_sriox_tx_bell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t data:16; uint64_t dest_id:16; @@ -951,6 +1592,18 @@ union cvmx_sriox_tx_bell { uint64_t id16:1; uint64_t reserved_2_2:1; uint64_t priority:2; +#else + uint64_t priority:2; + uint64_t reserved_2_2:1; + uint64_t id16:1; + uint64_t src_id:1; + uint64_t reserved_5_7:3; + uint64_t pending:1; + uint64_t reserved_9_15:7; + uint64_t dest_id:16; + uint64_t data:16; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_sriox_tx_bell_s cn63xx; struct cvmx_sriox_tx_bell_s cn63xxp1; @@ -960,6 +1613,7 @@ union cvmx_sriox_tx_bell { union cvmx_sriox_tx_bell_info { uint64_t u64; struct cvmx_sriox_tx_bell_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t data:16; uint64_t dest_id:16; @@ -971,6 +1625,19 @@ union cvmx_sriox_tx_bell_info { uint64_t id16:1; uint64_t reserved_2_2:1; uint64_t priority:2; +#else + uint64_t priority:2; + uint64_t reserved_2_2:1; + uint64_t id16:1; + uint64_t src_id:1; + uint64_t retry:1; + uint64_t error:1; + uint64_t timeout:1; + uint64_t reserved_8_15:8; + uint64_t dest_id:16; + uint64_t data:16; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_sriox_tx_bell_info_s cn63xx; struct cvmx_sriox_tx_bell_info_s cn63xxp1; @@ -980,6 +1647,7 @@ union cvmx_sriox_tx_bell_info { union cvmx_sriox_tx_ctrl { uint64_t u64; struct cvmx_sriox_tx_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_53_63:11; uint64_t tag_th2:5; uint64_t reserved_45_47:3; @@ -992,6 +1660,20 @@ union cvmx_sriox_tx_ctrl { uint64_t tx_th1:4; uint64_t reserved_4_7:4; uint64_t tx_th0:4; +#else + uint64_t tx_th0:4; + uint64_t reserved_4_7:4; + uint64_t tx_th1:4; + uint64_t reserved_12_15:4; + uint64_t tx_th2:4; + uint64_t reserved_20_31:12; + uint64_t tag_th0:5; + uint64_t reserved_37_39:3; + uint64_t tag_th1:5; + uint64_t reserved_45_47:3; + uint64_t tag_th2:5; + uint64_t reserved_53_63:11; +#endif } s; struct cvmx_sriox_tx_ctrl_s cn63xx; struct cvmx_sriox_tx_ctrl_s cn63xxp1; @@ -1001,8 +1683,13 @@ union cvmx_sriox_tx_ctrl { union cvmx_sriox_tx_emphasis { uint64_t u64; struct cvmx_sriox_tx_emphasis_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t emph:4; +#else + uint64_t emph:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_sriox_tx_emphasis_s cn63xx; struct cvmx_sriox_tx_emphasis_s cn66xx; @@ -1011,11 +1698,19 @@ union cvmx_sriox_tx_emphasis { union cvmx_sriox_tx_status { uint64_t u64; struct cvmx_sriox_tx_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t s2m_pr3:8; uint64_t s2m_pr2:8; uint64_t s2m_pr1:8; uint64_t s2m_pr0:8; +#else + uint64_t s2m_pr0:8; + uint64_t s2m_pr1:8; + uint64_t s2m_pr2:8; + uint64_t s2m_pr3:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_tx_status_s cn63xx; struct cvmx_sriox_tx_status_s cn63xxp1; @@ -1025,9 +1720,15 @@ union cvmx_sriox_tx_status { union cvmx_sriox_wr_done_counts { uint64_t u64; struct cvmx_sriox_wr_done_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bad:16; uint64_t good:16; +#else + uint64_t good:16; + uint64_t bad:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_wr_done_counts_s cn63xx; struct cvmx_sriox_wr_done_counts_s cn66xx; diff --git a/arch/mips/include/asm/octeon/cvmx-srxx-defs.h b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h index d82b366c279f..c98e625cd4ed 100644 --- a/arch/mips/include/asm/octeon/cvmx-srxx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,27 +28,29 @@ #ifndef __CVMX_SRXX_DEFS_H__ #define __CVMX_SRXX_DEFS_H__ -#define CVMX_SRXX_COM_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000200ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SRXX_IGN_RX_FULL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000218ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SRXX_SPI4_CALX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000000ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SRXX_SPI4_STAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000208ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SRXX_SW_TICK_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000220ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SRXX_SW_TICK_DAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000228ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull) union cvmx_srxx_com_ctl { uint64_t u64; struct cvmx_srxx_com_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t prts:4; uint64_t st_en:1; uint64_t reserved_1_2:2; uint64_t inf_en:1; +#else + uint64_t inf_en:1; + uint64_t reserved_1_2:2; + uint64_t st_en:1; + uint64_t prts:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_srxx_com_ctl_s cn38xx; struct cvmx_srxx_com_ctl_s cn38xxp2; @@ -59,8 +61,13 @@ union cvmx_srxx_com_ctl { union cvmx_srxx_ign_rx_full { uint64_t u64; struct cvmx_srxx_ign_rx_full_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ignore:16; +#else + uint64_t ignore:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_srxx_ign_rx_full_s cn38xx; struct cvmx_srxx_ign_rx_full_s cn38xxp2; @@ -71,12 +78,21 @@ union cvmx_srxx_ign_rx_full { union cvmx_srxx_spi4_calx { uint64_t u64; struct cvmx_srxx_spi4_calx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t oddpar:1; uint64_t prt3:4; uint64_t prt2:4; uint64_t prt1:4; uint64_t prt0:4; +#else + uint64_t prt0:4; + uint64_t prt1:4; + uint64_t prt2:4; + uint64_t prt3:4; + uint64_t oddpar:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_srxx_spi4_calx_s cn38xx; struct cvmx_srxx_spi4_calx_s cn38xxp2; @@ -87,10 +103,17 @@ union cvmx_srxx_spi4_calx { union cvmx_srxx_spi4_stat { uint64_t u64; struct cvmx_srxx_spi4_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t m:8; uint64_t reserved_7_7:1; uint64_t len:7; +#else + uint64_t len:7; + uint64_t reserved_7_7:1; + uint64_t m:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_srxx_spi4_stat_s cn38xx; struct cvmx_srxx_spi4_stat_s cn38xxp2; @@ -101,12 +124,21 @@ union cvmx_srxx_spi4_stat { union cvmx_srxx_sw_tick_ctl { uint64_t u64; struct cvmx_srxx_sw_tick_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t eop:1; uint64_t sop:1; uint64_t mod:4; uint64_t opc:4; uint64_t adr:4; +#else + uint64_t adr:4; + uint64_t opc:4; + uint64_t mod:4; + uint64_t sop:1; + uint64_t eop:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_srxx_sw_tick_ctl_s cn38xx; struct cvmx_srxx_sw_tick_ctl_s cn58xx; @@ -116,7 +148,11 @@ union cvmx_srxx_sw_tick_ctl { union cvmx_srxx_sw_tick_dat { uint64_t u64; struct cvmx_srxx_sw_tick_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dat:64; +#else uint64_t dat:64; +#endif } s; struct cvmx_srxx_sw_tick_dat_s cn38xx; struct cvmx_srxx_sw_tick_dat_s cn58xx; diff --git a/arch/mips/include/asm/octeon/cvmx-stxx-defs.h b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h index 4f209b62cae1..146354005d3b 100644 --- a/arch/mips/include/asm/octeon/cvmx-stxx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,47 +28,39 @@ #ifndef __CVMX_STXX_DEFS_H__ #define __CVMX_STXX_DEFS_H__ -#define CVMX_STXX_ARB_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000608ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_BCKPRS_CNT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000688ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_COM_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000600ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_DIP_CNT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000690ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_IGN_CAL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000610ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_INT_MSK(block_id) \ - CVMX_ADD_IO_SEG(0x00011800900006A0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_INT_REG(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000698ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_INT_SYNC(block_id) \ - CVMX_ADD_IO_SEG(0x00011800900006A8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_MIN_BST(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000618ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_SPI4_CALX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000400ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_SPI4_DAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000628ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_SPI4_STAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000630ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_STAT_BYTES_HI(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000648ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_STAT_BYTES_LO(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000680ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_STAT_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000638ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_STAT_PKT_XMT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000640ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull) union cvmx_stxx_arb_ctl { uint64_t u64; struct cvmx_stxx_arb_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mintrn:1; uint64_t reserved_4_4:1; uint64_t igntpa:1; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t igntpa:1; + uint64_t reserved_4_4:1; + uint64_t mintrn:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_stxx_arb_ctl_s cn38xx; struct cvmx_stxx_arb_ctl_s cn38xxp2; @@ -79,8 +71,13 @@ union cvmx_stxx_arb_ctl { union cvmx_stxx_bckprs_cnt { uint64_t u64; struct cvmx_stxx_bckprs_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_stxx_bckprs_cnt_s cn38xx; struct cvmx_stxx_bckprs_cnt_s cn38xxp2; @@ -91,10 +88,17 @@ union cvmx_stxx_bckprs_cnt { union cvmx_stxx_com_ctl { uint64_t u64; struct cvmx_stxx_com_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t st_en:1; uint64_t reserved_1_2:2; uint64_t inf_en:1; +#else + uint64_t inf_en:1; + uint64_t reserved_1_2:2; + uint64_t st_en:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_stxx_com_ctl_s cn38xx; struct cvmx_stxx_com_ctl_s cn38xxp2; @@ -105,9 +109,15 @@ union cvmx_stxx_com_ctl { union cvmx_stxx_dip_cnt { uint64_t u64; struct cvmx_stxx_dip_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t frmmax:4; uint64_t dipmax:4; +#else + uint64_t dipmax:4; + uint64_t frmmax:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_stxx_dip_cnt_s cn38xx; struct cvmx_stxx_dip_cnt_s cn38xxp2; @@ -118,8 +128,13 @@ union cvmx_stxx_dip_cnt { union cvmx_stxx_ign_cal { uint64_t u64; struct cvmx_stxx_ign_cal_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t igntpa:16; +#else + uint64_t igntpa:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_stxx_ign_cal_s cn38xx; struct cvmx_stxx_ign_cal_s cn38xxp2; @@ -130,6 +145,7 @@ union cvmx_stxx_ign_cal { union cvmx_stxx_int_msk { uint64_t u64; struct cvmx_stxx_int_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t frmerr:1; uint64_t unxfrm:1; @@ -139,6 +155,17 @@ union cvmx_stxx_int_msk { uint64_t ovrbst:1; uint64_t calpar1:1; uint64_t calpar0:1; +#else + uint64_t calpar0:1; + uint64_t calpar1:1; + uint64_t ovrbst:1; + uint64_t datovr:1; + uint64_t diperr:1; + uint64_t nosync:1; + uint64_t unxfrm:1; + uint64_t frmerr:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_stxx_int_msk_s cn38xx; struct cvmx_stxx_int_msk_s cn38xxp2; @@ -149,6 +176,7 @@ union cvmx_stxx_int_msk { union cvmx_stxx_int_reg { uint64_t u64; struct cvmx_stxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t syncerr:1; uint64_t frmerr:1; @@ -159,6 +187,18 @@ union cvmx_stxx_int_reg { uint64_t ovrbst:1; uint64_t calpar1:1; uint64_t calpar0:1; +#else + uint64_t calpar0:1; + uint64_t calpar1:1; + uint64_t ovrbst:1; + uint64_t datovr:1; + uint64_t diperr:1; + uint64_t nosync:1; + uint64_t unxfrm:1; + uint64_t frmerr:1; + uint64_t syncerr:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_stxx_int_reg_s cn38xx; struct cvmx_stxx_int_reg_s cn38xxp2; @@ -169,6 +209,7 @@ union cvmx_stxx_int_reg { union cvmx_stxx_int_sync { uint64_t u64; struct cvmx_stxx_int_sync_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t frmerr:1; uint64_t unxfrm:1; @@ -178,6 +219,17 @@ union cvmx_stxx_int_sync { uint64_t ovrbst:1; uint64_t calpar1:1; uint64_t calpar0:1; +#else + uint64_t calpar0:1; + uint64_t calpar1:1; + uint64_t ovrbst:1; + uint64_t datovr:1; + uint64_t diperr:1; + uint64_t nosync:1; + uint64_t unxfrm:1; + uint64_t frmerr:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_stxx_int_sync_s cn38xx; struct cvmx_stxx_int_sync_s cn38xxp2; @@ -188,8 +240,13 @@ union cvmx_stxx_int_sync { union cvmx_stxx_min_bst { uint64_t u64; struct cvmx_stxx_min_bst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t minb:9; +#else + uint64_t minb:9; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_stxx_min_bst_s cn38xx; struct cvmx_stxx_min_bst_s cn38xxp2; @@ -200,12 +257,21 @@ union cvmx_stxx_min_bst { union cvmx_stxx_spi4_calx { uint64_t u64; struct cvmx_stxx_spi4_calx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t oddpar:1; uint64_t prt3:4; uint64_t prt2:4; uint64_t prt1:4; uint64_t prt0:4; +#else + uint64_t prt0:4; + uint64_t prt1:4; + uint64_t prt2:4; + uint64_t prt3:4; + uint64_t oddpar:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_stxx_spi4_calx_s cn38xx; struct cvmx_stxx_spi4_calx_s cn38xxp2; @@ -216,9 +282,15 @@ union cvmx_stxx_spi4_calx { union cvmx_stxx_spi4_dat { uint64_t u64; struct cvmx_stxx_spi4_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t alpha:16; uint64_t max_t:16; +#else + uint64_t max_t:16; + uint64_t alpha:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_stxx_spi4_dat_s cn38xx; struct cvmx_stxx_spi4_dat_s cn38xxp2; @@ -229,10 +301,17 @@ union cvmx_stxx_spi4_dat { union cvmx_stxx_spi4_stat { uint64_t u64; struct cvmx_stxx_spi4_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t m:8; uint64_t reserved_7_7:1; uint64_t len:7; +#else + uint64_t len:7; + uint64_t reserved_7_7:1; + uint64_t m:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_stxx_spi4_stat_s cn38xx; struct cvmx_stxx_spi4_stat_s cn38xxp2; @@ -243,8 +322,13 @@ union cvmx_stxx_spi4_stat { union cvmx_stxx_stat_bytes_hi { uint64_t u64; struct cvmx_stxx_stat_bytes_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_stxx_stat_bytes_hi_s cn38xx; struct cvmx_stxx_stat_bytes_hi_s cn38xxp2; @@ -255,8 +339,13 @@ union cvmx_stxx_stat_bytes_hi { union cvmx_stxx_stat_bytes_lo { uint64_t u64; struct cvmx_stxx_stat_bytes_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_stxx_stat_bytes_lo_s cn38xx; struct cvmx_stxx_stat_bytes_lo_s cn38xxp2; @@ -267,9 +356,15 @@ union cvmx_stxx_stat_bytes_lo { union cvmx_stxx_stat_ctl { uint64_t u64; struct cvmx_stxx_stat_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t clr:1; uint64_t bckprs:4; +#else + uint64_t bckprs:4; + uint64_t clr:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_stxx_stat_ctl_s cn38xx; struct cvmx_stxx_stat_ctl_s cn38xxp2; @@ -280,8 +375,13 @@ union cvmx_stxx_stat_ctl { union cvmx_stxx_stat_pkt_xmt { uint64_t u64; struct cvmx_stxx_stat_pkt_xmt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_stxx_stat_pkt_xmt_s cn38xx; struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2; diff --git a/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h index 594f1b68cd62..bc5b80c6bbe2 100644 --- a/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -25,8 +25,8 @@ * Contact Cavium Networks for more information ***********************license end**************************************/ -#ifndef __CVMX_UCTLX_TYPEDEFS_H__ -#define __CVMX_UCTLX_TYPEDEFS_H__ +#ifndef __CVMX_UCTLX_DEFS_H__ +#define __CVMX_UCTLX_DEFS_H__ #define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull)) #define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull)) @@ -45,6 +45,7 @@ union cvmx_uctlx_bist_status { uint64_t u64; struct cvmx_uctlx_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t data_bis:1; uint64_t desc_bis:1; @@ -52,14 +53,29 @@ union cvmx_uctlx_bist_status { uint64_t orbm_bis:1; uint64_t wrbm_bis:1; uint64_t ppaf_bis:1; +#else + uint64_t ppaf_bis:1; + uint64_t wrbm_bis:1; + uint64_t orbm_bis:1; + uint64_t erbm_bis:1; + uint64_t desc_bis:1; + uint64_t data_bis:1; + uint64_t reserved_6_63:58; +#endif } s; - struct cvmx_uctlx_bist_status_s cn63xx; - struct cvmx_uctlx_bist_status_s cn63xxp1; + struct cvmx_uctlx_bist_status_s cn61xx; + struct cvmx_uctlx_bist_status_s cn63xx; + struct cvmx_uctlx_bist_status_s cn63xxp1; + struct cvmx_uctlx_bist_status_s cn66xx; + struct cvmx_uctlx_bist_status_s cn68xx; + struct cvmx_uctlx_bist_status_s cn68xxp1; + struct cvmx_uctlx_bist_status_s cnf71xx; }; union cvmx_uctlx_clk_rst_ctl { uint64_t u64; struct cvmx_uctlx_clk_rst_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t clear_bist:1; uint64_t start_bist:1; @@ -81,14 +97,43 @@ union cvmx_uctlx_clk_rst_ctl { uint64_t p_por:1; uint64_t p_prst:1; uint64_t hrst:1; +#else + uint64_t hrst:1; + uint64_t p_prst:1; + uint64_t p_por:1; + uint64_t p_com_on:1; + uint64_t reserved_4_4:1; + uint64_t p_refclk_div:2; + uint64_t p_refclk_sel:2; + uint64_t h_div:4; + uint64_t o_clkdiv_en:1; + uint64_t h_clkdiv_en:1; + uint64_t h_clkdiv_rst:1; + uint64_t h_clkdiv_byp:1; + uint64_t o_clkdiv_rst:1; + uint64_t app_start_clk:1; + uint64_t ohci_susp_lgcy:1; + uint64_t ohci_sm:1; + uint64_t ohci_clkcktrst:1; + uint64_t ehci_sm:1; + uint64_t start_bist:1; + uint64_t clear_bist:1; + uint64_t reserved_25_63:39; +#endif } s; - struct cvmx_uctlx_clk_rst_ctl_s cn63xx; - struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1; + struct cvmx_uctlx_clk_rst_ctl_s cn61xx; + struct cvmx_uctlx_clk_rst_ctl_s cn63xx; + struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1; + struct cvmx_uctlx_clk_rst_ctl_s cn66xx; + struct cvmx_uctlx_clk_rst_ctl_s cn68xx; + struct cvmx_uctlx_clk_rst_ctl_s cn68xxp1; + struct cvmx_uctlx_clk_rst_ctl_s cnf71xx; }; union cvmx_uctlx_ehci_ctl { uint64_t u64; struct cvmx_uctlx_ehci_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t desc_rbm:1; uint64_t reg_nb:1; @@ -101,45 +146,96 @@ union cvmx_uctlx_ehci_ctl { uint64_t inv_reg_a2:1; uint64_t ehci_64b_addr_en:1; uint64_t l2c_addr_msb:8; +#else + uint64_t l2c_addr_msb:8; + uint64_t ehci_64b_addr_en:1; + uint64_t inv_reg_a2:1; + uint64_t l2c_desc_emod:2; + uint64_t l2c_buff_emod:2; + uint64_t l2c_stt:1; + uint64_t l2c_0pag:1; + uint64_t l2c_bc:1; + uint64_t l2c_dc:1; + uint64_t reg_nb:1; + uint64_t desc_rbm:1; + uint64_t reserved_20_63:44; +#endif } s; - struct cvmx_uctlx_ehci_ctl_s cn63xx; - struct cvmx_uctlx_ehci_ctl_s cn63xxp1; + struct cvmx_uctlx_ehci_ctl_s cn61xx; + struct cvmx_uctlx_ehci_ctl_s cn63xx; + struct cvmx_uctlx_ehci_ctl_s cn63xxp1; + struct cvmx_uctlx_ehci_ctl_s cn66xx; + struct cvmx_uctlx_ehci_ctl_s cn68xx; + struct cvmx_uctlx_ehci_ctl_s cn68xxp1; + struct cvmx_uctlx_ehci_ctl_s cnf71xx; }; union cvmx_uctlx_ehci_fla { uint64_t u64; struct cvmx_uctlx_ehci_fla_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t fla:6; +#else + uint64_t fla:6; + uint64_t reserved_6_63:58; +#endif } s; - struct cvmx_uctlx_ehci_fla_s cn63xx; - struct cvmx_uctlx_ehci_fla_s cn63xxp1; + struct cvmx_uctlx_ehci_fla_s cn61xx; + struct cvmx_uctlx_ehci_fla_s cn63xx; + struct cvmx_uctlx_ehci_fla_s cn63xxp1; + struct cvmx_uctlx_ehci_fla_s cn66xx; + struct cvmx_uctlx_ehci_fla_s cn68xx; + struct cvmx_uctlx_ehci_fla_s cn68xxp1; + struct cvmx_uctlx_ehci_fla_s cnf71xx; }; union cvmx_uctlx_erto_ctl { uint64_t u64; struct cvmx_uctlx_erto_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t to_val:27; uint64_t reserved_0_4:5; +#else + uint64_t reserved_0_4:5; + uint64_t to_val:27; + uint64_t reserved_32_63:32; +#endif } s; - struct cvmx_uctlx_erto_ctl_s cn63xx; - struct cvmx_uctlx_erto_ctl_s cn63xxp1; + struct cvmx_uctlx_erto_ctl_s cn61xx; + struct cvmx_uctlx_erto_ctl_s cn63xx; + struct cvmx_uctlx_erto_ctl_s cn63xxp1; + struct cvmx_uctlx_erto_ctl_s cn66xx; + struct cvmx_uctlx_erto_ctl_s cn68xx; + struct cvmx_uctlx_erto_ctl_s cn68xxp1; + struct cvmx_uctlx_erto_ctl_s cnf71xx; }; union cvmx_uctlx_if_ena { uint64_t u64; struct cvmx_uctlx_if_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t en:1; +#else + uint64_t en:1; + uint64_t reserved_1_63:63; +#endif } s; - struct cvmx_uctlx_if_ena_s cn63xx; - struct cvmx_uctlx_if_ena_s cn63xxp1; + struct cvmx_uctlx_if_ena_s cn61xx; + struct cvmx_uctlx_if_ena_s cn63xx; + struct cvmx_uctlx_if_ena_s cn63xxp1; + struct cvmx_uctlx_if_ena_s cn66xx; + struct cvmx_uctlx_if_ena_s cn68xx; + struct cvmx_uctlx_if_ena_s cn68xxp1; + struct cvmx_uctlx_if_ena_s cnf71xx; }; union cvmx_uctlx_int_ena { uint64_t u64; struct cvmx_uctlx_int_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ec_ovf_e:1; uint64_t oc_ovf_e:1; @@ -149,14 +245,31 @@ union cvmx_uctlx_int_ena { uint64_t or_psh_f:1; uint64_t er_psh_f:1; uint64_t pp_psh_f:1; +#else + uint64_t pp_psh_f:1; + uint64_t er_psh_f:1; + uint64_t or_psh_f:1; + uint64_t cf_psh_f:1; + uint64_t wb_psh_f:1; + uint64_t wb_pop_e:1; + uint64_t oc_ovf_e:1; + uint64_t ec_ovf_e:1; + uint64_t reserved_8_63:56; +#endif } s; - struct cvmx_uctlx_int_ena_s cn63xx; - struct cvmx_uctlx_int_ena_s cn63xxp1; + struct cvmx_uctlx_int_ena_s cn61xx; + struct cvmx_uctlx_int_ena_s cn63xx; + struct cvmx_uctlx_int_ena_s cn63xxp1; + struct cvmx_uctlx_int_ena_s cn66xx; + struct cvmx_uctlx_int_ena_s cn68xx; + struct cvmx_uctlx_int_ena_s cn68xxp1; + struct cvmx_uctlx_int_ena_s cnf71xx; }; union cvmx_uctlx_int_reg { uint64_t u64; struct cvmx_uctlx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ec_ovf_e:1; uint64_t oc_ovf_e:1; @@ -166,14 +279,31 @@ union cvmx_uctlx_int_reg { uint64_t or_psh_f:1; uint64_t er_psh_f:1; uint64_t pp_psh_f:1; +#else + uint64_t pp_psh_f:1; + uint64_t er_psh_f:1; + uint64_t or_psh_f:1; + uint64_t cf_psh_f:1; + uint64_t wb_psh_f:1; + uint64_t wb_pop_e:1; + uint64_t oc_ovf_e:1; + uint64_t ec_ovf_e:1; + uint64_t reserved_8_63:56; +#endif } s; - struct cvmx_uctlx_int_reg_s cn63xx; - struct cvmx_uctlx_int_reg_s cn63xxp1; + struct cvmx_uctlx_int_reg_s cn61xx; + struct cvmx_uctlx_int_reg_s cn63xx; + struct cvmx_uctlx_int_reg_s cn63xxp1; + struct cvmx_uctlx_int_reg_s cn66xx; + struct cvmx_uctlx_int_reg_s cn68xx; + struct cvmx_uctlx_int_reg_s cn68xxp1; + struct cvmx_uctlx_int_reg_s cnf71xx; }; union cvmx_uctlx_ohci_ctl { uint64_t u64; struct cvmx_uctlx_ohci_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t reg_nb:1; uint64_t l2c_dc:1; @@ -185,35 +315,73 @@ union cvmx_uctlx_ohci_ctl { uint64_t inv_reg_a2:1; uint64_t reserved_8_8:1; uint64_t l2c_addr_msb:8; +#else + uint64_t l2c_addr_msb:8; + uint64_t reserved_8_8:1; + uint64_t inv_reg_a2:1; + uint64_t l2c_desc_emod:2; + uint64_t l2c_buff_emod:2; + uint64_t l2c_stt:1; + uint64_t l2c_0pag:1; + uint64_t l2c_bc:1; + uint64_t l2c_dc:1; + uint64_t reg_nb:1; + uint64_t reserved_19_63:45; +#endif } s; - struct cvmx_uctlx_ohci_ctl_s cn63xx; - struct cvmx_uctlx_ohci_ctl_s cn63xxp1; + struct cvmx_uctlx_ohci_ctl_s cn61xx; + struct cvmx_uctlx_ohci_ctl_s cn63xx; + struct cvmx_uctlx_ohci_ctl_s cn63xxp1; + struct cvmx_uctlx_ohci_ctl_s cn66xx; + struct cvmx_uctlx_ohci_ctl_s cn68xx; + struct cvmx_uctlx_ohci_ctl_s cn68xxp1; + struct cvmx_uctlx_ohci_ctl_s cnf71xx; }; union cvmx_uctlx_orto_ctl { uint64_t u64; struct cvmx_uctlx_orto_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t to_val:24; uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t to_val:24; + uint64_t reserved_32_63:32; +#endif } s; - struct cvmx_uctlx_orto_ctl_s cn63xx; - struct cvmx_uctlx_orto_ctl_s cn63xxp1; + struct cvmx_uctlx_orto_ctl_s cn61xx; + struct cvmx_uctlx_orto_ctl_s cn63xx; + struct cvmx_uctlx_orto_ctl_s cn63xxp1; + struct cvmx_uctlx_orto_ctl_s cn66xx; + struct cvmx_uctlx_orto_ctl_s cn68xx; + struct cvmx_uctlx_orto_ctl_s cn68xxp1; + struct cvmx_uctlx_orto_ctl_s cnf71xx; }; union cvmx_uctlx_ppaf_wm { uint64_t u64; struct cvmx_uctlx_ppaf_wm_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t wm:5; +#else + uint64_t wm:5; + uint64_t reserved_5_63:59; +#endif } s; - struct cvmx_uctlx_ppaf_wm_s cn63xx; - struct cvmx_uctlx_ppaf_wm_s cn63xxp1; + struct cvmx_uctlx_ppaf_wm_s cn61xx; + struct cvmx_uctlx_ppaf_wm_s cn63xx; + struct cvmx_uctlx_ppaf_wm_s cn63xxp1; + struct cvmx_uctlx_ppaf_wm_s cn66xx; + struct cvmx_uctlx_ppaf_wm_s cnf71xx; }; union cvmx_uctlx_uphy_ctl_status { uint64_t u64; struct cvmx_uctlx_uphy_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t bist_done:1; uint64_t bist_err:1; @@ -225,14 +393,33 @@ union cvmx_uctlx_uphy_ctl_status { uint64_t uphy_bist:1; uint64_t bist_en:1; uint64_t ate_reset:1; +#else + uint64_t ate_reset:1; + uint64_t bist_en:1; + uint64_t uphy_bist:1; + uint64_t vtest_en:1; + uint64_t siddq:1; + uint64_t lsbist:1; + uint64_t fsbist:1; + uint64_t hsbist:1; + uint64_t bist_err:1; + uint64_t bist_done:1; + uint64_t reserved_10_63:54; +#endif } s; - struct cvmx_uctlx_uphy_ctl_status_s cn63xx; - struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1; + struct cvmx_uctlx_uphy_ctl_status_s cn61xx; + struct cvmx_uctlx_uphy_ctl_status_s cn63xx; + struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1; + struct cvmx_uctlx_uphy_ctl_status_s cn66xx; + struct cvmx_uctlx_uphy_ctl_status_s cn68xx; + struct cvmx_uctlx_uphy_ctl_status_s cn68xxp1; + struct cvmx_uctlx_uphy_ctl_status_s cnf71xx; }; union cvmx_uctlx_uphy_portx_ctl_status { uint64_t u64; struct cvmx_uctlx_uphy_portx_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_43_63:21; uint64_t tdata_out:4; uint64_t txbiststuffenh:1; @@ -253,9 +440,36 @@ union cvmx_uctlx_uphy_portx_ctl_status { uint64_t tdata_sel:1; uint64_t taddr_in:4; uint64_t tdata_in:8; +#else + uint64_t tdata_in:8; + uint64_t taddr_in:4; + uint64_t tdata_sel:1; + uint64_t tclk:1; + uint64_t loop_en:1; + uint64_t compdistune:3; + uint64_t sqrxtune:3; + uint64_t txfslstune:4; + uint64_t txpreemphasistune:1; + uint64_t txrisetune:1; + uint64_t txvreftune:4; + uint64_t txhsvxtune:2; + uint64_t portreset:1; + uint64_t vbusvldext:1; + uint64_t dppulldown:1; + uint64_t dmpulldown:1; + uint64_t txbiststuffen:1; + uint64_t txbiststuffenh:1; + uint64_t tdata_out:4; + uint64_t reserved_43_63:21; +#endif } s; + struct cvmx_uctlx_uphy_portx_ctl_status_s cn61xx; struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx; struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1; + struct cvmx_uctlx_uphy_portx_ctl_status_s cn66xx; + struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xx; + struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xxp1; + struct cvmx_uctlx_uphy_portx_ctl_status_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h index 23b895cb260b..14dd11f4492a 100644 --- a/arch/mips/include/asm/octeon/octeon-model.h +++ b/arch/mips/include/asm/octeon/octeon-model.h @@ -61,6 +61,16 @@ #define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000 /* Match all cn6XXX Octeon models. */ #define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 +/* Match all cnf7XXX Octeon models. */ +#define OM_MATCH_F7XXX_FAMILY_MODELS 0x80000000 + +/* + * CNF7XXX models with new revision encoding + */ +#define OCTEON_CNF71XX_PASS1_0 0x000d9400 + +#define OCTEON_CNF71XX (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CNF71XX_PASS1_X (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) /* * CN6XXX models with new revision encoding @@ -313,6 +323,14 @@ static inline int __octeon_is_model_runtime__(uint32_t model) const char *octeon_model_get_string(uint32_t chip_id); const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer); +/* + * Return the octeon family, i.e., ProcessorID of the PrID register. + */ +static inline uint32_t cvmx_get_octeon_family(void) +{ + return cvmx_get_proc_id() & OCTEON_FAMILY_MASK; +} + #include <asm/octeon/octeon-feature.h> #endif /* __OCTEON_MODEL_H__ */ diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index c4a1b31966bb..790939dd8244 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -52,6 +52,7 @@ extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task); extern void octeon_init_cvmcount(void); extern void octeon_setup_delays(void); +extern void octeon_io_clk_delay(unsigned long); #define OCTEON_ARGV_MAX_ARGS 64 #define OCTOEN_SERIAL_LEN 20 @@ -254,4 +255,7 @@ extern uint64_t octeon_bootloader_entry_addr; extern void (*octeon_irq_setup_secondary)(void); +typedef void (*octeon_irq_ip4_handler_t)(void); +void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t); + #endif /* __ASM_OCTEON_OCTEON_H */ diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index e9fe7e97ce4c..da4ba49adcf6 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -79,9 +79,9 @@ /* implemented in software */ #define _PAGE_PRESENT_SHIFT (0) #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) -/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */ -#define _PAGE_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) -#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; }) +/* implemented in software, should be unused if cpu_has_rixi. */ +#define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) +#define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; }) /* implemented in software */ #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) @@ -104,12 +104,12 @@ #endif /* Page cannot be executed */ -#define _PAGE_NO_EXEC_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT) -#define _PAGE_NO_EXEC ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; }) +#define _PAGE_NO_EXEC_SHIFT (cpu_has_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT) +#define _PAGE_NO_EXEC ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_EXEC_SHIFT; }) /* Page cannot be read */ -#define _PAGE_NO_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) -#define _PAGE_NO_READ ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; }) +#define _PAGE_NO_READ_SHIFT (cpu_has_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) +#define _PAGE_NO_READ ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_READ_SHIFT; }) #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) @@ -155,7 +155,7 @@ */ static inline uint64_t pte_to_entrylo(unsigned long pte_val) { - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { int sa; #ifdef CONFIG_32BIT sa = 31 - _PAGE_NO_READ_SHIFT; @@ -220,7 +220,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #endif -#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ)) +#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ)) #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) #define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index b2202a68cf0f..c02158be836c 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -22,15 +22,15 @@ struct mm_struct; struct vm_area_struct; #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (cpu_has_rixi ? 0 : _PAGE_READ) | \ _page_cachable_default) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ - (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default) -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ +#define PAGE_COPY __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \ + (cpu_has_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default) +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \ _page_cachable_default) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ _PAGE_GLOBAL | _page_cachable_default) -#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \ +#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \ _page_cachable_default) #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) @@ -299,7 +299,7 @@ static inline pte_t pte_mkdirty(pte_t pte) static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { if (!(pte_val(pte) & _PAGE_NO_READ)) pte_val(pte) |= _PAGE_SILENT_READ; } else { diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index ca97e0ecb64b..946e010f2018 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -139,10 +139,10 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define _TIF_WORK_SYSCALL_EXIT (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT) /* work to do on interrupt/exception return */ -#define _TIF_WORK_MASK (0x0000ffef & \ - ~(_TIF_SECCOMP | _TIF_SYSCALL_AUDIT)) +#define _TIF_WORK_MASK \ + (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME) /* work to do on any return to u-space */ -#define _TIF_ALLWORK_MASK (0x8000ffff & ~_TIF_SECCOMP) +#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK | _TIF_WORK_SYSCALL_EXIT) #endif /* __KERNEL__ */ diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 3d9f75f7ffc9..7e0bf17c9324 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -90,6 +90,8 @@ Ip_u2u1u3(_dsrl); Ip_u2u1u3(_dsrl32); Ip_u3u1u2(_dsubu); Ip_0(_eret); +Ip_u2u1msbu3(_ext); +Ip_u2u1msbu3(_ins); Ip_u1(_j); Ip_u1(_jal); Ip_u1(_jr); diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h index bebbde01be92..161fc4d976e4 100644 --- a/arch/mips/include/asm/unistd.h +++ b/arch/mips/include/asm/unistd.h @@ -367,16 +367,17 @@ #define __NR_setns (__NR_Linux + 344) #define __NR_process_vm_readv (__NR_Linux + 345) #define __NR_process_vm_writev (__NR_Linux + 346) +#define __NR_kcmp (__NR_Linux + 347) /* * Offset of the last Linux o32 flavoured syscall */ -#define __NR_Linux_syscalls 346 +#define __NR_Linux_syscalls 347 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #define __NR_O32_Linux 4000 -#define __NR_O32_Linux_syscalls 346 +#define __NR_O32_Linux_syscalls 347 #if _MIPS_SIM == _MIPS_SIM_ABI64 @@ -690,16 +691,17 @@ #define __NR_setns (__NR_Linux + 303) #define __NR_process_vm_readv (__NR_Linux + 304) #define __NR_process_vm_writev (__NR_Linux + 305) +#define __NR_kcmp (__NR_Linux + 306) /* * Offset of the last Linux 64-bit flavoured syscall */ -#define __NR_Linux_syscalls 305 +#define __NR_Linux_syscalls 306 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ #define __NR_64_Linux 5000 -#define __NR_64_Linux_syscalls 305 +#define __NR_64_Linux_syscalls 306 #if _MIPS_SIM == _MIPS_SIM_NABI32 @@ -1018,16 +1020,17 @@ #define __NR_setns (__NR_Linux + 308) #define __NR_process_vm_readv (__NR_Linux + 309) #define __NR_process_vm_writev (__NR_Linux + 310) +#define __NR_kcmp (__NR_Linux + 311) /* * Offset of the last N32 flavoured syscall */ -#define __NR_Linux_syscalls 310 +#define __NR_Linux_syscalls 311 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ #define __NR_N32_Linux 6000 -#define __NR_N32_Linux_syscalls 310 +#define __NR_N32_Linux_syscalls 311 #ifdef __KERNEL__ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index c6136cb4cd40..d6c2a7476bac 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -34,28 +34,11 @@ obj-$(CONFIG_MODULES) += mips_ksyms.o module.o obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o -obj-$(CONFIG_CPU_LOONGSON2) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o -obj-$(CONFIG_CPU_R4300) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R4X00) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R5500) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R8000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o -obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o -obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_XLP) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP_UP) += smp-up.o diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 51095dd9599d..75323925e537 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -15,6 +15,7 @@ #include <asm/smtc_ipi.h> #include <asm/time.h> #include <asm/cevt-r4k.h> +#include <asm/gic.h> /* * The SMTC Kernel for the 34K, 1004K, et. al. replaces several @@ -98,6 +99,10 @@ void mips_event_handler(struct clock_event_device *dev) */ static int c0_compare_int_pending(void) { +#ifdef CONFIG_IRQ_GIC + if (cpu_has_veic) + return gic_get_timer_pending(); +#endif return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP); } diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 1b51046191e8..bc58bd10a607 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -421,8 +421,12 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) config3 = read_c0_config3(); - if (config3 & MIPS_CONF3_SM) + if (config3 & MIPS_CONF3_SM) { c->ases |= MIPS_ASE_SMARTMIPS; + c->options |= MIPS_CPU_RIXI; + } + if (config3 & MIPS_CONF3_RXI) + c->options |= MIPS_CPU_RIXI; if (config3 & MIPS_CONF3_DSP) c->ases |= MIPS_ASE_DSP; if (config3 & MIPS_CONF3_VINT) @@ -857,6 +861,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_1004K; __cpu_name[cpu] = "MIPS 1004Kc"; break; + case PRID_IMP_1074K: + c->cputype = CPU_74K; + __cpu_name[cpu] = "MIPS 1074Kc"; + break; } spram_config(); diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S index 37acfa036d44..a6c133212003 100644 --- a/arch/mips/kernel/entry.S +++ b/arch/mips/kernel/entry.S @@ -77,7 +77,7 @@ FEXPORT(syscall_exit) and t0, a2, t0 bnez t0, syscall_exit_work -FEXPORT(restore_all) # restore full frame +restore_all: # restore full frame #ifdef CONFIG_MIPS_MT_SMTC #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP /* Re-arm any temporarily masked interrupts not explicitly "acked" */ @@ -117,7 +117,7 @@ FEXPORT(restore_all) # restore full frame RESTORE_TEMP RESTORE_AT RESTORE_STATIC -FEXPORT(restore_partial) # restore partial frame +restore_partial: # restore partial frame #ifdef CONFIG_TRACE_IRQFLAGS SAVE_STATIC SAVE_AT @@ -164,9 +164,18 @@ work_notifysig: # deal with pending signals and jal do_notify_resume # a2 already loaded j resume_userspace -FEXPORT(syscall_exit_work_partial) +FEXPORT(syscall_exit_partial) + local_irq_disable # make sure need_resched doesn't + # change between and return + LONG_L a2, TI_FLAGS($28) # current->work + li t0, _TIF_ALLWORK_MASK + and t0, a2 + beqz t0, restore_partial SAVE_STATIC syscall_exit_work: + LONG_L t0, PT_STATUS(sp) # returning to kernel mode? + andi t0, t0, KU_USER + beqz t0, resume_kernel li t0, _TIF_WORK_SYSCALL_EXIT and t0, a2 # a2 is preloaded with TI_FLAGS beqz t0, work_pending # trace bit set? diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index 0c527f652196..485e6a961b31 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c @@ -1,5 +1,11 @@ -#undef DEBUG - +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ #include <linux/bitmap.h> #include <linux/init.h> #include <linux/smp.h> @@ -7,33 +13,80 @@ #include <asm/io.h> #include <asm/gic.h> +#include <asm/setup.h> +#include <asm/traps.h> #include <asm/gcmpregs.h> #include <linux/hardirq.h> #include <asm-generic/bitops/find.h> +unsigned long _gic_base; +unsigned int gic_irq_base; +unsigned int gic_irq_flags[GIC_NUM_INTRS]; -static unsigned long _gic_base; -static unsigned int _irqbase; -static unsigned int gic_irq_flags[GIC_NUM_INTRS]; -#define GIC_IRQ_FLAG_EDGE 0x0001 +/* The index into this array is the vector # of the interrupt. */ +struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS]; -struct gic_pcpu_mask pcpu_masks[NR_CPUS]; +static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; static struct gic_pending_regs pending_regs[NR_CPUS]; static struct gic_intrmask_regs intrmask_regs[NR_CPUS]; +unsigned int gic_get_timer_pending(void) +{ + unsigned int vpe_pending; + + GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0); + GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending); + return (vpe_pending & GIC_VPE_PEND_TIMER_MSK); +} + +void gic_bind_eic_interrupt(int irq, int set) +{ + /* Convert irq vector # to hw int # */ + irq -= GIC_PIN_TO_VEC_OFFSET; + + /* Set irq to use shadow set */ + GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set); +} + void gic_send_ipi(unsigned int intr) { - pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__, - read_c0_status()); GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr); } -/* This is Malta specific and needs to be exported */ +static void gic_eic_irq_dispatch(void) +{ + unsigned int cause = read_c0_cause(); + int irq; + + irq = (cause & ST0_IM) >> STATUSB_IP2; + if (irq == 0) + irq = -1; + + if (irq >= 0) + do_IRQ(gic_irq_base + irq); + else + spurious_interrupt(); +} + static void __init vpe_local_setup(unsigned int numvpes) { - int i; - unsigned long timer_interrupt = 5, perf_interrupt = 5; + unsigned long timer_intr = GIC_INT_TMR; + unsigned long perf_intr = GIC_INT_PERFCTR; unsigned int vpe_ctl; + int i; + + if (cpu_has_veic) { + /* + * GIC timer interrupt -> CPU HW Int X (vector X+2) -> + * map to pin X+2-1 (since GIC adds 1) + */ + timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET); + /* + * GIC perfcnt interrupt -> CPU HW Int X (vector X+2) -> + * map to pin X+2-1 (since GIC adds 1) + */ + perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET); + } /* * Setup the default performance counter timer interrupts @@ -46,11 +99,20 @@ static void __init vpe_local_setup(unsigned int numvpes) GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl); if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK) GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), - GIC_MAP_TO_PIN_MSK | timer_interrupt); + GIC_MAP_TO_PIN_MSK | timer_intr); + if (cpu_has_veic) { + set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET, + gic_eic_irq_dispatch); + gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK; + } if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK) GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), - GIC_MAP_TO_PIN_MSK | perf_interrupt); + GIC_MAP_TO_PIN_MSK | perf_intr); + if (cpu_has_veic) { + set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch); + gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK; + } } } @@ -80,51 +142,30 @@ unsigned int gic_get_int(void) bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS); bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS); - i = find_first_bit(pending, GIC_NUM_INTRS); - - pr_debug("CPU%d: %s pend=%d\n", smp_processor_id(), __func__, i); - - return i; -} - -static void gic_irq_ack(struct irq_data *d) -{ - unsigned int irq = d->irq - _irqbase; - - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); - GIC_CLR_INTR_MASK(irq); - - if (gic_irq_flags[irq] & GIC_IRQ_FLAG_EDGE) - GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); + return find_first_bit(pending, GIC_NUM_INTRS); } static void gic_mask_irq(struct irq_data *d) { - unsigned int irq = d->irq - _irqbase; - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); - GIC_CLR_INTR_MASK(irq); + GIC_CLR_INTR_MASK(d->irq - gic_irq_base); } static void gic_unmask_irq(struct irq_data *d) { - unsigned int irq = d->irq - _irqbase; - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); - GIC_SET_INTR_MASK(irq); + GIC_SET_INTR_MASK(d->irq - gic_irq_base); } #ifdef CONFIG_SMP - static DEFINE_SPINLOCK(gic_lock); static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool force) { - unsigned int irq = d->irq - _irqbase; + unsigned int irq = (d->irq - gic_irq_base); cpumask_t tmp = CPU_MASK_NONE; unsigned long flags; int i; - pr_debug("%s(%d) called\n", __func__, irq); cpumask_and(&tmp, cpumask, cpu_online_mask); if (cpus_empty(tmp)) return -1; @@ -154,7 +195,7 @@ static struct irq_chip gic_irq_controller = { .irq_mask = gic_mask_irq, .irq_mask_ack = gic_mask_irq, .irq_unmask = gic_unmask_irq, - .irq_eoi = gic_unmask_irq, + .irq_eoi = gic_finish_irq, #ifdef CONFIG_SMP .irq_set_affinity = gic_set_affinity, #endif @@ -164,6 +205,8 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, unsigned int pin, unsigned int polarity, unsigned int trigtype, unsigned int flags) { + struct gic_shared_intr_map *map_ptr; + /* Setup Intr to Pin mapping */ if (pin & GIC_MAP_TO_NMI_MSK) { GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin); @@ -178,6 +221,14 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, GIC_MAP_TO_PIN_MSK | pin); /* Setup Intr to CPU mapping */ GIC_SH_MAP_TO_VPE_SMASK(intr, cpu); + if (cpu_has_veic) { + set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET, + gic_eic_irq_dispatch); + map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET]; + if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR) + BUG(); + map_ptr->intr_list[map_ptr->num_shared_intr++] = intr; + } } /* Setup Intr Polarity */ @@ -191,26 +242,39 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, /* Initialise per-cpu Interrupt software masks */ if (flags & GIC_FLAG_IPI) set_bit(intr, pcpu_masks[cpu].pcpu_mask); - if (flags & GIC_FLAG_TRANSPARENT) + if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0)) GIC_SET_INTR_MASK(intr); if (trigtype == GIC_TRIG_EDGE) - gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE; + gic_irq_flags[intr] |= GIC_TRIG_EDGE; } static void __init gic_basic_init(int numintrs, int numvpes, struct gic_intr_map *intrmap, int mapsize) { unsigned int i, cpu; + unsigned int pin_offset = 0; + + board_bind_eic_interrupt = &gic_bind_eic_interrupt; /* Setup defaults */ for (i = 0; i < numintrs; i++) { GIC_SET_POLARITY(i, GIC_POL_POS); GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL); GIC_CLR_INTR_MASK(i); - if (i < GIC_NUM_INTRS) + if (i < GIC_NUM_INTRS) { gic_irq_flags[i] = 0; + gic_shared_intr_map[i].num_shared_intr = 0; + gic_shared_intr_map[i].local_intr_mask = 0; + } } + /* + * In EIC mode, the HW_INT# is offset by (2-1). Need to subtract + * one because the GIC will add one (since 0=no intr). + */ + if (cpu_has_veic) + pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET); + /* Setup specifics */ for (i = 0; i < mapsize; i++) { cpu = intrmap[i].cpunum; @@ -220,16 +284,13 @@ static void __init gic_basic_init(int numintrs, int numvpes, continue; gic_setup_intr(i, intrmap[i].cpunum, - intrmap[i].pin, + intrmap[i].pin + pin_offset, intrmap[i].polarity, intrmap[i].trigtype, intrmap[i].flags); } vpe_local_setup(numvpes); - - for (i = _irqbase; i < (_irqbase + numintrs); i++) - irq_set_chip(i, &gic_irq_controller); } void __init gic_init(unsigned long gic_base_addr, @@ -242,7 +303,7 @@ void __init gic_init(unsigned long gic_base_addr, _gic_base = (unsigned long) ioremap_nocache(gic_base_addr, gic_addrspace_size); - _irqbase = irqbase; + gic_irq_base = irqbase; GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> @@ -251,8 +312,9 @@ void __init gic_init(unsigned long gic_base_addr, numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >> GIC_SH_CONFIG_NUMVPES_SHF; - - pr_debug("%s called\n", __func__); + numvpes = numvpes + 1; gic_basic_init(numintrs, numvpes, intr_map, intr_map_size); + + gic_platform_init(numintrs, &gic_irq_controller); } diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index a632bc144efa..374f66e05f3d 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -69,18 +69,7 @@ stack_done: 1: sw v0, PT_R2(sp) # result o32_syscall_exit: - local_irq_disable # make sure need_resched and - # signals dont change between - # sampling and return - lw a2, TI_FLAGS($28) # current->work - li t0, _TIF_ALLWORK_MASK - and t0, a2 - bnez t0, o32_syscall_exit_work - - j restore_partial - -o32_syscall_exit_work: - j syscall_exit_work_partial + j syscall_exit_partial /* ------------------------------------------------------------------------ */ @@ -593,6 +582,7 @@ einval: li v0, -ENOSYS sys sys_setns 2 sys sys_process_vm_readv 6 /* 4345 */ sys sys_process_vm_writev 6 + sys sys_kcmp 5 .endm /* We pre-compute the number of _instruction_ bytes needed to diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 3b5a5e9ae49c..169de6a6d916 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -72,18 +72,7 @@ NESTED(handle_sys64, PT_SIZE, sp) 1: sd v0, PT_R2(sp) # result n64_syscall_exit: - local_irq_disable # make sure need_resched and - # signals dont change between - # sampling and return - LONG_L a2, TI_FLAGS($28) # current->work - li t0, _TIF_ALLWORK_MASK - and t0, a2, t0 - bnez t0, n64_syscall_exit_work - - j restore_partial - -n64_syscall_exit_work: - j syscall_exit_work_partial + j syscall_exit_partial /* ------------------------------------------------------------------------ */ @@ -432,4 +421,5 @@ sys_call_table: PTR sys_setns PTR sys_process_vm_readv PTR sys_process_vm_writev /* 5305 */ + PTR sys_kcmp .size sys_call_table,.-sys_call_table diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index 6be6f7020923..f6ba8381ee01 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -70,18 +70,7 @@ NESTED(handle_sysn32, PT_SIZE, sp) sd t1, PT_R0(sp) # save it for syscall restarting 1: sd v0, PT_R2(sp) # result - local_irq_disable # make sure need_resched and - # signals dont change between - # sampling and return - LONG_L a2, TI_FLAGS($28) # current->work - li t0, _TIF_ALLWORK_MASK - and t0, a2, t0 - bnez t0, n32_syscall_exit_work - - j restore_partial - -n32_syscall_exit_work: - j syscall_exit_work_partial + j syscall_exit_partial /* ------------------------------------------------------------------------ */ @@ -432,4 +421,5 @@ EXPORT(sysn32_call_table) PTR sys_setns PTR compat_sys_process_vm_readv PTR compat_sys_process_vm_writev /* 6310 */ + PTR sys_kcmp .size sysn32_call_table,.-sysn32_call_table diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 54228553691d..53c2d7245764 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -99,18 +99,7 @@ NESTED(handle_sys, PT_SIZE, sp) 1: sd v0, PT_R2(sp) # result o32_syscall_exit: - local_irq_disable # make need_resched and - # signals dont change between - # sampling and return - LONG_L a2, TI_FLAGS($28) - li t0, _TIF_ALLWORK_MASK - and t0, a2, t0 - bnez t0, o32_syscall_exit_work - - j restore_partial - -o32_syscall_exit_work: - j syscall_exit_work_partial + j syscall_exit_partial /* ------------------------------------------------------------------------ */ @@ -550,4 +539,5 @@ sys_call_table: PTR sys_setns PTR compat_sys_process_vm_readv /* 4345 */ PTR compat_sys_process_vm_writev + PTR sys_kcmp .size sys_call_table,.-sys_call_table diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index f2c09cfc60ac..0e1a5b8ae817 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -560,14 +560,6 @@ static void do_signal(struct pt_regs *regs) siginfo_t info; int signr; - /* - * We want the common case to go fast, which is why we may in certain - * cases get here from kernel mode. Just return without doing anything - * if so. - */ - if (!user_mode(regs)) - return; - signr = get_signal_to_deliver(&info, &ka, regs, NULL); if (signr > 0) { /* Whee! Actually deliver the signal. */ diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index ff17868734cf..2defa2bbdaa7 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -150,6 +150,7 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action) static void __cpuinit vsmp_init_secondary(void) { +#ifdef CONFIG_IRQ_GIC extern int gic_present; /* This is Malta specific: IPI,performance and timer interrupts */ @@ -157,6 +158,7 @@ static void __cpuinit vsmp_init_secondary(void) change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 | STATUSF_IP7); else +#endif change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7); } diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig index 20bdf40b3efa..d84f361f1e45 100644 --- a/arch/mips/lantiq/Kconfig +++ b/arch/mips/lantiq/Kconfig @@ -2,6 +2,7 @@ if LANTIQ config SOC_TYPE_XWAY bool + select PINCTRL_XWAY default n choice @@ -19,6 +20,7 @@ config SOC_XWAY config SOC_FALCON bool "FALCON" + select PINCTRL_FALCON endchoice diff --git a/arch/mips/lantiq/falcon/prom.c b/arch/mips/lantiq/falcon/prom.c index c1d278f05a3a..aa9497947859 100644 --- a/arch/mips/lantiq/falcon/prom.c +++ b/arch/mips/lantiq/falcon/prom.c @@ -8,6 +8,8 @@ */ #include <linux/kernel.h> +#include <asm/cacheflush.h> +#include <asm/traps.h> #include <asm/io.h> #include <lantiq_soc.h> @@ -84,4 +86,7 @@ void __init ltq_soc_detect(struct ltq_soc_info *i) unreachable(); break; } + + board_nmi_handler_setup = ltq_soc_nmi_setup; + board_ejtag_handler_setup = ltq_soc_ejtag_setup; } diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c index ba0123d13d40..2d4ced332b37 100644 --- a/arch/mips/lantiq/falcon/sysctrl.c +++ b/arch/mips/lantiq/falcon/sysctrl.c @@ -171,6 +171,7 @@ static inline void clkdev_add_sys(const char *dev, unsigned int module, clk->cl.con_id = NULL; clk->cl.clk = clk; clk->module = module; + clk->bits = bits; clk->activate = sysctl_activate; clk->deactivate = sysctl_deactivate; clk->enable = sysctl_clken; diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 57c1a4e51408..f36acd1b3808 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -55,8 +55,8 @@ */ #define LTQ_ICU_EBU_IRQ 22 -#define ltq_icu_w32(x, y) ltq_w32((x), ltq_icu_membase + (y)) -#define ltq_icu_r32(x) ltq_r32(ltq_icu_membase + (x)) +#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y)) +#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x)) #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) @@ -82,17 +82,18 @@ static unsigned short ltq_eiu_irq[MAX_EIU] = { }; static int exin_avail; -static void __iomem *ltq_icu_membase; +static void __iomem *ltq_icu_membase[MAX_IM]; static void __iomem *ltq_eiu_membase; +static struct irq_domain *ltq_domain; void ltq_disable_irq(struct irq_data *d) { u32 ier = LTQ_ICU_IM0_IER; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; + int im = offset / INT_NUM_IM_OFFSET; - ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET); offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier); + ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); } void ltq_mask_and_ack_irq(struct irq_data *d) @@ -100,32 +101,31 @@ void ltq_mask_and_ack_irq(struct irq_data *d) u32 ier = LTQ_ICU_IM0_IER; u32 isr = LTQ_ICU_IM0_ISR; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; + int im = offset / INT_NUM_IM_OFFSET; - ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET); - isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET); offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier); - ltq_icu_w32(BIT(offset), isr); + ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); + ltq_icu_w32(im, BIT(offset), isr); } static void ltq_ack_irq(struct irq_data *d) { u32 isr = LTQ_ICU_IM0_ISR; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; + int im = offset / INT_NUM_IM_OFFSET; - isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET); offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(BIT(offset), isr); + ltq_icu_w32(im, BIT(offset), isr); } void ltq_enable_irq(struct irq_data *d) { u32 ier = LTQ_ICU_IM0_IER; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; + int im = offset / INT_NUM_IM_OFFSET; - ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET); offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(ltq_icu_r32(ier) | BIT(offset), ier); + ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier); } static unsigned int ltq_startup_eiu_irq(struct irq_data *d) @@ -192,7 +192,7 @@ static void ltq_hw_irqdispatch(int module) { u32 irq; - irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET)); + irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR); if (irq == 0) return; @@ -220,10 +220,14 @@ DEFINE_HWx_IRQDISPATCH(2) DEFINE_HWx_IRQDISPATCH(3) DEFINE_HWx_IRQDISPATCH(4) +#if MIPS_CPU_TIMER_IRQ == 7 static void ltq_hw5_irqdispatch(void) { do_IRQ(MIPS_CPU_TIMER_IRQ); } +#else +DEFINE_HWx_IRQDISPATCH(5) +#endif #ifdef CONFIG_MIPS_MT_SMP void __init arch_init_ipiirq(int irq, struct irqaction *action) @@ -271,11 +275,11 @@ asmlinkage void plat_irq_dispatch(void) unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; unsigned int i; - if (pending & CAUSEF_IP7) { + if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) { do_IRQ(MIPS_CPU_TIMER_IRQ); goto out; } else { - for (i = 0; i < 5; i++) { + for (i = 0; i < MAX_IM; i++) { if (pending & (CAUSEF_IP2 << i)) { ltq_hw_irqdispatch(i); goto out; @@ -293,6 +297,9 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) struct irq_chip *chip = <q_irq_type; int i; + if (hw < MIPS_CPU_IRQ_CASCADE) + return 0; + for (i = 0; i < exin_avail; i++) if (hw == ltq_eiu_irq[i]) chip = <q_eiu_type; @@ -318,19 +325,23 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) struct resource res; int i; - if (of_address_to_resource(node, 0, &res)) - panic("Failed to get icu memory range"); + for (i = 0; i < MAX_IM; i++) { + if (of_address_to_resource(node, i, &res)) + panic("Failed to get icu memory range"); - if (request_mem_region(res.start, resource_size(&res), res.name) < 0) - pr_err("Failed to request icu memory"); + if (request_mem_region(res.start, resource_size(&res), + res.name) < 0) + pr_err("Failed to request icu memory"); - ltq_icu_membase = ioremap_nocache(res.start, resource_size(&res)); - if (!ltq_icu_membase) - panic("Failed to remap icu memory"); + ltq_icu_membase[i] = ioremap_nocache(res.start, + resource_size(&res)); + if (!ltq_icu_membase[i]) + panic("Failed to remap icu memory"); + } /* the external interrupts are optional and xway only */ eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu"); - if (eiu_node && of_address_to_resource(eiu_node, 0, &res)) { + if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) { /* find out how many external irq sources we have */ const __be32 *count = of_get_property(node, "lantiq,count", NULL); @@ -351,17 +362,17 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) } /* turn off all irqs by default */ - for (i = 0; i < 5; i++) { + for (i = 0; i < MAX_IM; i++) { /* make sure all irqs are turned off by default */ - ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET)); + ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER); /* clear all possibly pending interrupts */ - ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); + ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR); } mips_cpu_irq_init(); - for (i = 2; i <= 6; i++) - setup_irq(i, &cascade); + for (i = 0; i < MAX_IM; i++) + setup_irq(i + 2, &cascade); if (cpu_has_vint) { pr_info("Setting up vectored interrupts\n"); @@ -373,7 +384,8 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) set_vi_handler(7, ltq_hw5_irqdispatch); } - irq_domain_add_linear(node, 6 * INT_NUM_IM_OFFSET, + ltq_domain = irq_domain_add_linear(node, + (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE, &irq_domain_ops, 0); #if defined(CONFIG_MIPS_MT_SMP) @@ -397,12 +409,20 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) /* tell oprofile which irq to use */ cp0_perfcount_irq = LTQ_PERF_IRQ; + + /* + * if the timer irq is not one of the mips irqs we need to + * create a mapping + */ + if (MIPS_CPU_TIMER_IRQ != 7) + irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ); + return 0; } unsigned int __cpuinit get_c0_compare_int(void) { - return CP0_LEGACY_COMPARE_IRQ; + return MIPS_CPU_TIMER_IRQ; } static struct of_device_id __initdata of_irq_ids[] = { diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index dc3194f6ee42..70a58c747bd0 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1 +1 @@ -obj-y := prom.o sysctrl.o clk.o reset.o gpio.o dma.o +obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c deleted file mode 100644 index 2ab39e93d9be..000000000000 --- a/arch/mips/lantiq/xway/gpio.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin <blogic@openwrt.org> - */ - -#include <linux/slab.h> -#include <linux/export.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/ioport.h> -#include <linux/io.h> - -#include <lantiq_soc.h> - -#define LTQ_GPIO_OUT 0x00 -#define LTQ_GPIO_IN 0x04 -#define LTQ_GPIO_DIR 0x08 -#define LTQ_GPIO_ALTSEL0 0x0C -#define LTQ_GPIO_ALTSEL1 0x10 -#define LTQ_GPIO_OD 0x14 - -#define PINS_PER_PORT 16 -#define MAX_PORTS 3 - -#define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p))) -#define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r) -#define ltq_gpio_clearbit(m, r, p) ltq_w32_mask((1 << p), 0, m + r) - -struct ltq_gpio { - void __iomem *membase; - struct gpio_chip chip; -}; - -static struct ltq_gpio ltq_gpio_port[MAX_PORTS]; - -int ltq_gpio_request(unsigned int pin, unsigned int alt0, - unsigned int alt1, unsigned int dir, const char *name) -{ - int id = 0; - - if (pin >= (MAX_PORTS * PINS_PER_PORT)) - return -EINVAL; - if (gpio_request(pin, name)) { - pr_err("failed to setup lantiq gpio: %s\n", name); - return -EBUSY; - } - if (dir) - gpio_direction_output(pin, 1); - else - gpio_direction_input(pin); - while (pin >= PINS_PER_PORT) { - pin -= PINS_PER_PORT; - id++; - } - if (alt0) - ltq_gpio_setbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL0, pin); - else - ltq_gpio_clearbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL0, pin); - if (alt1) - ltq_gpio_setbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL1, pin); - else - ltq_gpio_clearbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL1, pin); - return 0; -} -EXPORT_SYMBOL(ltq_gpio_request); - -static void ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) -{ - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - if (value) - ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset); - else - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset); -} - -static int ltq_gpio_get(struct gpio_chip *chip, unsigned int offset) -{ - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - return ltq_gpio_getbit(ltq_gpio->membase, LTQ_GPIO_IN, offset); -} - -static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) -{ - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); - - return 0; -} - -static int ltq_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); - ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); - ltq_gpio_set(chip, offset, value); - - return 0; -} - -static int ltq_gpio_req(struct gpio_chip *chip, unsigned offset) -{ - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset); - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset); - return 0; -} - -static int ltq_gpio_probe(struct platform_device *pdev) -{ - struct resource *res; - - if (pdev->id >= MAX_PORTS) { - dev_err(&pdev->dev, "invalid gpio port %d\n", - pdev->id); - return -EINVAL; - } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "failed to get memory for gpio port %d\n", - pdev->id); - return -ENOENT; - } - res = devm_request_mem_region(&pdev->dev, res->start, - resource_size(res), dev_name(&pdev->dev)); - if (!res) { - dev_err(&pdev->dev, - "failed to request memory for gpio port %d\n", - pdev->id); - return -EBUSY; - } - ltq_gpio_port[pdev->id].membase = devm_ioremap_nocache(&pdev->dev, - res->start, resource_size(res)); - if (!ltq_gpio_port[pdev->id].membase) { - dev_err(&pdev->dev, "failed to remap memory for gpio port %d\n", - pdev->id); - return -ENOMEM; - } - ltq_gpio_port[pdev->id].chip.label = "ltq_gpio"; - ltq_gpio_port[pdev->id].chip.direction_input = ltq_gpio_direction_input; - ltq_gpio_port[pdev->id].chip.direction_output = - ltq_gpio_direction_output; - ltq_gpio_port[pdev->id].chip.get = ltq_gpio_get; - ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set; - ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req; - ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id; - ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT; - platform_set_drvdata(pdev, <q_gpio_port[pdev->id]); - return gpiochip_add(<q_gpio_port[pdev->id].chip); -} - -static struct platform_driver -ltq_gpio_driver = { - .probe = ltq_gpio_probe, - .driver = { - .name = "ltq_gpio", - .owner = THIS_MODULE, - }, -}; - -int __init ltq_gpio_init(void) -{ - int ret = platform_driver_register(<q_gpio_driver); - - if (ret) - pr_info("ltq_gpio : Error registering platform driver!"); - return ret; -} - -postcore_initcall(ltq_gpio_init); diff --git a/arch/mips/lantiq/xway/gptu.c b/arch/mips/lantiq/xway/gptu.c new file mode 100644 index 000000000000..cbb56fc022bc --- /dev/null +++ b/arch/mips/lantiq/xway/gptu.c @@ -0,0 +1,214 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin <blogic@openwrt.org> + * Copyright (C) 2012 Lantiq GmbH + */ + +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <linux/of_irq.h> + +#include <lantiq_soc.h> +#include "../clk.h" + +/* the magic ID byte of the core */ +#define GPTU_MAGIC 0x59 +/* clock control register */ +#define GPTU_CLC 0x00 +/* id register */ +#define GPTU_ID 0x08 +/* interrupt node enable */ +#define GPTU_IRNEN 0xf4 +/* interrupt control register */ +#define GPTU_IRCR 0xf8 +/* interrupt capture register */ +#define GPTU_IRNCR 0xfc +/* there are 3 identical blocks of 2 timers. calculate register offsets */ +#define GPTU_SHIFT(x) (x % 2 ? 4 : 0) +#define GPTU_BASE(x) (((x >> 1) * 0x20) + 0x10) +/* timer control register */ +#define GPTU_CON(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00) +/* timer auto reload register */ +#define GPTU_RUN(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08) +/* timer manual reload register */ +#define GPTU_RLD(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10) +/* timer count register */ +#define GPTU_CNT(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18) + +/* GPTU_CON(x) */ +#define CON_CNT BIT(2) +#define CON_EDGE_ANY (BIT(7) | BIT(6)) +#define CON_SYNC BIT(8) +#define CON_CLK_INT BIT(10) + +/* GPTU_RUN(x) */ +#define RUN_SEN BIT(0) +#define RUN_RL BIT(2) + +/* set clock to runmode */ +#define CLC_RMC BIT(8) +/* bring core out of suspend */ +#define CLC_SUSPEND BIT(4) +/* the disable bit */ +#define CLC_DISABLE BIT(0) + +#define gptu_w32(x, y) ltq_w32((x), gptu_membase + (y)) +#define gptu_r32(x) ltq_r32(gptu_membase + (x)) + +enum gptu_timer { + TIMER1A = 0, + TIMER1B, + TIMER2A, + TIMER2B, + TIMER3A, + TIMER3B +}; + +static void __iomem *gptu_membase; +static struct resource irqres[6]; + +static irqreturn_t timer_irq_handler(int irq, void *priv) +{ + int timer = irq - irqres[0].start; + gptu_w32(1 << timer, GPTU_IRNCR); + return IRQ_HANDLED; +} + +static void gptu_hwinit(void) +{ + gptu_w32(0x00, GPTU_IRNEN); + gptu_w32(0xff, GPTU_IRNCR); + gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC); +} + +static void gptu_hwexit(void) +{ + gptu_w32(0x00, GPTU_IRNEN); + gptu_w32(0xff, GPTU_IRNCR); + gptu_w32(CLC_DISABLE, GPTU_CLC); +} + +static int gptu_enable(struct clk *clk) +{ + int ret = request_irq(irqres[clk->bits].start, timer_irq_handler, + IRQF_TIMER, "gtpu", NULL); + if (ret) { + pr_err("gptu: failed to request irq\n"); + return ret; + } + + gptu_w32(CON_CNT | CON_EDGE_ANY | CON_SYNC | CON_CLK_INT, + GPTU_CON(clk->bits)); + gptu_w32(1, GPTU_RLD(clk->bits)); + gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN); + gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits)); + return 0; +} + +static void gptu_disable(struct clk *clk) +{ + gptu_w32(0, GPTU_RUN(clk->bits)); + gptu_w32(0, GPTU_CON(clk->bits)); + gptu_w32(0, GPTU_RLD(clk->bits)); + gptu_w32(gptu_r32(GPTU_IRNEN) & ~BIT(clk->bits), GPTU_IRNEN); + free_irq(irqres[clk->bits].start, NULL); +} + +static inline void clkdev_add_gptu(struct device *dev, const char *con, + unsigned int timer) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = dev_name(dev); + clk->cl.con_id = con; + clk->cl.clk = clk; + clk->enable = gptu_enable; + clk->disable = gptu_disable; + clk->bits = timer; + clkdev_add(&clk->cl); +} + +static int __devinit gptu_probe(struct platform_device *pdev) +{ + struct clk *clk; + struct resource *res; + + if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 6) != 6) { + dev_err(&pdev->dev, "Failed to get IRQ list\n"); + return -EINVAL; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Failed to get resource\n"); + return -ENOMEM; + } + + /* remap gptu register range */ + gptu_membase = devm_request_and_ioremap(&pdev->dev, res); + if (!gptu_membase) { + dev_err(&pdev->dev, "Failed to remap resource\n"); + return -ENOMEM; + } + + /* enable our clock */ + clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Failed to get clock\n"); + return -ENOENT; + } + clk_enable(clk); + + /* power up the core */ + gptu_hwinit(); + + /* the gptu has a ID register */ + if (((gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) { + dev_err(&pdev->dev, "Failed to find magic\n"); + gptu_hwexit(); + return -ENAVAIL; + } + + /* register the clocks */ + clkdev_add_gptu(&pdev->dev, "timer1a", TIMER1A); + clkdev_add_gptu(&pdev->dev, "timer1b", TIMER1B); + clkdev_add_gptu(&pdev->dev, "timer2a", TIMER2A); + clkdev_add_gptu(&pdev->dev, "timer2b", TIMER2B); + clkdev_add_gptu(&pdev->dev, "timer3a", TIMER3A); + clkdev_add_gptu(&pdev->dev, "timer3b", TIMER3B); + + dev_info(&pdev->dev, "gptu: 6 timers loaded\n"); + + return 0; +} + +static const struct of_device_id gptu_match[] = { + { .compatible = "lantiq,gptu-xway" }, + {}, +}; +MODULE_DEVICE_TABLE(of, dma_match); + +static struct platform_driver dma_driver = { + .probe = gptu_probe, + .driver = { + .name = "gptu-xway", + .owner = THIS_MODULE, + .of_match_table = gptu_match, + }, +}; + +int __init gptu_init(void) +{ + int ret = platform_driver_register(&dma_driver); + + if (ret) + pr_info("gptu: Error registering platform driver\n"); + return ret; +} + +arch_initcall(gptu_init); diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index befbb760ab76..2917b56b6b25 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -145,7 +145,8 @@ static int pci_enable(struct clk *clk) { unsigned int val = ltq_cgu_r32(ifccr); /* set bus clock speed */ - if (of_machine_is_compatible("lantiq,ar9")) { + if (of_machine_is_compatible("lantiq,ar9") || + of_machine_is_compatible("lantiq,vr9")) { val &= ~0x1f00000; if (clk->rate == CLOCK_33M) val |= 0xe00000; @@ -187,10 +188,12 @@ static int clkout_enable(struct clk *clk) for (i = 0; i < 4; i++) { if (clk->rates[i] == clk->rate) { int shift = 14 - (2 * clk->module); + int enable = 7 - clk->module; unsigned int val = ltq_cgu_r32(ifccr); val &= ~(3 << shift); val |= i << shift; + val |= enable; ltq_cgu_w32(val, ifccr); return 0; } diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 399a50a541d4..c4a82e841c73 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -8,28 +8,9 @@ lib-y += csum_partial.o delay.o memcpy.o memset.o \ obj-y += iomap.o obj-$(CONFIG_PCI) += iomap-pci.o -obj-$(CONFIG_CPU_LOONGSON2) += dump_tlb.o -obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o -obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o -obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o -obj-$(CONFIG_CPU_R10000) += dump_tlb.o +obj-$(CONFIG_CPU_GENERIC_DUMP_TLB) += dump_tlb.o obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o -obj-$(CONFIG_CPU_R4300) += dump_tlb.o -obj-$(CONFIG_CPU_R4X00) += dump_tlb.o -obj-$(CONFIG_CPU_R5000) += dump_tlb.o -obj-$(CONFIG_CPU_R5432) += dump_tlb.o -obj-$(CONFIG_CPU_R5500) += dump_tlb.o -obj-$(CONFIG_CPU_R6000) += -obj-$(CONFIG_CPU_R8000) += -obj-$(CONFIG_CPU_RM7000) += dump_tlb.o -obj-$(CONFIG_CPU_RM9000) += dump_tlb.o -obj-$(CONFIG_CPU_SB1) += dump_tlb.o obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o -obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o -obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o -obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o -obj-$(CONFIG_CPU_XLR) += dump_tlb.o -obj-$(CONFIG_CPU_XLP) += dump_tlb.o # libgcc-style stuff needed in the kernel obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o diff --git a/arch/mips/mipssim/Makefile b/arch/mips/mipssim/Makefile deleted file mode 100644 index 01410a3f1729..000000000000 --- a/arch/mips/mipssim/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. -# Copyright (C) 2007 MIPS Technologies, Inc. -# written by Ralf Baechle (ralf@linux-mips.org) -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# - -obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o - -obj-$(CONFIG_EARLY_PRINTK) += sim_console.o -obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o diff --git a/arch/mips/mipssim/Platform b/arch/mips/mipssim/Platform deleted file mode 100644 index 3df60b8a12ef..000000000000 --- a/arch/mips/mipssim/Platform +++ /dev/null @@ -1,6 +0,0 @@ -# -# MIPS SIM -# -platform-$(CONFIG_MIPS_SIM) += mipssim/ -cflags-$(CONFIG_MIPS_SIM) += -I$(srctree)/arch/mips/include/asm/mach-mipssim -load-$(CONFIG_MIPS_SIM) += 0x80100000 diff --git a/arch/mips/mipssim/sim_console.c b/arch/mips/mipssim/sim_console.c deleted file mode 100644 index a2f41672cd5d..000000000000 --- a/arch/mips/mipssim/sim_console.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2007 MIPS Technologies, Inc. - * written by Ralf Baechle - */ -#include <linux/init.h> -#include <linux/io.h> -#include <linux/serial_reg.h> - -static inline unsigned int serial_in(int offset) -{ - return inb(0x3f8 + offset); -} - -static inline void serial_out(int offset, int value) -{ - outb(value, 0x3f8 + offset); -} - -void __init prom_putchar(char c) -{ - while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) - ; - - serial_out(UART_TX, c); -} diff --git a/arch/mips/mipssim/sim_int.c b/arch/mips/mipssim/sim_int.c deleted file mode 100644 index 5c779be6f082..000000000000 --- a/arch/mips/mipssim/sim_int.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ -#include <linux/init.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/kernel_stat.h> -#include <asm/mips-boards/simint.h> -#include <asm/irq_cpu.h> - -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - return -clz(pending) + 31 - CAUSEB_IP; -#else - unsigned int a0 = 7; - unsigned int t0; - - t0 = s0 & 0xf000; - t0 = t0 < 1; - t0 = t0 << 2; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0xc000; - t0 = t0 < 1; - t0 = t0 << 1; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0x8000; - t0 = t0 < 1; - /* t0 = t0 << 2; */ - a0 = a0 - t0; - /* s0 = s0 << t0; */ - - return a0; -#endif -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - int irq; - - irq = irq_ffs(pending); - - if (irq > 0) - do_IRQ(MIPS_CPU_IRQ_BASE + irq); - else - spurious_interrupt(); -} - -void __init arch_init_irq(void) -{ - mips_cpu_irq_init(); -} diff --git a/arch/mips/mipssim/sim_mem.c b/arch/mips/mipssim/sim_mem.c deleted file mode 100644 index 953d836a7713..000000000000 --- a/arch/mips/mipssim/sim_mem.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/bootmem.h> -#include <linux/pfn.h> - -#include <asm/bootinfo.h> -#include <asm/page.h> -#include <asm/sections.h> - -#include <asm/mips-boards/prom.h> - -/*#define DEBUG*/ - -enum simmem_memtypes { - simmem_reserved = 0, - simmem_free, -}; -struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; - -#ifdef DEBUG -static char *mtypes[3] = { - "SIM reserved memory", - "SIM free memory", -}; -#endif - -struct prom_pmemblock * __init prom_getmdesc(void) -{ - unsigned int memsize; - - memsize = 0x02000000; - pr_info("Setting default memory size 0x%08x\n", memsize); - - memset(mdesc, 0, sizeof(mdesc)); - - mdesc[0].type = simmem_reserved; - mdesc[0].base = 0x00000000; - mdesc[0].size = 0x00001000; - - mdesc[1].type = simmem_free; - mdesc[1].base = 0x00001000; - mdesc[1].size = 0x000ff000; - - mdesc[2].type = simmem_reserved; - mdesc[2].base = 0x00100000; - mdesc[2].size = CPHYSADDR(PFN_ALIGN(&_end)) - mdesc[2].base; - - mdesc[3].type = simmem_free; - mdesc[3].base = CPHYSADDR(PFN_ALIGN(&_end)); - mdesc[3].size = memsize - mdesc[3].base; - - return &mdesc[0]; -} - -static int __init prom_memtype_classify(unsigned int type) -{ - switch (type) { - case simmem_free: - return BOOT_MEM_RAM; - case simmem_reserved: - default: - return BOOT_MEM_RESERVED; - } -} - -void __init prom_meminit(void) -{ - struct prom_pmemblock *p; - - p = prom_getmdesc(); - - while (p->size) { - long type; - unsigned long base, size; - - type = prom_memtype_classify(p->type); - base = p->base; - size = p->size; - - add_memory_region(base, size, type); - p++; - } -} - -void __init prom_free_prom_memory(void) -{ - int i; - unsigned long addr; - - for (i = 0; i < boot_mem_map.nr_map; i++) { - if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) - continue; - - addr = boot_mem_map.map[i].addr; - free_init_pages("prom memory", - addr, addr + boot_mem_map.map[i].size); - } -} diff --git a/arch/mips/mipssim/sim_platform.c b/arch/mips/mipssim/sim_platform.c deleted file mode 100644 index 53210a8c5dec..000000000000 --- a/arch/mips/mipssim/sim_platform.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 by Ralf Baechle (ralf@linux-mips.org) - */ -#include <linux/init.h> -#include <linux/if_ether.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> - -static char mipsnet_string[] = "mipsnet"; - -static struct platform_device eth1_device = { - .name = mipsnet_string, - .id = 0, -}; - -/* - * Create a platform device for the GPI port that receives the - * image data from the embedded camera. - */ -static int __init mipsnet_devinit(void) -{ - int err; - - err = platform_device_register(ð1_device); - if (err) - printk(KERN_ERR "%s: registration failed\n", mipsnet_string); - - return err; -} - -device_initcall(mipsnet_devinit); diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c deleted file mode 100644 index 256e0cdaa499..000000000000 --- a/arch/mips/mipssim/sim_setup.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ - -#include <linux/init.h> -#include <linux/string.h> -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/ioport.h> -#include <linux/tty.h> -#include <linux/serial.h> -#include <linux/serial_core.h> -#include <linux/serial_8250.h> - -#include <asm/cpu.h> -#include <asm/bootinfo.h> -#include <asm/mips-boards/generic.h> -#include <asm/mips-boards/prom.h> -#include <asm/time.h> -#include <asm/mips-boards/sim.h> -#include <asm/mips-boards/simint.h> -#include <asm/smp-ops.h> - - -static void __init serial_init(void); -unsigned int _isbonito; - -const char *get_system_type(void) -{ - return "MIPSsim"; -} - -void __init plat_mem_setup(void) -{ - set_io_port_base(0xbfd00000); - - serial_init(); -} - -extern struct plat_smp_ops ssmtc_smp_ops; - -void __init prom_init(void) -{ - set_io_port_base(0xbfd00000); - - prom_meminit(); - - if (cpu_has_mipsmt) { - if (!register_vsmp_smp_ops()) - return; - -#ifdef CONFIG_MIPS_MT_SMTC - register_smp_ops(&ssmtc_smp_ops); - return; -#endif - } - - register_up_smp_ops(); -} - -static void __init serial_init(void) -{ -#ifdef CONFIG_SERIAL_8250 - struct uart_port s; - - memset(&s, 0, sizeof(s)); - - s.iobase = 0x3f8; - - /* hardware int 4 - the serial int, is CPU int 6 - but poll for now */ - s.irq = 0; - s.uartclk = 1843200; - s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; - s.iotype = UPIO_PORT; - s.regshift = 0; - s.timeout = 4; - - if (early_serial_setup(&s) != 0) { - printk(KERN_ERR "Serial setup failed!\n"); - } - -#endif -} diff --git a/arch/mips/mipssim/sim_smtc.c b/arch/mips/mipssim/sim_smtc.c deleted file mode 100644 index 3c104abd8aa5..000000000000 --- a/arch/mips/mipssim/sim_smtc.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ -/* - * Simulator Platform-specific hooks for SMTC operation - */ -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/cpumask.h> -#include <linux/interrupt.h> -#include <linux/smp.h> - -#include <linux/atomic.h> -#include <asm/cpu.h> -#include <asm/processor.h> -#include <asm/smtc.h> -#include <asm/mmu_context.h> -#include <asm/smtc_ipi.h> - -/* VPE/SMP Prototype implements platform interfaces directly */ - -/* - * Cause the specified action to be performed on a targeted "CPU" - */ - -static void ssmtc_send_ipi_single(int cpu, unsigned int action) -{ - smtc_send_ipi(cpu, LINUX_SMP_IPI, action); - /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ -} - -static inline void ssmtc_send_ipi_mask(const struct cpumask *mask, - unsigned int action) -{ - unsigned int i; - - for_each_cpu(i, mask) - ssmtc_send_ipi_single(i, action); -} - -/* - * Post-config but pre-boot cleanup entry point - */ -static void __cpuinit ssmtc_init_secondary(void) -{ - smtc_init_secondary(); -} - -/* - * SMP initialization finalization entry point - */ -static void __cpuinit ssmtc_smp_finish(void) -{ - smtc_smp_finish(); -} - -/* - * Hook for after all CPUs are online - */ -static void ssmtc_cpus_done(void) -{ -} - -/* - * Platform "CPU" startup hook - */ -static void __cpuinit ssmtc_boot_secondary(int cpu, struct task_struct *idle) -{ - smtc_boot_secondary(cpu, idle); -} - -static void __init ssmtc_smp_setup(void) -{ - if (read_c0_config3() & (1 << 2)) - mipsmt_build_cpu_map(0); -} - -/* - * Platform SMP pre-initialization - */ -static void ssmtc_prepare_cpus(unsigned int max_cpus) -{ - /* - * As noted above, we can assume a single CPU for now - * but it may be multithreaded. - */ - - if (read_c0_config3() & (1 << 2)) { - mipsmt_prepare_cpus(); - } -} - -struct plat_smp_ops ssmtc_smp_ops = { - .send_ipi_single = ssmtc_send_ipi_single, - .send_ipi_mask = ssmtc_send_ipi_mask, - .init_secondary = ssmtc_init_secondary, - .smp_finish = ssmtc_smp_finish, - .cpus_done = ssmtc_cpus_done, - .boot_secondary = ssmtc_boot_secondary, - .smp_setup = ssmtc_smp_setup, - .prepare_cpus = ssmtc_prepare_cpus, -}; diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c deleted file mode 100644 index 77bad3c04280..000000000000 --- a/arch/mips/mipssim/sim_time.c +++ /dev/null @@ -1,117 +0,0 @@ -#include <linux/types.h> -#include <linux/init.h> -#include <linux/kernel_stat.h> -#include <linux/sched.h> -#include <linux/spinlock.h> -#include <linux/interrupt.h> -#include <linux/mc146818rtc.h> -#include <linux/smp.h> -#include <linux/timex.h> - -#include <asm/hardirq.h> -#include <asm/div64.h> -#include <asm/cpu.h> -#include <asm/setup.h> -#include <asm/time.h> -#include <asm/irq.h> -#include <asm/mc146818-time.h> -#include <asm/msc01_ic.h> - -#include <asm/mips-boards/generic.h> -#include <asm/mips-boards/prom.h> -#include <asm/mips-boards/simint.h> - - -unsigned long cpu_khz; - -/* - * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect - */ -static unsigned int __init estimate_cpu_frequency(void) -{ - unsigned int prid = read_c0_prid() & 0xffff00; - unsigned int count; - -#if 1 - /* - * hardwire the board frequency to 12MHz. - */ - - if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || - (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) - count = 12000000; - else - count = 6000000; -#else - unsigned int flags; - - local_irq_save(flags); - - /* Start counter exactly on falling edge of update flag */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); - while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - - /* Start r4k counter. */ - write_c0_count(0); - - /* Read counter exactly on falling edge of update flag */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); - while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - - count = read_c0_count(); - - /* restore interrupts */ - local_irq_restore(flags); -#endif - - mips_hpt_frequency = count; - - if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && - (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) - count *= 2; - - count += 5000; /* round */ - count -= count%10000; - - return count; -} - -static int mips_cpu_timer_irq; - -static void mips_timer_dispatch(void) -{ - do_IRQ(mips_cpu_timer_irq); -} - - -unsigned __cpuinit get_c0_compare_int(void) -{ -#ifdef MSC01E_INT_BASE - if (cpu_has_veic) { - set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); - mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; - - return mips_cpu_timer_irq; - } -#endif - if (cpu_has_vint) - set_vi_handler(cp0_compare_irq, mips_timer_dispatch); - mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; - - return mips_cpu_timer_irq; -} - -void __init plat_time_init(void) -{ - unsigned int est_freq; - - /* Set Data mode - binary. */ - CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); - - est_freq = estimate_cpu_frequency(); - - printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000, - (est_freq % 1000000) * 100 / 1000000); - - cpu_khz = est_freq / 1000; -} diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index fd6203f14f1f..90ceb963aaf1 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -11,27 +11,12 @@ obj-$(CONFIG_64BIT) += pgtable-64.o obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o -obj-$(CONFIG_CPU_LOONGSON2) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o -obj-$(CONFIG_CPU_R4300) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R4X00) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R5000) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R5500) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o -obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o -obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o -obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o -obj-$(CONFIG_CPU_XLP) += c-r4k.o tlb-r4k.o cex-gen.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index f092c265dc63..4c32ede464b5 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -786,6 +786,25 @@ static inline void rm7k_erratum31(void) } } +static inline void alias_74k_erratum(struct cpuinfo_mips *c) +{ + /* + * Early versions of the 74K do not update the cache tags on a + * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG + * aliases. In this case it is better to treat the cache as always + * having aliases. + */ + if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0)) + c->dcache.flags |= MIPS_CACHE_VTAG; + if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0)) + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); + if (((c->processor_id & 0xff00) == PRID_IMP_1074K) && + ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) { + c->dcache.flags |= MIPS_CACHE_VTAG; + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); + } +} + static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way", "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" }; @@ -1056,6 +1075,8 @@ static void __cpuinit probe_pcache(void) case CPU_34K: case CPU_74K: case CPU_1004K: + if (c->cputype == CPU_74K) + alias_74k_erratum(c); if ((read_c0_config7() & (1 << 16))) { /* effectively physically indexed dcache, thus no virtual aliases. */ diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 829320c7b175..07cec4407b0c 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -142,7 +142,7 @@ EXPORT_SYMBOL(_page_cachable_default); static inline void setup_protection_map(void) { - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { protection_map[0] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); protection_map[1] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); protection_map[2] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index c14f6dfed995..7a19957735e9 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -114,7 +114,7 @@ good_area: if (!(vma->vm_flags & VM_WRITE)) goto bad_area; } else { - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { if (address == regs->cp0_epc && !(vma->vm_flags & VM_EXEC)) { #if 0 pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] XI violation\n", diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index d2572cb232db..87b9cfcc30ff 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -401,7 +401,7 @@ void __cpuinit tlb_init(void) current_cpu_type() == CPU_R14000) write_c0_framemask(0); - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { /* * Enable the no read, no exec bits, and enable large virtual * address. diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 03eb0ef91580..e09d49256908 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -449,8 +449,20 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, } if (cpu_has_mips_r2) { - if (cpu_has_mips_r2_exec_hazard) + /* + * The architecture spec says an ehb is required here, + * but a number of cores do not have the hazard and + * using an ehb causes an expensive pipeline stall. + */ + switch (current_cpu_type()) { + case CPU_M14KC: + case CPU_74K: + break; + + default: uasm_i_ehb(p); + break; + } tlbw(p); return; } @@ -586,7 +598,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p, unsigned int reg) { - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); } else { @@ -921,6 +933,13 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) #endif uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); + + if (cpu_has_mips_r2) { + uasm_i_ext(p, tmp, tmp, PGDIR_SHIFT, (32 - PGDIR_SHIFT)); + uasm_i_ins(p, ptr, tmp, PGD_T_LOG2, (32 - PGDIR_SHIFT)); + return; + } + uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ @@ -956,6 +975,15 @@ static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) { + if (cpu_has_mips_r2) { + /* PTE ptr offset is obtained from BadVAddr */ + UASM_i_MFC0(p, tmp, C0_BADVADDR); + UASM_i_LW(p, ptr, 0, ptr); + uasm_i_ext(p, tmp, tmp, PAGE_SHIFT+1, PGDIR_SHIFT-PAGE_SHIFT-1); + uasm_i_ins(p, ptr, tmp, PTE_T_LOG2+1, PGDIR_SHIFT-PAGE_SHIFT-1); + return; + } + /* * Bug workaround for the Nevada. It seems as if under certain * circumstances the move from cp0_context might produce a @@ -990,7 +1018,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, if (cpu_has_64bits) { uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); @@ -1017,7 +1045,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ if (r45k_bvahwbug()) build_tlb_probe_entry(p); - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); @@ -1183,7 +1211,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, UASM_i_LW(p, even, 0, ptr); /* get even pte */ UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ } - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_NO_EXEC)); uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_NO_EXEC)); uasm_i_drotr(p, even, even, @@ -1545,7 +1573,7 @@ build_pte_present(u32 **p, struct uasm_reloc **r, { int t = scratch >= 0 ? scratch : pte; - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { if (use_bbit_insns()) { uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); uasm_i_nop(p); @@ -1875,7 +1903,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void) if (m4kc_tlbp_war()) build_tlb_probe_entry(&p); - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { /* * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. @@ -1929,7 +1957,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void) build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); build_tlb_probe_entry(&p); - if (kernel_uses_smartmips_rixi) { + if (cpu_has_rixi) { /* * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 64a28e819064..39b891056227 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -63,11 +63,12 @@ enum opcode { insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, - insn_j, insn_jal, insn_jr, insn_ld, insn_ldx, insn_ll, insn_lld, - insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0, insn_or, insn_ori, - insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, - insn_sra, insn_srl, insn_subu, insn_sw, insn_syscall, insn_tlbp, - insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, + insn_ext, insn_ins, insn_j, insn_jal, insn_jr, insn_ld, insn_ldx, + insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0, + insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, + insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, + insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, + insn_xori, }; struct insn { @@ -115,6 +116,9 @@ static struct insn insn_table[] __uasminitdata = { { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, + { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, + { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, + { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, @@ -341,6 +345,13 @@ Ip_u2u1msbu3(op) \ } \ UASM_EXPORT_SYMBOL(uasm_i##op); +#define I_u2u1msbdu3(op) \ +Ip_u2u1msbu3(op) \ +{ \ + build_insn(buf, insn##op, b, a, d-1, c); \ +} \ +UASM_EXPORT_SYMBOL(uasm_i##op); + #define I_u1u2(op) \ Ip_u1u2(op) \ { \ @@ -394,6 +405,8 @@ I_u2u1u3(_drotr) I_u2u1u3(_drotr32) I_u3u1u2(_dsubu) I_0(_eret) +I_u2u1msbdu3(_ext) +I_u2u1msbu3(_ins) I_u1(_j) I_u1(_jal) I_u1(_jr) diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index fea823f18479..647b86383184 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -750,3 +750,37 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup) return retval; } + +void gic_enable_interrupt(int irq_vec) +{ + GIC_SET_INTR_MASK(irq_vec); +} + +void gic_disable_interrupt(int irq_vec) +{ + GIC_CLR_INTR_MASK(irq_vec); +} + +void gic_irq_ack(struct irq_data *d) +{ + int irq = (d->irq - gic_irq_base); + + GIC_CLR_INTR_MASK(irq); + + if (gic_irq_flags[irq] & GIC_TRIG_EDGE) + GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); +} + +void gic_finish_irq(struct irq_data *d) +{ + /* Enable interrupts. */ + GIC_SET_INTR_MASK(d->irq - gic_irq_base); +} + +void __init gic_platform_init(int irqs, struct irq_chip *irq_controller) +{ + int i; + + for (i = gic_irq_base; i < (gic_irq_base + irqs); i++) + irq_set_chip(i, irq_controller); +} diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile new file mode 100644 index 000000000000..626afeac4386 --- /dev/null +++ b/arch/mips/mti-sead3/Makefile @@ -0,0 +1,19 @@ +# +# Carsten Langgaard, carstenl@mips.com +# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. +# +# Copyright (C) 2008 Wind River Systems, Inc. +# written by Ralf Baechle <ralf@linux-mips.org> +# +obj-y := sead3-lcd.o sead3-cmdline.o \ + sead3-display.o sead3-init.o sead3-int.o \ + sead3-mtd.o sead3-net.o \ + sead3-memory.o sead3-platform.o \ + sead3-reset.o sead3-setup.o sead3-time.o + +obj-y += sead3-i2c-dev.o sead3-i2c.o \ + sead3-pic32-i2c-drv.o sead3-pic32-bus.o \ + leds-sead3.o sead3-leds.o + +obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o +obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o diff --git a/arch/mips/mti-sead3/Platform b/arch/mips/mti-sead3/Platform new file mode 100644 index 000000000000..387092427145 --- /dev/null +++ b/arch/mips/mti-sead3/Platform @@ -0,0 +1,7 @@ +# +# MIPS SEAD-3 board +# +platform-$(CONFIG_MIPS_SEAD3) += mti-sead3/ +cflags-$(CONFIG_MIPS_SEAD3) += -I$(srctree)/arch/mips/include/asm/mach-sead3 +load-$(CONFIG_MIPS_SEAD3) += 0xffffffff80100000 +all-$(CONFIG_MIPS_SEAD3) := $(COMPRESSION_FNAME).srec diff --git a/arch/mips/mti-sead3/leds-sead3.c b/arch/mips/mti-sead3/leds-sead3.c new file mode 100644 index 000000000000..a95ac5985206 --- /dev/null +++ b/arch/mips/mti-sead3/leds-sead3.c @@ -0,0 +1,128 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/err.h> +#include <linux/io.h> + +#define DRVNAME "sead3-led" + +static struct platform_device *pdev; + +static void sead3_pled_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + pr_debug("sead3_pled_set\n"); + writel(value, (void __iomem *)0xBF000210); /* FIXME */ +} + +static void sead3_fled_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + pr_debug("sead3_fled_set\n"); + writel(value, (void __iomem *)0xBF000218); /* FIXME */ +} + +static struct led_classdev sead3_pled = { + .name = "sead3::pled", + .brightness_set = sead3_pled_set, +}; + +static struct led_classdev sead3_fled = { + .name = "sead3::fled", + .brightness_set = sead3_fled_set, +}; + +#ifdef CONFIG_PM +static int sead3_led_suspend(struct platform_device *dev, + pm_message_t state) +{ + led_classdev_suspend(&sead3_pled); + led_classdev_suspend(&sead3_fled); + return 0; +} + +static int sead3_led_resume(struct platform_device *dev) +{ + led_classdev_resume(&sead3_pled); + led_classdev_resume(&sead3_fled); + return 0; +} +#else +#define sead3_led_suspend NULL +#define sead3_led_resume NULL +#endif + +static int sead3_led_probe(struct platform_device *pdev) +{ + int ret; + + ret = led_classdev_register(&pdev->dev, &sead3_pled); + if (ret < 0) + return ret; + + ret = led_classdev_register(&pdev->dev, &sead3_fled); + if (ret < 0) + led_classdev_unregister(&sead3_pled); + + return ret; +} + +static int sead3_led_remove(struct platform_device *pdev) +{ + led_classdev_unregister(&sead3_pled); + led_classdev_unregister(&sead3_fled); + return 0; +} + +static struct platform_driver sead3_led_driver = { + .probe = sead3_led_probe, + .remove = sead3_led_remove, + .suspend = sead3_led_suspend, + .resume = sead3_led_resume, + .driver = { + .name = DRVNAME, + .owner = THIS_MODULE, + }, +}; + +static int __init sead3_led_init(void) +{ + int ret; + + ret = platform_driver_register(&sead3_led_driver); + if (ret < 0) + goto out; + + pdev = platform_device_register_simple(DRVNAME, -1, NULL, 0); + if (IS_ERR(pdev)) { + ret = PTR_ERR(pdev); + platform_driver_unregister(&sead3_led_driver); + goto out; + } + +out: + return ret; +} + +static void __exit sead3_led_exit(void) +{ + platform_device_unregister(pdev); + platform_driver_unregister(&sead3_led_driver); +} + +module_init(sead3_led_init); +module_exit(sead3_led_exit); + +MODULE_AUTHOR("Kristian Kielhofner <kris@krisk.org>"); +MODULE_DESCRIPTION("SEAD3 LED driver"); +MODULE_LICENSE("GPL"); + diff --git a/arch/mips/mti-sead3/sead3-cmdline.c b/arch/mips/mti-sead3/sead3-cmdline.c new file mode 100644 index 000000000000..a2e6cec67f57 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-cmdline.c @@ -0,0 +1,46 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/init.h> +#include <linux/string.h> + +#include <asm/bootinfo.h> + +extern int prom_argc; +extern int *_prom_argv; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension. + */ +#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +void __init prom_init_cmdline(void) +{ + char *cp; + int actr; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while (actr < prom_argc) { + strcpy(cp, prom_argv(actr)); + cp += strlen(prom_argv(actr)); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) { + /* get rid of trailing space */ + --cp; + *cp = '\0'; + } +} diff --git a/arch/mips/mti-sead3/sead3-console.c b/arch/mips/mti-sead3/sead3-console.c new file mode 100644 index 000000000000..b36739108a0f --- /dev/null +++ b/arch/mips/mti-sead3/sead3-console.c @@ -0,0 +1,46 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/init.h> +#include <linux/console.h> +#include <linux/serial_reg.h> +#include <linux/io.h> + +#define SEAD_UART1_REGS_BASE 0xbf000800 /* ttyS1 = DB9 port */ +#define SEAD_UART0_REGS_BASE 0xbf000900 /* ttyS0 = USB port */ +#define PORT(base_addr, offset) ((unsigned int __iomem *)(base_addr+(offset)*4)) + +static char console_port = 1; + +static inline unsigned int serial_in(int offset, unsigned int base_addr) +{ + return __raw_readl(PORT(base_addr, offset)) & 0xff; +} + +static inline void serial_out(int offset, int value, unsigned int base_addr) +{ + __raw_writel(value, PORT(base_addr, offset)); +} + +void __init prom_init_early_console(char port) +{ + console_port = port; +} + +int prom_putchar(char c) +{ + unsigned int base_addr; + + base_addr = console_port ? SEAD_UART1_REGS_BASE : SEAD_UART0_REGS_BASE; + + while ((serial_in(UART_LSR, base_addr) & UART_LSR_THRE) == 0) + ; + + serial_out(UART_TX, c, base_addr); + + return 1; +} diff --git a/arch/mips/mti-sead3/sead3-display.c b/arch/mips/mti-sead3/sead3-display.c new file mode 100644 index 000000000000..8308c7fc188a --- /dev/null +++ b/arch/mips/mti-sead3/sead3-display.c @@ -0,0 +1,78 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/timer.h> +#include <linux/io.h> +#include <asm/mips-boards/generic.h> +#include <asm/mips-boards/prom.h> + +static unsigned int display_count; +static unsigned int max_display_count; + +#define LCD_DISPLAY_POS_BASE 0x1f000400 +#define DISPLAY_LCDINSTRUCTION (0*2) +#define DISPLAY_LCDDATA (1*2) +#define DISPLAY_CPLDSTATUS (2*2) +#define DISPLAY_CPLDDATA (3*2) +#define LCD_SETDDRAM 0x80 +#define LCD_IR_BF 0x80 + +const char display_string[] = " LINUX ON SEAD3 "; + +static void scroll_display_message(unsigned long data); +static DEFINE_TIMER(mips_scroll_timer, scroll_display_message, HZ, 0); + +static void lcd_wait(unsigned int __iomem *display) +{ + /* Wait for CPLD state machine to become idle. */ + do { } while (__raw_readl(display + DISPLAY_CPLDSTATUS) & 1); + + do { + __raw_readl(display + DISPLAY_LCDINSTRUCTION); + + /* Wait for CPLD state machine to become idle. */ + do { } while (__raw_readl(display + DISPLAY_CPLDSTATUS) & 1); + } while (__raw_readl(display + DISPLAY_CPLDDATA) & LCD_IR_BF); +} + +void mips_display_message(const char *str) +{ + static unsigned int __iomem *display; + char ch; + int i; + + if (unlikely(display == NULL)) + display = ioremap_nocache(LCD_DISPLAY_POS_BASE, + (8 * sizeof(int))); + + for (i = 0; i < 16; i++) { + if (*str) + ch = *str++; + else + ch = ' '; + lcd_wait(display); + __raw_writel((LCD_SETDDRAM | i), + (display + DISPLAY_LCDINSTRUCTION)); + lcd_wait(display); + __raw_writel(ch, display + DISPLAY_LCDDATA); + } +} + +static void scroll_display_message(unsigned long data) +{ + mips_display_message(&display_string[display_count++]); + if (display_count == max_display_count) + display_count = 0; + mod_timer(&mips_scroll_timer, jiffies + HZ); +} + +void mips_scroll_message(void) +{ + del_timer_sync(&mips_scroll_timer); + max_display_count = strlen(display_string) + 1 - 16; + mod_timer(&mips_scroll_timer, jiffies + 1); +} diff --git a/arch/mips/mti-sead3/sead3-ehci.c b/arch/mips/mti-sead3/sead3-ehci.c new file mode 100644 index 000000000000..772fc056a92d --- /dev/null +++ b/arch/mips/mti-sead3/sead3-ehci.c @@ -0,0 +1,47 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/module.h> +#include <linux/irq.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> + +struct resource ehci_resources[] = { + { + .start = 0x1b200000, + .end = 0x1b200fff, + .flags = IORESOURCE_MEM + }, + { + .start = MIPS_CPU_IRQ_BASE + 2, + .flags = IORESOURCE_IRQ + } +}; + +u64 sead3_usbdev_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device ehci_device = { + .name = "sead3-ehci", + .id = 0, + .dev = { + .dma_mask = &sead3_usbdev_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32) + }, + .num_resources = ARRAY_SIZE(ehci_resources), + .resource = ehci_resources +}; + +static int __init ehci_init(void) +{ + return platform_device_register(&ehci_device); +} + +module_init(ehci_init); + +MODULE_AUTHOR("Chris Dearman <chris@mips.com>"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("EHCI probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-i2c-dev.c b/arch/mips/mti-sead3/sead3-i2c-dev.c new file mode 100644 index 000000000000..eca0b53a71dd --- /dev/null +++ b/arch/mips/mti-sead3/sead3-i2c-dev.c @@ -0,0 +1,33 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/init.h> +#include <linux/i2c.h> + +static struct i2c_board_info __initdata sead3_i2c_devices[] = { + { + I2C_BOARD_INFO("adt7476", 0x2c), + .irq = 0, + }, + { + I2C_BOARD_INFO("m41t80", 0x68), + .irq = 0, + }, +}; + +static int __init sead3_i2c_init(void) +{ + int err; + + err = i2c_register_board_info(0, sead3_i2c_devices, + ARRAY_SIZE(sead3_i2c_devices)); + if (err < 0) + pr_err("sead3-i2c-dev: cannot register board I2C devices\n"); + return err; +} + +arch_initcall(sead3_i2c_init); diff --git a/arch/mips/mti-sead3/sead3-i2c-drv.c b/arch/mips/mti-sead3/sead3-i2c-drv.c new file mode 100644 index 000000000000..0375ee66bca3 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-i2c-drv.c @@ -0,0 +1,405 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/init.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/platform_device.h> + +#define PIC32_I2CxCON 0x0000 +#define PIC32_I2CCON_ON (1<<15) +#define PIC32_I2CCON_ACKDT (1<<5) +#define PIC32_I2CCON_ACKEN (1<<4) +#define PIC32_I2CCON_RCEN (1<<3) +#define PIC32_I2CCON_PEN (1<<2) +#define PIC32_I2CCON_RSEN (1<<1) +#define PIC32_I2CCON_SEN (1<<0) +#define PIC32_I2CxCONCLR 0x0004 +#define PIC32_I2CxCONSET 0x0008 +#define PIC32_I2CxSTAT 0x0010 +#define PIC32_I2CxSTATCLR 0x0014 +#define PIC32_I2CSTAT_ACKSTAT (1<<15) +#define PIC32_I2CSTAT_TRSTAT (1<<14) +#define PIC32_I2CSTAT_BCL (1<<10) +#define PIC32_I2CSTAT_IWCOL (1<<7) +#define PIC32_I2CSTAT_I2COV (1<<6) +#define PIC32_I2CxBRG 0x0040 +#define PIC32_I2CxTRN 0x0050 +#define PIC32_I2CxRCV 0x0060 + +static DEFINE_SPINLOCK(pic32_bus_lock); + +static void __iomem *bus_xfer = (void __iomem *)0xbf000600; +static void __iomem *bus_status = (void __iomem *)0xbf000060; + +#define DELAY() udelay(100) + +static inline unsigned int ioready(void) +{ + return readl(bus_status) & 1; +} + +static inline void wait_ioready(void) +{ + do { } while (!ioready()); +} + +static inline void wait_ioclear(void) +{ + do { } while (ioready()); +} + +static inline void check_ioclear(void) +{ + if (ioready()) { + do { + (void) readl(bus_xfer); + DELAY(); + } while (ioready()); + } +} + +static u32 pic32_bus_readl(u32 reg) +{ + unsigned long flags; + u32 status, val; + + spin_lock_irqsave(&pic32_bus_lock, flags); + + check_ioclear(); + writel((0x01 << 24) | (reg & 0x00ffffff), bus_xfer); + DELAY(); + wait_ioready(); + status = readl(bus_xfer); + DELAY(); + val = readl(bus_xfer); + wait_ioclear(); + + spin_unlock_irqrestore(&pic32_bus_lock, flags); + + return val; +} + +static void pic32_bus_writel(u32 val, u32 reg) +{ + unsigned long flags; + u32 status; + + spin_lock_irqsave(&pic32_bus_lock, flags); + + check_ioclear(); + writel((0x10 << 24) | (reg & 0x00ffffff), bus_xfer); + DELAY(); + writel(val, bus_xfer); + DELAY(); + wait_ioready(); + status = readl(bus_xfer); + wait_ioclear(); + + spin_unlock_irqrestore(&pic32_bus_lock, flags); +} + +struct pic32_i2c_platform_data { + u32 base; + struct i2c_adapter adap; + u32 xfer_timeout; + u32 ack_timeout; + u32 ctl_timeout; +}; + +static inline void pic32_i2c_start(struct pic32_i2c_platform_data *adap) +{ + pic32_bus_writel(PIC32_I2CCON_SEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void pic32_i2c_stop(struct pic32_i2c_platform_data *adap) +{ + pic32_bus_writel(PIC32_I2CCON_PEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void pic32_i2c_ack(struct pic32_i2c_platform_data *adap) +{ + pic32_bus_writel(PIC32_I2CCON_ACKDT, adap->base + PIC32_I2CxCONCLR); + pic32_bus_writel(PIC32_I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void pic32_i2c_nack(struct pic32_i2c_platform_data *adap) +{ + pic32_bus_writel(PIC32_I2CCON_ACKDT, adap->base + PIC32_I2CxCONSET); + pic32_bus_writel(PIC32_I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET); +} + +static inline int pic32_i2c_idle(struct pic32_i2c_platform_data *adap) +{ + int i; + + for (i = 0; i < adap->ctl_timeout; i++) { + if (((pic32_bus_readl(adap->base + PIC32_I2CxCON) & + (PIC32_I2CCON_ACKEN | PIC32_I2CCON_RCEN | + PIC32_I2CCON_PEN | PIC32_I2CCON_RSEN | + PIC32_I2CCON_SEN)) == 0) && + ((pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & + (PIC32_I2CSTAT_TRSTAT)) == 0)) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static inline u32 pic32_i2c_master_write(struct pic32_i2c_platform_data *adap, + u32 byte) +{ + pic32_bus_writel(byte, adap->base + PIC32_I2CxTRN); + return pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & + PIC32_I2CSTAT_IWCOL; +} + +static inline u32 pic32_i2c_master_read(struct pic32_i2c_platform_data *adap) +{ + pic32_bus_writel(PIC32_I2CCON_RCEN, adap->base + PIC32_I2CxCONSET); + while (pic32_bus_readl(adap->base + PIC32_I2CxCON) & PIC32_I2CCON_RCEN) + ; + pic32_bus_writel(PIC32_I2CSTAT_I2COV, adap->base + PIC32_I2CxSTATCLR); + return pic32_bus_readl(adap->base + PIC32_I2CxRCV); +} + +static int pic32_i2c_address(struct pic32_i2c_platform_data *adap, + unsigned int addr, int rd) +{ + pic32_i2c_idle(adap); + pic32_i2c_start(adap); + pic32_i2c_idle(adap); + + addr <<= 1; + if (rd) + addr |= 1; + + if (pic32_i2c_master_write(adap, addr)) + return -EIO; + pic32_i2c_idle(adap); + if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & + PIC32_I2CSTAT_ACKSTAT) + return -EIO; + return 0; +} + +static int sead3_i2c_read(struct pic32_i2c_platform_data *adap, + unsigned char *buf, unsigned int len) +{ + u32 data; + int i; + + i = 0; + while (i < len) { + data = pic32_i2c_master_read(adap); + buf[i++] = data; + if (i < len) + pic32_i2c_ack(adap); + else + pic32_i2c_nack(adap); + } + + pic32_i2c_stop(adap); + pic32_i2c_idle(adap); + return 0; +} + +static int sead3_i2c_write(struct pic32_i2c_platform_data *adap, + unsigned char *buf, unsigned int len) +{ + int i; + u32 data; + + i = 0; + while (i < len) { + data = buf[i]; + if (pic32_i2c_master_write(adap, data)) + return -EIO; + pic32_i2c_idle(adap); + if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & + PIC32_I2CSTAT_ACKSTAT) + return -EIO; + i++; + } + + pic32_i2c_stop(adap); + pic32_i2c_idle(adap); + return 0; +} + +static int sead3_pic32_platform_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg *msgs, int num) +{ + struct pic32_i2c_platform_data *adap = i2c_adap->algo_data; + struct i2c_msg *p; + int i, err = 0; + + for (i = 0; i < num; i++) { +#define __BUFSIZE 80 + int ii; + static char buf[__BUFSIZE]; + char *b = buf; + + p = &msgs[i]; + b += sprintf(buf, " [%d bytes]", p->len); + if ((p->flags & I2C_M_RD) == 0) { + for (ii = 0; ii < p->len; ii++) { + if (b < &buf[__BUFSIZE-4]) { + b += sprintf(b, " %02x", p->buf[ii]); + } else { + strcat(b, "..."); + break; + } + } + } + } + + for (i = 0; !err && i < num; i++) { + p = &msgs[i]; + err = pic32_i2c_address(adap, p->addr, p->flags & I2C_M_RD); + if (err || !p->len) + continue; + if (p->flags & I2C_M_RD) + err = sead3_i2c_read(adap, p->buf, p->len); + else + err = sead3_i2c_write(adap, p->buf, p->len); + } + + /* Return the number of messages processed, or the error code. */ + if (err == 0) + err = num; + + return err; +} + +static u32 sead3_pic32_platform_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm sead3_platform_algo = { + .master_xfer = sead3_pic32_platform_xfer, + .functionality = sead3_pic32_platform_func, +}; + +static void sead3_i2c_platform_setup(struct pic32_i2c_platform_data *priv) +{ + pic32_bus_writel(500, priv->base + PIC32_I2CxBRG); + pic32_bus_writel(PIC32_I2CCON_ON, priv->base + PIC32_I2CxCONCLR); + pic32_bus_writel(PIC32_I2CCON_ON, priv->base + PIC32_I2CxCONSET); + pic32_bus_writel(PIC32_I2CSTAT_BCL | PIC32_I2CSTAT_IWCOL, + priv->base + PIC32_I2CxSTATCLR); +} + +static int __devinit sead3_i2c_platform_probe(struct platform_device *pdev) +{ + struct pic32_i2c_platform_data *priv; + struct resource *r; + int ret; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + ret = -ENODEV; + goto out; + } + + priv = kzalloc(sizeof(struct pic32_i2c_platform_data), GFP_KERNEL); + if (!priv) { + ret = -ENOMEM; + goto out; + } + + priv->base = r->start; + if (!priv->base) { + ret = -EBUSY; + goto out_mem; + } + + priv->xfer_timeout = 200; + priv->ack_timeout = 200; + priv->ctl_timeout = 200; + + priv->adap.nr = pdev->id; + priv->adap.algo = &sead3_platform_algo; + priv->adap.algo_data = priv; + priv->adap.dev.parent = &pdev->dev; + strlcpy(priv->adap.name, "SEAD3 PIC32", sizeof(priv->adap.name)); + + sead3_i2c_platform_setup(priv); + + ret = i2c_add_numbered_adapter(&priv->adap); + if (ret == 0) { + platform_set_drvdata(pdev, priv); + return 0; + } + +out_mem: + kfree(priv); +out: + return ret; +} + +static int __devexit sead3_i2c_platform_remove(struct platform_device *pdev) +{ + struct pic32_i2c_platform_data *priv = platform_get_drvdata(pdev); + + platform_set_drvdata(pdev, NULL); + i2c_del_adapter(&priv->adap); + kfree(priv); + return 0; +} + +#ifdef CONFIG_PM +static int sead3_i2c_platform_suspend(struct platform_device *pdev, + pm_message_t state) +{ + dev_dbg(&pdev->dev, "i2c_platform_disable\n"); + return 0; +} + +static int sead3_i2c_platform_resume(struct platform_device *pdev) +{ + struct pic32_i2c_platform_data *priv = platform_get_drvdata(pdev); + + dev_dbg(&pdev->dev, "sead3_i2c_platform_setup\n"); + sead3_i2c_platform_setup(priv); + + return 0; +} +#else +#define sead3_i2c_platform_suspend NULL +#define sead3_i2c_platform_resume NULL +#endif + +static struct platform_driver sead3_i2c_platform_driver = { + .driver = { + .name = "sead3-i2c", + .owner = THIS_MODULE, + }, + .probe = sead3_i2c_platform_probe, + .remove = __devexit_p(sead3_i2c_platform_remove), + .suspend = sead3_i2c_platform_suspend, + .resume = sead3_i2c_platform_resume, +}; + +static int __init sead3_i2c_platform_init(void) +{ + return platform_driver_register(&sead3_i2c_platform_driver); +} +module_init(sead3_i2c_platform_init); + +static void __exit sead3_i2c_platform_exit(void) +{ + platform_driver_unregister(&sead3_i2c_platform_driver); +} +module_exit(sead3_i2c_platform_exit); + +MODULE_AUTHOR("Chris Dearman, MIPS Technologies INC."); +MODULE_DESCRIPTION("SEAD3 PIC32 I2C driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/mips/mti-sead3/sead3-i2c.c b/arch/mips/mti-sead3/sead3-i2c.c new file mode 100644 index 000000000000..f70d5fc58ef5 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-i2c.c @@ -0,0 +1,37 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/module.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <irq.h> + +struct resource sead3_i2c_resources[] = { + { + .start = 0x805200, + .end = 0x8053ff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device sead3_i2c_device = { + .name = "sead3-i2c", + .id = 0, + .num_resources = ARRAY_SIZE(sead3_i2c_resources), + .resource = sead3_i2c_resources, +}; + +static int __init sead3_i2c_init(void) +{ + return platform_device_register(&sead3_i2c_device); +} + +module_init(sead3_i2c_init); + +MODULE_AUTHOR("Chris Dearman <chris@mips.com>"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("I2C probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c new file mode 100644 index 000000000000..a958cad6fff6 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-init.c @@ -0,0 +1,91 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/init.h> +#include <linux/io.h> + +#include <asm/bootinfo.h> +#include <asm/cacheflush.h> +#include <asm/traps.h> +#include <asm/mips-boards/generic.h> +#include <asm/mips-boards/prom.h> + +extern void prom_init_early_console(char port); + +extern char except_vec_nmi; +extern char except_vec_ejtag_debug; + +int prom_argc; +int *_prom_argv, *_prom_envp; + +#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) + +char *prom_getenv(char *envname) +{ + /* + * Return a pointer to the given environment variable. + * In 64-bit mode: we're using 64-bit pointers, but all pointers + * in the PROM structures are only 32-bit, so we need some + * workarounds, if we are running in 64-bit mode. + */ + int i, index = 0; + + i = strlen(envname); + + while (prom_envp(index)) { + if (strncmp(envname, prom_envp(index), i) == 0) + return prom_envp(index+1); + index += 2; + } + + return NULL; +} + +static void __init mips_nmi_setup(void) +{ + void *base; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa80) : + (void *)(CAC_BASE + 0x380); + memcpy(base, &except_vec_nmi, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + +static void __init mips_ejtag_setup(void) +{ + void *base; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa00) : + (void *)(CAC_BASE + 0x300); + memcpy(base, &except_vec_ejtag_debug, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + +void __init prom_init(void) +{ + prom_argc = fw_arg0; + _prom_argv = (int *) fw_arg1; + _prom_envp = (int *) fw_arg2; + + board_nmi_handler_setup = mips_nmi_setup; + board_ejtag_handler_setup = mips_ejtag_setup; + + prom_init_cmdline(); + prom_meminit(); +#ifdef CONFIG_EARLY_PRINTK + if ((strstr(prom_getcmdline(), "console=ttyS0")) != NULL) + prom_init_early_console(0); + else if ((strstr(prom_getcmdline(), "console=ttyS1")) != NULL) + prom_init_early_console(1); +#endif +#ifdef CONFIG_SERIAL_8250_CONSOLE + if ((strstr(prom_getcmdline(), "console=")) == NULL) + strcat(prom_getcmdline(), " console=ttyS0,38400n8r"); +#endif +} diff --git a/arch/mips/mti-sead3/sead3-int.c b/arch/mips/mti-sead3/sead3-int.c new file mode 100644 index 000000000000..e26e08274fc5 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-int.c @@ -0,0 +1,158 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <asm/gic.h> +#include <asm/irq_cpu.h> +#include <asm/setup.h> + +#include <asm/mips-boards/sead3int.h> + +#define SEAD_CONFIG_GIC_PRESENT_SHF 1 +#define SEAD_CONFIG_GIC_PRESENT_MSK (1 << SEAD_CONFIG_GIC_PRESENT_SHF) +#define SEAD_CONFIG_BASE 0x1b100110 +#define SEAD_CONFIG_SIZE 4 + +int gic_present; +static unsigned long sead3_config_reg; + +/* + * This table defines the setup for each external GIC interrupt. It is + * indexed by interrupt number. + */ +#define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK +static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { + { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED }, + { GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED }, + { GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED }, + { GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED }, + { GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED }, + { GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED }, + { GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED }, +}; + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + int irq; + + irq = (fls(pending) - CAUSEB_IP - 1); + if (irq >= 0) + do_IRQ(MIPS_CPU_IRQ_BASE + irq); + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + int i; + + if (!cpu_has_veic) { + mips_cpu_irq_init(); + + if (cpu_has_vint) { + /* install generic handler */ + for (i = 0; i < 8; i++) + set_vi_handler(i, plat_irq_dispatch); + } + } + + sead3_config_reg = (unsigned long)ioremap_nocache(SEAD_CONFIG_BASE, + SEAD_CONFIG_SIZE); + gic_present = (REG32(sead3_config_reg) & SEAD_CONFIG_GIC_PRESENT_MSK) >> + SEAD_CONFIG_GIC_PRESENT_SHF; + pr_info("GIC: %spresent\n", (gic_present) ? "" : "not "); + pr_info("EIC: %s\n", + (current_cpu_data.options & MIPS_CPU_VEIC) ? "on" : "off"); + + if (gic_present) + gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); +} + +void gic_enable_interrupt(int irq_vec) +{ + unsigned int i, irq_source; + + /* enable all the interrupts associated with this vector */ + for (i = 0; i < gic_shared_intr_map[irq_vec].num_shared_intr; i++) { + irq_source = gic_shared_intr_map[irq_vec].intr_list[i]; + GIC_SET_INTR_MASK(irq_source); + } + /* enable all local interrupts associated with this vector */ + if (gic_shared_intr_map[irq_vec].local_intr_mask) { + GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0); + GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), + gic_shared_intr_map[irq_vec].local_intr_mask); + } +} + +void gic_disable_interrupt(int irq_vec) +{ + unsigned int i, irq_source; + + /* disable all the interrupts associated with this vector */ + for (i = 0; i < gic_shared_intr_map[irq_vec].num_shared_intr; i++) { + irq_source = gic_shared_intr_map[irq_vec].intr_list[i]; + GIC_CLR_INTR_MASK(irq_source); + } + /* disable all local interrupts associated with this vector */ + if (gic_shared_intr_map[irq_vec].local_intr_mask) { + GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0); + GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), + gic_shared_intr_map[irq_vec].local_intr_mask); + } +} + +void gic_irq_ack(struct irq_data *d) +{ + GIC_CLR_INTR_MASK(d->irq - gic_irq_base); +} + +void gic_finish_irq(struct irq_data *d) +{ + unsigned int irq = (d->irq - gic_irq_base); + unsigned int i, irq_source; + + /* Clear edge detectors. */ + for (i = 0; i < gic_shared_intr_map[irq].num_shared_intr; i++) { + irq_source = gic_shared_intr_map[irq].intr_list[i]; + if (gic_irq_flags[irq_source] & GIC_TRIG_EDGE) + GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq_source); + } + + /* Enable interrupts. */ + GIC_SET_INTR_MASK(irq); +} + +void __init gic_platform_init(int irqs, struct irq_chip *irq_controller) +{ + int i; + + /* + * For non-EIC mode, we want to setup the GIC in pass-through + * mode, as if the GIC didn't exist. Do not map any interrupts + * for an external interrupt controller. + */ + if (!cpu_has_veic) + return; + + for (i = gic_irq_base; i < (gic_irq_base + irqs); i++) + irq_set_chip_and_handler(i, irq_controller, handle_percpu_irq); +} diff --git a/arch/mips/mti-sead3/sead3-lcd.c b/arch/mips/mti-sead3/sead3-lcd.c new file mode 100644 index 000000000000..10b10ed21f77 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-lcd.c @@ -0,0 +1,43 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/init.h> +#include <linux/platform_device.h> + +static struct resource __initdata sead3_lcd_resource = { + .start = 0x1f000400, + .end = 0x1f00041f, + .flags = IORESOURCE_MEM, +}; + +static __init int sead3_lcd_add(void) +{ + struct platform_device *pdev; + int retval; + + /* SEAD-3 and Cobalt platforms use same display type. */ + pdev = platform_device_alloc("cobalt-lcd", -1); + if (!pdev) + return -ENOMEM; + + retval = platform_device_add_resources(pdev, &sead3_lcd_resource, 1); + if (retval) + goto err_free_device; + + retval = platform_device_add(pdev); + if (retval) + goto err_free_device; + + return 0; + +err_free_device: + platform_device_put(pdev); + + return retval; +} + +device_initcall(sead3_lcd_add); diff --git a/arch/mips/mti-sead3/sead3-leds.c b/arch/mips/mti-sead3/sead3-leds.c new file mode 100644 index 000000000000..20102a6d4141 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-leds.c @@ -0,0 +1,83 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/module.h> +#include <linux/leds.h> +#include <linux/platform_device.h> + +#define LEDFLAGS(bits, shift) \ + ((bits << 8) | (shift << 8)) + +#define LEDBITS(id, shift, bits) \ + .name = id #shift, \ + .flags = LEDFLAGS(bits, shift) + +struct led_info led_data_info[] = { + { LEDBITS("bit", 0, 1) }, + { LEDBITS("bit", 1, 1) }, + { LEDBITS("bit", 2, 1) }, + { LEDBITS("bit", 3, 1) }, + { LEDBITS("bit", 4, 1) }, + { LEDBITS("bit", 5, 1) }, + { LEDBITS("bit", 6, 1) }, + { LEDBITS("bit", 7, 1) }, + { LEDBITS("all", 0, 8) }, +}; + +static struct led_platform_data led_data = { + .num_leds = ARRAY_SIZE(led_data_info), + .leds = led_data_info +}; + +static struct resource pled_resources[] = { + { + .start = 0x1f000210, + .end = 0x1f000217, + .flags = IORESOURCE_MEM + } +}; + +static struct platform_device pled_device = { + .name = "sead3::pled", + .id = 0, + .dev = { + .platform_data = &led_data, + }, + .num_resources = ARRAY_SIZE(pled_resources), + .resource = pled_resources +}; + + +static struct resource fled_resources[] = { + { + .start = 0x1f000218, + .end = 0x1f00021f, + .flags = IORESOURCE_MEM + } +}; + +static struct platform_device fled_device = { + .name = "sead3::fled", + .id = 0, + .dev = { + .platform_data = &led_data, + }, + .num_resources = ARRAY_SIZE(fled_resources), + .resource = fled_resources +}; + +static int __init led_init(void) +{ + platform_device_register(&pled_device); + return platform_device_register(&fled_device); +} + +module_init(led_init); + +MODULE_AUTHOR("Chris Dearman <chris@mips.com>"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("LED probe driver for SEAD-3"); diff --git a/arch/mips/mti-sead3/sead3-memory.c b/arch/mips/mti-sead3/sead3-memory.c new file mode 100644 index 000000000000..da9244106f86 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-memory.c @@ -0,0 +1,138 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/bootmem.h> + +#include <asm/bootinfo.h> +#include <asm/sections.h> +#include <asm/mips-boards/prom.h> + +enum yamon_memtypes { + yamon_dontuse, + yamon_prom, + yamon_free, +}; + +static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; + +/* determined physical memory size, not overridden by command line args */ +unsigned long physical_memsize = 0L; + +struct prom_pmemblock * __init prom_getmdesc(void) +{ + char *memsize_str, *ptr; + unsigned int memsize; + static char cmdline[COMMAND_LINE_SIZE] __initdata; + long val; + int tmp; + + /* otherwise look in the environment */ + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + pr_warn("memsize not set in boot prom, set to default 32Mb\n"); + physical_memsize = 0x02000000; + } else { + tmp = kstrtol(memsize_str, 0, &val); + physical_memsize = (unsigned long)val; + } + +#ifdef CONFIG_CPU_BIG_ENDIAN + /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last + word of physical memory */ + physical_memsize -= PAGE_SIZE; +#endif + + /* Check the command line for a memsize directive that overrides + the physical/default amount */ + strcpy(cmdline, arcs_cmdline); + ptr = strstr(cmdline, "memsize="); + if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) + ptr = strstr(ptr, " memsize="); + + if (ptr) + memsize = memparse(ptr + 8, &ptr); + else + memsize = physical_memsize; + + memset(mdesc, 0, sizeof(mdesc)); + + mdesc[0].type = yamon_dontuse; + mdesc[0].base = 0x00000000; + mdesc[0].size = 0x00001000; + + mdesc[1].type = yamon_prom; + mdesc[1].base = 0x00001000; + mdesc[1].size = 0x000ef000; + + /* + * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the + * south bridge and PCI access always forwarded to the ISA Bus and + * BIOSCS# is always generated. + * This mean that this area can't be used as DMA memory for PCI + * devices. + */ + mdesc[2].type = yamon_dontuse; + mdesc[2].base = 0x000f0000; + mdesc[2].size = 0x00010000; + + mdesc[3].type = yamon_dontuse; + mdesc[3].base = 0x00100000; + mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - + mdesc[3].base; + + mdesc[4].type = yamon_free; + mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); + mdesc[4].size = memsize - mdesc[4].base; + + return &mdesc[0]; +} + +static int __init prom_memtype_classify(unsigned int type) +{ + switch (type) { + case yamon_free: + return BOOT_MEM_RAM; + case yamon_prom: + return BOOT_MEM_ROM_DATA; + default: + return BOOT_MEM_RESERVED; + } +} + +void __init prom_meminit(void) +{ + struct prom_pmemblock *p; + + p = prom_getmdesc(); + + while (p->size) { + long type; + unsigned long base, size; + + type = prom_memtype_classify(p->type); + base = p->base; + size = p->size; + + add_memory_region(base, size, type); + p++; + } +} + +void __init prom_free_prom_memory(void) +{ + unsigned long addr; + int i; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) + continue; + + addr = boot_mem_map.map[i].addr; + free_init_pages("prom memory", + addr, addr + boot_mem_map.map[i].size); + } +} diff --git a/arch/mips/mti-sead3/sead3-mtd.c b/arch/mips/mti-sead3/sead3-mtd.c new file mode 100644 index 000000000000..ffa35f509789 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-mtd.c @@ -0,0 +1,54 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> + +static struct mtd_partition sead3_mtd_partitions[] = { + { + .name = "User FS", + .offset = 0x00000000, + .size = 0x01fc0000, + }, { + .name = "Board Config", + .offset = 0x01fc0000, + .size = 0x00040000, + .mask_flags = MTD_WRITEABLE + }, +}; + +static struct physmap_flash_data sead3_flash_data = { + .width = 4, + .nr_parts = ARRAY_SIZE(sead3_mtd_partitions), + .parts = sead3_mtd_partitions +}; + +static struct resource sead3_flash_resource = { + .start = 0x1c000000, + .end = 0x1dffffff, + .flags = IORESOURCE_MEM +}; + +static struct platform_device sead3_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &sead3_flash_data, + }, + .num_resources = 1, + .resource = &sead3_flash_resource, +}; + +static int __init sead3_mtd_init(void) +{ + platform_device_register(&sead3_flash); + + return 0; +} + +module_init(sead3_mtd_init) diff --git a/arch/mips/mti-sead3/sead3-net.c b/arch/mips/mti-sead3/sead3-net.c new file mode 100644 index 000000000000..04d704df6098 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-net.c @@ -0,0 +1,51 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/module.h> +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/smsc911x.h> + +static struct smsc911x_platform_config sead3_smsc911x_data = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +struct resource sead3_net_resourcess[] = { + { + .start = 0x1f010000, + .end = 0x1f01ffff, + .flags = IORESOURCE_MEM + }, + { + .start = MIPS_CPU_IRQ_BASE + 6, + .flags = IORESOURCE_IRQ + } +}; + +static struct platform_device sead3_net_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .platform_data = &sead3_smsc911x_data, + }, + .num_resources = ARRAY_SIZE(sead3_net_resourcess), + .resource = sead3_net_resourcess +}; + +static int __init sead3_net_init(void) +{ + return platform_device_register(&sead3_net_device); +} + +module_init(sead3_net_init); + +MODULE_AUTHOR("Chris Dearman <chris@mips.com>"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Network probe driver for SEAD-3"); diff --git a/arch/mips/mti-sead3/sead3-pic32-bus.c b/arch/mips/mti-sead3/sead3-pic32-bus.c new file mode 100644 index 000000000000..9f0d89bc800e --- /dev/null +++ b/arch/mips/mti-sead3/sead3-pic32-bus.c @@ -0,0 +1,103 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/delay.h> +#include <linux/kernel.h> +#include <linux/spinlock.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/errno.h> + +#define PIC32_NULL 0x00 +#define PIC32_RD 0x01 +#define PIC32_SYSRD 0x02 +#define PIC32_WR 0x10 +#define PIC32_SYSWR 0x20 +#define PIC32_IRQ_CLR 0x40 +#define PIC32_STATUS 0x80 + +#define DELAY() udelay(100) /* FIXME: needed? */ + +/* spinlock to ensure atomic access to PIC32 */ +static DEFINE_SPINLOCK(pic32_bus_lock); + +/* FIXME: io_remap these */ +static void __iomem *bus_xfer = (void __iomem *)0xbf000600; +static void __iomem *bus_status = (void __iomem *)0xbf000060; + +static inline unsigned int ioready(void) +{ + return readl(bus_status) & 1; +} + +static inline void wait_ioready(void) +{ + do { } while (!ioready()); +} + +static inline void wait_ioclear(void) +{ + do { } while (ioready()); +} + +static inline void check_ioclear(void) +{ + if (ioready()) { + pr_debug("ioclear: initially busy\n"); + do { + (void) readl(bus_xfer); + DELAY(); + } while (ioready()); + pr_debug("ioclear: cleared busy\n"); + } +} + +u32 pic32_bus_readl(u32 reg) +{ + unsigned long flags; + u32 status, val; + + spin_lock_irqsave(&pic32_bus_lock, flags); + + check_ioclear(); + + writel((PIC32_RD << 24) | (reg & 0x00ffffff), bus_xfer); + DELAY(); + wait_ioready(); + status = readl(bus_xfer); + DELAY(); + val = readl(bus_xfer); + wait_ioclear(); + + pr_debug("pic32_bus_readl: *%x -> %x (status=%x)\n", reg, val, status); + + spin_unlock_irqrestore(&pic32_bus_lock, flags); + + return val; +} + +void pic32_bus_writel(u32 val, u32 reg) +{ + unsigned long flags; + u32 status; + + spin_lock_irqsave(&pic32_bus_lock, flags); + + check_ioclear(); + + writel((PIC32_WR << 24) | (reg & 0x00ffffff), bus_xfer); + DELAY(); + writel(val, bus_xfer); + DELAY(); + wait_ioready(); + status = readl(bus_xfer); + wait_ioclear(); + + pr_debug("pic32_bus_writel: *%x <- %x (status=%x)\n", reg, val, status); + + spin_unlock_irqrestore(&pic32_bus_lock, flags); +} diff --git a/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c b/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c new file mode 100644 index 000000000000..46509b0a620d --- /dev/null +++ b/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c @@ -0,0 +1,435 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/delay.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/spinlock.h> +#include <linux/platform_device.h> +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/i2c.h> +#include <linux/slab.h> + +#define PIC32_I2CxCON 0x0000 +#define PIC32_I2CxCONCLR 0x0004 +#define PIC32_I2CxCONSET 0x0008 +#define PIC32_I2CxCONINV 0x000C +#define I2CCON_ON (1<<15) +#define I2CCON_FRZ (1<<14) +#define I2CCON_SIDL (1<<13) +#define I2CCON_SCLREL (1<<12) +#define I2CCON_STRICT (1<<11) +#define I2CCON_A10M (1<<10) +#define I2CCON_DISSLW (1<<9) +#define I2CCON_SMEN (1<<8) +#define I2CCON_GCEN (1<<7) +#define I2CCON_STREN (1<<6) +#define I2CCON_ACKDT (1<<5) +#define I2CCON_ACKEN (1<<4) +#define I2CCON_RCEN (1<<3) +#define I2CCON_PEN (1<<2) +#define I2CCON_RSEN (1<<1) +#define I2CCON_SEN (1<<0) + +#define PIC32_I2CxSTAT 0x0010 +#define PIC32_I2CxSTATCLR 0x0014 +#define PIC32_I2CxSTATSET 0x0018 +#define PIC32_I2CxSTATINV 0x001C +#define I2CSTAT_ACKSTAT (1<<15) +#define I2CSTAT_TRSTAT (1<<14) +#define I2CSTAT_BCL (1<<10) +#define I2CSTAT_GCSTAT (1<<9) +#define I2CSTAT_ADD10 (1<<8) +#define I2CSTAT_IWCOL (1<<7) +#define I2CSTAT_I2COV (1<<6) +#define I2CSTAT_DA (1<<5) +#define I2CSTAT_P (1<<4) +#define I2CSTAT_S (1<<3) +#define I2CSTAT_RW (1<<2) +#define I2CSTAT_RBF (1<<1) +#define I2CSTAT_TBF (1<<0) + +#define PIC32_I2CxADD 0x0020 +#define PIC32_I2CxADDCLR 0x0024 +#define PIC32_I2CxADDSET 0x0028 +#define PIC32_I2CxADDINV 0x002C +#define PIC32_I2CxMSK 0x0030 +#define PIC32_I2CxMSKCLR 0x0034 +#define PIC32_I2CxMSKSET 0x0038 +#define PIC32_I2CxMSKINV 0x003C +#define PIC32_I2CxBRG 0x0040 +#define PIC32_I2CxBRGCLR 0x0044 +#define PIC32_I2CxBRGSET 0x0048 +#define PIC32_I2CxBRGINV 0x004C +#define PIC32_I2CxTRN 0x0050 +#define PIC32_I2CxTRNCLR 0x0054 +#define PIC32_I2CxTRNSET 0x0058 +#define PIC32_I2CxTRNINV 0x005C +#define PIC32_I2CxRCV 0x0060 + +struct i2c_platform_data { + u32 base; + struct i2c_adapter adap; + u32 xfer_timeout; + u32 ack_timeout; + u32 ctl_timeout; +}; + +extern u32 pic32_bus_readl(u32 reg); +extern void pic32_bus_writel(u32 val, u32 reg); + +static inline void +StartI2C(struct i2c_platform_data *adap) +{ + pr_debug("StartI2C\n"); + pic32_bus_writel(I2CCON_SEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void +StopI2C(struct i2c_platform_data *adap) +{ + pr_debug("StopI2C\n"); + pic32_bus_writel(I2CCON_PEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void +AckI2C(struct i2c_platform_data *adap) +{ + pr_debug("AckI2C\n"); + pic32_bus_writel(I2CCON_ACKDT, adap->base + PIC32_I2CxCONCLR); + pic32_bus_writel(I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void +NotAckI2C(struct i2c_platform_data *adap) +{ + pr_debug("NakI2C\n"); + pic32_bus_writel(I2CCON_ACKDT, adap->base + PIC32_I2CxCONSET); + pic32_bus_writel(I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET); +} + +static inline int +IdleI2C(struct i2c_platform_data *adap) +{ + int i; + + pr_debug("IdleI2C\n"); + for (i = 0; i < adap->ctl_timeout; i++) { + if (((pic32_bus_readl(adap->base + PIC32_I2CxCON) & + (I2CCON_ACKEN | I2CCON_RCEN | I2CCON_PEN | I2CCON_RSEN | + I2CCON_SEN)) == 0) && + ((pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & + (I2CSTAT_TRSTAT)) == 0)) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static inline u32 +MasterWriteI2C(struct i2c_platform_data *adap, u32 byte) +{ + pr_debug("MasterWriteI2C\n"); + + pic32_bus_writel(byte, adap->base + PIC32_I2CxTRN); + + return pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_IWCOL; +} + +static inline u32 +MasterReadI2C(struct i2c_platform_data *adap) +{ + pr_debug("MasterReadI2C\n"); + + pic32_bus_writel(I2CCON_RCEN, adap->base + PIC32_I2CxCONSET); + + while (pic32_bus_readl(adap->base + PIC32_I2CxCON) & I2CCON_RCEN) + ; + + pic32_bus_writel(I2CSTAT_I2COV, adap->base + PIC32_I2CxSTATCLR); + + return pic32_bus_readl(adap->base + PIC32_I2CxRCV); +} + +static int +do_address(struct i2c_platform_data *adap, unsigned int addr, int rd) +{ + pr_debug("doaddress\n"); + + IdleI2C(adap); + StartI2C(adap); + IdleI2C(adap); + + addr <<= 1; + if (rd) + addr |= 1; + + if (MasterWriteI2C(adap, addr)) + return -EIO; + IdleI2C(adap); + if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_ACKSTAT) + return -EIO; + return 0; +} + +static int +i2c_read(struct i2c_platform_data *adap, unsigned char *buf, + unsigned int len) +{ + int i; + u32 data; + + pr_debug("i2c_read\n"); + + i = 0; + while (i < len) { + data = MasterReadI2C(adap); + buf[i++] = data; + if (i < len) + AckI2C(adap); + else + NotAckI2C(adap); + } + + StopI2C(adap); + IdleI2C(adap); + return 0; +} + +static int +i2c_write(struct i2c_platform_data *adap, unsigned char *buf, + unsigned int len) +{ + int i; + u32 data; + + pr_debug("i2c_write\n"); + + i = 0; + while (i < len) { + data = buf[i]; + if (MasterWriteI2C(adap, data)) + return -EIO; + IdleI2C(adap); + if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & + I2CSTAT_ACKSTAT) + return -EIO; + i++; + } + + StopI2C(adap); + IdleI2C(adap); + return 0; +} + +static int +platform_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) +{ + struct i2c_platform_data *adap = i2c_adap->algo_data; + struct i2c_msg *p; + int i, err = 0; + + pr_debug("platform_xfer\n"); + for (i = 0; i < num; i++) { +#define __BUFSIZE 80 + int ii; + static char buf[__BUFSIZE]; + char *b = buf; + + p = &msgs[i]; + b += sprintf(buf, " [%d bytes]", p->len); + if ((p->flags & I2C_M_RD) == 0) { + for (ii = 0; ii < p->len; ii++) { + if (b < &buf[__BUFSIZE-4]) { + b += sprintf(b, " %02x", p->buf[ii]); + } else { + strcat(b, "..."); + break; + } + } + } + pr_debug("xfer%d: DevAddr: %04x Op:%s Data:%s\n", i, p->addr, + (p->flags & I2C_M_RD) ? "Rd" : "Wr", buf); + } + + + for (i = 0; !err && i < num; i++) { + p = &msgs[i]; + err = do_address(adap, p->addr, p->flags & I2C_M_RD); + if (err || !p->len) + continue; + if (p->flags & I2C_M_RD) + err = i2c_read(adap, p->buf, p->len); + else + err = i2c_write(adap, p->buf, p->len); + } + + /* Return the number of messages processed, or the error code. */ + if (err == 0) + err = num; + + return err; +} + +static u32 +platform_func(struct i2c_adapter *adap) +{ + pr_debug("platform_algo\n"); + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm platform_algo = { + .master_xfer = platform_xfer, + .functionality = platform_func, +}; + +static void i2c_platform_setup(struct i2c_platform_data *priv) +{ + pr_debug("i2c_platform_setup\n"); + + pic32_bus_writel(500, priv->base + PIC32_I2CxBRG); + pic32_bus_writel(I2CCON_ON, priv->base + PIC32_I2CxCONCLR); + pic32_bus_writel(I2CCON_ON, priv->base + PIC32_I2CxCONSET); + pic32_bus_writel((I2CSTAT_BCL | I2CSTAT_IWCOL), + (priv->base + PIC32_I2CxSTATCLR)); +} + +static void i2c_platform_disable(struct i2c_platform_data *priv) +{ + pr_debug("i2c_platform_disable\n"); +} + +static int __devinit +i2c_platform_probe(struct platform_device *pdev) +{ + struct i2c_platform_data *priv; + struct resource *r; + int ret; + + pr_debug("i2c_platform_probe\n"); + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + ret = -ENODEV; + goto out; + } + + priv = kzalloc(sizeof(struct i2c_platform_data), GFP_KERNEL); + if (!priv) { + ret = -ENOMEM; + goto out; + } + + /* FIXME: need to allocate resource in PIC32 space */ +#if 0 + priv->base = bus_request_region(r->start, resource_size(r), + pdev->name); +#else + priv->base = r->start; +#endif + if (!priv->base) { + ret = -EBUSY; + goto out_mem; + } + + priv->xfer_timeout = 200; + priv->ack_timeout = 200; + priv->ctl_timeout = 200; + + priv->adap.nr = pdev->id; + priv->adap.algo = &platform_algo; + priv->adap.algo_data = priv; + priv->adap.dev.parent = &pdev->dev; + strlcpy(priv->adap.name, "PIC32 I2C", sizeof(priv->adap.name)); + + i2c_platform_setup(priv); + + ret = i2c_add_numbered_adapter(&priv->adap); + if (ret == 0) { + platform_set_drvdata(pdev, priv); + return 0; + } + + i2c_platform_disable(priv); + +out_mem: + kfree(priv); +out: + return ret; +} + +static int __devexit +i2c_platform_remove(struct platform_device *pdev) +{ + struct i2c_platform_data *priv = platform_get_drvdata(pdev); + + pr_debug("i2c_platform_remove\n"); + platform_set_drvdata(pdev, NULL); + i2c_del_adapter(&priv->adap); + i2c_platform_disable(priv); + kfree(priv); + return 0; +} + +#ifdef CONFIG_PM +static int +i2c_platform_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct i2c_platform_data *priv = platform_get_drvdata(pdev); + + dev_dbg(&pdev->dev, "i2c_platform_disable\n"); + i2c_platform_disable(priv); + + return 0; +} + +static int +i2c_platform_resume(struct platform_device *pdev) +{ + struct i2c_platform_data *priv = platform_get_drvdata(pdev); + + dev_dbg(&pdev->dev, "i2c_platform_setup\n"); + i2c_platform_setup(priv); + + return 0; +} +#else +#define i2c_platform_suspend NULL +#define i2c_platform_resume NULL +#endif + +static struct platform_driver i2c_platform_driver = { + .driver = { + .name = "i2c_pic32", + .owner = THIS_MODULE, + }, + .probe = i2c_platform_probe, + .remove = __devexit_p(i2c_platform_remove), + .suspend = i2c_platform_suspend, + .resume = i2c_platform_resume, +}; + +static int __init +i2c_platform_init(void) +{ + pr_debug("i2c_platform_init\n"); + return platform_driver_register(&i2c_platform_driver); +} + +static void __exit +i2c_platform_exit(void) +{ + pr_debug("i2c_platform_exit\n"); + platform_driver_unregister(&i2c_platform_driver); +} + +MODULE_AUTHOR("Chris Dearman, MIPS Technologies INC."); +MODULE_DESCRIPTION("PIC32 I2C driver"); +MODULE_LICENSE("GPL"); + +module_init(i2c_platform_init); +module_exit(i2c_platform_exit); diff --git a/arch/mips/mti-sead3/sead3-platform.c b/arch/mips/mti-sead3/sead3-platform.c new file mode 100644 index 000000000000..6c3b33dbed18 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-platform.c @@ -0,0 +1,45 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/module.h> +#include <linux/init.h> +#include <linux/serial_8250.h> + +#define UART(base, int) \ +{ \ + .mapbase = base, \ + .irq = int, \ + .uartclk = 14745600, \ + .iotype = UPIO_MEM32, \ + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, \ + .regshift = 2, \ +} + +static struct plat_serial8250_port uart8250_data[] = { + UART(0x1f000900, MIPS_CPU_IRQ_BASE + 4), /* ttyS0 = USB */ + UART(0x1f000800, MIPS_CPU_IRQ_BASE + 4), /* ttyS1 = RS232 */ + { }, +}; + +static struct platform_device uart8250_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = uart8250_data, + }, +}; + +static int __init uart8250_init(void) +{ + return platform_device_register(&uart8250_device); +} + +module_init(uart8250_init); + +MODULE_AUTHOR("Chris Dearman <chris@mips.com>"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("8250 UART probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-reset.c b/arch/mips/mti-sead3/sead3-reset.c new file mode 100644 index 000000000000..20475c5e7b9c --- /dev/null +++ b/arch/mips/mti-sead3/sead3-reset.c @@ -0,0 +1,39 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/io.h> +#include <linux/pm.h> + +#include <asm/reboot.h> +#include <asm/mips-boards/generic.h> + +static void mips_machine_restart(char *command) +{ + unsigned int __iomem *softres_reg = + ioremap(SOFTRES_REG, sizeof(unsigned int)); + + __raw_writel(GORESET, softres_reg); +} + +static void mips_machine_halt(void) +{ + unsigned int __iomem *softres_reg = + ioremap(SOFTRES_REG, sizeof(unsigned int)); + + __raw_writel(GORESET, softres_reg); +} + +static int __init mips_reboot_setup(void) +{ + _machine_restart = mips_machine_restart; + _machine_halt = mips_machine_halt; + pm_power_off = mips_machine_halt; + + return 0; +} + +arch_initcall(mips_reboot_setup); diff --git a/arch/mips/mti-sead3/sead3-serial.c b/arch/mips/mti-sead3/sead3-serial.c new file mode 100644 index 000000000000..bc52705bbee4 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-serial.c @@ -0,0 +1,45 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/module.h> +#include <linux/init.h> +#include <linux/serial_8250.h> + +#define UART(base, int) \ +{ \ + .mapbase = base, \ + .irq = int, \ + .uartclk = 14745600, \ + .iotype = UPIO_MEM32, \ + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, \ + .regshift = 2, \ +} + +static struct plat_serial8250_port uart8250_data[] = { + UART(0x1f000900, MIPS_CPU_IRQ_BASE + 4), /* ttyS0 = USB */ + UART(0x1f000800, MIPS_CPU_IRQ_BASE + 4), /* ttyS1 = RS232 */ + { }, +}; + +static struct platform_device uart8250_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = uart8250_data, + }, +}; + +static int __init uart8250_init(void) +{ + return platform_device_register(&uart8250_device); +} + +module_init(uart8250_init); + +MODULE_AUTHOR("Chris Dearman <chris@mips.com>"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("8250 UART probe driver for the SEAD-3 platform"); diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c new file mode 100644 index 000000000000..8ad46ad31b49 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-setup.c @@ -0,0 +1,20 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/init.h> + +int coherentio; /* 0 => no DMA cache coherency (may be set by user) */ +int hw_coherentio; /* 0 => no HW DMA cache coherency (reflects real HW) */ + +const char *get_system_type(void) +{ + return "MIPS SEAD3"; +} + +void __init plat_mem_setup(void) +{ +} diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c new file mode 100644 index 000000000000..048e781a17a0 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-time.c @@ -0,0 +1,117 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include <linux/init.h> + +#include <asm/setup.h> +#include <asm/time.h> +#include <asm/irq.h> +#include <asm/mips-boards/generic.h> +#include <asm/mips-boards/prom.h> + +unsigned long cpu_khz; + +static int mips_cpu_timer_irq; +static int mips_cpu_perf_irq; + +static void mips_timer_dispatch(void) +{ + do_IRQ(mips_cpu_timer_irq); +} + +static void mips_perf_dispatch(void) +{ + do_IRQ(mips_cpu_perf_irq); +} + +static void __iomem *status_reg = (void __iomem *)0xbf000410; + +/* + * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect. + */ +static unsigned int __init estimate_cpu_frequency(void) +{ + unsigned int prid = read_c0_prid() & 0xffff00; + unsigned int tick = 0; + unsigned int freq; + unsigned int orig; + unsigned long flags; + + local_irq_save(flags); + + orig = readl(status_reg) & 0x2; /* get original sample */ + /* wait for transition */ + while ((readl(status_reg) & 0x2) == orig) + ; + orig = orig ^ 0x2; /* flip the bit */ + + write_c0_count(0); + + /* wait 1 second (the sampling clock transitions every 10ms) */ + while (tick < 100) { + /* wait for transition */ + while ((readl(status_reg) & 0x2) == orig) + ; + orig = orig ^ 0x2; /* flip the bit */ + tick++; + } + + freq = read_c0_count(); + + local_irq_restore(flags); + + mips_hpt_frequency = freq; + + /* Adjust for processor */ + if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && + (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) + freq *= 2; + + freq += 5000; /* rounding */ + freq -= freq%10000; + + return freq ; +} + +void read_persistent_clock(struct timespec *ts) +{ + ts->tv_sec = 0; + ts->tv_nsec = 0; +} + +static void __init plat_perf_setup(void) +{ + if (cp0_perfcount_irq >= 0) { + if (cpu_has_vint) + set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); + mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; + } +} + +unsigned int __cpuinit get_c0_compare_int(void) +{ + if (cpu_has_vint) + set_vi_handler(cp0_compare_irq, mips_timer_dispatch); + mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; + return mips_cpu_timer_irq; +} + +void __init plat_time_init(void) +{ + unsigned int est_freq; + + est_freq = estimate_cpu_frequency(); + + pr_debug("CPU frequency %d.%02d MHz\n", (est_freq / 1000000), + (est_freq % 1000000) * 100 / 1000000); + + cpu_khz = est_freq / 1000; + + mips_scroll_message(); + + plat_perf_setup(); +} diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig index 75bec44b5856..8059eb76f8eb 100644 --- a/arch/mips/netlogic/Kconfig +++ b/arch/mips/netlogic/Kconfig @@ -1,2 +1,17 @@ +if NLM_XLP_BOARD || NLM_XLR_BOARD + +if NLM_XLP_BOARD +config DT_XLP_EVP + bool "Built-in device tree for XLP EVP/SVP boards" + default y + help + Add an FDT blob for XLP EVP and SVP boards into the kernel. + This DTB will be used if the firmware does not pass in a DTB + pointer to the kernel. The corresponding DTS file is at + arch/mips/netlogic/dts/xlp_evp.dts +endif + config NLM_COMMON bool + +endif diff --git a/arch/mips/netlogic/Makefile b/arch/mips/netlogic/Makefile index 36d169b2ca6d..7602d1386614 100644 --- a/arch/mips/netlogic/Makefile +++ b/arch/mips/netlogic/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_NLM_COMMON) += common/ obj-$(CONFIG_CPU_XLR) += xlr/ obj-$(CONFIG_CPU_XLP) += xlp/ +obj-$(CONFIG_CPU_XLP) += dts/ diff --git a/arch/mips/netlogic/dts/Makefile b/arch/mips/netlogic/dts/Makefile new file mode 100644 index 000000000000..67ae3fe296f0 --- /dev/null +++ b/arch/mips/netlogic/dts/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o + +$(obj)/%.dtb: $(obj)/%.dts + $(call if_changed,dtc) diff --git a/arch/mips/netlogic/dts/xlp_evp.dts b/arch/mips/netlogic/dts/xlp_evp.dts new file mode 100644 index 000000000000..e14f42308064 --- /dev/null +++ b/arch/mips/netlogic/dts/xlp_evp.dts @@ -0,0 +1,124 @@ +/* + * XLP8XX Device Tree Source for EVP boards + */ + +/dts-v1/; +/ { + model = "netlogic,XLP-EVP"; + compatible = "netlogic,xlp"; + #address-cells = <2>; + #size-cells = <2>; + + memory { + device_type = "memory"; + reg = <0 0x00100000 0 0x0FF00000 // 255M at 1M + 0 0x20000000 0 0xa0000000 // 2560M at 512M + 0 0xe0000000 1 0x00000000>; + }; + + soc { + #address-cells = <2>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG + 1 0 0 0x16000000 0x01000000>; // GBU chipselects + + serial0: serial@30000 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0 0x30100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <133333333>; + interrupt-parent = <&pic>; + interrupts = <17>; + }; + serial1: serial@31000 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0 0x31100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <133333333>; + interrupt-parent = <&pic>; + interrupts = <18>; + }; + i2c0: ocores@32000 { + compatible = "opencores,i2c-ocores"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x32100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <32000000>; + interrupt-parent = <&pic>; + interrupts = <30>; + }; + i2c1: ocores@33000 { + compatible = "opencores,i2c-ocores"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x33100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <32000000>; + interrupt-parent = <&pic>; + interrupts = <31>; + + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; + + dtt@4c { + compatible = "national,lm90"; + reg = <0x4c>; + }; + }; + pic: pic@4000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0 0x4000 0x200>; + }; + + nor_flash@1,0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + reg = <1 0 0x1000000>; + + partition@0 { + label = "x-loader"; + reg = <0x0 0x100000>; /* 1M */ + read-only; + }; + + partition@100000 { + label = "u-boot"; + reg = <0x100000 0x100000>; /* 1M */ + }; + + partition@200000 { + label = "kernel"; + reg = <0x200000 0x500000>; /* 5M */ + }; + + partition@700000 { + label = "rootfs"; + reg = <0x700000 0x800000>; /* 8M */ + }; + + partition@f00000 { + label = "env"; + reg = <0xf00000 0x100000>; /* 1M */ + read-only; + }; + }; + }; + + chosen { + bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; + }; +}; diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile index 6b4b972218f0..a84d6ed3746c 100644 --- a/arch/mips/netlogic/xlp/Makefile +++ b/arch/mips/netlogic/xlp/Makefile @@ -1,4 +1,3 @@ -obj-y += setup.o platform.o nlm_hal.o -obj-$(CONFIG_OF) += of.o +obj-y += setup.o nlm_hal.o obj-$(CONFIG_SMP) += wakeup.o obj-$(CONFIG_USB) += usb-init.o diff --git a/arch/mips/netlogic/xlp/of.c b/arch/mips/netlogic/xlp/of.c deleted file mode 100644 index 8e3921c0c201..000000000000 --- a/arch/mips/netlogic/xlp/of.c +++ /dev/null @@ -1,34 +0,0 @@ -#include <linux/bootmem.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/of_fdt.h> -#include <asm/byteorder.h> - -static int __init reserve_mem_mach(unsigned long addr, unsigned long size) -{ - return reserve_bootmem(addr, size, BOOTMEM_DEFAULT); -} - -void __init free_mem_mach(unsigned long addr, unsigned long size) -{ - return free_bootmem(addr, size); -} - -void __init device_tree_init(void) -{ - unsigned long base, size; - - if (!initial_boot_params) - return; - - base = virt_to_phys((void *)initial_boot_params); - size = be32_to_cpu(initial_boot_params->totalsize); - - /* Before we do anything, lets reserve the dt blob */ - reserve_mem_mach(base, size); - - unflatten_device_tree(); - - /* free the space reserved for the dt blob */ - free_mem_mach(base, size); -} diff --git a/arch/mips/netlogic/xlp/platform.c b/arch/mips/netlogic/xlp/platform.c deleted file mode 100644 index 2c510d585447..000000000000 --- a/arch/mips/netlogic/xlp/platform.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/dma-mapping.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/serial.h> -#include <linux/serial_8250.h> -#include <linux/pci.h> -#include <linux/serial_reg.h> -#include <linux/spinlock.h> - -#include <asm/time.h> -#include <asm/addrspace.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/pic.h> -#include <asm/netlogic/xlp-hal/uart.h> - -static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset) -{ - return nlm_read_reg(p->iobase, offset); -} - -static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value) -{ - nlm_write_reg(p->iobase, offset, value); -} - -#define PORT(_irq) \ - { \ - .irq = _irq, \ - .regshift = 2, \ - .iotype = UPIO_MEM32, \ - .flags = (UPF_SKIP_TEST|UPF_FIXED_TYPE|\ - UPF_BOOT_AUTOCONF), \ - .uartclk = XLP_IO_CLK, \ - .type = PORT_16550A, \ - .serial_in = nlm_xlp_uart_in, \ - .serial_out = nlm_xlp_uart_out, \ - } - -static struct plat_serial8250_port xlp_uart_data[] = { - PORT(PIC_UART_0_IRQ), - PORT(PIC_UART_1_IRQ), - {}, -}; - -static struct platform_device uart_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = xlp_uart_data, - }, -}; - -static int __init nlm_platform_uart_init(void) -{ - unsigned long mmio; - - mmio = (unsigned long)nlm_get_uart_regbase(0, 0); - xlp_uart_data[0].iobase = mmio; - xlp_uart_data[0].membase = (void __iomem *)mmio; - xlp_uart_data[0].mapbase = mmio; - - mmio = (unsigned long)nlm_get_uart_regbase(0, 1); - xlp_uart_data[1].iobase = mmio; - xlp_uart_data[1].membase = (void __iomem *)mmio; - xlp_uart_data[1].mapbase = mmio; - - return platform_device_register(&uart_device); -} - -arch_initcall(nlm_platform_uart_init); diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c index 3dec9f28b65b..d8997098defd 100644 --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c @@ -35,6 +35,7 @@ #include <linux/kernel.h> #include <linux/serial_8250.h> #include <linux/pm.h> +#include <linux/bootmem.h> #include <asm/reboot.h> #include <asm/time.h> @@ -56,6 +57,7 @@ unsigned long nlm_common_ebase = 0x0; /* default to uniprocessor */ uint32_t nlm_coremask = 1, nlm_cpumask = 1; int nlm_threads_per_core = 1; +extern u32 __dtb_start[]; static void nlm_linux_exit(void) { @@ -96,9 +98,18 @@ void __init prom_init(void) { void *fdtp; - fdtp = (void *)(long)fw_arg0; xlp_mmu_init(); nlm_hal_init(); + + /* + * If no FDT pointer is passed in, use the built-in FDT. + * device_tree_init() does not handle CKSEG0 pointers in + * 64-bit, so convert pointer. + */ + fdtp = (void *)(long)fw_arg0; + if (!fdtp) + fdtp = __dtb_start; + fdtp = phys_to_virt(__pa(fdtp)); early_init_devtree(fdtp); nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); @@ -112,6 +123,25 @@ void __init prom_init(void) #endif } +void __init device_tree_init(void) +{ + unsigned long base, size; + + if (!initial_boot_params) + return; + + base = virt_to_phys((void *)initial_boot_params); + size = be32_to_cpu(initial_boot_params->totalsize); + + /* Before we do anything, lets reserve the dt blob */ + reserve_bootmem(base, size, BOOTMEM_DEFAULT); + + unflatten_device_tree(); + + /* free the space reserved for the dt blob */ + free_bootmem(base, size); +} + static struct of_device_id __initdata xlp_ids[] = { { .compatible = "simple-bus", }, {}, diff --git a/drivers/gpio/gpio-stp-xway.c b/drivers/gpio/gpio-stp-xway.c index e35096bf3cfb..8bead0bb6459 100644 --- a/drivers/gpio/gpio-stp-xway.c +++ b/drivers/gpio/gpio-stp-xway.c @@ -82,7 +82,7 @@ struct xway_stp { struct gpio_chip gc; void __iomem *virt; u32 edge; /* rising or falling edge triggered shift register */ - u16 shadow; /* shadow the shift registers state */ + u32 shadow; /* shadow the shift registers state */ u8 groups; /* we can drive 1-3 groups of 8bit each */ u8 dsl; /* the 2 LSBs can be driven by the dsl core */ u8 phy1; /* 3 bits can be driven by phy1 */ diff --git a/drivers/net/ethernet/broadcom/bcm63xx_enet.h b/drivers/net/ethernet/broadcom/bcm63xx_enet.h index 0e3048b788c2..133d5857b9e2 100644 --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h @@ -10,6 +10,7 @@ #include <bcm63xx_regs.h> #include <bcm63xx_irq.h> #include <bcm63xx_io.h> +#include <bcm63xx_iudma.h> /* default number of descriptor */ #define BCMENET_DEF_RX_DESC 64 @@ -31,35 +32,6 @@ #define BCMENET_MAX_MTU 2046 /* - * rx/tx dma descriptor - */ -struct bcm_enet_desc { - u32 len_stat; - u32 address; -}; - -#define DMADESC_LENGTH_SHIFT 16 -#define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT) -#define DMADESC_OWNER_MASK (1 << 15) -#define DMADESC_EOP_MASK (1 << 14) -#define DMADESC_SOP_MASK (1 << 13) -#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK) -#define DMADESC_WRAP_MASK (1 << 12) - -#define DMADESC_UNDER_MASK (1 << 9) -#define DMADESC_APPEND_CRC (1 << 8) -#define DMADESC_OVSIZE_MASK (1 << 4) -#define DMADESC_RXER_MASK (1 << 2) -#define DMADESC_CRC_MASK (1 << 1) -#define DMADESC_OV_MASK (1 << 0) -#define DMADESC_ERR_MASK (DMADESC_UNDER_MASK | \ - DMADESC_OVSIZE_MASK | \ - DMADESC_RXER_MASK | \ - DMADESC_CRC_MASK | \ - DMADESC_OV_MASK) - - -/* * MIB Counters register definitions */ #define ETH_MIB_TX_GD_OCTETS 0 diff --git a/drivers/net/ethernet/octeon/octeon_mgmt.c b/drivers/net/ethernet/octeon/octeon_mgmt.c index a688a2ddcfd6..f97719c48516 100644 --- a/drivers/net/ethernet/octeon/octeon_mgmt.c +++ b/drivers/net/ethernet/octeon/octeon_mgmt.c @@ -3,13 +3,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2009 Cavium Networks + * Copyright (C) 2009-2012 Cavium, Inc */ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/etherdevice.h> #include <linux/capability.h> +#include <linux/net_tstamp.h> #include <linux/interrupt.h> #include <linux/netdevice.h> #include <linux/spinlock.h> @@ -33,8 +34,7 @@ #define OCTEON_MGMT_NAPI_WEIGHT 16 -/* - * Ring sizes that are powers of two allow for more efficient modulo +/* Ring sizes that are powers of two allow for more efficient modulo * opertions. */ #define OCTEON_MGMT_RX_RING_SIZE 512 @@ -93,6 +93,7 @@ union mgmt_port_ring_entry { #define AGL_GMX_RX_ADR_CAM4 0x1a0 #define AGL_GMX_RX_ADR_CAM5 0x1a8 +#define AGL_GMX_TX_CLK 0x208 #define AGL_GMX_TX_STATS_CTL 0x268 #define AGL_GMX_TX_CTL 0x270 #define AGL_GMX_TX_STAT0 0x280 @@ -110,8 +111,10 @@ struct octeon_mgmt { struct net_device *netdev; u64 mix; u64 agl; + u64 agl_prt_ctl; int port; int irq; + bool has_rx_tstamp; u64 *tx_ring; dma_addr_t tx_ring_handle; unsigned int tx_next; @@ -131,6 +134,7 @@ struct octeon_mgmt { spinlock_t lock; unsigned int last_duplex; unsigned int last_link; + unsigned int last_speed; struct device *dev; struct napi_struct napi; struct tasklet_struct tx_clean_tasklet; @@ -140,6 +144,8 @@ struct octeon_mgmt { resource_size_t mix_size; resource_size_t agl_phys; resource_size_t agl_size; + resource_size_t agl_prt_ctl_phys; + resource_size_t agl_prt_ctl_size; }; static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable) @@ -166,22 +172,22 @@ static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable) spin_unlock_irqrestore(&p->lock, flags); } -static inline void octeon_mgmt_enable_rx_irq(struct octeon_mgmt *p) +static void octeon_mgmt_enable_rx_irq(struct octeon_mgmt *p) { octeon_mgmt_set_rx_irq(p, 1); } -static inline void octeon_mgmt_disable_rx_irq(struct octeon_mgmt *p) +static void octeon_mgmt_disable_rx_irq(struct octeon_mgmt *p) { octeon_mgmt_set_rx_irq(p, 0); } -static inline void octeon_mgmt_enable_tx_irq(struct octeon_mgmt *p) +static void octeon_mgmt_enable_tx_irq(struct octeon_mgmt *p) { octeon_mgmt_set_tx_irq(p, 1); } -static inline void octeon_mgmt_disable_tx_irq(struct octeon_mgmt *p) +static void octeon_mgmt_disable_tx_irq(struct octeon_mgmt *p) { octeon_mgmt_set_tx_irq(p, 0); } @@ -233,6 +239,28 @@ static void octeon_mgmt_rx_fill_ring(struct net_device *netdev) } } +static ktime_t ptp_to_ktime(u64 ptptime) +{ + ktime_t ktimebase; + u64 ptpbase; + unsigned long flags; + + local_irq_save(flags); + /* Fill the icache with the code */ + ktime_get_real(); + /* Flush all pending operations */ + mb(); + /* Read the time and PTP clock as close together as + * possible. It is important that this sequence take the same + * amount of time to reduce jitter + */ + ktimebase = ktime_get_real(); + ptpbase = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_HI); + local_irq_restore(flags); + + return ktime_sub_ns(ktimebase, ptpbase - ptptime); +} + static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) { union cvmx_mixx_orcnt mix_orcnt; @@ -272,6 +300,20 @@ static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) dma_unmap_single(p->dev, re.s.addr, re.s.len, DMA_TO_DEVICE); + + /* Read the hardware TX timestamp if one was recorded */ + if (unlikely(re.s.tstamp)) { + struct skb_shared_hwtstamps ts; + /* Read the timestamp */ + u64 ns = cvmx_read_csr(CVMX_MIXX_TSTAMP(p->port)); + /* Remove the timestamp from the FIFO */ + cvmx_write_csr(CVMX_MIXX_TSCTL(p->port), 0); + /* Tell the kernel about the timestamp */ + ts.syststamp = ptp_to_ktime(ns); + ts.hwtstamp = ns_to_ktime(ns); + skb_tstamp_tx(skb, &ts); + } + dev_kfree_skb_any(skb); cleaned++; @@ -372,14 +414,23 @@ static int octeon_mgmt_receive_one(struct octeon_mgmt *p) /* A good packet, send it up. */ skb_put(skb, re.s.len); good: + /* Process the RX timestamp if it was recorded */ + if (p->has_rx_tstamp) { + /* The first 8 bytes are the timestamp */ + u64 ns = *(u64 *)skb->data; + struct skb_shared_hwtstamps *ts; + ts = skb_hwtstamps(skb); + ts->hwtstamp = ns_to_ktime(ns); + ts->syststamp = ptp_to_ktime(ns); + __skb_pull(skb, 8); + } skb->protocol = eth_type_trans(skb, netdev); netdev->stats.rx_packets++; netdev->stats.rx_bytes += skb->len; netif_receive_skb(skb); rc = 0; } else if (re.s.code == RING_ENTRY_CODE_MORE) { - /* - * Packet split across skbs. This can happen if we + /* Packet split across skbs. This can happen if we * increase the MTU. Buffers that are already in the * rx ring can then end up being too small. As the rx * ring is refilled, buffers sized for the new MTU @@ -409,8 +460,7 @@ good: } else { /* Some other error, discard it. */ dev_kfree_skb_any(skb); - /* - * Error statistics are accumulated in + /* Error statistics are accumulated in * octeon_mgmt_update_rx_stats. */ } @@ -488,7 +538,7 @@ static void octeon_mgmt_reset_hw(struct octeon_mgmt *p) mix_ctl.s.reset = 1; cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); cvmx_read_csr(p->mix + MIX_CTL); - cvmx_wait(64); + octeon_io_clk_delay(64); mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST); if (mix_bist.u64) @@ -537,8 +587,7 @@ static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) cam_mode = 0; available_cam_entries = 8; } else { - /* - * One CAM entry for the primary address, leaves seven + /* One CAM entry for the primary address, leaves seven * for the secondary addresses. */ available_cam_entries = 7 - netdev->uc.count; @@ -595,12 +644,10 @@ static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr) { - struct sockaddr *sa = addr; + int r = eth_mac_addr(netdev, addr); - if (!is_valid_ether_addr(sa->sa_data)) - return -EADDRNOTAVAIL; - - memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN); + if (r) + return r; octeon_mgmt_set_rx_filtering(netdev); @@ -612,8 +659,7 @@ static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu) struct octeon_mgmt *p = netdev_priv(netdev); int size_without_fcs = new_mtu + OCTEON_MGMT_RX_HEADROOM; - /* - * Limit the MTU to make sure the ethernet packets are between + /* Limit the MTU to make sure the ethernet packets are between * 64 bytes and 16383 bytes. */ if (size_without_fcs < 64 || size_without_fcs > 16383) { @@ -656,53 +702,258 @@ static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id) return IRQ_HANDLED; } +static int octeon_mgmt_ioctl_hwtstamp(struct net_device *netdev, + struct ifreq *rq, int cmd) +{ + struct octeon_mgmt *p = netdev_priv(netdev); + struct hwtstamp_config config; + union cvmx_mio_ptp_clock_cfg ptp; + union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl; + bool have_hw_timestamps = false; + + if (copy_from_user(&config, rq->ifr_data, sizeof(config))) + return -EFAULT; + + if (config.flags) /* reserved for future extensions */ + return -EINVAL; + + /* Check the status of hardware for tiemstamps */ + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + /* Get the current state of the PTP clock */ + ptp.u64 = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_CFG); + if (!ptp.s.ext_clk_en) { + /* The clock has not been configured to use an + * external source. Program it to use the main clock + * reference. + */ + u64 clock_comp = (NSEC_PER_SEC << 32) / octeon_get_io_clock_rate(); + if (!ptp.s.ptp_en) + cvmx_write_csr(CVMX_MIO_PTP_CLOCK_COMP, clock_comp); + pr_info("PTP Clock: Using sclk reference at %lld Hz\n", + (NSEC_PER_SEC << 32) / clock_comp); + } else { + /* The clock is already programmed to use a GPIO */ + u64 clock_comp = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_COMP); + pr_info("PTP Clock: Using GPIO %d at %lld Hz\n", + ptp.s.ext_clk_in, + (NSEC_PER_SEC << 32) / clock_comp); + } + + /* Enable the clock if it wasn't done already */ + if (!ptp.s.ptp_en) { + ptp.s.ptp_en = 1; + cvmx_write_csr(CVMX_MIO_PTP_CLOCK_CFG, ptp.u64); + } + have_hw_timestamps = true; + } + + if (!have_hw_timestamps) + return -EINVAL; + + switch (config.tx_type) { + case HWTSTAMP_TX_OFF: + case HWTSTAMP_TX_ON: + break; + default: + return -ERANGE; + } + + switch (config.rx_filter) { + case HWTSTAMP_FILTER_NONE: + p->has_rx_tstamp = false; + rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL); + rxx_frm_ctl.s.ptp_mode = 0; + cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); + break; + case HWTSTAMP_FILTER_ALL: + case HWTSTAMP_FILTER_SOME: + case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: + case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: + case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: + case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: + case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: + case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: + case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: + case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: + case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: + case HWTSTAMP_FILTER_PTP_V2_EVENT: + case HWTSTAMP_FILTER_PTP_V2_SYNC: + case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: + p->has_rx_tstamp = have_hw_timestamps; + config.rx_filter = HWTSTAMP_FILTER_ALL; + if (p->has_rx_tstamp) { + rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL); + rxx_frm_ctl.s.ptp_mode = 1; + cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); + } + break; + default: + return -ERANGE; + } + + if (copy_to_user(rq->ifr_data, &config, sizeof(config))) + return -EFAULT; + + return 0; +} + static int octeon_mgmt_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) { struct octeon_mgmt *p = netdev_priv(netdev); - if (!netif_running(netdev)) + switch (cmd) { + case SIOCSHWTSTAMP: + return octeon_mgmt_ioctl_hwtstamp(netdev, rq, cmd); + default: + if (p->phydev) + return phy_mii_ioctl(p->phydev, rq, cmd); return -EINVAL; + } +} - if (!p->phydev) - return -EINVAL; +static void octeon_mgmt_disable_link(struct octeon_mgmt *p) +{ + union cvmx_agl_gmx_prtx_cfg prtx_cfg; - return phy_mii_ioctl(p->phydev, rq, cmd); + /* Disable GMX before we make any changes. */ + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); + prtx_cfg.s.en = 0; + prtx_cfg.s.tx_en = 0; + prtx_cfg.s.rx_en = 0; + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); + + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + int i; + for (i = 0; i < 10; i++) { + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); + if (prtx_cfg.s.tx_idle == 1 || prtx_cfg.s.rx_idle == 1) + break; + mdelay(1); + i++; + } + } +} + +static void octeon_mgmt_enable_link(struct octeon_mgmt *p) +{ + union cvmx_agl_gmx_prtx_cfg prtx_cfg; + + /* Restore the GMX enable state only if link is set */ + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); + prtx_cfg.s.tx_en = 1; + prtx_cfg.s.rx_en = 1; + prtx_cfg.s.en = 1; + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); +} + +static void octeon_mgmt_update_link(struct octeon_mgmt *p) +{ + union cvmx_agl_gmx_prtx_cfg prtx_cfg; + + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); + + if (!p->phydev->link) + prtx_cfg.s.duplex = 1; + else + prtx_cfg.s.duplex = p->phydev->duplex; + + switch (p->phydev->speed) { + case 10: + prtx_cfg.s.speed = 0; + prtx_cfg.s.slottime = 0; + + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + prtx_cfg.s.burst = 1; + prtx_cfg.s.speed_msb = 1; + } + break; + case 100: + prtx_cfg.s.speed = 0; + prtx_cfg.s.slottime = 0; + + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + prtx_cfg.s.burst = 1; + prtx_cfg.s.speed_msb = 0; + } + break; + case 1000: + /* 1000 MBits is only supported on 6XXX chips */ + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + prtx_cfg.s.speed = 1; + prtx_cfg.s.speed_msb = 0; + /* Only matters for half-duplex */ + prtx_cfg.s.slottime = 1; + prtx_cfg.s.burst = p->phydev->duplex; + } + break; + case 0: /* No link */ + default: + break; + } + + /* Write the new GMX setting with the port still disabled. */ + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); + + /* Read GMX CFG again to make sure the config is completed. */ + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); + + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + union cvmx_agl_gmx_txx_clk agl_clk; + union cvmx_agl_prtx_ctl prtx_ctl; + + prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); + agl_clk.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_CLK); + /* MII (both speeds) and RGMII 1000 speed. */ + agl_clk.s.clk_cnt = 1; + if (prtx_ctl.s.mode == 0) { /* RGMII mode */ + if (p->phydev->speed == 10) + agl_clk.s.clk_cnt = 50; + else if (p->phydev->speed == 100) + agl_clk.s.clk_cnt = 5; + } + cvmx_write_csr(p->agl + AGL_GMX_TX_CLK, agl_clk.u64); + } } static void octeon_mgmt_adjust_link(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - union cvmx_agl_gmx_prtx_cfg prtx_cfg; unsigned long flags; int link_changed = 0; + if (!p->phydev) + return; + spin_lock_irqsave(&p->lock, flags); - if (p->phydev->link) { - if (!p->last_link) - link_changed = 1; - if (p->last_duplex != p->phydev->duplex) { - p->last_duplex = p->phydev->duplex; - prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); - prtx_cfg.s.duplex = p->phydev->duplex; - cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); - } - } else { - if (p->last_link) - link_changed = -1; + + + if (!p->phydev->link && p->last_link) + link_changed = -1; + + if (p->phydev->link + && (p->last_duplex != p->phydev->duplex + || p->last_link != p->phydev->link + || p->last_speed != p->phydev->speed)) { + octeon_mgmt_disable_link(p); + link_changed = 1; + octeon_mgmt_update_link(p); + octeon_mgmt_enable_link(p); } + p->last_link = p->phydev->link; + p->last_speed = p->phydev->speed; + p->last_duplex = p->phydev->duplex; + spin_unlock_irqrestore(&p->lock, flags); if (link_changed != 0) { if (link_changed > 0) { - netif_carrier_on(netdev); pr_info("%s: Link is up - %d/%s\n", netdev->name, p->phydev->speed, DUPLEX_FULL == p->phydev->duplex ? "Full" : "Half"); } else { - netif_carrier_off(netdev); pr_info("%s: Link is down\n", netdev->name); } } @@ -723,9 +974,7 @@ static int octeon_mgmt_init_phy(struct net_device *netdev) PHY_INTERFACE_MODE_MII); if (!p->phydev) - return -1; - - phy_start_aneg(p->phydev); + return -ENODEV; return 0; } @@ -733,12 +982,10 @@ static int octeon_mgmt_init_phy(struct net_device *netdev) static int octeon_mgmt_open(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union cvmx_mixx_ctl mix_ctl; union cvmx_agl_gmx_inf_mode agl_gmx_inf_mode; union cvmx_mixx_oring1 oring1; union cvmx_mixx_iring1 iring1; - union cvmx_agl_gmx_prtx_cfg prtx_cfg; union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl; union cvmx_mixx_irhwm mix_irhwm; union cvmx_mixx_orhwm mix_orhwm; @@ -785,9 +1032,30 @@ static int octeon_mgmt_open(struct net_device *netdev) } while (mix_ctl.s.reset); } - agl_gmx_inf_mode.u64 = 0; - agl_gmx_inf_mode.s.en = 1; - cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); + if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) { + agl_gmx_inf_mode.u64 = 0; + agl_gmx_inf_mode.s.en = 1; + cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); + } + if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) + || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { + /* Force compensation values, as they are not + * determined properly by HW + */ + union cvmx_agl_gmx_drv_ctl drv_ctl; + + drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL); + if (p->port) { + drv_ctl.s.byp_en1 = 1; + drv_ctl.s.nctl1 = 6; + drv_ctl.s.pctl1 = 6; + } else { + drv_ctl.s.byp_en = 1; + drv_ctl.s.nctl = 6; + drv_ctl.s.pctl = 6; + } + cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64); + } oring1.u64 = 0; oring1.s.obase = p->tx_ring_handle >> 3; @@ -799,18 +1067,12 @@ static int octeon_mgmt_open(struct net_device *netdev) iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE; cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64); - /* Disable packet I/O. */ - prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); - prtx_cfg.s.en = 0; - cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); - memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN); octeon_mgmt_set_mac_address(netdev, &sa); octeon_mgmt_change_mtu(netdev, netdev->mtu); - /* - * Enable the port HW. Packets are not allowed until + /* Enable the port HW. Packets are not allowed until * cvmx_mgmt_port_enable() is called. */ mix_ctl.u64 = 0; @@ -819,27 +1081,70 @@ static int octeon_mgmt_open(struct net_device *netdev) mix_ctl.s.nbtarb = 0; /* Arbitration mode */ /* MII CB-request FIFO programmable high watermark */ mix_ctl.s.mrq_hwm = 1; +#ifdef __LITTLE_ENDIAN + mix_ctl.s.lendian = 1; +#endif cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); - if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) - || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { - /* - * Force compensation values, as they are not - * determined properly by HW - */ - union cvmx_agl_gmx_drv_ctl drv_ctl; + /* Read the PHY to find the mode of the interface. */ + if (octeon_mgmt_init_phy(netdev)) { + dev_err(p->dev, "Cannot initialize PHY on MIX%d.\n", p->port); + goto err_noirq; + } - drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL); - if (port) { - drv_ctl.s.byp_en1 = 1; - drv_ctl.s.nctl1 = 6; - drv_ctl.s.pctl1 = 6; - } else { - drv_ctl.s.byp_en = 1; - drv_ctl.s.nctl = 6; - drv_ctl.s.pctl = 6; + /* Set the mode of the interface, RGMII/MII. */ + if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && p->phydev) { + union cvmx_agl_prtx_ctl agl_prtx_ctl; + int rgmii_mode = (p->phydev->supported & + (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)) != 0; + + agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); + agl_prtx_ctl.s.mode = rgmii_mode ? 0 : 1; + cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); + + /* MII clocks counts are based on the 125Mhz + * reference, which has an 8nS period. So our delays + * need to be multiplied by this factor. + */ +#define NS_PER_PHY_CLK 8 + + /* Take the DLL and clock tree out of reset */ + agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); + agl_prtx_ctl.s.clkrst = 0; + if (rgmii_mode) { + agl_prtx_ctl.s.dllrst = 0; + agl_prtx_ctl.s.clktx_byp = 0; } - cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64); + cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); + cvmx_read_csr(p->agl_prt_ctl); /* Force write out before wait */ + + /* Wait for the DLL to lock. External 125 MHz + * reference clock must be stable at this point. + */ + ndelay(256 * NS_PER_PHY_CLK); + + /* Enable the interface */ + agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); + agl_prtx_ctl.s.enable = 1; + cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); + + /* Read the value back to force the previous write */ + agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); + + /* Enable the compensation controller */ + agl_prtx_ctl.s.comp = 1; + agl_prtx_ctl.s.drv_byp = 0; + cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); + /* Force write out before wait. */ + cvmx_read_csr(p->agl_prt_ctl); + + /* For compensation state to lock. */ + ndelay(1040 * NS_PER_PHY_CLK); + + /* Some Ethernet switches cannot handle standard + * Interframe Gap, increase to 16 bytes. + */ + cvmx_write_csr(CVMX_AGL_GMX_TX_IFG, 0x88); } octeon_mgmt_rx_fill_ring(netdev); @@ -870,7 +1175,7 @@ static int octeon_mgmt_open(struct net_device *netdev) /* Interrupt when we have 1 or more packets to clean. */ mix_orhwm.u64 = 0; - mix_orhwm.s.orhwm = 1; + mix_orhwm.s.orhwm = 0; cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64); /* Enable receive and transmit interrupts */ @@ -879,13 +1184,12 @@ static int octeon_mgmt_open(struct net_device *netdev) mix_intena.s.othena = 1; cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); - /* Enable packet I/O. */ rxx_frm_ctl.u64 = 0; + rxx_frm_ctl.s.ptp_mode = p->has_rx_tstamp ? 1 : 0; rxx_frm_ctl.s.pre_align = 1; - /* - * When set, disables the length check for non-min sized pkts + /* When set, disables the length check for non-min sized pkts * with padding in the client data. */ rxx_frm_ctl.s.pad_len = 1; @@ -903,33 +1207,26 @@ static int octeon_mgmt_open(struct net_device *netdev) rxx_frm_ctl.s.ctl_drp = 1; /* Strip off the preamble */ rxx_frm_ctl.s.pre_strp = 1; - /* - * This port is configured to send PREAMBLE+SFD to begin every + /* This port is configured to send PREAMBLE+SFD to begin every * frame. GMX checks that the PREAMBLE is sent correctly. */ rxx_frm_ctl.s.pre_chk = 1; cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); - /* Enable the AGL block */ - agl_gmx_inf_mode.u64 = 0; - agl_gmx_inf_mode.s.en = 1; - cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); - - /* Configure the port duplex and enables */ - prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); - prtx_cfg.s.tx_en = 1; - prtx_cfg.s.rx_en = 1; - prtx_cfg.s.en = 1; - p->last_duplex = 1; - prtx_cfg.s.duplex = p->last_duplex; - cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); + /* Configure the port duplex, speed and enables */ + octeon_mgmt_disable_link(p); + if (p->phydev) + octeon_mgmt_update_link(p); + octeon_mgmt_enable_link(p); p->last_link = 0; - netif_carrier_off(netdev); - - if (octeon_mgmt_init_phy(netdev)) { - dev_err(p->dev, "Cannot initialize PHY.\n"); - goto err_noirq; + p->last_speed = 0; + /* PHY is not present in simulator. The carrier is enabled + * while initializing the phy for simulator, leave it enabled. + */ + if (p->phydev) { + netif_carrier_off(netdev); + phy_start_aneg(p->phydev); } netif_wake_queue(netdev); @@ -959,6 +1256,7 @@ static int octeon_mgmt_stop(struct net_device *netdev) if (p->phydev) phy_disconnect(p->phydev); + p->phydev = NULL; netif_carrier_off(netdev); @@ -991,6 +1289,7 @@ static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) int rv = NETDEV_TX_BUSY; re.d64 = 0; + re.s.tstamp = ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) != 0); re.s.len = skb->len; re.s.addr = dma_map_single(p->dev, skb->data, skb->len, @@ -1031,6 +1330,7 @@ static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) /* Ring the bell. */ cvmx_write_csr(p->mix + MIX_ORING2, 1); + netdev->trans_start = jiffies; rv = NETDEV_TX_OK; out: octeon_mgmt_update_tx_stats(netdev); @@ -1068,7 +1368,7 @@ static int octeon_mgmt_get_settings(struct net_device *netdev, if (p->phydev) return phy_ethtool_gset(p->phydev, cmd); - return -EINVAL; + return -EOPNOTSUPP; } static int octeon_mgmt_set_settings(struct net_device *netdev, @@ -1082,23 +1382,37 @@ static int octeon_mgmt_set_settings(struct net_device *netdev, if (p->phydev) return phy_ethtool_sset(p->phydev, cmd); - return -EINVAL; + return -EOPNOTSUPP; +} + +static int octeon_mgmt_nway_reset(struct net_device *dev) +{ + struct octeon_mgmt *p = netdev_priv(dev); + + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + + if (p->phydev) + return phy_start_aneg(p->phydev); + + return -EOPNOTSUPP; } static const struct ethtool_ops octeon_mgmt_ethtool_ops = { .get_drvinfo = octeon_mgmt_get_drvinfo, - .get_link = ethtool_op_get_link, .get_settings = octeon_mgmt_get_settings, - .set_settings = octeon_mgmt_set_settings + .set_settings = octeon_mgmt_set_settings, + .nway_reset = octeon_mgmt_nway_reset, + .get_link = ethtool_op_get_link, }; static const struct net_device_ops octeon_mgmt_ops = { .ndo_open = octeon_mgmt_open, .ndo_stop = octeon_mgmt_stop, .ndo_start_xmit = octeon_mgmt_xmit, - .ndo_set_rx_mode = octeon_mgmt_set_rx_filtering, + .ndo_set_rx_mode = octeon_mgmt_set_rx_filtering, .ndo_set_mac_address = octeon_mgmt_set_mac_address, - .ndo_do_ioctl = octeon_mgmt_ioctl, + .ndo_do_ioctl = octeon_mgmt_ioctl, .ndo_change_mtu = octeon_mgmt_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = octeon_mgmt_poll_controller, @@ -1113,6 +1427,7 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) const u8 *mac; struct resource *res_mix; struct resource *res_agl; + struct resource *res_agl_prt_ctl; int len; int result; @@ -1120,6 +1435,8 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) if (netdev == NULL) return -ENOMEM; + SET_NETDEV_DEV(netdev, &pdev->dev); + dev_set_drvdata(&pdev->dev, netdev); p = netdev_priv(netdev); netif_napi_add(netdev, &p->napi, octeon_mgmt_napi_poll, @@ -1127,6 +1444,7 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) p->netdev = netdev; p->dev = &pdev->dev; + p->has_rx_tstamp = false; data = of_get_property(pdev->dev.of_node, "cell-index", &len); if (data && len == sizeof(*data)) { @@ -1159,10 +1477,19 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) goto err; } + res_agl_prt_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 3); + if (res_agl_prt_ctl == NULL) { + dev_err(&pdev->dev, "no 'reg' resource\n"); + result = -ENXIO; + goto err; + } + p->mix_phys = res_mix->start; p->mix_size = resource_size(res_mix); p->agl_phys = res_agl->start; p->agl_size = resource_size(res_agl); + p->agl_prt_ctl_phys = res_agl_prt_ctl->start; + p->agl_prt_ctl_size = resource_size(res_agl_prt_ctl); if (!devm_request_mem_region(&pdev->dev, p->mix_phys, p->mix_size, @@ -1181,10 +1508,18 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) goto err; } + if (!devm_request_mem_region(&pdev->dev, p->agl_prt_ctl_phys, + p->agl_prt_ctl_size, res_agl_prt_ctl->name)) { + result = -ENXIO; + dev_err(&pdev->dev, "request_mem_region (%s) failed\n", + res_agl_prt_ctl->name); + goto err; + } p->mix = (u64)devm_ioremap(&pdev->dev, p->mix_phys, p->mix_size); p->agl = (u64)devm_ioremap(&pdev->dev, p->agl_phys, p->agl_size); - + p->agl_prt_ctl = (u64)devm_ioremap(&pdev->dev, p->agl_prt_ctl_phys, + p->agl_prt_ctl_size); spin_lock_init(&p->lock); skb_queue_head_init(&p->tx_list); @@ -1199,14 +1534,19 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) mac = of_get_mac_address(pdev->dev.of_node); - if (mac) - memcpy(netdev->dev_addr, mac, 6); + if (mac && is_valid_ether_addr(mac)) { + memcpy(netdev->dev_addr, mac, ETH_ALEN); + netdev->addr_assign_type &= ~NET_ADDR_RANDOM; + } else { + eth_hw_addr_random(netdev); + } p->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64); pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; + netif_carrier_off(netdev); result = register_netdev(netdev); if (result) goto err; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 33e3df9e39ca..7bf914df6e91 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -68,10 +68,21 @@ config PINCTRL_IMX6Q help Say Y here to enable the imx6q pinctrl driver +config PINCTRL_LANTIQ + bool + depends on LANTIQ + select PINMUX + select PINCONF + config PINCTRL_PXA3xx bool select PINMUX +config PINCTRL_FALCON + bool + depends on SOC_FALCON + depends on PINCTRL_LANTIQ + config PINCTRL_MMP2 bool "MMP2 pin controller driver" depends on ARCH_MMP @@ -199,6 +210,11 @@ config PINCTRL_ARMADA_XP source "drivers/pinctrl/spear/Kconfig" +config PINCTRL_XWAY + bool + depends on SOC_TYPE_XWAY + depends on PINCTRL_LANTIQ + endmenu endif diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f162e0196300..f395ba5cec25 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o +obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o @@ -40,5 +41,7 @@ obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o +obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o +obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o obj-$(CONFIG_PLAT_SPEAR) += spear/ diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c new file mode 100644 index 000000000000..ee7305903470 --- /dev/null +++ b/drivers/pinctrl/pinctrl-falcon.c @@ -0,0 +1,468 @@ +/* + * linux/drivers/pinctrl/pinmux-falcon.c + * based on linux/drivers/pinctrl/pinmux-pxa910.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com> + * Copyright (C) 2012 John Crispin <blogic@openwrt.org> + */ + +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/slab.h> +#include <linux/export.h> +#include <linux/err.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/of_address.h> +#include <linux/of_gpio.h> +#include <linux/platform_device.h> + +#include "pinctrl-lantiq.h" + +#include <lantiq_soc.h> + +/* Multiplexer Control Register */ +#define LTQ_PADC_MUX(x) (x * 0x4) +/* Pull Up Enable Register */ +#define LTQ_PADC_PUEN 0x80 +/* Pull Down Enable Register */ +#define LTQ_PADC_PDEN 0x84 +/* Slew Rate Control Register */ +#define LTQ_PADC_SRC 0x88 +/* Drive Current Control Register */ +#define LTQ_PADC_DCC 0x8C +/* Pad Control Availability Register */ +#define LTQ_PADC_AVAIL 0xF0 + +#define pad_r32(p, reg) ltq_r32(p + reg) +#define pad_w32(p, val, reg) ltq_w32(val, p + reg) +#define pad_w32_mask(c, clear, set, reg) \ + pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg) + +#define pad_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p))) + +#define PORTS 5 +#define PINS 32 +#define PORT(x) (x / PINS) +#define PORT_PIN(x) (x % PINS) + +#define MFP_FALCON(a, f0, f1, f2, f3) \ +{ \ + .name = #a, \ + .pin = a, \ + .func = { \ + FALCON_MUX_##f0, \ + FALCON_MUX_##f1, \ + FALCON_MUX_##f2, \ + FALCON_MUX_##f3, \ + }, \ +} + +#define GRP_MUX(a, m, p) \ +{ \ + .name = a, \ + .mux = FALCON_MUX_##m, \ + .pins = p, \ + .npins = ARRAY_SIZE(p), \ +} + +enum falcon_mux { + FALCON_MUX_GPIO = 0, + FALCON_MUX_RST, + FALCON_MUX_NTR, + FALCON_MUX_MDIO, + FALCON_MUX_LED, + FALCON_MUX_SPI, + FALCON_MUX_ASC, + FALCON_MUX_I2C, + FALCON_MUX_HOSTIF, + FALCON_MUX_SLIC, + FALCON_MUX_JTAG, + FALCON_MUX_PCM, + FALCON_MUX_MII, + FALCON_MUX_PHY, + FALCON_MUX_NONE = 0xffff, +}; + +static struct pinctrl_pin_desc falcon_pads[PORTS * PINS]; +static int pad_count[PORTS]; + +static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len) +{ + int base = bank * PINS; + int i; + + for (i = 0; i < len; i++) { + /* strlen("ioXYZ") + 1 = 6 */ + char *name = kzalloc(6, GFP_KERNEL); + snprintf(name, 6, "io%d", base + i); + d[i].number = base + i; + d[i].name = name; + } + pad_count[bank] = len; +} + +static struct ltq_mfp_pin falcon_mfp[] = { + /* pin f0 f1 f2 f3 */ + MFP_FALCON(GPIO0, RST, GPIO, NONE, NONE), + MFP_FALCON(GPIO1, GPIO, GPIO, NONE, NONE), + MFP_FALCON(GPIO2, GPIO, GPIO, NONE, NONE), + MFP_FALCON(GPIO3, GPIO, GPIO, NONE, NONE), + MFP_FALCON(GPIO4, NTR, GPIO, NONE, NONE), + MFP_FALCON(GPIO5, NTR, GPIO, NONE, NONE), + MFP_FALCON(GPIO6, RST, GPIO, NONE, NONE), + MFP_FALCON(GPIO7, MDIO, GPIO, NONE, NONE), + MFP_FALCON(GPIO8, MDIO, GPIO, NONE, NONE), + MFP_FALCON(GPIO9, LED, GPIO, NONE, NONE), + MFP_FALCON(GPIO10, LED, GPIO, NONE, NONE), + MFP_FALCON(GPIO11, LED, GPIO, NONE, NONE), + MFP_FALCON(GPIO12, LED, GPIO, NONE, NONE), + MFP_FALCON(GPIO13, LED, GPIO, NONE, NONE), + MFP_FALCON(GPIO14, LED, GPIO, NONE, NONE), + MFP_FALCON(GPIO32, ASC, GPIO, NONE, NONE), + MFP_FALCON(GPIO33, ASC, GPIO, NONE, NONE), + MFP_FALCON(GPIO34, SPI, GPIO, NONE, NONE), + MFP_FALCON(GPIO35, SPI, GPIO, NONE, NONE), + MFP_FALCON(GPIO36, SPI, GPIO, NONE, NONE), + MFP_FALCON(GPIO37, SPI, GPIO, NONE, NONE), + MFP_FALCON(GPIO38, SPI, GPIO, NONE, NONE), + MFP_FALCON(GPIO39, I2C, GPIO, NONE, NONE), + MFP_FALCON(GPIO40, I2C, GPIO, NONE, NONE), + MFP_FALCON(GPIO41, HOSTIF, GPIO, HOSTIF, JTAG), + MFP_FALCON(GPIO42, HOSTIF, GPIO, HOSTIF, NONE), + MFP_FALCON(GPIO43, SLIC, GPIO, NONE, NONE), + MFP_FALCON(GPIO44, SLIC, GPIO, PCM, ASC), + MFP_FALCON(GPIO45, SLIC, GPIO, PCM, ASC), + MFP_FALCON(GPIO64, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO65, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO66, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO67, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO68, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO69, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO70, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO71, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO72, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO73, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO74, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO75, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO76, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO77, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO78, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO79, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO80, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO81, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO82, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO83, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO84, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO85, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO86, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO87, MII, GPIO, NONE, NONE), + MFP_FALCON(GPIO88, PHY, GPIO, NONE, NONE), +}; + +static const unsigned pins_por[] = {GPIO0}; +static const unsigned pins_ntr[] = {GPIO4}; +static const unsigned pins_ntr8k[] = {GPIO5}; +static const unsigned pins_hrst[] = {GPIO6}; +static const unsigned pins_mdio[] = {GPIO7, GPIO8}; +static const unsigned pins_bled[] = {GPIO7, GPIO10, GPIO11, + GPIO12, GPIO13, GPIO14}; +static const unsigned pins_asc0[] = {GPIO32, GPIO33}; +static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36}; +static const unsigned pins_spi_cs0[] = {GPIO37}; +static const unsigned pins_spi_cs1[] = {GPIO38}; +static const unsigned pins_i2c[] = {GPIO39, GPIO40}; +static const unsigned pins_jtag[] = {GPIO41}; +static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45}; +static const unsigned pins_pcm[] = {GPIO44, GPIO45}; +static const unsigned pins_asc1[] = {GPIO44, GPIO45}; + +static struct ltq_pin_group falcon_grps[] = { + GRP_MUX("por", RST, pins_por), + GRP_MUX("ntr", NTR, pins_ntr), + GRP_MUX("ntr8k", NTR, pins_ntr8k), + GRP_MUX("hrst", RST, pins_hrst), + GRP_MUX("mdio", MDIO, pins_mdio), + GRP_MUX("bootled", LED, pins_bled), + GRP_MUX("asc0", ASC, pins_asc0), + GRP_MUX("spi", SPI, pins_spi), + GRP_MUX("spi cs0", SPI, pins_spi_cs0), + GRP_MUX("spi cs1", SPI, pins_spi_cs1), + GRP_MUX("i2c", I2C, pins_i2c), + GRP_MUX("jtag", JTAG, pins_jtag), + GRP_MUX("slic", SLIC, pins_slic), + GRP_MUX("pcm", PCM, pins_pcm), + GRP_MUX("asc1", ASC, pins_asc1), +}; + +static const char * const ltq_rst_grps[] = {"por", "hrst"}; +static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k"}; +static const char * const ltq_mdio_grps[] = {"mdio"}; +static const char * const ltq_bled_grps[] = {"bootled"}; +static const char * const ltq_asc_grps[] = {"asc0", "asc1"}; +static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"}; +static const char * const ltq_i2c_grps[] = {"i2c"}; +static const char * const ltq_jtag_grps[] = {"jtag"}; +static const char * const ltq_slic_grps[] = {"slic"}; +static const char * const ltq_pcm_grps[] = {"pcm"}; + +static struct ltq_pmx_func falcon_funcs[] = { + {"rst", ARRAY_AND_SIZE(ltq_rst_grps)}, + {"ntr", ARRAY_AND_SIZE(ltq_ntr_grps)}, + {"mdio", ARRAY_AND_SIZE(ltq_mdio_grps)}, + {"led", ARRAY_AND_SIZE(ltq_bled_grps)}, + {"asc", ARRAY_AND_SIZE(ltq_asc_grps)}, + {"spi", ARRAY_AND_SIZE(ltq_spi_grps)}, + {"i2c", ARRAY_AND_SIZE(ltq_i2c_grps)}, + {"jtag", ARRAY_AND_SIZE(ltq_jtag_grps)}, + {"slic", ARRAY_AND_SIZE(ltq_slic_grps)}, + {"pcm", ARRAY_AND_SIZE(ltq_pcm_grps)}, +}; + + + + +/* --------- pinconf related code --------- */ +static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev, + unsigned group, unsigned long *config) +{ + return -ENOTSUPP; +} + +static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev, + unsigned group, unsigned long config) +{ + return -ENOTSUPP; +} + +static int falcon_pinconf_get(struct pinctrl_dev *pctrldev, + unsigned pin, unsigned long *config) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config); + void __iomem *mem = info->membase[PORT(pin)]; + + switch (param) { + case LTQ_PINCONF_PARAM_DRIVE_CURRENT: + *config = LTQ_PINCONF_PACK(param, + !!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin))); + break; + + case LTQ_PINCONF_PARAM_SLEW_RATE: + *config = LTQ_PINCONF_PACK(param, + !!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin))); + break; + + case LTQ_PINCONF_PARAM_PULL: + if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin))) + *config = LTQ_PINCONF_PACK(param, 1); + else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin))) + *config = LTQ_PINCONF_PACK(param, 2); + else + *config = LTQ_PINCONF_PACK(param, 0); + + break; + + default: + return -ENOTSUPP; + } + + return 0; +} + +static int falcon_pinconf_set(struct pinctrl_dev *pctrldev, + unsigned pin, unsigned long config) +{ + enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config); + int arg = LTQ_PINCONF_UNPACK_ARG(config); + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + void __iomem *mem = info->membase[PORT(pin)]; + u32 reg; + + switch (param) { + case LTQ_PINCONF_PARAM_DRIVE_CURRENT: + reg = LTQ_PADC_DCC; + break; + + case LTQ_PINCONF_PARAM_SLEW_RATE: + reg = LTQ_PADC_SRC; + break; + + case LTQ_PINCONF_PARAM_PULL: + if (arg == 1) + reg = LTQ_PADC_PDEN; + else + reg = LTQ_PADC_PUEN; + break; + + default: + pr_err("%s: Invalid config param %04x\n", + pinctrl_dev_get_name(pctrldev), param); + return -ENOTSUPP; + } + + pad_w32(mem, BIT(PORT_PIN(pin)), reg); + if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin)))) + return -ENOTSUPP; + return 0; +} + +static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev, + struct seq_file *s, unsigned offset) +{ +} + +static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev, + struct seq_file *s, unsigned selector) +{ +} + +struct pinconf_ops falcon_pinconf_ops = { + .pin_config_get = falcon_pinconf_get, + .pin_config_set = falcon_pinconf_set, + .pin_config_group_get = falcon_pinconf_group_get, + .pin_config_group_set = falcon_pinconf_group_set, + .pin_config_dbg_show = falcon_pinconf_dbg_show, + .pin_config_group_dbg_show = falcon_pinconf_group_dbg_show, +}; + +static struct pinctrl_desc falcon_pctrl_desc = { + .owner = THIS_MODULE, + .pins = falcon_pads, + .confops = &falcon_pinconf_ops, +}; + +static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev, + int mfp, int mux) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + int port = PORT(info->mfp[mfp].pin); + + if ((port >= PORTS) || (!info->membase[port])) + return -ENODEV; + + pad_w32(info->membase[port], mux, + LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin))); + return 0; +} + +static const struct ltq_cfg_param falcon_cfg_params[] = { + {"lantiq,pull", LTQ_PINCONF_PARAM_PULL}, + {"lantiq,drive-current", LTQ_PINCONF_PARAM_DRIVE_CURRENT}, + {"lantiq,slew-rate", LTQ_PINCONF_PARAM_SLEW_RATE}, +}; + +static struct ltq_pinmux_info falcon_info = { + .desc = &falcon_pctrl_desc, + .apply_mux = falcon_mux_apply, +}; + + + + +/* --------- register the pinctrl layer --------- */ + +int pinctrl_falcon_get_range_size(int id) +{ + u32 avail; + + if ((id >= PORTS) || (!falcon_info.membase[id])) + return -EINVAL; + + avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL); + + return fls(avail); +} + +void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range) +{ + pinctrl_add_gpio_range(falcon_info.pctrl, range); +} + +static int pinctrl_falcon_probe(struct platform_device *pdev) +{ + struct device_node *np; + int pad_count = 0; + int ret = 0; + + /* load and remap the pad resources of the different banks */ + for_each_compatible_node(np, NULL, "lantiq,pad-falcon") { + struct platform_device *ppdev = of_find_device_by_node(np); + const __be32 *bank = of_get_property(np, "lantiq,bank", NULL); + struct resource res; + u32 avail; + int pins; + + if (!ppdev) { + dev_err(&pdev->dev, "failed to find pad pdev\n"); + continue; + } + if (!bank || *bank >= PORTS) + continue; + if (of_address_to_resource(np, 0, &res)) + continue; + falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL); + if (IS_ERR(falcon_info.clk[*bank])) { + dev_err(&ppdev->dev, "failed to get clock\n"); + return PTR_ERR(falcon_info.clk[*bank]); + } + falcon_info.membase[*bank] = + devm_request_and_ioremap(&pdev->dev, &res); + if (!falcon_info.membase[*bank]) { + dev_err(&pdev->dev, + "Failed to remap memory for bank %d\n", + *bank); + return -ENOMEM; + } + avail = pad_r32(falcon_info.membase[*bank], + LTQ_PADC_AVAIL); + pins = fls(avail); + lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins); + pad_count += pins; + clk_enable(falcon_info.clk[*bank]); + dev_dbg(&pdev->dev, "found %s with %d pads\n", + res.name, pins); + } + dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count); + falcon_pctrl_desc.name = dev_name(&pdev->dev); + falcon_pctrl_desc.npins = pad_count; + + falcon_info.mfp = falcon_mfp; + falcon_info.num_mfp = ARRAY_SIZE(falcon_mfp); + falcon_info.grps = falcon_grps; + falcon_info.num_grps = ARRAY_SIZE(falcon_grps); + falcon_info.funcs = falcon_funcs; + falcon_info.num_funcs = ARRAY_SIZE(falcon_funcs); + + ret = ltq_pinctrl_register(pdev, &falcon_info); + if (!ret) + dev_info(&pdev->dev, "Init done\n"); + return ret; +} + +static const struct of_device_id falcon_match[] = { + { .compatible = "lantiq,pinctrl-falcon" }, + {}, +}; +MODULE_DEVICE_TABLE(of, falcon_match); + +static struct platform_driver pinctrl_falcon_driver = { + .probe = pinctrl_falcon_probe, + .driver = { + .name = "pinctrl-falcon", + .owner = THIS_MODULE, + .of_match_table = falcon_match, + }, +}; + +int __init pinctrl_falcon_init(void) +{ + return platform_driver_register(&pinctrl_falcon_driver); +} + +core_initcall_sync(pinctrl_falcon_init); diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c new file mode 100644 index 000000000000..07ba7682cf22 --- /dev/null +++ b/drivers/pinctrl/pinctrl-lantiq.c @@ -0,0 +1,342 @@ +/* + * linux/drivers/pinctrl/pinctrl-lantiq.c + * based on linux/drivers/pinctrl/pinctrl-pxa3xx.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin <blogic@openwrt.org> + */ + +#include <linux/module.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/of.h> + +#include "pinctrl-lantiq.h" + +static int ltq_get_group_count(struct pinctrl_dev *pctrldev) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + return info->num_grps; +} + +static const char *ltq_get_group_name(struct pinctrl_dev *pctrldev, + unsigned selector) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + if (selector >= info->num_grps) + return NULL; + return info->grps[selector].name; +} + +static int ltq_get_group_pins(struct pinctrl_dev *pctrldev, + unsigned selector, + const unsigned **pins, + unsigned *num_pins) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + if (selector >= info->num_grps) + return -EINVAL; + *pins = info->grps[selector].pins; + *num_pins = info->grps[selector].npins; + return 0; +} + +void ltq_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + kfree(map[i].data.configs.configs); + kfree(map); +} + +static void ltq_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned offset) +{ + seq_printf(s, " %s", dev_name(pctldev->dev)); +} + +static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); + unsigned long configs[3]; + unsigned num_configs = 0; + struct property *prop; + const char *group, *pin; + const char *function; + int ret, i; + + ret = of_property_read_string(np, "lantiq,function", &function); + if (!ret) { + of_property_for_each_string(np, "lantiq,groups", prop, group) { + (*map)->type = PIN_MAP_TYPE_MUX_GROUP; + (*map)->name = function; + (*map)->data.mux.group = group; + (*map)->data.mux.function = function; + (*map)++; + } + if (of_find_property(np, "lantiq,pins", NULL)) + dev_err(pctldev->dev, + "%s mixes pins and groups settings\n", + np->name); + return 0; + } + + for (i = 0; i < info->num_params; i++) { + u32 val; + int ret = of_property_read_u32(np, + info->params[i].property, &val); + if (!ret) + configs[num_configs++] = + LTQ_PINCONF_PACK(info->params[i].param, + val); + } + + if (!num_configs) + return -EINVAL; + + of_property_for_each_string(np, "lantiq,pins", prop, pin) { + (*map)->data.configs.configs = kmemdup(configs, + num_configs * sizeof(unsigned long), + GFP_KERNEL); + (*map)->type = PIN_MAP_TYPE_CONFIGS_PIN; + (*map)->name = pin; + (*map)->data.configs.group_or_pin = pin; + (*map)->data.configs.num_configs = num_configs; + (*map)++; + } + return 0; +} + +static int ltq_pinctrl_dt_subnode_size(struct device_node *np) +{ + int ret; + + ret = of_property_count_strings(np, "lantiq,groups"); + if (ret < 0) + ret = of_property_count_strings(np, "lantiq,pins"); + return ret; +} + +int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned *num_maps) +{ + struct pinctrl_map *tmp; + struct device_node *np; + int ret; + + *num_maps = 0; + for_each_child_of_node(np_config, np) + *num_maps += ltq_pinctrl_dt_subnode_size(np); + *map = kzalloc(*num_maps * sizeof(struct pinctrl_map), GFP_KERNEL); + if (!*map) + return -ENOMEM; + tmp = *map; + + for_each_child_of_node(np_config, np) { + ret = ltq_pinctrl_dt_subnode_to_map(pctldev, np, &tmp); + if (ret < 0) { + ltq_pinctrl_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + return 0; +} + +static struct pinctrl_ops ltq_pctrl_ops = { + .get_groups_count = ltq_get_group_count, + .get_group_name = ltq_get_group_name, + .get_group_pins = ltq_get_group_pins, + .pin_dbg_show = ltq_pinctrl_pin_dbg_show, + .dt_node_to_map = ltq_pinctrl_dt_node_to_map, + .dt_free_map = ltq_pinctrl_dt_free_map, +}; + +static int ltq_pmx_func_count(struct pinctrl_dev *pctrldev) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + + return info->num_funcs; +} + +static const char *ltq_pmx_func_name(struct pinctrl_dev *pctrldev, + unsigned selector) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + + if (selector >= info->num_funcs) + return NULL; + + return info->funcs[selector].name; +} + +static int ltq_pmx_get_groups(struct pinctrl_dev *pctrldev, + unsigned func, + const char * const **groups, + unsigned * const num_groups) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + + *groups = info->funcs[func].groups; + *num_groups = info->funcs[func].num_groups; + + return 0; +} + +/* Return function number. If failure, return negative value. */ +static int match_mux(const struct ltq_mfp_pin *mfp, unsigned mux) +{ + int i; + for (i = 0; i < LTQ_MAX_MUX; i++) { + if (mfp->func[i] == mux) + break; + } + if (i >= LTQ_MAX_MUX) + return -EINVAL; + return i; +} + +/* dont assume .mfp is linearly mapped. find the mfp with the correct .pin */ +static int match_mfp(const struct ltq_pinmux_info *info, int pin) +{ + int i; + for (i = 0; i < info->num_mfp; i++) { + if (info->mfp[i].pin == pin) + return i; + } + return -1; +} + +/* check whether current pin configuration is valid. Negative for failure */ +static int match_group_mux(const struct ltq_pin_group *grp, + const struct ltq_pinmux_info *info, + unsigned mux) +{ + int i, pin, ret = 0; + for (i = 0; i < grp->npins; i++) { + pin = match_mfp(info, grp->pins[i]); + if (pin < 0) { + dev_err(info->dev, "could not find mfp for pin %d\n", + grp->pins[i]); + return -EINVAL; + } + ret = match_mux(&info->mfp[pin], mux); + if (ret < 0) { + dev_err(info->dev, "Can't find mux %d on pin%d\n", + mux, pin); + break; + } + } + return ret; +} + +static int ltq_pmx_enable(struct pinctrl_dev *pctrldev, + unsigned func, + unsigned group) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + const struct ltq_pin_group *pin_grp = &info->grps[group]; + int i, pin, pin_func, ret; + + if (!pin_grp->npins || + (match_group_mux(pin_grp, info, pin_grp->mux) < 0)) { + dev_err(info->dev, "Failed to set the pin group: %s\n", + info->grps[group].name); + return -EINVAL; + } + for (i = 0; i < pin_grp->npins; i++) { + pin = match_mfp(info, pin_grp->pins[i]); + if (pin < 0) { + dev_err(info->dev, "could not find mfp for pin %d\n", + pin_grp->pins[i]); + return -EINVAL; + } + pin_func = match_mux(&info->mfp[pin], pin_grp->mux); + ret = info->apply_mux(pctrldev, pin, pin_func); + if (ret) { + dev_err(info->dev, + "failed to apply mux %d for pin %d\n", + pin_func, pin); + return ret; + } + } + return 0; +} + +static void ltq_pmx_disable(struct pinctrl_dev *pctrldev, + unsigned func, + unsigned group) +{ + /* + * Nothing to do here. However, pinconf_check_ops() requires this + * callback to be defined. + */ +} + +static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev, + struct pinctrl_gpio_range *range, + unsigned pin) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + int mfp = match_mfp(info, pin + (range->id * 32)); + int pin_func; + + if (mfp < 0) { + dev_err(info->dev, "could not find mfp for pin %d\n", pin); + return -EINVAL; + } + + pin_func = match_mux(&info->mfp[mfp], 0); + if (pin_func < 0) { + dev_err(info->dev, "No GPIO function on pin%d\n", mfp); + return -EINVAL; + } + + return info->apply_mux(pctrldev, mfp, pin_func); +} + +static struct pinmux_ops ltq_pmx_ops = { + .get_functions_count = ltq_pmx_func_count, + .get_function_name = ltq_pmx_func_name, + .get_function_groups = ltq_pmx_get_groups, + .enable = ltq_pmx_enable, + .disable = ltq_pmx_disable, + .gpio_request_enable = ltq_pmx_gpio_request_enable, +}; + +/* + * allow different socs to register with the generic part of the lanti + * pinctrl code + */ +int ltq_pinctrl_register(struct platform_device *pdev, + struct ltq_pinmux_info *info) +{ + struct pinctrl_desc *desc; + + if (!info) + return -EINVAL; + desc = info->desc; + desc->pctlops = <q_pctrl_ops; + desc->pmxops = <q_pmx_ops; + info->dev = &pdev->dev; + + info->pctrl = pinctrl_register(desc, &pdev->dev, info); + if (!info->pctrl) { + dev_err(&pdev->dev, "failed to register LTQ pinmux driver\n"); + return -EINVAL; + } + platform_set_drvdata(pdev, info); + return 0; +} diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h new file mode 100644 index 000000000000..4419d32a0ade --- /dev/null +++ b/drivers/pinctrl/pinctrl-lantiq.h @@ -0,0 +1,194 @@ +/* + * linux/drivers/pinctrl/pinctrl-lantiq.h + * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin <blogic@openwrt.org> + */ + +#ifndef __PINCTRL_LANTIQ_H + +#include <linux/clkdev.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> + +#include "core.h" + +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) + +#define LTQ_MAX_MUX 4 +#define MFPR_FUNC_MASK 0x3 + +#define LTQ_PINCONF_PACK(param, arg) ((param) << 16 | (arg)) +#define LTQ_PINCONF_UNPACK_PARAM(conf) ((conf) >> 16) +#define LTQ_PINCONF_UNPACK_ARG(conf) ((conf) & 0xffff) + +enum ltq_pinconf_param { + LTQ_PINCONF_PARAM_PULL, + LTQ_PINCONF_PARAM_OPEN_DRAIN, + LTQ_PINCONF_PARAM_DRIVE_CURRENT, + LTQ_PINCONF_PARAM_SLEW_RATE, +}; + +struct ltq_cfg_param { + const char *property; + enum ltq_pinconf_param param; +}; + +struct ltq_mfp_pin { + const char *name; + const unsigned int pin; + const unsigned short func[LTQ_MAX_MUX]; +}; + +struct ltq_pin_group { + const char *name; + const unsigned mux; + const unsigned *pins; + const unsigned npins; +}; + +struct ltq_pmx_func { + const char *name; + const char * const *groups; + const unsigned num_groups; +}; + +struct ltq_pinmux_info { + struct device *dev; + struct pinctrl_dev *pctrl; + + /* we need to manage up to 5 pad controllers */ + void __iomem *membase[5]; + + /* the descriptor for the subsystem */ + struct pinctrl_desc *desc; + + /* we expose our pads to the subsystem */ + struct pinctrl_pin_desc *pads; + + /* the number of pads. this varies between socs */ + unsigned int num_pads; + + /* these are our multifunction pins */ + const struct ltq_mfp_pin *mfp; + unsigned int num_mfp; + + /* a number of multifunction pins can be grouped together */ + const struct ltq_pin_group *grps; + unsigned int num_grps; + + /* a mapping between function string and id */ + const struct ltq_pmx_func *funcs; + unsigned int num_funcs; + + /* the pinconf options that we are able to read from the DT */ + const struct ltq_cfg_param *params; + unsigned int num_params; + + /* the pad controller can have a irq mapping */ + const unsigned *exin; + unsigned int num_exin; + + /* we need 5 clocks max */ + struct clk *clk[5]; + + /* soc specific callback used to apply muxing */ + int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux); +}; + +enum ltq_pin { + GPIO0 = 0, + GPIO1, + GPIO2, + GPIO3, + GPIO4, + GPIO5, + GPIO6, + GPIO7, + GPIO8, + GPIO9, + GPIO10, /* 10 */ + GPIO11, + GPIO12, + GPIO13, + GPIO14, + GPIO15, + GPIO16, + GPIO17, + GPIO18, + GPIO19, + GPIO20, /* 20 */ + GPIO21, + GPIO22, + GPIO23, + GPIO24, + GPIO25, + GPIO26, + GPIO27, + GPIO28, + GPIO29, + GPIO30, /* 30 */ + GPIO31, + GPIO32, + GPIO33, + GPIO34, + GPIO35, + GPIO36, + GPIO37, + GPIO38, + GPIO39, + GPIO40, /* 40 */ + GPIO41, + GPIO42, + GPIO43, + GPIO44, + GPIO45, + GPIO46, + GPIO47, + GPIO48, + GPIO49, + GPIO50, /* 50 */ + GPIO51, + GPIO52, + GPIO53, + GPIO54, + GPIO55, + + GPIO64, + GPIO65, + GPIO66, + GPIO67, + GPIO68, + GPIO69, + GPIO70, + GPIO71, + GPIO72, + GPIO73, + GPIO74, + GPIO75, + GPIO76, + GPIO77, + GPIO78, + GPIO79, + GPIO80, + GPIO81, + GPIO82, + GPIO83, + GPIO84, + GPIO85, + GPIO86, + GPIO87, + GPIO88, +}; + +extern int ltq_pinctrl_register(struct platform_device *pdev, + struct ltq_pinmux_info *info); +extern int ltq_pinctrl_unregister(struct platform_device *pdev); +#endif /* __PINCTRL_PXA3XX_H */ diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c new file mode 100644 index 000000000000..f8d917d40c92 --- /dev/null +++ b/drivers/pinctrl/pinctrl-xway.c @@ -0,0 +1,781 @@ +/* + * linux/drivers/pinctrl/pinmux-xway.c + * based on linux/drivers/pinctrl/pinmux-pxa910.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin <blogic@openwrt.org> + */ + +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <linux/of_address.h> +#include <linux/of_gpio.h> +#include <linux/ioport.h> +#include <linux/io.h> +#include <linux/device.h> +#include <linux/module.h> +#include <linux/io.h> +#include <linux/platform_device.h> + +#include "pinctrl-lantiq.h" + +#include <lantiq_soc.h> + +/* we have 3 1/2 banks of 16 bit each */ +#define PINS 16 +#define PORT3 3 +#define PORT(x) (x / PINS) +#define PORT_PIN(x) (x % PINS) + +/* we have 2 mux bits that can be set for each pin */ +#define MUX_ALT0 0x1 +#define MUX_ALT1 0x2 + +/* + * each bank has this offset apart from the 1/2 bank that is mixed into the + * other 3 ranges + */ +#define REG_OFF 0x30 + +/* these are the offsets to our registers */ +#define GPIO_BASE(p) (REG_OFF * PORT(p)) +#define GPIO_OUT(p) GPIO_BASE(p) +#define GPIO_IN(p) (GPIO_BASE(p) + 0x04) +#define GPIO_DIR(p) (GPIO_BASE(p) + 0x08) +#define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C) +#define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10) +#define GPIO_OD(p) (GPIO_BASE(p) + 0x14) +#define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c) +#define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20) + +/* the 1/2 port needs special offsets for some registers */ +#define GPIO3_OD (GPIO_BASE(0) + 0x24) +#define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28) +#define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C) +#define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24) + +/* macros to help us access the registers */ +#define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p))) +#define gpio_setbit(m, r, p) ltq_w32_mask(0, BIT(p), m + r) +#define gpio_clearbit(m, r, p) ltq_w32_mask(BIT(p), 0, m + r) + +#define MFP_XWAY(a, f0, f1, f2, f3) \ + { \ + .name = #a, \ + .pin = a, \ + .func = { \ + XWAY_MUX_##f0, \ + XWAY_MUX_##f1, \ + XWAY_MUX_##f2, \ + XWAY_MUX_##f3, \ + }, \ + } + +#define GRP_MUX(a, m, p) \ + { .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), } + +#define FUNC_MUX(f, m) \ + { .func = f, .mux = XWAY_MUX_##m, } + +#define XWAY_MAX_PIN 32 +#define XR9_MAX_PIN 56 + +enum xway_mux { + XWAY_MUX_GPIO = 0, + XWAY_MUX_SPI, + XWAY_MUX_ASC, + XWAY_MUX_PCI, + XWAY_MUX_CGU, + XWAY_MUX_EBU, + XWAY_MUX_JTAG, + XWAY_MUX_EXIN, + XWAY_MUX_TDM, + XWAY_MUX_STP, + XWAY_MUX_SIN, + XWAY_MUX_GPT, + XWAY_MUX_NMI, + XWAY_MUX_MDIO, + XWAY_MUX_MII, + XWAY_MUX_EPHY, + XWAY_MUX_DFE, + XWAY_MUX_SDIO, + XWAY_MUX_NONE = 0xffff, +}; + +static const struct ltq_mfp_pin xway_mfp[] = { + /* pin f0 f1 f2 f3 */ + MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM), + MFP_XWAY(GPIO1, GPIO, EXIN, NONE, NONE), + MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE), + MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI), + MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC), + MFP_XWAY(GPIO5, GPIO, STP, NONE, NONE), + MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC), + MFP_XWAY(GPIO7, GPIO, CGU, PCI, NONE), + MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE), + MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN), + MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE), + MFP_XWAY(GPIO11, GPIO, ASC, PCI, SPI), + MFP_XWAY(GPIO12, GPIO, ASC, NONE, NONE), + MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE), + MFP_XWAY(GPIO14, GPIO, CGU, PCI, NONE), + MFP_XWAY(GPIO15, GPIO, SPI, JTAG, NONE), + MFP_XWAY(GPIO16, GPIO, SPI, NONE, JTAG), + MFP_XWAY(GPIO17, GPIO, SPI, NONE, JTAG), + MFP_XWAY(GPIO18, GPIO, SPI, NONE, JTAG), + MFP_XWAY(GPIO19, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO20, GPIO, JTAG, NONE, NONE), + MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT), + MFP_XWAY(GPIO22, GPIO, SPI, NONE, NONE), + MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP), + MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI), + MFP_XWAY(GPIO25, GPIO, TDM, NONE, ASC), + MFP_XWAY(GPIO26, GPIO, EBU, NONE, TDM), + MFP_XWAY(GPIO27, GPIO, TDM, NONE, ASC), + MFP_XWAY(GPIO28, GPIO, GPT, NONE, NONE), + MFP_XWAY(GPIO29, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO30, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE), + MFP_XWAY(GPIO32, GPIO, NONE, NONE, EBU), + MFP_XWAY(GPIO33, GPIO, NONE, NONE, EBU), + MFP_XWAY(GPIO34, GPIO, NONE, NONE, EBU), + MFP_XWAY(GPIO35, GPIO, NONE, NONE, EBU), + MFP_XWAY(GPIO36, GPIO, SIN, NONE, EBU), + MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO39, GPIO, EXIN, NONE, NONE), + MFP_XWAY(GPIO40, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE), + MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE), + MFP_XWAY(GPIO44, GPIO, NONE, NONE, SIN), + MFP_XWAY(GPIO45, GPIO, NONE, NONE, SIN), + MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN), + MFP_XWAY(GPIO47, GPIO, NONE, NONE, SIN), + MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE), +}; + +static const struct ltq_mfp_pin ase_mfp[] = { + /* pin f0 f1 f2 f3 */ + MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM), + MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU), + MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY), + MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU), + MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII), + MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT), + MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN), + MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG), + MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG), + MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG), + MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG), + MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG), + MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO), + MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU), + MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU), + MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO), + MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO), + MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO), + MFP_XWAY(GPIO21, GPIO, EBU, MII, SDIO), + MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU), + MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU), + MFP_XWAY(GPIO24, GPIO, EBU, NONE, MII), + MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT), + MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO), + MFP_XWAY(GPIO27, GPIO, EBU, NONE, MII), + MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO), + MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN), + MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE), +}; + +static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35}; +static const unsigned pins_asc0[] = {GPIO11, GPIO12}; +static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10}; +static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6}; +static const unsigned pins_nmi[] = {GPIO8}; +static const unsigned pins_mdio[] = {GPIO42, GPIO43}; + +static const unsigned pins_ebu_a24[] = {GPIO13}; +static const unsigned pins_ebu_clk[] = {GPIO21}; +static const unsigned pins_ebu_cs1[] = {GPIO23}; +static const unsigned pins_ebu_a23[] = {GPIO24}; +static const unsigned pins_ebu_wait[] = {GPIO26}; +static const unsigned pins_ebu_a25[] = {GPIO31}; +static const unsigned pins_ebu_rdy[] = {GPIO48}; +static const unsigned pins_ebu_rd[] = {GPIO49}; + +static const unsigned pins_nand_ale[] = {GPIO13}; +static const unsigned pins_nand_cs1[] = {GPIO23}; +static const unsigned pins_nand_cle[] = {GPIO24}; +static const unsigned pins_nand_rdy[] = {GPIO48}; +static const unsigned pins_nand_rd[] = {GPIO49}; + +static const unsigned pins_exin0[] = {GPIO0}; +static const unsigned pins_exin1[] = {GPIO1}; +static const unsigned pins_exin2[] = {GPIO2}; +static const unsigned pins_exin3[] = {GPIO39}; +static const unsigned pins_exin4[] = {GPIO46}; +static const unsigned pins_exin5[] = {GPIO9}; + +static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18}; +static const unsigned pins_spi_cs1[] = {GPIO15}; +static const unsigned pins_spi_cs2[] = {GPIO21}; +static const unsigned pins_spi_cs3[] = {GPIO13}; +static const unsigned pins_spi_cs4[] = {GPIO10}; +static const unsigned pins_spi_cs5[] = {GPIO9}; +static const unsigned pins_spi_cs6[] = {GPIO11}; + +static const unsigned pins_gpt1[] = {GPIO28}; +static const unsigned pins_gpt2[] = {GPIO21}; +static const unsigned pins_gpt3[] = {GPIO6}; + +static const unsigned pins_clkout0[] = {GPIO8}; +static const unsigned pins_clkout1[] = {GPIO7}; +static const unsigned pins_clkout2[] = {GPIO3}; +static const unsigned pins_clkout3[] = {GPIO2}; + +static const unsigned pins_pci_gnt1[] = {GPIO30}; +static const unsigned pins_pci_gnt2[] = {GPIO23}; +static const unsigned pins_pci_gnt3[] = {GPIO19}; +static const unsigned pins_pci_gnt4[] = {GPIO38}; +static const unsigned pins_pci_req1[] = {GPIO29}; +static const unsigned pins_pci_req2[] = {GPIO31}; +static const unsigned pins_pci_req3[] = {GPIO3}; +static const unsigned pins_pci_req4[] = {GPIO37}; + +static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11}; +static const unsigned ase_pins_asc[] = {GPIO5, GPIO6}; +static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3}; +static const unsigned ase_pins_ephy[] = {GPIO2, GPIO3, GPIO4}; +static const unsigned ase_pins_dfe[] = {GPIO1, GPIO2}; + +static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10}; +static const unsigned ase_pins_spi_cs1[] = {GPIO7}; +static const unsigned ase_pins_spi_cs2[] = {GPIO15}; +static const unsigned ase_pins_spi_cs3[] = {GPIO14}; + +static const unsigned ase_pins_exin0[] = {GPIO6}; +static const unsigned ase_pins_exin1[] = {GPIO29}; +static const unsigned ase_pins_exin2[] = {GPIO0}; + +static const unsigned ase_pins_gpt1[] = {GPIO5}; +static const unsigned ase_pins_gpt2[] = {GPIO4}; +static const unsigned ase_pins_gpt3[] = {GPIO25}; + +static const struct ltq_pin_group xway_grps[] = { + GRP_MUX("exin0", EXIN, pins_exin0), + GRP_MUX("exin1", EXIN, pins_exin1), + GRP_MUX("exin2", EXIN, pins_exin2), + GRP_MUX("jtag", JTAG, pins_jtag), + GRP_MUX("ebu a23", EBU, pins_ebu_a23), + GRP_MUX("ebu a24", EBU, pins_ebu_a24), + GRP_MUX("ebu a25", EBU, pins_ebu_a25), + GRP_MUX("ebu clk", EBU, pins_ebu_clk), + GRP_MUX("ebu cs1", EBU, pins_ebu_cs1), + GRP_MUX("ebu wait", EBU, pins_ebu_wait), + GRP_MUX("nand ale", EBU, pins_nand_ale), + GRP_MUX("nand cs1", EBU, pins_nand_cs1), + GRP_MUX("nand cle", EBU, pins_nand_cle), + GRP_MUX("spi", SPI, pins_spi), + GRP_MUX("spi_cs1", SPI, pins_spi_cs1), + GRP_MUX("spi_cs2", SPI, pins_spi_cs2), + GRP_MUX("spi_cs3", SPI, pins_spi_cs3), + GRP_MUX("spi_cs4", SPI, pins_spi_cs4), + GRP_MUX("spi_cs5", SPI, pins_spi_cs5), + GRP_MUX("spi_cs6", SPI, pins_spi_cs6), + GRP_MUX("asc0", ASC, pins_asc0), + GRP_MUX("asc0 cts rts", ASC, pins_asc0_cts_rts), + GRP_MUX("stp", STP, pins_stp), + GRP_MUX("nmi", NMI, pins_nmi), + GRP_MUX("gpt1", GPT, pins_gpt1), + GRP_MUX("gpt2", GPT, pins_gpt2), + GRP_MUX("gpt3", GPT, pins_gpt3), + GRP_MUX("clkout0", CGU, pins_clkout0), + GRP_MUX("clkout1", CGU, pins_clkout1), + GRP_MUX("clkout2", CGU, pins_clkout2), + GRP_MUX("clkout3", CGU, pins_clkout3), + GRP_MUX("gnt1", PCI, pins_pci_gnt1), + GRP_MUX("gnt2", PCI, pins_pci_gnt2), + GRP_MUX("gnt3", PCI, pins_pci_gnt3), + GRP_MUX("req1", PCI, pins_pci_req1), + GRP_MUX("req2", PCI, pins_pci_req2), + GRP_MUX("req3", PCI, pins_pci_req3), +/* xrx only */ + GRP_MUX("nand rdy", EBU, pins_nand_rdy), + GRP_MUX("nand rd", EBU, pins_nand_rd), + GRP_MUX("exin3", EXIN, pins_exin3), + GRP_MUX("exin4", EXIN, pins_exin4), + GRP_MUX("exin5", EXIN, pins_exin5), + GRP_MUX("gnt4", PCI, pins_pci_gnt4), + GRP_MUX("req4", PCI, pins_pci_gnt4), + GRP_MUX("mdio", MDIO, pins_mdio), +}; + +static const struct ltq_pin_group ase_grps[] = { + GRP_MUX("exin0", EXIN, ase_pins_exin0), + GRP_MUX("exin1", EXIN, ase_pins_exin1), + GRP_MUX("exin2", EXIN, ase_pins_exin2), + GRP_MUX("jtag", JTAG, ase_pins_jtag), + GRP_MUX("stp", STP, ase_pins_stp), + GRP_MUX("asc", ASC, ase_pins_asc), + GRP_MUX("gpt1", GPT, ase_pins_gpt1), + GRP_MUX("gpt2", GPT, ase_pins_gpt2), + GRP_MUX("gpt3", GPT, ase_pins_gpt3), + GRP_MUX("ephy", EPHY, ase_pins_ephy), + GRP_MUX("dfe", DFE, ase_pins_dfe), + GRP_MUX("spi", SPI, ase_pins_spi), + GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1), + GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2), + GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3), +}; + +static const char * const xway_pci_grps[] = {"gnt1", "gnt2", + "gnt3", "req1", + "req2", "req3"}; +static const char * const xway_spi_grps[] = {"spi", "spi_cs1", + "spi_cs2", "spi_cs3", + "spi_cs4", "spi_cs5", + "spi_cs6"}; +static const char * const xway_cgu_grps[] = {"clkout0", "clkout1", + "clkout2", "clkout3"}; +static const char * const xway_ebu_grps[] = {"ebu a23", "ebu a24", + "ebu a25", "ebu cs1", + "ebu wait", "ebu clk", + "nand ale", "nand cs1", + "nand cle"}; +static const char * const xway_exin_grps[] = {"exin0", "exin1", "exin2"}; +static const char * const xway_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; +static const char * const xway_asc_grps[] = {"asc0", "asc0 cts rts"}; +static const char * const xway_jtag_grps[] = {"jtag"}; +static const char * const xway_stp_grps[] = {"stp"}; +static const char * const xway_nmi_grps[] = {"nmi"}; + +/* ar9/vr9/gr9 */ +static const char * const xrx_mdio_grps[] = {"mdio"}; +static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24", + "ebu a25", "ebu cs1", + "ebu wait", "ebu clk", + "nand ale", "nand cs1", + "nand cle", "nand rdy", + "nand rd"}; +static const char * const xrx_exin_grps[] = {"exin0", "exin1", "exin2", + "exin3", "exin4", "exin5"}; +static const char * const xrx_pci_grps[] = {"gnt1", "gnt2", + "gnt3", "gnt4", + "req1", "req2", + "req3", "req4"}; + +/* ase */ +static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"}; +static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; +static const char * const ase_dfe_grps[] = {"dfe"}; +static const char * const ase_ephy_grps[] = {"ephy"}; +static const char * const ase_asc_grps[] = {"asc"}; +static const char * const ase_jtag_grps[] = {"jtag"}; +static const char * const ase_stp_grps[] = {"stp"}; +static const char * const ase_spi_grps[] = {"spi", "spi_cs1", + "spi_cs2", "spi_cs3"}; + +static const struct ltq_pmx_func danube_funcs[] = { + {"spi", ARRAY_AND_SIZE(xway_spi_grps)}, + {"asc", ARRAY_AND_SIZE(xway_asc_grps)}, + {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)}, + {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)}, + {"exin", ARRAY_AND_SIZE(xway_exin_grps)}, + {"stp", ARRAY_AND_SIZE(xway_stp_grps)}, + {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)}, + {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)}, + {"pci", ARRAY_AND_SIZE(xway_pci_grps)}, + {"ebu", ARRAY_AND_SIZE(xway_ebu_grps)}, +}; + +static const struct ltq_pmx_func xrx_funcs[] = { + {"spi", ARRAY_AND_SIZE(xway_spi_grps)}, + {"asc", ARRAY_AND_SIZE(xway_asc_grps)}, + {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)}, + {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)}, + {"exin", ARRAY_AND_SIZE(xrx_exin_grps)}, + {"stp", ARRAY_AND_SIZE(xway_stp_grps)}, + {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)}, + {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)}, + {"pci", ARRAY_AND_SIZE(xrx_pci_grps)}, + {"ebu", ARRAY_AND_SIZE(xrx_ebu_grps)}, + {"mdio", ARRAY_AND_SIZE(xrx_mdio_grps)}, +}; + +static const struct ltq_pmx_func ase_funcs[] = { + {"spi", ARRAY_AND_SIZE(ase_spi_grps)}, + {"asc", ARRAY_AND_SIZE(ase_asc_grps)}, + {"jtag", ARRAY_AND_SIZE(ase_jtag_grps)}, + {"exin", ARRAY_AND_SIZE(ase_exin_grps)}, + {"stp", ARRAY_AND_SIZE(ase_stp_grps)}, + {"gpt", ARRAY_AND_SIZE(ase_gpt_grps)}, + {"ephy", ARRAY_AND_SIZE(ase_ephy_grps)}, + {"dfe", ARRAY_AND_SIZE(ase_dfe_grps)}, +}; + +/* --------- pinconf related code --------- */ +static int xway_pinconf_get(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *config) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); + enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config); + int port = PORT(pin); + u32 reg; + + switch (param) { + case LTQ_PINCONF_PARAM_OPEN_DRAIN: + if (port == PORT3) + reg = GPIO3_OD; + else + reg = GPIO_OD(port); + *config = LTQ_PINCONF_PACK(param, + !!gpio_getbit(info->membase[0], reg, PORT_PIN(port))); + break; + + case LTQ_PINCONF_PARAM_PULL: + if (port == PORT3) + reg = GPIO3_PUDEN; + else + reg = GPIO_PUDEN(port); + if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port))) { + *config = LTQ_PINCONF_PACK(param, 0); + break; + } + + if (port == PORT3) + reg = GPIO3_PUDSEL; + else + reg = GPIO_PUDSEL(port); + if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port))) + *config = LTQ_PINCONF_PACK(param, 2); + else + *config = LTQ_PINCONF_PACK(param, 1); + break; + + default: + dev_err(pctldev->dev, "Invalid config param %04x\n", param); + return -ENOTSUPP; + } + return 0; +} + +static int xway_pinconf_set(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long config) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); + enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config); + int arg = LTQ_PINCONF_UNPACK_ARG(config); + int port = PORT(pin); + u32 reg; + + switch (param) { + case LTQ_PINCONF_PARAM_OPEN_DRAIN: + if (port == PORT3) + reg = GPIO3_OD; + else + reg = GPIO_OD(port); + gpio_setbit(info->membase[0], reg, PORT_PIN(port)); + break; + + case LTQ_PINCONF_PARAM_PULL: + if (port == PORT3) + reg = GPIO3_PUDEN; + else + reg = GPIO_PUDEN(port); + if (arg == 0) { + gpio_clearbit(info->membase[0], reg, PORT_PIN(port)); + break; + } + gpio_setbit(info->membase[0], reg, PORT_PIN(port)); + + if (port == PORT3) + reg = GPIO3_PUDSEL; + else + reg = GPIO_PUDSEL(port); + if (arg == 1) + gpio_clearbit(info->membase[0], reg, PORT_PIN(port)); + else if (arg == 2) + gpio_setbit(info->membase[0], reg, PORT_PIN(port)); + else + dev_err(pctldev->dev, "Invalid pull value %d\n", arg); + break; + + default: + dev_err(pctldev->dev, "Invalid config param %04x\n", param); + return -ENOTSUPP; + } + return 0; +} + +struct pinconf_ops xway_pinconf_ops = { + .pin_config_get = xway_pinconf_get, + .pin_config_set = xway_pinconf_set, +}; + +static struct pinctrl_desc xway_pctrl_desc = { + .owner = THIS_MODULE, + .confops = &xway_pinconf_ops, +}; + +static inline int xway_mux_apply(struct pinctrl_dev *pctrldev, + int pin, int mux) +{ + struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + int port = PORT(pin); + u32 alt1_reg = GPIO_ALT1(pin); + + if (port == PORT3) + alt1_reg = GPIO3_ALT1; + + if (mux & MUX_ALT0) + gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); + else + gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); + + if (mux & MUX_ALT1) + gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin)); + else + gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin)); + + return 0; +} + +static const struct ltq_cfg_param xway_cfg_params[] = { + {"lantiq,pull", LTQ_PINCONF_PARAM_PULL}, + {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN}, +}; + +static struct ltq_pinmux_info xway_info = { + .desc = &xway_pctrl_desc, + .apply_mux = xway_mux_apply, + .params = xway_cfg_params, + .num_params = ARRAY_SIZE(xway_cfg_params), +}; + +/* --------- gpio_chip related code --------- */ +static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val) +{ + struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); + + if (val) + gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); + else + gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); +} + +static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin) +{ + struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); + + return gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin)); +} + +static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) +{ + struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); + + gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); + + return 0; +} + +static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val) +{ + struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); + + gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); + xway_gpio_set(chip, pin, val); + + return 0; +} + +static int xway_gpio_req(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + + return pinctrl_request_gpio(gpio); +} + +static void xway_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + + pinctrl_free_gpio(gpio); +} + +static struct gpio_chip xway_chip = { + .label = "gpio-xway", + .direction_input = xway_gpio_dir_in, + .direction_output = xway_gpio_dir_out, + .get = xway_gpio_get, + .set = xway_gpio_set, + .request = xway_gpio_req, + .free = xway_gpio_free, + .base = -1, +}; + + +/* --------- register the pinctrl layer --------- */ +static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9}; +static const unsigned ase_exin_pins_map[] = {GPIO6, GPIO29, GPIO0}; + +static struct pinctrl_xway_soc { + int pin_count; + const struct ltq_mfp_pin *mfp; + const struct ltq_pin_group *grps; + unsigned int num_grps; + const struct ltq_pmx_func *funcs; + unsigned int num_funcs; + const unsigned *exin; + unsigned int num_exin; +} soc_cfg[] = { + /* legacy xway */ + {XWAY_MAX_PIN, xway_mfp, + xway_grps, ARRAY_SIZE(xway_grps), + danube_funcs, ARRAY_SIZE(danube_funcs), + xway_exin_pin_map, 3}, + /* xway xr9 series */ + {XR9_MAX_PIN, xway_mfp, + xway_grps, ARRAY_SIZE(xway_grps), + xrx_funcs, ARRAY_SIZE(xrx_funcs), + xway_exin_pin_map, 6}, + /* xway ase series */ + {XWAY_MAX_PIN, ase_mfp, + ase_grps, ARRAY_SIZE(ase_grps), + ase_funcs, ARRAY_SIZE(ase_funcs), + ase_exin_pins_map, 3}, +}; + +static struct pinctrl_gpio_range xway_gpio_range = { + .name = "XWAY GPIO", + .gc = &xway_chip, +}; + +static const struct of_device_id xway_match[] = { + { .compatible = "lantiq,pinctrl-xway", .data = &soc_cfg[0]}, + { .compatible = "lantiq,pinctrl-xr9", .data = &soc_cfg[1]}, + { .compatible = "lantiq,pinctrl-ase", .data = &soc_cfg[2]}, + {}, +}; +MODULE_DEVICE_TABLE(of, xway_match); + +static int __devinit pinmux_xway_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + const struct pinctrl_xway_soc *xway_soc; + struct resource *res; + int ret, i; + + /* get and remap our register range */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Failed to get resource\n"); + return -ENOENT; + } + xway_info.membase[0] = devm_request_and_ioremap(&pdev->dev, res); + if (!xway_info.membase[0]) { + dev_err(&pdev->dev, "Failed to remap resource\n"); + return -ENOMEM; + } + + match = of_match_device(xway_match, &pdev->dev); + if (match) + xway_soc = (const struct pinctrl_xway_soc *) match->data; + else + xway_soc = &soc_cfg[0]; + + /* find out how many pads we have */ + xway_chip.ngpio = xway_soc->pin_count; + + /* load our pad descriptors */ + xway_info.pads = devm_kzalloc(&pdev->dev, + sizeof(struct pinctrl_pin_desc) * xway_chip.ngpio, + GFP_KERNEL); + if (!xway_info.pads) { + dev_err(&pdev->dev, "Failed to allocate pads\n"); + return -ENOMEM; + } + for (i = 0; i < xway_chip.ngpio; i++) { + /* strlen("ioXY") + 1 = 5 */ + char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL); + + if (!name) { + dev_err(&pdev->dev, "Failed to allocate pad name\n"); + return -ENOMEM; + } + snprintf(name, 5, "io%d", i); + xway_info.pads[i].number = GPIO0 + i; + xway_info.pads[i].name = name; + } + xway_pctrl_desc.pins = xway_info.pads; + + /* load the gpio chip */ + xway_chip.dev = &pdev->dev; + of_gpiochip_add(&xway_chip); + ret = gpiochip_add(&xway_chip); + if (ret) { + dev_err(&pdev->dev, "Failed to register gpio chip\n"); + return ret; + } + + /* setup the data needed by pinctrl */ + xway_pctrl_desc.name = dev_name(&pdev->dev); + xway_pctrl_desc.npins = xway_chip.ngpio; + + xway_info.num_pads = xway_chip.ngpio; + xway_info.num_mfp = xway_chip.ngpio; + xway_info.mfp = xway_soc->mfp; + xway_info.grps = xway_soc->grps; + xway_info.num_grps = xway_soc->num_grps; + xway_info.funcs = xway_soc->funcs; + xway_info.num_funcs = xway_soc->num_funcs; + xway_info.exin = xway_soc->exin; + xway_info.num_exin = xway_soc->num_exin; + + /* register with the generic lantiq layer */ + ret = ltq_pinctrl_register(pdev, &xway_info); + if (ret) { + dev_err(&pdev->dev, "Failed to register pinctrl driver\n"); + return ret; + } + + /* finish with registering the gpio range in pinctrl */ + xway_gpio_range.npins = xway_chip.ngpio; + xway_gpio_range.base = xway_chip.base; + pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range); + dev_info(&pdev->dev, "Init done\n"); + return 0; +} + +static struct platform_driver pinmux_xway_driver = { + .probe = pinmux_xway_probe, + .driver = { + .name = "pinctrl-xway", + .owner = THIS_MODULE, + .of_match_table = xway_match, + }, +}; + +static int __init pinmux_xway_init(void) +{ + return platform_driver_register(&pinmux_xway_driver); +} + +core_initcall_sync(pinmux_xway_init); diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index ecc31a1f73fc..8c2ff2490d99 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -237,6 +237,13 @@ config SPI_OC_TINY help This is the driver for OpenCores tiny SPI master controller. +config SPI_OCTEON + tristate "Cavium OCTEON SPI controller" + depends on CPU_CAVIUM_OCTEON + help + SPI host driver for the hardware found on some Cavium OCTEON + SOCs. + config SPI_OMAP_UWIRE tristate "OMAP1 MicroWire" depends on ARCH_OMAP1 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 22fd3a7251bc..c48df47e4b0f 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o +obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-octeon.c new file mode 100644 index 000000000000..ea8fb2efb0f8 --- /dev/null +++ b/drivers/spi/spi-octeon.c @@ -0,0 +1,362 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011, 2012 Cavium, Inc. + */ + +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/spi/spi.h> +#include <linux/module.h> +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/of.h> + +#include <asm/octeon/octeon.h> +#include <asm/octeon/cvmx-mpi-defs.h> + +#define OCTEON_SPI_CFG 0 +#define OCTEON_SPI_STS 0x08 +#define OCTEON_SPI_TX 0x10 +#define OCTEON_SPI_DAT0 0x80 + +#define OCTEON_SPI_MAX_BYTES 9 + +#define OCTEON_SPI_MAX_CLOCK_HZ 16000000 + +struct octeon_spi { + struct spi_master *my_master; + u64 register_base; + u64 last_cfg; + u64 cs_enax; +}; + +struct octeon_spi_setup { + u32 max_speed_hz; + u8 chip_select; + u8 mode; + u8 bits_per_word; +}; + +static void octeon_spi_wait_ready(struct octeon_spi *p) +{ + union cvmx_mpi_sts mpi_sts; + unsigned int loops = 0; + + do { + if (loops++) + __delay(500); + mpi_sts.u64 = cvmx_read_csr(p->register_base + OCTEON_SPI_STS); + } while (mpi_sts.s.busy); +} + +static int octeon_spi_do_transfer(struct octeon_spi *p, + struct spi_message *msg, + struct spi_transfer *xfer, + bool last_xfer) +{ + union cvmx_mpi_cfg mpi_cfg; + union cvmx_mpi_tx mpi_tx; + unsigned int clkdiv; + unsigned int speed_hz; + int mode; + bool cpha, cpol; + int bits_per_word; + const u8 *tx_buf; + u8 *rx_buf; + int len; + int i; + + struct octeon_spi_setup *msg_setup = spi_get_ctldata(msg->spi); + + speed_hz = msg_setup->max_speed_hz; + mode = msg_setup->mode; + cpha = mode & SPI_CPHA; + cpol = mode & SPI_CPOL; + bits_per_word = msg_setup->bits_per_word; + + if (xfer->speed_hz) + speed_hz = xfer->speed_hz; + if (xfer->bits_per_word) + bits_per_word = xfer->bits_per_word; + + if (speed_hz > OCTEON_SPI_MAX_CLOCK_HZ) + speed_hz = OCTEON_SPI_MAX_CLOCK_HZ; + + clkdiv = octeon_get_io_clock_rate() / (2 * speed_hz); + + mpi_cfg.u64 = 0; + + mpi_cfg.s.clkdiv = clkdiv; + mpi_cfg.s.cshi = (mode & SPI_CS_HIGH) ? 1 : 0; + mpi_cfg.s.lsbfirst = (mode & SPI_LSB_FIRST) ? 1 : 0; + mpi_cfg.s.wireor = (mode & SPI_3WIRE) ? 1 : 0; + mpi_cfg.s.idlelo = cpha != cpol; + mpi_cfg.s.cslate = cpha ? 1 : 0; + mpi_cfg.s.enable = 1; + + if (msg_setup->chip_select < 4) + p->cs_enax |= 1ull << (12 + msg_setup->chip_select); + mpi_cfg.u64 |= p->cs_enax; + + if (mpi_cfg.u64 != p->last_cfg) { + p->last_cfg = mpi_cfg.u64; + cvmx_write_csr(p->register_base + OCTEON_SPI_CFG, mpi_cfg.u64); + } + tx_buf = xfer->tx_buf; + rx_buf = xfer->rx_buf; + len = xfer->len; + while (len > OCTEON_SPI_MAX_BYTES) { + for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) { + u8 d; + if (tx_buf) + d = *tx_buf++; + else + d = 0; + cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d); + } + mpi_tx.u64 = 0; + mpi_tx.s.csid = msg_setup->chip_select; + mpi_tx.s.leavecs = 1; + mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0; + mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES; + cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64); + + octeon_spi_wait_ready(p); + if (rx_buf) + for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) { + u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i)); + *rx_buf++ = (u8)v; + } + len -= OCTEON_SPI_MAX_BYTES; + } + + for (i = 0; i < len; i++) { + u8 d; + if (tx_buf) + d = *tx_buf++; + else + d = 0; + cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d); + } + + mpi_tx.u64 = 0; + mpi_tx.s.csid = msg_setup->chip_select; + if (last_xfer) + mpi_tx.s.leavecs = xfer->cs_change; + else + mpi_tx.s.leavecs = !xfer->cs_change; + mpi_tx.s.txnum = tx_buf ? len : 0; + mpi_tx.s.totnum = len; + cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64); + + octeon_spi_wait_ready(p); + if (rx_buf) + for (i = 0; i < len; i++) { + u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i)); + *rx_buf++ = (u8)v; + } + + if (xfer->delay_usecs) + udelay(xfer->delay_usecs); + + return xfer->len; +} + +static int octeon_spi_validate_bpw(struct spi_device *spi, u32 speed) +{ + switch (speed) { + case 8: + break; + default: + dev_err(&spi->dev, "Error: %d bits per word not supported\n", + speed); + return -EINVAL; + } + return 0; +} + +static int octeon_spi_transfer_one_message(struct spi_master *master, + struct spi_message *msg) +{ + struct octeon_spi *p = spi_master_get_devdata(master); + unsigned int total_len = 0; + int status = 0; + struct spi_transfer *xfer; + + /* + * We better have set the configuration via a call to .setup + * before we get here. + */ + if (spi_get_ctldata(msg->spi) == NULL) { + status = -EINVAL; + goto err; + } + + list_for_each_entry(xfer, &msg->transfers, transfer_list) { + if (xfer->bits_per_word) { + status = octeon_spi_validate_bpw(msg->spi, + xfer->bits_per_word); + if (status) + goto err; + } + } + + list_for_each_entry(xfer, &msg->transfers, transfer_list) { + bool last_xfer = &xfer->transfer_list == msg->transfers.prev; + int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer); + if (r < 0) { + status = r; + goto err; + } + total_len += r; + } +err: + msg->status = status; + msg->actual_length = total_len; + spi_finalize_current_message(master); + return status; +} + +static struct octeon_spi_setup *octeon_spi_new_setup(struct spi_device *spi) +{ + struct octeon_spi_setup *setup = kzalloc(sizeof(*setup), GFP_KERNEL); + if (!setup) + return NULL; + + setup->max_speed_hz = spi->max_speed_hz; + setup->chip_select = spi->chip_select; + setup->mode = spi->mode; + setup->bits_per_word = spi->bits_per_word; + return setup; +} + +static int octeon_spi_setup(struct spi_device *spi) +{ + int r; + struct octeon_spi_setup *new_setup; + struct octeon_spi_setup *old_setup = spi_get_ctldata(spi); + + r = octeon_spi_validate_bpw(spi, spi->bits_per_word); + if (r) + return r; + + new_setup = octeon_spi_new_setup(spi); + if (!new_setup) + return -ENOMEM; + + spi_set_ctldata(spi, new_setup); + kfree(old_setup); + + return 0; +} + +static void octeon_spi_cleanup(struct spi_device *spi) +{ + struct octeon_spi_setup *old_setup = spi_get_ctldata(spi); + spi_set_ctldata(spi, NULL); + kfree(old_setup); +} + +static int octeon_spi_nop_transfer_hardware(struct spi_master *master) +{ + return 0; +} + +static int __devinit octeon_spi_probe(struct platform_device *pdev) +{ + + struct resource *res_mem; + struct spi_master *master; + struct octeon_spi *p; + int err = -ENOENT; + + master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi)); + if (!master) + return -ENOMEM; + p = spi_master_get_devdata(master); + platform_set_drvdata(pdev, p); + p->my_master = master; + + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (res_mem == NULL) { + dev_err(&pdev->dev, "found no memory resource\n"); + err = -ENXIO; + goto fail; + } + if (!devm_request_mem_region(&pdev->dev, res_mem->start, + resource_size(res_mem), res_mem->name)) { + dev_err(&pdev->dev, "request_mem_region failed\n"); + goto fail; + } + p->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start, + resource_size(res_mem)); + + /* Dynamic bus numbering */ + master->bus_num = -1; + master->num_chipselect = 4; + master->mode_bits = SPI_CPHA | + SPI_CPOL | + SPI_CS_HIGH | + SPI_LSB_FIRST | + SPI_3WIRE; + + master->setup = octeon_spi_setup; + master->cleanup = octeon_spi_cleanup; + master->prepare_transfer_hardware = octeon_spi_nop_transfer_hardware; + master->transfer_one_message = octeon_spi_transfer_one_message; + master->unprepare_transfer_hardware = octeon_spi_nop_transfer_hardware; + + master->dev.of_node = pdev->dev.of_node; + err = spi_register_master(master); + if (err) { + dev_err(&pdev->dev, "register master failed: %d\n", err); + goto fail; + } + + dev_info(&pdev->dev, "OCTEON SPI bus driver\n"); + + return 0; +fail: + spi_master_put(master); + return err; +} + +static int __devexit octeon_spi_remove(struct platform_device *pdev) +{ + struct octeon_spi *p = platform_get_drvdata(pdev); + u64 register_base = p->register_base; + + spi_unregister_master(p->my_master); + + /* Clear the CSENA* and put everything in a known state. */ + cvmx_write_csr(register_base + OCTEON_SPI_CFG, 0); + + return 0; +} + +static struct of_device_id octeon_spi_match[] = { + { .compatible = "cavium,octeon-3010-spi", }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_spi_match); + +static struct platform_driver octeon_spi_driver = { + .driver = { + .name = "spi-octeon", + .owner = THIS_MODULE, + .of_match_table = octeon_spi_match, + }, + .probe = octeon_spi_probe, + .remove = __devexit_p(octeon_spi_remove), +}; + +module_platform_driver(octeon_spi_driver); + +MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver"); +MODULE_AUTHOR("David Daney"); +MODULE_LICENSE("GPL"); |