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| author | Yuantian Tang <andy.tang@nxp.com> | 2019-04-22 12:15:08 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-04-25 21:22:45 +0300 |
| commit | f34b2c26fc7d120b26cb181b8d4115675ec58244 (patch) | |
| tree | 4d2c4071266a4e4e62fd48319ed5f72dda073f25 | |
| parent | 9e98c678c2d6ae3a17cb2de55d17f69dddaa231b (diff) | |
| download | linux-f34b2c26fc7d120b26cb181b8d4115675ec58244.tar.xz | |
dt-bindings: qoriq-clock: add more PLL divider clocks support
More PLL divider clocks are needed by clock consumer IP. So update
the PLL divider description to make it more general.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qoriq-clock.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index c655f28d5918..27aeed056872 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -83,8 +83,8 @@ second cell is the clock index for the specified type. 1 cmux index (n in CLKCnCSR) 2 hwaccel index (n in CLKCGnHWACSR) 3 fman 0 for fm1, 1 for fm2 - 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4 - 4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8 + 4 platform pll n=pll/(n+1). For example, when n=1, + that means output_freq=PLL_freq/2. 5 coreclk must be 0 3. Example |