kernel/linux.git/virt/kvm/arm, branch v4.11.2

KVM: arm/arm64: vgic: Fix GICC_PMR uaccess on GICv3 and clarify ABI

2017-04-04T12:33:59+00:00

As an oversight, for GICv2, we accidentally export the GICC_PMR register in the format of the GICH_VMCR.VMPriMask field in the lower 5 bits of a word, meaning that userspace must always use the lower 5 bits to communicate with the KVM device and must shift the value left by 3 places to obtain the actual priority mask level. Since GICv3 supports the full 8 bits of priority masking in the ICH_VMCR, we have to fix the value we export when emulating a GICv2 on top of a hardware GICv3 and exporting the emulated GICv2 state to userspace. Take the chance to clarify this aspect of the ABI. Reviewed-by: Marc Zyngier Signed-off-by: Christoffer Dall

KVM: arm64: Ensure LRs are clear when they should be

2017-04-04T12:33:58+00:00

We currently have some code to clear the list registers on GICv3, but we never call this code, because the caller got nuked when removing the old vgic. We also used to have a similar GICv2 part, but that got lost in the process too. Let's reintroduce the logic for GICv2 and call the logic when we initialize the use of hypervisors on the CPU, for example when first loading KVM or when exiting a low power state. Reviewed-by: Marc Zyngier Signed-off-by: Christoffer Dall Signed-off-by: Marc Zyngier

KVM: arm/arm64: VGIC: Fix command handling while ITS being disabled

2017-03-07T15:44:08+00:00

The ITS spec says that ITS commands are only processed when the ITS is enabled (section 8.19.4, Enabled, bit[0]). Our emulation was not taking this into account. Fix this by checking the enabled state before handling CWRITER writes. On the other hand that means that CWRITER could advance while the ITS is disabled, and enabling it would need those commands to be processed. Fix this case as well by refactoring actual command processing and calling this from both the GITS_CWRITER and GITS_CTLR handlers. Reviewed-by: Eric Auger Reviewed-by: Christoffer Dall Signed-off-by: Andre Przywara Signed-off-by: Marc Zyngier

KVM: arm/arm64: Let vcpu thread modify its own active state

2017-03-07T14:48:16+00:00

Currently, if a vcpu thread tries to change the active state of an interrupt which is already on the same vcpu's AP list, it will loop forever. Since the VGIC mmio handler is called after a vcpu has already synced back the LR state to the struct vgic_irq, we can just let it proceed safely. Cc: stable@vger.kernel.org Reviewed-by: Marc Zyngier Signed-off-by: Jintack Lim Signed-off-by: Christoffer Dall Signed-off-by: Marc Zyngier

KVM: arm/arm64: vgic-v3: Don't pretend to support IRQ/FIQ bypass

2017-03-06T10:30:57+00:00

Our GICv3 emulation always presents ICC_SRE_EL1 with DIB/DFB set to zero, which implies that there is a way to bypass the GIC and inject raw IRQ/FIQ by driving the CPU pins. Of course, we don't allow that when the GIC is configured, but we fail to indicate that to the guest. The obvious fix is to set these bits (and never let them being changed again). Reported-by: Peter Maydell Acked-by: Christoffer Dall Reviewed-by: Eric Auger Signed-off-by: Marc Zyngier

KVM: arm/arm64: Emulate the EL1 phys timer registers

2017-02-08T15:13:37+00:00

Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL. Now VMs are able to use the EL1 physical timer. Signed-off-by: Jintack Lim Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier

KVM: arm/arm64: Set up a background timer for the physical timer emulation

2017-02-08T15:13:36+00:00

Set a background timer for the EL1 physical timer emulation while VMs are running, so that VMs get the physical timer interrupts in a timely manner. Schedule the background timer on entry to the VM and cancel it on exit. This would not have any performance impact to the guest OSes that currently use the virtual timer since the physical timer is always not enabled. Signed-off-by: Jintack Lim Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier

KVM: arm/arm64: Set a background timer to the earliest timer expiration

2017-02-08T15:13:35+00:00

When scheduling a background timer, consider both of the virtual and physical timer and pick the earliest expiration time. Signed-off-by: Jintack Lim Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier

KVM: arm/arm64: Update the physical timer interrupt level

2017-02-08T15:13:35+00:00

Now that we maintain the EL1 physical timer register states of VMs, update the physical timer interrupt level along with the virtual one. Signed-off-by: Jintack Lim Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier

KVM: arm/arm64: Initialize the emulated EL1 physical timer

2017-02-08T15:13:34+00:00

Initialize the emulated EL1 physical timer with the default irq number. Signed-off-by: Jintack Lim Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier