kernel/linux.git/tools/testing/selftests/rseq/param_test.c, branch v6.12.80

selftests/rseq: Do not skip !allowed_cpus for mm_cid

2024-01-22T18:40:36+00:00

Indexing with mm_cid is incompatible with skipping disallowed cpumask, because concurrency IDs are based on a virtual ID allocation which is unrelated to the physical CPU mask. These issues can be reproduced by running the rseq selftests under a taskset which excludes CPU 0, e.g. taskset -c 10-20 ./run_param_test.sh Signed-off-by: Mathieu Desnoyers Cc: Shuah Khan Cc: Peter Zijlstra Cc: "Paul E. McKenney" Cc: Boqun Feng Signed-off-by: Shuah Khan

selftests/rseq: fix kselftest Clang build warnings

2023-09-27T01:24:57+00:00

When building with Clang, I am getting many warnings from the selftests/rseq tree. Here's one such example from rseq tree: | param_test.c:1234:10: error: address argument to atomic operation must be a pointer to _Atomic type ('intptr_t *' (aka 'long *') invalid) | 1234 | while (!atomic_load(&args->percpu_list_ptr)) {} | | ^ ~~~~~~~~~~~~~~~~~~~~~~ | /usr/local/google/home/justinstitt/repos/tc-build/build/llvm/final/lib/clang/18/include/stdatomic.h:140:29: note: expanded from macro 'atomic_load' | 140 | #define atomic_load(object) __c11_atomic_load(object, __ATOMIC_SEQ_CST) | | ^ ~~~~~~ Use compiler builtins `__atomic_load_n()` and `__atomic_store_n()` with accompanying __ATOMIC_ACQUIRE and __ATOMIC_RELEASE, respectively. This will fix the warnings because the compiler builtins do not expect their arguments to have _Atomic type. This should also make TSAN happier. Link: https://github.com/ClangBuiltLinux/linux/issues/1698 Link: https://github.com/ClangBuiltLinux/continuous-integration2/issues/61 Suggested-by: Mathieu Desnoyers Signed-off-by: Justin Stitt Reviewed-by: Mathieu Desnoyers Signed-off-by: Shuah Khan

selftests/rseq: parametrized test: Report/abort on negative concurrency ID

2022-12-27T11:52:15+00:00

Report and abort when a negative concurrency ID value is observed by the spinlock test. Signed-off-by: Mathieu Desnoyers Signed-off-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/20221122203932.231377-21-mathieu.desnoyers@efficios.com

selftests/rseq: Implement parametrized mm_cid test

2022-12-27T11:52:15+00:00

Adapt to the rseq.h API changes introduced by commits "selftests/rseq: : Template memory ordering and percpu access mode". Build a new param_test_mm_cid, param_test_mm_cid_benchmark, and param_test_mm_cid_compare_twice executables to test the new "mm_cid" rseq field. Signed-off-by: Mathieu Desnoyers Signed-off-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/20221122203932.231377-20-mathieu.desnoyers@efficios.com

selftests/rseq: Remove RSEQ_SKIP_FASTPATH code

2022-12-27T11:52:12+00:00

This code is not currently build by the test Makefile, adds complexity, and is not overall useful considering that the abort handling loops to retry the fast-path. Signed-off-by: Mathieu Desnoyers Signed-off-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/20221122203932.231377-10-mathieu.desnoyers@efficios.com

Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

2022-03-25T17:11:38+00:00

Pull RISC-V updates from Palmer Dabbelt: - Support for Sv57-based virtual memory. - Various improvements for the MicroChip PolarFire SOC and the associated Icicle dev board, which should allow upstream kernels to boot without any additional modifications. - An improved memmove() implementation. - Support for the new Ssconfpmf and SBI PMU extensions, which allows for a much more useful perf implementation on RISC-V systems. - Support for restartable sequences. * tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (36 commits) rseq/selftests: Add support for RISC-V RISC-V: Add support for restartable sequence MAINTAINERS: Add entry for RISC-V PMU drivers Documentation: riscv: Remove the old documentation RISC-V: Add sscofpmf extension support RISC-V: Add perf platform driver based on SBI PMU extension RISC-V: Add RISC-V SBI PMU extension definitions RISC-V: Add a simple platform driver for RISC-V legacy perf RISC-V: Add a perf core library for pmu drivers RISC-V: Add CSR encodings for all HPMCOUNTERS RISC-V: Remove the current perf implementation RISC-V: Improve /proc/cpuinfo output for ISA extensions RISC-V: Do no continue isa string parsing without correct XLEN RISC-V: Implement multi-letter ISA extension probing framework RISC-V: Extract multi-letter extension names from "riscv, isa" RISC-V: Minimal parser for "riscv, isa" strings RISC-V: Correctly print supported extensions riscv: Fixed misaligned memory access. Fixed pointer comparison. MAINTAINERS: update riscv/microchip entry riscv: dts: microchip: add new peripherals to icicle kit device tree ...

rseq/selftests: Add support for RISC-V

2022-03-22T21:45:19+00:00

Add support for RISC-V in the rseq selftests, which covers both 64-bit and 32-bit ISA with little endian mode. Signed-off-by: Vincent Chen Tested-by: Eric Lin Reviewed-by: Mathieu Desnoyers Signed-off-by: Palmer Dabbelt

selftests/rseq: Fix warnings about #if checks of undefined tokens

2022-02-02T12:11:36+00:00

Signed-off-by: Mathieu Desnoyers Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/20220124171253.22072-12-mathieu.desnoyers@efficios.com

selftests/rseq: Fix ppc32 offsets by using long rather than off_t

2022-02-02T12:11:36+00:00

The semantic of off_t is for file offsets. We mean to use it as an offset from a pointer. We really expect it to fit in a single register, and not use a 64-bit type on 32-bit architectures. Fix runtime issues on ppc32 where the offset is always 0 due to inconsistency between the argument type (off_t -> 64-bit) and type expected by the inline assembler (32-bit). Signed-off-by: Mathieu Desnoyers Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/20220124171253.22072-11-mathieu.desnoyers@efficios.com

selftests/rseq: Remove useless assignment to cpu variable

2022-02-02T12:11:34+00:00

Signed-off-by: Mathieu Desnoyers Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/20220124171253.22072-4-mathieu.desnoyers@efficios.com