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<title>kernel/linux.git/tools/testing/selftests/riscv, branch v6.18.22</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.18.22</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.18.22'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2025-09-19T01:26:07+00:00</updated>
<entry>
<title>selftests: riscv: Add README for RISC-V KSelfTest</title>
<updated>2025-09-19T01:26:07+00:00</updated>
<author>
<name>Bala-Vignesh-Reddy</name>
<email>reddybalavignesh9979@gmail.com</email>
</author>
<published>2025-08-15T18:07:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f68cd7ddd014b60451922207bff2ea3beea0d8cb'/>
<id>urn:sha1:f68cd7ddd014b60451922207bff2ea3beea0d8cb</id>
<content type='text'>
Add a README file for RISC-V specific kernel selftests under
tools/testing/selftests/riscv/. This mirrors the existing README
for arm64, providing clear guidance on how the tests are architecture
specific and skipped on non-riscv systems. It also includes
standard make commands for building, running and installing the
tests, along with a reference to general kselftest documentation.

Signed-off-by: Bala-Vignesh-Reddy &lt;reddybalavignesh9979@gmail.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20250815180724.14459-1-reddybalavignesh9979@gmail.com
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;</content>
</entry>
<entry>
<title>selftests: riscv: fix v_exec_initval_nolibc.c</title>
<updated>2025-04-01T07:03:04+00:00</updated>
<author>
<name>Ignacio Encinas</name>
<email>ignacio@iencinas.com</email>
</author>
<published>2025-03-06T19:49:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=79ba5c1c7767a539f42c6f6db46961b0bec2bc03'/>
<id>urn:sha1:79ba5c1c7767a539f42c6f6db46961b0bec2bc03</id>
<content type='text'>
Vector registers are zero initialized by the kernel. Stop accepting
"all ones" as a clean value.

Note that this was not working as expected given that
	value == 0xff
can be assumed to be always false by the compiler as value's range is
[-128, 127]. Both GCC (-Wtype-limits) and clang
(-Wtautological-constant-out-of-range-compare) warn about this.

Reviewed-by: Charlie Jenkins &lt;charlie@rivosinc.com&gt;
Tested-by: Charlie Jenkins &lt;charlie@rivosinc.com&gt;
Signed-off-by: Ignacio Encinas &lt;ignacio@iencinas.com&gt;
Link: https://lore.kernel.org/r/20250306-fix-v_exec_initval_nolibc-v2-1-97f9dc8a7faf@iencinas.com
Signed-off-by: Alexandre Ghiti &lt;alexghiti@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: selftests: Add TEST_ZICBOM into CBO tests</title>
<updated>2025-03-18T12:44:17+00:00</updated>
<author>
<name>Yunhui Cui</name>
<email>cuiyunhui@bytedance.com</email>
</author>
<published>2025-02-26T06:32:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=36dec9e44805f80d32277be76d16c88373bdc20d'/>
<id>urn:sha1:36dec9e44805f80d32277be76d16c88373bdc20d</id>
<content type='text'>
Add test for Zicbom and its block size into CBO tests, when
Zicbom is present, test that cbo.clean/flush may be issued and works.
As the software can't verify the clean/flush functions, we just judged
that cbo.clean/flush isn't executed illegally.

Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Signed-off-by: Yunhui Cui &lt;cuiyunhui@bytedance.com&gt;
Link: https://lore.kernel.org/r/20250226063206.71216-4-cuiyunhui@bytedance.com
Signed-off-by: Alexandre Ghiti &lt;alexghiti@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'riscv-for-linus-6.14-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux</title>
<updated>2025-01-31T23:13:25+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2025-01-31T23:13:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=1b5f3c51fbb8042efb314484b47b2092cdd40bf6'/>
<id>urn:sha1:1b5f3c51fbb8042efb314484b47b2092cdd40bf6</id>
<content type='text'>
Pull RISC-V updates from Palmer Dabbelt:

 - The PH1520 pinctrl and dwmac drivers are enabeled in defconfig

 - A redundant AQRL barrier has been removed from the futex cmpxchg
   implementation

 - Support for the T-Head vector extensions, which includes exposing
   these extensions to userspace on systems that implement them

 - Some more page table information is now printed on die() and systems
   that cause PA overflows

* tag 'riscv-for-linus-6.14-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: add a warning when physical memory address overflows
  riscv/mm/fault: add show_pte() before die()
  riscv: Add ghostwrite vulnerability
  selftests: riscv: Support xtheadvector in vector tests
  selftests: riscv: Fix vector tests
  riscv: hwprobe: Document thead vendor extensions and xtheadvector extension
  riscv: hwprobe: Add thead vendor extension probing
  riscv: vector: Support xtheadvector save/restore
  riscv: Add xtheadvector instruction definitions
  riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT
  RISC-V: define the elements of the VCSR vector CSR
  riscv: vector: Use vlenb from DT for thead
  riscv: Add thead and xtheadvector as a vendor extension
  riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree
  dt-bindings: cpus: add a thead vlen register length property
  dt-bindings: riscv: Add xtheadvector ISA extension description
  RISC-V: Mark riscv_v_init() as __init
  riscv: defconfig: drop RT_GROUP_SCHED=y
  riscv/futex: Optimize atomic cmpxchg
  riscv: defconfig: enable pinctrl and dwmac support for TH1520
</content>
</entry>
<entry>
<title>selftests: riscv: Support xtheadvector in vector tests</title>
<updated>2025-01-18T20:33:38+00:00</updated>
<author>
<name>Charlie Jenkins</name>
<email>charlie@rivosinc.com</email>
</author>
<published>2024-11-14T02:21:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c384c5d4a2aed5b6a10de1fcc2f5b46ad4aeeea8'/>
<id>urn:sha1:c384c5d4a2aed5b6a10de1fcc2f5b46ad4aeeea8</id>
<content type='text'>
Extend existing vector tests to be compatible with the xtheadvector
instructions.

Signed-off-by: Charlie Jenkins &lt;charlie@rivosinc.com&gt;
Tested-by: Yangyu Chen &lt;cyy@cyyself.name&gt;
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-13-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>selftests: riscv: Fix vector tests</title>
<updated>2025-01-18T20:33:37+00:00</updated>
<author>
<name>Charlie Jenkins</name>
<email>charlie@rivosinc.com</email>
</author>
<published>2024-11-14T02:21:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=57d7713af93e4b7344d3022fad9ddf0f10f815ec'/>
<id>urn:sha1:57d7713af93e4b7344d3022fad9ddf0f10f815ec</id>
<content type='text'>
Overhaul the riscv vector tests to use kselftest_harness to help the
test cases correctly report the results and decouple the individual test
cases from each other. With this refactoring, only run the test cases if
vector is reported and properly report the test case as skipped
otherwise. The v_initval_nolibc test was previously not checking if
vector was supported and used a function (malloc) which invalidates
the state of the vector registers.

Signed-off-by: Charlie Jenkins &lt;charlie@rivosinc.com&gt;
Tested-by: Yangyu Chen &lt;cyy@cyyself.name&gt;
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-12-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>Merge patch series "selftest: fix riscv/vector tests"</title>
<updated>2025-01-09T17:35:42+00:00</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@rivosinc.com</email>
</author>
<published>2025-01-09T17:35:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=89726fb01a12d639fbf1172f74f8215b1c2ebf24'/>
<id>urn:sha1:89726fb01a12d639fbf1172f74f8215b1c2ebf24</id>
<content type='text'>
This contains a pair of fixes for the vector self tests, which avoids
some warnings and provides proper status messages.

* b4-shazam-merge:
  tools: selftests: riscv: Add test count for vstate_prctl
  tools: selftests: riscv: Add pass message for v_initval_nolibc

Link: https://lore.kernel.org/r/20241220091730.28006-1-yongxuan.wang@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>tools: selftests: riscv: Add test count for vstate_prctl</title>
<updated>2025-01-09T17:35:40+00:00</updated>
<author>
<name>Yong-Xuan Wang</name>
<email>yongxuan.wang@sifive.com</email>
</author>
<published>2024-12-20T09:17:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ebdc22c51acee963e26cacb2cb63f8fa2f483808'/>
<id>urn:sha1:ebdc22c51acee963e26cacb2cb63f8fa2f483808</id>
<content type='text'>
Add the test count to drop the warning message.
"Planned tests != run tests (0 != 1)"

Fixes: 7cf6198ce22d ("selftests: Test RISC-V Vector prctl interface")
Signed-off-by: Yong-Xuan Wang &lt;yongxuan.wang@sifive.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Andy Chiu &lt;AndybnAC@gmail.com&gt;
Link: https://lore.kernel.org/r/20241220091730.28006-3-yongxuan.wang@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>tools: selftests: riscv: Add pass message for v_initval_nolibc</title>
<updated>2025-01-09T17:35:36+00:00</updated>
<author>
<name>Yong-Xuan Wang</name>
<email>yongxuan.wang@sifive.com</email>
</author>
<published>2024-12-20T09:17:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=503465d4dc40849af3cc18a517a5c06e155c5e33'/>
<id>urn:sha1:503465d4dc40849af3cc18a517a5c06e155c5e33</id>
<content type='text'>
Add the pass message after we successfully complete the test.

Fixes: 5c93c4c72fbc ("selftests: Test RISC-V Vector's first-use handler")
Signed-off-by: Yong-Xuan Wang &lt;yongxuan.wang@sifive.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Andy Chiu &lt;AndybnAC@gmail.com&gt;
Link: https://lore.kernel.org/r/20241220091730.28006-2-yongxuan.wang@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>riscv: selftests: Fix warnings pointer masking test</title>
<updated>2024-12-17T22:23:18+00:00</updated>
<author>
<name>Charlie Jenkins</name>
<email>charlie@rivosinc.com</email>
</author>
<published>2024-12-12T07:01:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=498d5b14db8c9118be139f668720c67bea2dc344'/>
<id>urn:sha1:498d5b14db8c9118be139f668720c67bea2dc344</id>
<content type='text'>
When compiling the pointer masking tests with -Wall this warning
is present:

pointer_masking.c: In function ‘test_tagged_addr_abi_sysctl’:
pointer_masking.c:203:9: warning: ignoring return value of ‘pwrite’
declared with attribute ‘warn_unused_result’ [-Wunused-result]
  203 |         pwrite(fd, &amp;value, 1, 0); |
      ^~~~~~~~~~~~~~~~~~~~~~~~ pointer_masking.c:208:9: warning:
ignoring return value of ‘pwrite’ declared with attribute
‘warn_unused_result’ [-Wunused-result]
  208 |         pwrite(fd, &amp;value, 1, 0);

I came across this on riscv64-linux-gnu-gcc (Ubuntu
11.4.0-1ubuntu1~22.04).

Fix this by checking that the number of bytes written equal the expected
number of bytes written.

Fixes: 7470b5afd150 ("riscv: selftests: Add a pointer masking test")
Signed-off-by: Charlie Jenkins &lt;charlie@rivosinc.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20241211-fix_warnings_pointer_masking_tests-v6-1-c7ae708fbd2f@rivosinc.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
</feed>
