<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/tools/testing/selftests/kvm/include/riscv, branch v6.19.12</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.19.12</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.19.12'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2025-09-16T05:23:55+00:00</updated>
<entry>
<title>KVM: riscv: selftests: Add missing headers for new testcases</title>
<updated>2025-09-16T05:23:55+00:00</updated>
<author>
<name>Dong Yang</name>
<email>dayss1224@gmail.com</email>
</author>
<published>2025-09-01T07:35:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f4103c1171a4e661a61783e16073160be31b956f'/>
<id>urn:sha1:f4103c1171a4e661a61783e16073160be31b956f</id>
<content type='text'>
Add missing headers to fix the build for new RISC-V KVM selftests.

Signed-off-by: Quan Zhou &lt;zhouquan@iscas.ac.cn&gt;
Signed-off-by: Dong Yang &lt;dayss1224@gmail.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/bfb66541918de68cd89b83bc3430af94bdc75a85.1756710918.git.dayss1224@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>KVM: riscv: selftests: Decode stval to identify exact exception type</title>
<updated>2025-05-21T04:04:37+00:00</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2025-04-30T08:16:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=3608b174ece5633dbd1f9afe37a48a2a9a0f0499'/>
<id>urn:sha1:3608b174ece5633dbd1f9afe37a48a2a9a0f0499</id>
<content type='text'>
Currently, the sbi_pmu_test continues if the exception type is illegal
instruction because access to hpmcounter will generate that. However
illegal instruction exception may occur due to the other reasons
which should result in test assertion.

Use the stval to decode the exact type of instructions and which csrs are
being accessed if it is csr access instructions. Assert in all cases
except if it is a csr access instructions that access valid PMU related
registers.

Take this opportunity to remove the CSR_CYCLEH reference as the test is
compiled for RV64 only.

Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Link: https://lore.kernel.org/r/20250430-kvm_selftest_improve-v3-2-eea270ff080b@rivosinc.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>KVM: riscv: selftests: Align the trap information wiht pt_regs</title>
<updated>2025-05-21T04:04:35+00:00</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2025-04-30T08:16:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e23bb06b17f81982450beb880b9c5a7fb4251164'/>
<id>urn:sha1:e23bb06b17f81982450beb880b9c5a7fb4251164</id>
<content type='text'>
The current exeception register structure in selftests are missing
few registers (e.g stval). Instead of adding it manually, change
the ex_regs to align with pt_regs to make it future proof.

Suggested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Link: https://lore.kernel.org/r/20250430-kvm_selftest_improve-v3-1-eea270ff080b@rivosinc.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>KVM: riscv: selftests: Add a test for PMU snapshot functionality</title>
<updated>2024-04-26T07:44:10+00:00</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2024-04-20T15:17:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=13cb706e28d9d4d3259954eb08c57b990e4429ea'/>
<id>urn:sha1:13cb706e28d9d4d3259954eb08c57b990e4429ea</id>
<content type='text'>
Verify PMU snapshot functionality by setting up the shared memory
correctly and reading the counter values from the shared memory
instead of the CSR.

Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Link: https://lore.kernel.org/r/20240420151741.962500-23-atishp@rivosinc.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>KVM: riscv: selftests: Add SBI PMU extension definitions</title>
<updated>2024-04-26T07:44:04+00:00</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2024-04-20T15:17:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=3203b9474356503ac5a28030b5d46d85a6491c5f'/>
<id>urn:sha1:3203b9474356503ac5a28030b5d46d85a6491c5f</id>
<content type='text'>
The SBI PMU extension definition is required for upcoming SBI PMU
selftests.

Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Link: https://lore.kernel.org/r/20240420151741.962500-21-atishp@rivosinc.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>KVM: riscv: selftests: Add helper functions for extension checks</title>
<updated>2024-04-26T07:44:00+00:00</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2024-04-20T15:17:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=97be675bfdb5086a6ad1aeeaa43df78b1afd5a0d'/>
<id>urn:sha1:97be675bfdb5086a6ad1aeeaa43df78b1afd5a0d</id>
<content type='text'>
__vcpu_has_ext can check both SBI and ISA extensions when the first
argument is properly converted to SBI/ISA extension IDs. Introduce
two helper functions to make life easier for developers so they
don't have to worry about the conversions.

Replace the current usages as well with new helpers.

Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20240420151741.962500-19-atishp@rivosinc.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>KVM: riscv: selftests: Move sbi definitions to its own header file</title>
<updated>2024-04-26T07:43:57+00:00</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2024-04-20T15:17:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9408a23fac62d31de067bd2b0099eb9151395345'/>
<id>urn:sha1:9408a23fac62d31de067bd2b0099eb9151395345</id>
<content type='text'>
The SBI definitions will continue to grow. Move the sbi related
definitions to its own header file from processor.h

Suggested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20240420151741.962500-18-atishp@rivosinc.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'kvm-x86-selftests-6.9' of https://github.com/kvm-x86/linux into HEAD</title>
<updated>2024-03-11T14:20:35+00:00</updated>
<author>
<name>Paolo Bonzini</name>
<email>pbonzini@redhat.com</email>
</author>
<published>2024-03-11T14:20:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4d4c02852abf01059e45a188f16f13f7ec78371c'/>
<id>urn:sha1:4d4c02852abf01059e45a188f16f13f7ec78371c</id>
<content type='text'>
KVM selftests changes for 6.9:

 - Add macros to reduce the amount of boilerplate code needed to write "simple"
   selftests, and to utilize selftest TAP infrastructure, which is especially
   beneficial for KVM selftests with multiple testcases.

 - Add basic smoke tests for SEV and SEV-ES, along with a pile of library
   support for handling private/encrypted/protected memory.

 - Fix benign bugs where tests neglect to close() guest_memfd files.
</content>
</entry>
<entry>
<title>KVM: riscv: selftests: Add sstc timer test</title>
<updated>2024-03-06T15:23:29+00:00</updated>
<author>
<name>Haibo Xu</name>
<email>haibo1.xu@intel.com</email>
</author>
<published>2024-01-22T09:58:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d0b94bcbb04262b9ffe6e172223e8cbb663a2c9d'/>
<id>urn:sha1:d0b94bcbb04262b9ffe6e172223e8cbb663a2c9d</id>
<content type='text'>
Add a KVM selftests to validate the Sstc timer functionality.
The test was ported from arm64 arch timer test.

Signed-off-by: Haibo Xu &lt;haibo1.xu@intel.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>KVM: riscv: selftests: Change vcpu_has_ext to a common function</title>
<updated>2024-03-06T15:23:27+00:00</updated>
<author>
<name>Haibo Xu</name>
<email>haibo1.xu@intel.com</email>
</author>
<published>2024-01-22T09:58:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=812806bd1e70f79cc69061f9fd9bb1d367990d37'/>
<id>urn:sha1:812806bd1e70f79cc69061f9fd9bb1d367990d37</id>
<content type='text'>
Move vcpu_has_ext to the processor.c and rename it to __vcpu_has_ext
so that other test cases can use it for vCPU extension check.

Signed-off-by: Haibo Xu &lt;haibo1.xu@intel.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
</feed>
