kernel/linux.git/tools/testing/selftests/kvm/include/riscv/processor.h, branch linux-6.19.y

KVM: riscv: selftests: Add missing headers for new testcases

2025-09-16T05:23:55+00:00

Add missing headers to fix the build for new RISC-V KVM selftests. Signed-off-by: Quan Zhou Signed-off-by: Dong Yang Reviewed-by: Andrew Jones Link: https://lore.kernel.org/r/bfb66541918de68cd89b83bc3430af94bdc75a85.1756710918.git.dayss1224@gmail.com Signed-off-by: Anup Patel

KVM: riscv: selftests: Decode stval to identify exact exception type

2025-05-21T04:04:37+00:00

Currently, the sbi_pmu_test continues if the exception type is illegal instruction because access to hpmcounter will generate that. However illegal instruction exception may occur due to the other reasons which should result in test assertion. Use the stval to decode the exact type of instructions and which csrs are being accessed if it is csr access instructions. Assert in all cases except if it is a csr access instructions that access valid PMU related registers. Take this opportunity to remove the CSR_CYCLEH reference as the test is compiled for RV64 only. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra Link: https://lore.kernel.org/r/20250430-kvm_selftest_improve-v3-2-eea270ff080b@rivosinc.com Signed-off-by: Anup Patel

KVM: riscv: selftests: Align the trap information wiht pt_regs

2025-05-21T04:04:35+00:00

The current exeception register structure in selftests are missing few registers (e.g stval). Instead of adding it manually, change the ex_regs to align with pt_regs to make it future proof. Suggested-by: Andrew Jones Reviewed-by: Andrew Jones Signed-off-by: Atish Patra Link: https://lore.kernel.org/r/20250430-kvm_selftest_improve-v3-1-eea270ff080b@rivosinc.com Signed-off-by: Anup Patel

KVM: riscv: selftests: Add helper functions for extension checks

2024-04-26T07:44:00+00:00

__vcpu_has_ext can check both SBI and ISA extensions when the first argument is properly converted to SBI/ISA extension IDs. Introduce two helper functions to make life easier for developers so they don't have to worry about the conversions. Replace the current usages as well with new helpers. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20240420151741.962500-19-atishp@rivosinc.com Signed-off-by: Anup Patel

KVM: riscv: selftests: Move sbi definitions to its own header file

2024-04-26T07:43:57+00:00

The SBI definitions will continue to grow. Move the sbi related definitions to its own header file from processor.h Suggested-by: Andrew Jones Reviewed-by: Andrew Jones Signed-off-by: Atish Patra Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20240420151741.962500-18-atishp@rivosinc.com Signed-off-by: Anup Patel

KVM: riscv: selftests: Add sstc timer test

2024-03-06T15:23:29+00:00

Add a KVM selftests to validate the Sstc timer functionality. The test was ported from arm64 arch timer test. Signed-off-by: Haibo Xu Reviewed-by: Andrew Jones Signed-off-by: Anup Patel

KVM: riscv: selftests: Change vcpu_has_ext to a common function

2024-03-06T15:23:27+00:00

Move vcpu_has_ext to the processor.c and rename it to __vcpu_has_ext so that other test cases can use it for vCPU extension check. Signed-off-by: Haibo Xu Reviewed-by: Andrew Jones Signed-off-by: Anup Patel

KVM: riscv: selftests: Add exception handling support

2024-03-06T15:21:41+00:00

Add the infrastructure for guest exception handling in riscv selftests. Customized handlers can be enabled by vm_install_exception_handler(vector) or vm_install_interrupt_handler(). The code is inspired from that of x86/arm64. Signed-off-by: Haibo Xu Reviewed-by: Andrew Jones Signed-off-by: Anup Patel

KVM: riscv: selftests: Switch to use macro from csr.h

2024-02-26T04:44:07+00:00

Signed-off-by: Haibo Xu Reviewed-by: Andrew Jones Signed-off-by: Anup Patel

RISC-V: KVM: selftests: Add steal_time test support

2023-12-30T05:56:45+00:00

With the introduction of steal-time accounting support for RISC-V KVM we can add RISC-V support to the steal_time test. Reviewed-by: Anup Patel Reviewed-by: Atish Patra Signed-off-by: Andrew Jones Signed-off-by: Anup Patel