kernel/linux.git/tools/testing/selftests/kvm/include/loongarch/processor.h, branch linux-7.1.yLinux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.1.y2026-04-09T10:56:38+00:00KVM: LoongArch: selftests: Add PMU overflow interrupt test2026-04-09T10:56:38+00:00Song Gaogaosong@loongson.cn2026-04-09T10:56:38+00:00urn:sha1:e47b8e1db9a9bbef6765e85b11e87f48e6b56846
Extend the PMU test suite to cover overflow interrupts. The test enables
the PMI (Performance Monitor Interrupt), sets counter 0 to one less than
the overflow value, and verifies that an interrupt is raised when the
counter overflows. A guest interrupt handler checks the interrupt cause
and disables further PMU interrupts upon success.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
KVM: LoongArch: selftests: Add basic PMU event counting test2026-04-09T10:56:37+00:00Song Gaogaosong@loongson.cn2026-04-09T10:56:37+00:00urn:sha1:11c840192768a5a63b6aed75273c5e8e416230ee
Introduce a basic PMU test that verifies hardware event counting for
four performance counters. The test enables the events for CPU cycles,
instructions retired, branch instructions, and branch misses, runs a
fixed number of loops, and checks that the counter values fall within
expected ranges. It also validates that the host supports PMU and that
the VM feature is enabled.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
KVM: LoongArch: selftests: Add cpucfg read/write helpers2026-04-09T10:56:37+00:00Song Gaogaosong@loongson.cn2026-04-09T10:56:37+00:00urn:sha1:fa19ea9a7bdb97575e05d72305a4c40a3a631357
Add helper macros and functions to read and write CPU configuration
registers (cpucfg) from the guest and from the VMM. This interface is
required in upcoming selftests for querying and setting CPU features,
such as PMU capabilities.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
KVM: LoongArch: selftests: Add timer interrupt test case2025-11-28T06:49:44+00:00Bibo Maomaobibo@loongson.cn2025-11-28T06:49:44+00:00urn:sha1:df41742343fad11fde06e085096003d64599785f
Add timer test case based on common arch_timer code, timer interrupt
with one-shot and period mode is tested.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
KVM: LoongArch: selftests: Add exception handler register interface2025-11-27T03:00:18+00:00Bibo Maomaobibo@loongson.cn2025-11-27T03:00:18+00:00urn:sha1:d84fe2f30b0a0cbe08260c00a84ffe42161c95ce
Add interrupt and exception handler register interface. When exception
happens, execute registered exception handler if exists, else report an
error.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
KVM: LoongArch: selftests: Add basic interfaces2025-11-27T03:00:18+00:00Bibo Maomaobibo@loongson.cn2025-11-27T03:00:18+00:00urn:sha1:1c5d3a1eab32db1ebb0d5d30736e9236e8a7014f
Add some basic function interfaces such as CSR register access, local
irq enable or disable APIs.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
KVM: LoongArch: selftests: Add system registers save/restore on exception2025-11-27T03:00:18+00:00Bibo Maomaobibo@loongson.cn2025-11-27T03:00:18+00:00urn:sha1:985a96983bedf04fa61315e68806f3468450c8a1
When system returns from exception with ertn instruction, PC comes from
LOONGARCH_CSR_ERA, and CSR.CRMD comes LOONGARCH_CSR_PRMD.
Here save CSR register CSR.ERA and CSR.PRMD into stack, and then restore
them from stack. So it can be modified by exception handlers in future.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
KVM: selftests: Add KVM selftests header files for LoongArch2025-05-20T12:20:23+00:00Bibo Maomaobibo@loongson.cn2025-05-20T12:20:23+00:00urn:sha1:21872c74b07b5f2e29f7bf7a8981e1e84c3ed5f7
Add KVM selftests header files for LoongArch, including processor.h
and kvm_util_arch.h. It mainly contains LoongArch CSR register and page
table entry definition.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>