kernel/linux.git/tools/perf/util/event.h, branch v5.18

perf intel-pt: Synthesize CFE (Control Flow Event) / EVD (Event Data) event

2022-02-15T20:12:13+00:00

Synthesize an attribute event and sample events for Intel PT Event Trace events represented by CFE and EVD packets. Committer notes: Make 'struct perf_synth_intel_evd evd[]' evd[0] at the end of 'struct perf_synth_intel_evt' as it is breaking the build with in many compilers with (e.g. clang version 13.0.0 (Fedora 13.0.0-3.fc35)): util/intel-pt.c:2213:31: error: field 'cfe' with variable sized type 'struct perf_synth_intel_evt' not at the end of a struct or class is a GNU extension [-Werror,-Wgnu-variable-sized-type-not-at-end] struct perf_synth_intel_evt cfe; ^ Signed-off-by: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Jiri Olsa Link: https://lore.kernel.org/r/20220124084201.2699795-15-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo

perf tools: Define new D (Intr Disable) and t (Intr Toggle) flags

2022-02-15T20:09:25+00:00

Define 2 new flags to represent: - when interrupts are disabled (D) - when interrupt disabling toggles (t) This gives 4 combinations: no flag, interrupts enabled t interrupts were enabled but become disabled D interrupts are disabled Dt interrupts were disabled but become enabled Committer notes: Those are control flow flags, as per 'tools/perf/Documentation/perf-intel-pt.txt: An interesting field that is not printed by default is 'flags' which can be displayed as follows: perf script --itrace=ibxwpe -F+flags The flags are "bcrosyiABExgh" which stand for branch, call, return, conditional, system, asynchronous, interrupt, transaction abort, trace begin, trace end, in transaction, VM-entry, and VM-exit respectively. Signed-off-by: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Jiri Olsa Link: https://lore.kernel.org/r/20220124084201.2699795-12-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo

perf tools: Define Intel PT iflag synthesized event

2022-02-15T20:08:56+00:00

Similar to other Intel PT synth events, define a structure to hold information about a change to the interrupt flag. Signed-off-by: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Jiri Olsa Link: https://lore.kernel.org/r/20220124084201.2699795-11-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo

perf tools: Define Intel PT CFE (Control Flow Event) / EVD (Event Data) event

2022-02-15T20:08:27+00:00

Similar to other Intel PT synth events, define structures to hold CFE and EVD data. Signed-off-by: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Jiri Olsa Link: https://lore.kernel.org/r/20220124084201.2699795-10-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo

perf tools: Prevent out-of-bounds access to registers

2021-12-11T11:19:46+00:00

The size of the cache of register values is arch-dependant (PERF_REGS_MAX). This has the potential of causing an out-of-bounds access in the function "perf_reg_value" if the local architecture contains less registers than the one the perf.data file was recorded on. Since the maximum number of registers is bound by the bitmask "u64 cache_mask", and the size of the cache when running under x86 systems is 64 already, fix the size to 64 and add a range-check to the function "perf_reg_value" to prevent out-of-bounds access. Reported-by: Alexandre Truong Reviewed-by: Kajol Jain Signed-off-by: German Gomez Acked-by: Jiri Olsa Cc: Alexander Shishkin Cc: John Garry Cc: Leo Yan Cc: Mark Rutland Cc: Mathieu Poirier Cc: Namhyung Kim Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-csky@vger.kernel.org Cc: linux-riscv@lists.infradead.org Link: https://lore.kernel.org/r/20211201123334.679131-2-german.gomez@arm.com Signed-off-by: Arnaldo Carvalho de Melo

perf tools: Add support for PERF_RECORD_AUX_OUTPUT_HW_ID

2021-10-20T14:22:27+00:00

The PERF_RECORD_AUX_OUTPUT_HW_ID event provides a way to match AUX output data like Intel PT PEBS-via-PT back to the event that it came from, by providing a hardware ID that is present in the AUX output. Reviewed-by: Alexander Shishkin Reviewed-by: Andi Kleen Signed-off-by: Adrian Hunter Cc: Jiri Olsa Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Peter Zijlstra Cc: x86@kernel.org Link: http://lore.kernel.org/lkml/20210907163903.11820-3-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo

perf script: Add missing PERF_IP_FLAG_CHARS for VM-Entry and VM-Exit

2021-05-21T19:41:37+00:00

Add 'g' (guest) for VM-Entry and 'h' (host) for VM-Exit. Fixes: c025d46cd932c ("perf script: Add branch types for VM-Entry and VM-Exit") Signed-off-by: Adrian Hunter Cc: Jiri Olsa Link: http://lore.kernel.org/lkml/20210521175127.27264-1-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo

perf sort: Display sort dimension p_stage_cyc only on supported archs

2021-03-26T11:50:00+00:00

The sort dimension "p_stage_cyc" is used to represent pipeline stage cycle information. Presently, this is used only in powerpc. For unsupported platforms, we don't want to display it in the perf report output columns. Hence add check in sort_dimension__add() and skip the sort key incase it is not applicable for the particular arch. Signed-off-by: Athira Rajeev Reviewed-by: Madhavan Srinivasan Acked-by: Jiri Olsa Cc: Kajol Jain Cc: Kan Liang Cc: Michael Ellerman Cc: Peter Zijlstra Cc: Ravi Bangoria Link: https://lore.kernel.org/r/1616425047-1666-6-git-send-email-atrajeev@linux.vnet.ibm.com Signed-off-by: Arnaldo Carvalho de Melo

perf tools: Support pipeline stage cycles for powerpc

2021-03-26T11:49:54+00:00

The pipeline stage cycles details can be recorded on powerpc from the contents of Performance Monitor Unit (PMU) registers. On ISA v3.1 platform, sampling registers exposes the cycles spent in different pipeline stages. Patch adds perf tools support to present two of the cycle counter information along with memory latency (weight). Re-use the field 'ins_lat' for storing the first pipeline stage cycle. This is stored in 'var2_w' field of 'perf_sample_weight'. Add a new field 'p_stage_cyc' to store the second pipeline stage cycle which is stored in 'var3_w' field of perf_sample_weight. Add new sort function 'Pipeline Stage Cycle' and include this in default_mem_sort_order[]. This new sort function may be used to denote some other pipeline stage in another architecture. So add this to list of sort entries that can have dynamic header string. Signed-off-by: Athira Rajeev Reviewed-by: Madhavan Srinivasan Acked-by: Jiri Olsa Cc: Jiri Olsa Cc: Kajol Jain Cc: Kan Liang Cc: Michael Ellerman Cc: Peter Zijlstra Cc: Ravi Bangoria Link: https://lore.kernel.org/r/1616425047-1666-5-git-send-email-atrajeev@linux.vnet.ibm.com Signed-off-by: Arnaldo Carvalho de Melo

perf sort: Add dynamic headers for perf report columns

2021-03-26T11:49:27+00:00

Currently the header string for different columns in perf report is fixed. Some fields of perf sample could have different meaning for different architectures than the meaning conveyed by the header string. An example is the new field 'var2_w' of perf_sample_weight structure. This is presently captured as 'Local INSTR Latency' in perf mem report. But this could be used to denote a different latency cycle in another architecture. Introduce a weak function arch_perf_header_entry() to set the arch specific header string for the fields which can contain dynamic header. If the architecture do not have this function, fall back to the default header string value. Signed-off-by: Athira Rajeev Reviewed-by: Madhavan Srinivasan Acked-by: Jiri Olsa Cc: Kajol Jain Cc: Kan Liang Cc: Michael Ellerman Cc: Peter Zijlstra Cc: Ravi Bangoria Link: https://lore.kernel.org/r/1616425047-1666-3-git-send-email-atrajeev@linux.vnet.ibm.com Signed-off-by: Arnaldo Carvalho de Melo