<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/tools/arch/riscv/include/asm, branch v6.12.81</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.81</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.81'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2025-12-01T10:43:31+00:00</updated>
<entry>
<title>tools: riscv: Fixed misalignment of CSR related definitions</title>
<updated>2025-12-01T10:43:31+00:00</updated>
<author>
<name>Chen Pei</name>
<email>cp0613@linux.alibaba.com</email>
</author>
<published>2025-11-14T07:12:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=b91ef042e21a81f3433e9ceae821a862f02a6472'/>
<id>urn:sha1:b91ef042e21a81f3433e9ceae821a862f02a6472</id>
<content type='text'>
[ Upstream commit e2cb69263e797c0aa6676bcef23e9e27e44c83b0 ]

The file tools/arch/riscv/include/asm/csr.h borrows from
arch/riscv/include/asm/csr.h, and subsequent modifications
related to CSR should maintain consistency.

Signed-off-by: Chen Pei &lt;cp0613@linux.alibaba.com&gt;
Link: https://patch.msgid.link/20251114071215.816-1-cp0613@linux.alibaba.com
[pjw@kernel.org: dropped Fixes: lines for patches that weren't broken; removed superfluous blank line]
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>tools: Add riscv barrier implementation</title>
<updated>2024-09-20T08:46:46+00:00</updated>
<author>
<name>Charlie Jenkins</name>
<email>charlie@rivosinc.com</email>
</author>
<published>2024-08-06T22:01:23+00:00</published>
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<id>urn:sha1:6d74d178fe6eaf61e384f3be6ba64150bddce8a6</id>
<content type='text'>
Many of the other architectures use their custom barrier implementations.
Use the barrier code from the kernel sources to optimize barriers in
tools.

Signed-off-by: Charlie Jenkins &lt;charlie@rivosinc.com&gt;
Reviewed-by: Andrea Parri &lt;parri.andrea@gmail.com&gt;
Link: https://lore.kernel.org/r/20240806-optimize_ring_buffer_read_riscv-v2-1-ca7e193ae198@rivosinc.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>tools: riscv: Add header file vdso/processor.h</title>
<updated>2024-02-26T04:44:04+00:00</updated>
<author>
<name>Haibo Xu</name>
<email>haibo1.xu@intel.com</email>
</author>
<published>2024-01-22T09:58:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=1d50c77208933fd1c18be8359633913d9c482e5a'/>
<id>urn:sha1:1d50c77208933fd1c18be8359633913d9c482e5a</id>
<content type='text'>
Borrow the cpu_relax() definitions from kernel's
arch/riscv/include/asm/vdso/processor.h to tools/ for riscv.

Signed-off-by: Haibo Xu &lt;haibo1.xu@intel.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>tools: riscv: Add header file csr.h</title>
<updated>2024-02-26T04:44:02+00:00</updated>
<author>
<name>Haibo Xu</name>
<email>haibo1.xu@intel.com</email>
</author>
<published>2024-01-22T09:58:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a69459d579df9200bc6f58ff04e1a8a4984016a7'/>
<id>urn:sha1:a69459d579df9200bc6f58ff04e1a8a4984016a7</id>
<content type='text'>
Borrow the csr definitions and operations from kernel's
arch/riscv/include/asm/csr.h to tools/ for riscv.

Signed-off-by: Haibo Xu &lt;haibo1.xu@intel.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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