kernel/linux.git/include/uapi/drm/drm_fourcc.h, branch v5.15.210

drm/fourcc: Add packed 10bit YUV 4:2:0 format

2022-12-31T12:14:10+00:00

[ Upstream commit 006ea1b5822f9019bd722ffc6242bc0880879e3d ] Adds a format that is 3 10bit YUV 4:2:0 samples packed into a 32bit word (with 2 spare bits). Supported on Broadcom BCM2711 chips. Signed-off-by: Dave Stevenson Signed-off-by: Maxime Ripard Acked-by: Thomas Zimmermann Link: https://lore.kernel.org/r/20211215091739.135042-2-maxime@cerno.tech Stable-dep-of: b230555f3257 ("drm/fourcc: Fix vsub/hsub for Q410 and Q401") Signed-off-by: Sasha Levin

drm/fourcc: fix integer type usage in uapi header

2022-07-07T15:53:34+00:00

[ Upstream commit 20b8264394b33adb1640a485a62a84bc1388b6a3 ] Kernel uapi headers are supposed to use __[us]{8,16,32,64} types defined by as opposed to 'uint32_t' and similar. See [1] for the relevant discussion about this topic. In this particular case, the usage of 'uint64_t' escaped headers_check as these macros are not being called here. However, the following program triggers a compilation error: #include int main() { unsigned long x = AMD_FMT_MOD_CLEAR(RB); return 0; } gcc error: drm.c:5:27: error: ‘uint64_t’ undeclared (first use in this function) 5 | unsigned long x = AMD_FMT_MOD_CLEAR(RB); | ^~~~~~~~~~~~~~~~~ This patch changes AMD_FMT_MOD_{SET,CLEAR} macros to use the correct integer types, which fixes the above issue. [1] https://lkml.org/lkml/2019/6/5/18 Fixes: 8ba16d599374 ("drm/fourcc: Add AMD DRM modifiers.") Signed-off-by: Carlos Llamas Reviewed-by: Simon Ser Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/fourcc: Add modifier definitions for Arm Fixed Rate Compression

2021-07-23T15:10:22+00:00

Arm Fixed Rate Compression (AFRC) is a proprietary fixed rate image compression protocol and format. It is designed to provide guaranteed bandwidth and memory footprint reductions in graphics and media use-cases. This patch aims to add modifier definitions for describing AFRC. Signed-off-by: Normunds Rieksts Reviewed-by: Liviu Dudau Signed-off-by: Liviu Dudau Link: https://patchwork.freedesktop.org/patch/msgid/20210701170709.39922-1-normunds.rieksts@arm.com

drm/fourcc: Add 16 bpc fixed point framebuffer formats.

2021-05-27T19:00:47+00:00

These are 16 bits per color channel unsigned normalized formats. They are supported by at least AMD display hw, and suitable for direct scanout of Vulkan swapchain images in the format VK_FORMAT_R16G16B16A16_UNORM. Reviewed-by: Ville Syrjälä Signed-off-by: Mario Kleiner Signed-off-by: Alex Deucher

Merge tag 'drm-intel-next-2021-01-27' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

2021-01-29T07:05:15+00:00

- HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (Anshuman) - Fix DP vswing settings and handling (Imre, Ville) - Various display code clean-up (Jani, Ville) - Various display refactoring, including split out of pps, aux, and fdi (Ja\ ni, Dave) - Add DG1 missing workarounds (Jose) - Fix display color conversion (Chris, Ville) - Try to guess PCH type even without ISA bridge (Zhenyu) - More backlight refactor (Lyude) - Support two CSC module on gen11 and later (Lee) - Async flips for all ilk+ platforms (Ville) - Clear color support for TGL (RK) - Add a helper to read data from a GEM object page (Imre) - VRR/Adaptive Sync Enabling on DP/eDP for TGL+ (Manasi, Ville Aditya) Signed-off-by: Dave Airlie From: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20210127140822.GA711686@intel.com

drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color

2021-01-22T13:57:28+00:00

Gen12 display can decompress surfaces compressed by render engine with Clear Color, add a new modifier as the driver needs to know the surface was compressed by render engine. V2: Description changes as suggested by Rafael. V3: Mention the Clear Color size of 64 bits in the comments(DK) v4: Fix trailing whitespaces v5: Explain Clear Color in the documentation. v6: Documentation Nitpicks(Nanley) Cc: Ville Syrjala Cc: Dhinakaran Pandiyan Cc: Kalyan Kondapally Cc: Rafael Antognolli Cc: Nanley Chery Signed-off-by: Radhakrishna Sripada Signed-off-by: Imre Deak Acked-by: Daniel Vetter Acked-by: Jani Nikula Acked-by: Nanley Chery Reviewed-by: Mika Kahola Link: https://patchwork.freedesktop.org/patch/msgid/20210114201314.783648-2-imre.deak@intel.com

drm/fourcc: fix Amlogic format modifier masks

2021-01-12T14:52:43+00:00

The comment says the layout and options use 8 bits, and the shift uses 8 bits. However the mask is 0xf, ie. 0b00001111 (4 bits). This could be surprising when introducing new layouts or options that take more than 4 bits, as this would silently drop the high bits. Make the masks consistent with the comment and the shift. Found when writing a drm_info patch [1]. [1]: https://github.com/ascent12/drm_info/pull/67 Signed-off-by: Simon Ser Fixes: d6528ec88309 ("drm/fourcc: Add modifier definitions for describing Amlogic Video Framebuffer Compression") Cc: Neil Armstrong Cc: Sam Ravnborg Cc: Kevin Hilman Cc: Daniel Vetter Acked-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/20210110125103.15447-1-contact@emersion.fr

drm/fourcc: fix AMD modifiers PACKERS field doc

2020-11-16T17:20:13+00:00

This field doesn't alias with BANK_XOR_BITS: PACKERS is bits 27:29 while BANK_XOR_BITS is bits 24:26. Fixes: 8ba16d599374 ("drm/fourcc: Add AMD DRM modifiers.") Reviewed-by: Bas Nieuwenhuizen Signed-off-by: Simon Ser Cc: Bas Nieuwenhuizen Cc: Alex Deucher Cc: Daniel Vetter Signed-off-by: Alex Deucher

drm/fourcc: add table describing AMD modifiers bit layout

2020-11-13T22:29:47+00:00

The table describes how each bit in the u64 value is used. Explicitly state which values a field can take if we have defines for them. Also add a note when a field isn't always populated. Forcing people to update the table when changing the bit layout should make it more obvious when there's a mistake, I hope. If we get to the point where the bit layout gets more complicated, it might be worth it to split the table into multiple tables (e.g. one for GFX8, one for GFX9+, and so on). Signed-off-by: Simon Ser Cc: Bas Nieuwenhuizen Cc: Alex Deucher Cc: Daniel Vetter Signed-off-by: Alex Deucher

drm/fourcc: Fix modifier field mask for AMD modifiers.

2020-11-13T22:29:47+00:00

The DCC_MAX_COMPRESSED_BLOCK has to contain one of AMD_FMT_MOD_DCC_BLOCK_* and with 3 values this doesn't fit in 1 bit. Fix this cleanly while it is only in drm-next. Fixes: 8ba16d599374 ("drm/fourcc: Add AMD DRM modifiers.") Reviewed-by: Alex Deucher Signed-off-by: Bas Nieuwenhuizen Signed-off-by: Alex Deucher