<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/include/soc/tegra, branch v7.2-rc1</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v7.2-rc1</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v7.2-rc1'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2026-06-09T14:53:10+00:00</updated>
<entry>
<title>Merge tag 'memory-controller-drv-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers</title>
<updated>2026-06-09T14:53:10+00:00</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2026-06-09T14:53:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8c3fb979f1b0bd2c6b273b552f8cb74965e3d1db'/>
<id>urn:sha1:8c3fb979f1b0bd2c6b273b552f8cb74965e3d1db</id>
<content type='text'>
Memory controller drivers for v7.2

1. Tegra MC/EMC:
   - Handle system sleep, necessary to re-program registers after system
     resume.  A few more improvements.
   - Add Tegra114 and Tegra238 Memory Controller, and Tegra114 External
     MC support.
   - Grow Tegra264 support.

2. Renesas XSPI: Document RZ/T2H and RZ/N2H variants, compatible with
   existing devices.

* tag 'memory-controller-drv-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: tegra264: Add full set of MC clients
  dt-bindings: memory: tegra264: Add full set of MC client IDs
  memory: tegra264: Skip clients without bpmp_id or type
  memory: renesas-rpc-if: Fix duplicate device name on multi-instance platforms
  dt-bindings: memory: renesas,rzg3e-xspi: Add RZ/T2H and RZ/N2H support
  memory: omap-gpmc: Silence W=1 kerneldoc warnings
  memory: tegra114-emc: Simplify tegra114_emc_interconnect_init() error message
  memory: tegra114-emc: Do not print error on icc_node_create() failure
  memory: tegra: Fix possible null pointer dereference
  memory: tegra: Add Tegra114 EMC driver
  memory: tegra: Implement EMEM regs and ICC ops for Tegra114
  dt-bindings: memory: Document Tegra114 External Memory Controller
  dt-bindings: memory: Document Tegra114 Memory Controller
  memory: tegra: Add Tegra238 MC support
  dt-bindings: memory: tegra: Add nvidia,tegra238-mc compatible
  memory: tegra: Restore MC interrupt masks on resume
  memory: tegra: Wire up system sleep PM ops
  memory: tegra: Make -&gt;resume() callback return void
  memory: tegra: Deduplicate rate request management code
  memory: atmel-ebi: Allow deferred probing

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>soc/tegra: pmc: Move legacy code behind CONFIG_ARM guard</title>
<updated>2026-05-31T05:21:14+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2025-02-04T18:04:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8318af5dd29c819d95ec5b878e7dab6090a9ed2b'/>
<id>urn:sha1:8318af5dd29c819d95ec5b878e7dab6090a9ed2b</id>
<content type='text'>
None of this legacy code is needed on 64-bit ARM devices, so it can be
moved behind a corresponding preprocessor guard. This more cleanly
separates out the legacy code from code needed on current platforms.

Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: pmc: Remove unused legacy functions</title>
<updated>2026-05-31T05:21:14+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2025-02-04T18:45:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=72a2a9023c329aca7e7f8d3997c9a26aa317a1fd'/>
<id>urn:sha1:72a2a9023c329aca7e7f8d3997c9a26aa317a1fd</id>
<content type='text'>
All callers of these functions have been replaced by their variants
taking a PMC context as an input, so they are no longer used and can be
removed.

Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Make -&gt;resume() callback return void</title>
<updated>2026-05-04T17:17:48+00:00</updated>
<author>
<name>Ashish Mhetre</name>
<email>amhetre@nvidia.com</email>
</author>
<published>2026-04-30T09:52:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4f42beeb9796e24e8009c46d1a2d676803e5ab24'/>
<id>urn:sha1:4f42beeb9796e24e8009c46d1a2d676803e5ab24</id>
<content type='text'>
tegra186_mc_resume() is the only implementation of the SoC -&gt;resume()
op in struct tegra_mc_ops, and it can never fail as the SID override
loop has no error path. The int return value is therefore not used.

Change the prototype to return void so callers do not need to deal
with a value that is always 0. If a future SoC needs to report
failure from resume, an int return type can be reintroduced then.

Signed-off-by: Ashish Mhetre &lt;amhetre@nvidia.com&gt;
Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Link: https://patch.msgid.link/20260430095202.1167651-2-amhetre@nvidia.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'tegra-for-7.1-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers</title>
<updated>2026-04-02T21:13:02+00:00</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2026-04-02T21:13:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f1aa30a4b23d905dd39944cdffdf68c8cc3e28a9'/>
<id>urn:sha1:f1aa30a4b23d905dd39944cdffdf68c8cc3e28a9</id>
<content type='text'>
firmware: tegra: Changes for v7.1-rc1

This introduces a new API for the BPMP to be pass along a specifier from
DT when getting a reference from a phandle. This is used to reference
specific instances of the PCI controller on Tegra264. The ABI header for
BPMP is updated to the latest version and BPMP APIs now use the more
intuitive ENODEV instead of the non SUSV4 ENOTSUPP error code for stub
implementations.

* tag 'tegra-for-7.1-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: bpmp: Use ENODEV instead of ENOTSUPP
  firmware: tegra: bpmp: Add tegra_bpmp_get_with_id() function
  soc/tegra: Update BPMP ABI header
  firmware: tegra: bpmp: Rename Tegra239 to Tegra238

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>soc/tegra: bpmp: Use ENODEV instead of ENOTSUPP</title>
<updated>2026-03-27T15:30:54+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2026-03-26T11:28:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e68d494b8946e9060e60427f365107194f90ba0d'/>
<id>urn:sha1:e68d494b8946e9060e60427f365107194f90ba0d</id>
<content type='text'>
ENOTSUPP is not a SUSV4 error code and checkpatch will warn about it.
It is also not very descriptive in the context of BPMP, so use the
ENODEV error code instead. For the stub implementations this is a more
accurate description of what the failure is.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>firmware: tegra: bpmp: Add tegra_bpmp_get_with_id() function</title>
<updated>2026-03-27T15:24:36+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2026-03-26T13:58:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=77344118720e31dcbac47d13c35da3b1de663529'/>
<id>urn:sha1:77344118720e31dcbac47d13c35da3b1de663529</id>
<content type='text'>
Some device tree bindings need to specify a parameter along with a BPMP
phandle reference to designate the ID associated with a given controller
that needs to interoperate with BPMP. Typically this is specified as an
extra cell in the nvidia,bpmp property, so add a helper to parse this ID
while resolving the phandle reference.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: Update BPMP ABI header</title>
<updated>2026-03-27T15:23:53+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2026-03-26T13:58:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=83c18a324570193140cafc12c88eb1e370564078'/>
<id>urn:sha1:83c18a324570193140cafc12c88eb1e370564078</id>
<content type='text'>
This update primarily adds various new commands and MRQs for Tegra264,
but also contains a few new annotations and fixes.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>firmware: tegra: bpmp: Rename Tegra239 to Tegra238</title>
<updated>2026-03-19T16:03:55+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2026-02-26T15:09:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d921f8d3b955ba09d321c612fc485b9e9ac438c0'/>
<id>urn:sha1:d921f8d3b955ba09d321c612fc485b9e9ac438c0</id>
<content type='text'>
This chip identifies as Tegra238, so update the BPMP ABI header to refer
to it by the correct name.

Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Prepare for supporting multiple intmask registers</title>
<updated>2026-03-07T17:02:41+00:00</updated>
<author>
<name>Ketan Patil</name>
<email>ketanp@nvidia.com</email>
</author>
<published>2026-02-26T16:31:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9f2614510960f0761144d14e1b4c4d82e0c098e9'/>
<id>urn:sha1:9f2614510960f0761144d14e1b4c4d82e0c098e9</id>
<content type='text'>
Add a new structure for the intmask register e.g. MC_INTMASK_0 and
it's mask value. Add an array of these new structures to prepare for
supporting multiple intmask registers. This is done in preparation for
adding support for Tegra264 which supports multiple intmask registers.

Signed-off-by: Ketan Patil &lt;ketanp@nvidia.com&gt;
Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Link: https://patch.msgid.link/20260226163115.1152181-6-ketanp@nvidia.com
[krzk: Fix checkpatch warning]
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
</feed>
