kernel/linux.git/include/soc/tegra, branch master

Merge tag 'tegra-for-7.1-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers

2026-04-02T21:13:02+00:00

firmware: tegra: Changes for v7.1-rc1 This introduces a new API for the BPMP to be pass along a specifier from DT when getting a reference from a phandle. This is used to reference specific instances of the PCI controller on Tegra264. The ABI header for BPMP is updated to the latest version and BPMP APIs now use the more intuitive ENODEV instead of the non SUSV4 ENOTSUPP error code for stub implementations. * tag 'tegra-for-7.1-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: bpmp: Use ENODEV instead of ENOTSUPP firmware: tegra: bpmp: Add tegra_bpmp_get_with_id() function soc/tegra: Update BPMP ABI header firmware: tegra: bpmp: Rename Tegra239 to Tegra238 Signed-off-by: Arnd Bergmann

soc/tegra: bpmp: Use ENODEV instead of ENOTSUPP

2026-03-27T15:30:54+00:00

ENOTSUPP is not a SUSV4 error code and checkpatch will warn about it. It is also not very descriptive in the context of BPMP, so use the ENODEV error code instead. For the stub implementations this is a more accurate description of what the failure is. Signed-off-by: Thierry Reding

firmware: tegra: bpmp: Add tegra_bpmp_get_with_id() function

2026-03-27T15:24:36+00:00

Some device tree bindings need to specify a parameter along with a BPMP phandle reference to designate the ID associated with a given controller that needs to interoperate with BPMP. Typically this is specified as an extra cell in the nvidia,bpmp property, so add a helper to parse this ID while resolving the phandle reference. Signed-off-by: Thierry Reding

soc/tegra: Update BPMP ABI header

2026-03-27T15:23:53+00:00

This update primarily adds various new commands and MRQs for Tegra264, but also contains a few new annotations and fixes. Signed-off-by: Thierry Reding

firmware: tegra: bpmp: Rename Tegra239 to Tegra238

2026-03-19T16:03:55+00:00

This chip identifies as Tegra238, so update the BPMP ABI header to refer to it by the correct name. Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding

memory: tegra: Prepare for supporting multiple intmask registers

2026-03-07T17:02:41+00:00

Add a new structure for the intmask register e.g. MC_INTMASK_0 and it's mask value. Add an array of these new structures to prepare for supporting multiple intmask registers. This is done in preparation for adding support for Tegra264 which supports multiple intmask registers. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-6-ketanp@nvidia.com [krzk: Fix checkpatch warning] Signed-off-by: Krzysztof Kozlowski

memory: tegra: Group SoC specific fields

2026-03-07T17:02:29+00:00

Introduce new SoC specific fields in tegra_mc_soc struct for high address mask and error status type mask because Tegra264 has different values for these than the existing devices. Error status registers e.g. MC_ERR_STATUS_0 has few bits which indicate the type of the error. In order to obtain such type of error from error status register, we use error status type mask. Similarly, these error status registers have bits which indicate the higher address bits of the address responsible for mc error. In order to obtain such higher address, we use high address mask. Make this change to prepare for adding MC interrupt support for Tegra264. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-5-ketanp@nvidia.com [krzk: Fix checkpatch warning] Signed-off-by: Krzysztof Kozlowski

memory: tegra: Add support for multiple IRQs

2026-03-07T16:59:37+00:00

Add support to handle multiple MC interrupts lines, as supported by Tegra264. Turn the single IRQ handler callback into a counted array to allow specifying a separate handler for each interrupt. Move IRQ handlers into tegra_mc_soc struct, so as to specify SoC specific values. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-4-ketanp@nvidia.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Group error handling related registers

2026-03-07T16:59:35+00:00

Group MC error related registers into a struct as they could have SoC specific values. Tegra264 has different register offsets than the existing devices and so in order to add support for Tegra264 we need to first make this change. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-2-ketanp@nvidia.com Signed-off-by: Krzysztof Kozlowski

soc/tegra: pmc: Add PMC contextual functions

2026-01-18T07:48:30+00:00

Add implementations that take as argument a struct tegra_pmc * for most public APIs, as well as a function to obtain the PMC for any given device. This will allow transitioning away users from relying on a global variable storing the PMC context. Signed-off-by: Thierry Reding