kernel/linux.git/include/soc/tegra/mc.h, branch v6.12.80

interconnect: constify of_phandle_args in xlate

2024-02-25T22:38:17+00:00

The xlate callbacks are supposed to translate of_phandle_args to proper provider without modifying the of_phandle_args. Make the argument pointer to const for code safety and readability. Acked-by: Konrad Dybcio Acked-by: Thierry Reding # Tegra Signed-off-by: Krzysztof Kozlowski Acked-by: Alim Akhtar # Samsung Link: https://lore.kernel.org/r/20240220072213.35779-1-krzysztof.kozlowski@linaro.org Signed-off-by: Georgi Djakov

memory: tegra: Add SID override programming for MC clients

2023-11-21T09:09:28+00:00

For some devices the bootloader/firmware may set up the device in bypass. Memory clients like display needs kernel to program SID after resume because bootloader/firmware programs the SID of display device to bypass. In order to make sure that kernel IOMMU mappings for these devices work after resume, add SID override programming support for all memory clients on memory controller resume. This partially reverts 'commit ef86b2c2807f ("memory: tegra: Remove clients SID override programming")' Signed-off-by: Ashish Mhetre Link: https://lore.kernel.org/r/20231107112713.21399-1-amhetre@nvidia.com Signed-off-by: Krzysztof Kozlowski

iommu/tegra-gart: Remove tegra-gart

2023-09-25T09:40:54+00:00

Thierry says this is not used anymore, and doesn't think it makes sense as an iommu driver. The HW it supports is about 10 years old now and newer HW uses different IOMMU drivers. As this is the only driver with a GART approach, and it doesn't really meet the driver expectations from the IOMMU core, let's just remove it so we don't have to think about how to make it fit in. It has a number of identified problems: - The assignment of iommu_groups doesn't match the HW behavior - It claims to have an UNMANAGED domain but it is really an IDENTITY domain with a translation aperture. This is inconsistent with the core expectation for security sensitive operations - It doesn't implement a SW page table under struct iommu_domain so * It can't accept a map until the domain is attached * It forgets about all maps after the domain is detached * It doesn't clear the HW of maps once the domain is detached (made worse by having the wrong groups) Cc: Thierry Reding Cc: Dmitry Osipenko Acked-by: Thierry Reding Reviewed-by: Lu Baolu Reviewed-by: Jerry Snitselaar Signed-off-by: Jason Gunthorpe Link: https://lore.kernel.org/r/6-v8-81230027b2fa+9d-iommu_all_defdom_jgg@nvidia.com Signed-off-by: Joerg Roedel

memory: tegra: Add dummy implementation on Tegra194

2023-07-10T10:04:56+00:00

With the introduction of commit 9365bf006f53 ("PCI: tegra194: Add interconnect support in Tegra234"), the PCI driver on Tegra194 and later requires an interconnect provider. However, a provider is currently only exposed on Tegra234 and this causes PCI on Tegra194 to defer probe indefinitely. Fix this by adding a dummy implementation on Tegra194. This allows nodes to be provided to interconnect consumers, but doesn't do any bandwidth accounting or frequency scaling. Fixes: 9365bf006f53 ("PCI: tegra194: Add interconnect support in Tegra234") Reported-by: Jon Hunter Signed-off-by: Thierry Reding Reviewed-by: Sumit Gupta Tested-by: Sumit Gupta Link: https://lore.kernel.org/r/20230629160132.768940-1-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Make CPU cluster BW request a multiple of MC channels

2023-05-16T10:11:01+00:00

Make CPU cluster's bandwidth (BW) request a multiple of MC channels. CPU OPP tables have BW info per MC channel. But, the actual BW depends on the number of MC channels which can change as per the boot config. Get the number of MC channels which are actually enabled in current boot configuration and multiply the BW request from a CPU cluster with the number of enabled MC channels. This is not required to be done for other MC clients. Signed-off-by: Sumit Gupta Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding

memory: tegra: Add interconnect support for DRAM scaling in Tegra234

2023-05-16T10:11:00+00:00

Add Interconnect framework support to dynamically set the DRAM bandwidth from different clients. Both the MC and EMC drivers are added as ICC providers. The path for any request is: MC-Client[1-n] -> MC -> EMC -> EMEM/DRAM MC client's request for bandwidth will go to the MC driver which passes the client request info like BPMP Client ID, Client type and the Bandwidth to the BPMP-FW. The final DRAM freq to achieve the requested bandwidth is set by the BPMP-FW based on the passed parameters. Signed-off-by: Sumit Gupta Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding

memory: tegra: Add API for retrieving carveout bounds

2022-11-25T15:14:58+00:00

On Tegra234 NVDEC firmware is loaded from a secure carveout, where it has been loaded by a bootloader. When booting NVDEC, we need to tell it the address of this firmware, which we can determine by checking the starting address of the carveout. As such, add an MC API to query the bounds of carveouts, and add related information on Tegra234. Signed-off-by: Mikko Perttunen Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding

memory: tegra: Add MC error logging on Tegra186 onward

2022-05-09T08:46:14+00:00

Add support for logging memory controller errors on Tegra186, Tegra194 and Tegra234. On these SoCs, interrupts can occur on multiple channels. Add support required to read the status of interrupts across multiple channels, log and clear them. Also add new interrupts supported on these SoCs. Reviewed-by: Dmitry Osipenko Signed-off-by: Ashish Mhetre Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20220506132312.3910637-5-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Add memory controller channels support

2022-05-09T08:46:11+00:00

From Tegra186 onwards, the memory controller supports multiple channels. Add support for mapping the address spaces of these channels and specify the number of channels supported by Tegra186, Tegra194 and Tegra234. In case of old bindings, channels won't be present. If channels are not present then print a warning and continue so that backward compatibility will be preserved in driver. During error interrupts from memory controller, appropriate registers from these channels need to be accessed for logging error info. Signed-off-by: Ashish Mhetre Reviewed-by: Dmitry Osipenko Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20220506132312.3910637-4-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Add compile-test stub for tegra_mc_probe_device()

2021-06-20T19:22:30+00:00

The tegra_mc_probe_device() symbol is only available when the TEGRA_MC Kconfig option is enabled. Provide a stub if that's not the case so that the driver can be compile-tested. Reported-by: kernel test robot Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210618111846.1286166-1-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski